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6 Commits
glan
...
system76-4
Author | SHA1 | Date | |
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6392a92690 | ||
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f7222726d6 | ||
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de3ee05f93 | ||
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2477843e74 | ||
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82dec294f6 | ||
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49d376482b |
@@ -108,6 +108,10 @@ config MAINBOARD_VERSION
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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config CMOS_DEFAULT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
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default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
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config CONSOLE_POST
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config CONSOLE_POST
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default y
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default y
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3
src/mainboard/system76/adl/cmos-csme.default
Normal file
3
src/mainboard/system76/adl/cmos-csme.default
Normal file
@@ -0,0 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@@ -1,4 +1,6 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "s0ix_enable" = "1"
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register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
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register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 56,
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.tdp_pl2_override = 56,
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@@ -7,7 +7,7 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE),
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PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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@@ -16,7 +16,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
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PAD_NC(GPD11, NONE),
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PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
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/* ------- GPIO Group GPP_A ------- */
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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@@ -41,7 +41,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
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PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
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PAD_NC(GPP_A20, NONE),
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PAD_NC(GPP_A20, NONE),
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PAD_NC(GPP_A21, NONE),
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PAD_NC(GPP_A21, NONE),
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PAD_NC(GPP_A22, NONE),
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PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN
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PAD_NC(GPP_A23, NONE),
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PAD_NC(GPP_A23, NONE),
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/* ------- GPIO Group GPP_B ------- */
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/* ------- GPIO Group GPP_B ------- */
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@@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap
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PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
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PAD_CFG_GPO(GPP_C5, 1, PLTRST), // GPIO_LANRTD3
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PAD_CFG_GPO(GPP_C5, 1, PLTRST), // ESPI OR EC LESS strap
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
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// GPP_C8 missing
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// GPP_C8 missing
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@@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
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// GPP_F5 (CNVI_CLKREQ) programmed by FSP
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// GPP_F5 (CNVI_CLKREQ) programmed by FSP
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_CFG_GPO(GPP_F7, 1, PLTRST), // LAN_PLT_RST#
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PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
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// GPP_F8 missing
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// GPP_F8 missing
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PAD_NC(GPP_F9, NONE),
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PAD_NC(GPP_F9, NONE),
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PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#
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PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#
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@@ -165,7 +165,6 @@ chip soc/intel/alderlake
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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}"
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chip soc/intel/common/block/pcie/rtd3
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C5)" # GPIO_LANRTD3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST#
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST#
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register "srcclk_pin" = "6" # LAN_CLKREQ#
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register "srcclk_pin" = "6" # LAN_CLKREQ#
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device generic 0 on end
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device generic 0 on end
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@@ -133,6 +133,10 @@ config MAINBOARD_VERSION
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "serw13" if BOARD_SYSTEM76_SERW13
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default "serw13" if BOARD_SYSTEM76_SERW13
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config CMOS_DEFAULT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9
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default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
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config CONSOLE_POST
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config CONSOLE_POST
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default y
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default y
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3
src/mainboard/system76/rpl/cmos-csme.default
Normal file
3
src/mainboard/system76/rpl/cmos-csme.default
Normal file
@@ -0,0 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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@@ -1,4 +1,6 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "s0ix_enable" = "1"
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register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
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register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 56,
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.tdp_pl2_override = 56,
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@@ -14,6 +16,11 @@ chip soc/intel/alderlake
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.clk_req = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST#
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register "srcclk_pin" = "0" # SSD2_CLKREQ#
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device generic 0 on end
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end
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end
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end
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device ref pcie4_1 on
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device ref pcie4_1 on
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# CPU RP#3 x4, Clock 4 (SSD1)
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# CPU RP#3 x4, Clock 4 (SSD1)
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@@ -22,6 +29,11 @@ chip soc/intel/alderlake
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.clk_req = 4,
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.clk_req = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
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register "srcclk_pin" = "4" # SSD1_CLKREQ#
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device generic 0 on end
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end
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end
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end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp0 on end
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device ref tcss_xhci on
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device ref tcss_xhci on
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@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_CBFS_SERIAL
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select DRIVERS_GENERIC_CBFS_SERIAL
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select DRIVERS_GENERIC_CBFS_UUID
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select DRIVERS_GENERIC_CBFS_UUID
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select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
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select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
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