mb/system76/gaze17: 3060: Fix RTD3 configs

The gaze17, like the oryp9, ties all resets for RTD3 to BUF_PLT_RST#
instead of using dedicated lines and ties the enable GPIO to 3.3VS.

Disable RTD3 config for the CPU PCIe RP and disable L23 for the PCH SSD
slot to fix suspend with Western Digital drives.

Change-Id: Iab3796d98ce74e09e74abb48b437e74a60c7b6b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
---ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS

.gitignore

@@ -31,9 +31,6 @@ site-local
 # Development friendly files
 tags
 .clang_complete
-.cache
-compile_commands.json
-.vscode/
 
 # Cross-compile toolkits
 xgcc/
@@ -43,3 +40,5 @@ tarballs/
 *~
 *.kate-swp
 *.kdev4
+
+doxygen/*

.gitmodules

@@ -61,7 +61,3 @@
 	path = 3rdparty/stm
 	url = https://review.coreboot.org/STM
 	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = https://review.coreboot.org/goswid.git
-	branch = trunk

AUTHORS

@@ -108,7 +108,6 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
-Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

Documentation/.mdl_style.rb

@@ -1,9 +0,0 @@
-# See one of the following URLs for explanations of all the rules
-# https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-# https://web.archive.org/web/20220424164542/https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-
-all
-exclude_rule 'no-multiple-blanks'
-exclude_rule 'blanks-around-headers'
-exclude_rule 'blanks-around-lists'
-rule 'line-length', :line_length => 72

Documentation/Makefile

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 #
 # Makefile for coreboot paper.
 # hacked together by Stefan Reinauer <stepan@openbios.org>

Documentation/Makefile.sphinx

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 # Makefile for Sphinx documentation
 #
 

Documentation/RFC/intel-gpio-cleanup.md

@@ -51,7 +51,7 @@ index 28e78fb366..0cce41b316 100644
 @@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
                 /* Patch GPIO settings for SoC specifically */
                 soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
-
+ 
 -               if (CONFIG(DEBUG_GPIO))
 +               if (soc_pad_conf != pad_conf)
                         printk(BIOS_DEBUG,

Documentation/acpi/devicetree.md

@@ -0,0 +1,290 @@
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+### Naming and referencing devices
+
+When declaring a device, it can optionally be given an alias that can be
+referred to elsewhere. This is particularly useful to declare a device in one
+device tree while allowing its configuration to be more easily changed in an
+overlay. For instance, the AMD Picasso SoC definition
+(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
+by default:
+
+```
+chip soc/amd/picasso
+	device domain 0 on
+		...
+		device pci 00.2 alias iommu off end
+		...
+	end
+end
+```
+
+A device based on this SoC can override the configuration for the IOMMU without
+duplicating addresses, as in
+`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
+
+```
+chip soc/amd/picasso
+	device domain 0
+		...
+		device ref iommu on end
+		...
+	end
+end
+```
+
+In this example the override simply enables the IOMMU, but it could also
+set additional properties (or even add child devices) inside the IOMMU `device`
+block.
+
+---
+
+It is important to note that devices that use `device ref` syntax to override
+previous definitions of a device by alias must be placed at **exactly the same
+location in the device tree** as the original declaration. If not, this will
+actually create another device rather than overriding the properties of the
+existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
+were written as follows:
+
+```
+chip soc/amd/picasso
+	# NOTE: not inside domain 0!
+	device ref iommu on end
+end
+```
+
+Then this would leave the SoC's IOMMU disabled, and instead create a new device
+with no properties as a direct child of the SoC.
+
+## Device drivers
+
+Let's take a look at an example entry from
+``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
+
+```
+device pci 15.0 on
+	chip drivers/i2c/generic
+		register "hid" = ""ELAN0000""
+		register "desc" = ""ELAN Touchpad""
+		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+		register "wake" = "GPE0_DW0_21"
+		device i2c 15 on end
+	end
+end # I2C #0
+```
+
+When this entry is processed during ramstage, it will create a device in the
+ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
+generation routines in coreboot actually generate the raw bytecode that
+represents the device's structure, but looking at ASL code is easier to
+understand; see below for what the disassembled bytecode looks like:
+
+```
+Scope (\_SB.PCI0.I2C0)
+{
+    Device (D015)
+    {
+        Name (_HID, "ELAN0000")  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
+        Method (_STA, 0, NotSerialized)  // _STA: Status
+        {
+            Return (0x0F)
+        }
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                0x00, ResourceConsumer, , Exclusive, )
+            Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+            {
+                0x0000002D,
+            }
+        })
+        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
+        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+        {
+            0x15, // GPE #21
+            0x03  // Sleep state S3
+        })
+    }
+}
+```
+
+You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
+names/methods in the Device's scope.
+
+## Utilizing a device driver
+
+The device driver must be enabled for your build.  There will be a CONFIG option
+in the Kconfig file in the directory that the driver is in (e.g.,
+``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
+CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
+mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
+to be compiled into your build.
+
+## Diving into the above example:
+
+Let's take a look at how the devicetree language corresponds to the generated
+ASL.
+
+First, note this:
+
+```
+    chip drivers/i2c/generic
+```
+
+This means that the device driver we're using has a corresponding structure,
+located at ``src/drivers/i2c/generic/chip.h``, named **struct
+drivers_i2c_generic_config** and it contains many properties you can specify to
+be included in the ACPI table.
+
+### hid
+
+```
+    register "hid" = ""ELAN0000""
+```
+
+This corresponds to **const char *hid** in the struct.  In the ACPI ASL, it
+translates to:
+
+```
+    Name (_HID, "ELAN0000") // _HID: Hardware ID
+```
+
+under the device.  **This property is used to match the device to its driver
+during enumeration in the OS.**
+
+### desc
+
+```
+    register "desc" = ""ELAN Touchpad""
+```
+
+corresponds to **const char *desc** and in ASL:
+
+```
+    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
+```
+
+### irq
+
+It also adds the interrupt,
+
+```
+    Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+    {
+        0x0000002D,
+    }
+```
+
+which comes from:
+
+```
+    register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+```
+
+The GPIO pin IRQ settings control the "Level", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (level means it is a level-triggered
+interrupt as opposed to edge-triggered; active low means the interrupt is
+triggered when the signal is low).
+
+Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
+will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
+source.  Also note that the IRQ names are SoC-specific, and you will need to
+find the names in your SoC's header file.  The ACPI_* macros are defined in
+``src/arch/x86/include/acpi/acpi_device.h``.
+
+Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
+This is often done in a mainboard-specific file named ``gpio.c``.
+
+### wake
+
+The last register is:
+
+```
+    register "wake" = "GPE0_DW0_21"
+```
+
+which indicates that the method of waking the system using the touchpad will be
+through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
+this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
+elsewhere in the devicetree.
+
+The last bit of the definition of that device includes:
+
+```
+    device i2c 15 on end
+```
+
+which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
+meaning it will be exposed in the ACPI table.  The PCI device that the
+controller is located in determines which I2C bus the device is expected to be
+found on.  In this example, this is I2C bus 0.  This also determines the ACPI
+"Scope" that the device names and methods will live under, in this case
+"\_SB.PCI0.I2C0".
+
+## Other auto-generated names
+
+(see [ACPI specification
+6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
+for more details on ACPI methods)
+
+### _S0W (S0 Device Wake State)
+_S0W indicates the deepest S0 sleep state this device can wake itself from,
+which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
+
+### _PRW (Power Resources for Wake)
+_PRW indicates the power resources and events required for wake.  There are no
+dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
+as well as the deepest sleep state supporting waking the system (3), which is
+S3.
+
+### _STA (Status)
+The _STA method is generated automatically, and its values, 0xF, indicates the
+following:
+
+    Bit [0] – Set if the device is present.
+    Bit [1] – Set if the device is enabled and decoding its resources.
+    Bit [2] – Set if the device should be shown in the UI.
+    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
+
+### _CRS (Current resource settings)
+The _CRS method is generated automatically, as the driver knows it is an I2C
+controller, and so specifies how to configure the controller for proper
+operation with the touchpad.
+
+```
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                    0x00, ResourceConsumer, , Exclusive, )
+```
+
+## Notes
+
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/acpi/index.md

@@ -10,3 +10,7 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
+
+## devicetree
+
+- [Adding devices to a device tree](devicetree.md)

Documentation/community/forums.md

@@ -31,7 +31,7 @@ topics, including community and technical matters that benefit from
 an official decision.
 
 We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
+best with [Google Meet](https://meet.google.com/syn-toap-agu),
 using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
 for the agenda and meeting minutes. Neither the video conference nor
 the document require a Google account to participate, although editing

Documentation/contributing/coding_style.md

@@ -3,7 +3,7 @@
 This document describes the preferred C coding style for the
 coreboot project. It is in many ways exactly the same as the Linux
 kernel coding style. In fact, most of this document has been copied from
-the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/plain/Documentation/process/4.Coding.rst)
+the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD)
 
 The guidelines in this file should be seen as a strong suggestion, and
 should overrule personal preference. But they may be ignored in
@@ -66,7 +66,7 @@ case 'm':
 case 'K':
 case 'k':
 	mem <<= 10;
-	__fallthrough;
+	/* fall through */
 default:
 	break;
 }
@@ -818,9 +818,9 @@ Function return values and names
 
 Functions can return values of many different kinds, and one of the most
 common is a value indicating whether the function succeeded or failed.
-Such a value can be represented as an error-code integer (`CB_ERR_xxx`
-(negative number) = failure, `CB_SUCCESS` (0) = success) or a "succeeded"
-boolean (0 = failure, non-zero = success).
+Such a value can be represented as an error-code integer (-Exxx =
+failure, 0 = success) or a "succeeded" boolean (0 = failure, non-zero
+= success).
 
 Mixing up these two sorts of representations is a fertile source of
 difficult-to-find bugs. If the C language included a strong distinction
@@ -832,84 +832,21 @@ If the name of a function is an action or an imperative command,
 the function should return an error-code integer.  If the name
 is a predicate, the function should return a "succeeded" boolean.
 
-For example, "add work" is a command, and the `add_work()` function
-returns 0 for success or `CB_ERR` for failure. In the same way, "PCI
-device present" is a predicate, and the `pci_dev_present()` function
+For example, "add work" is a command, and the add_work() function
+returns 0 for success or -EBUSY for failure. In the same way, "PCI
+device present" is a predicate, and the pci_dev_present() function
 returns 1 if it succeeds in finding a matching device or 0 if it
 doesn't.
 
+All EXPORTed functions must respect this convention, and so should all
+public functions. Private (static) functions need not, but it is
+recommended that they do.
+
 Functions whose return value is the actual result of a computation,
 rather than an indication of whether the computation succeeded, are not
 subject to this rule. Generally they indicate failure by returning some
 out-of-range result. Typical examples would be functions that return
-pointers; they use NULL to report failure.
-
-Error handling, assertions and die()
------------------------------
-
-As firmware, coreboot has no means to let the user interactively fix things when
-something goes wrong. We either succeed to boot or the device becomes a brick
-that must be recovered through complicated external means (e.g. a flash
-programmer). Therefore, coreboot code should strive to continue booting
-wherever possible.
-
-In most cases, errors should be handled by logging a message of at least
-`BIOS_ERR` level, returning out of the function stack for the failed feature,
-and then continuing execution. For example, if a function reading the EDID of an
-eDP display panel encounters an I2C error, it should print a "cannot read EDID"
-message and return an error code. The calling display initialization function
-knows that without the EDID there is no way to initialize the display correctly,
-so it will also immediately return with an error code without running its
-remaining code that would initialize the SoC's display controller. Exeuction
-returns further up the function stack to the mainboard initialization code
-which continues booting despite the failed display initialization, since
-display functionality is non-essential to the system. (Code is encouraged but
-not required to use `enum cb_err` error codes to return these errors.)
-
-coreboot also has the `die()` function that completely halts execution. `die()`
-should only be used as a last resort, since it results in the worst user
-experience (bricked system). It is generally preferrable to continue executing
-even after a problem was encountered that might be fatal (e.g. SPI clock
-couldn't be configured correctly), because a slight chance of successfully
-booting is still better than not booting at all. The only cases where `die()`
-should be used are:
-
-1. There is no (simple) way to continue executing. For example, when loading the
-   next stage from SPI flash fails, we don't have any more code to execute. When
-   memory initialization fails, we have no space to load the ramstage into.
-
-2. Continuing execution would pose a security risk. All security features in
-   coreboot are optional, but when they are configured in the user must be able
-   to rely on them. For example, if CBFS verification is enabled and the file
-   hash when loading the romstage doesn't match what it should be, it is better
-   to stop execution than to jump to potentially malicious code.
-
-In addition to normal error logging with `printk()`, coreboot also offers the
-`assert()` macro. `assert()` should be used judiciously to confirm that
-conditions are true which the programmer _knows_ to be true, in order to catch
-programming errors and incorrect assumptions. It is therefore different from a
-normal `if ()`-check that is used to actually test for things which may turn
-out to be true or false based on external conditions. For example, anything
-that involves communicating with hardware, such as whether an attempt to read
-from SPI flash succeeded, should _not_ use `assert()` and should instead just
-be checked with a normal `if ()` and subsequent manual error handling. Hardware
-can always fail for various reasons and the programmer can never 100% assume in
-advance that it will work as expected. On the other hand, if a function takes a
-pointer parameter `ctx` and the contract for that function (as documented in a
-comment above its declaration) specifies that this parameter should point to a
-valid context structure, then adding an `assert(ctx)` line to that function may
-be a good idea. The programmer knows that this function should never be called
-with a NULL pointer (because that's how it is specified), and if it was actually
-called with a NULL pointer that would indicate a programming error on account of
-the caller.
-
-`assert()` can be configured to either just print an error message and continue
-execution (default), or call `die()` (when `CONFIG_FATAL_ASSERTS` is set).
-Developers are encouraged to always test their code with this option enabled to
-make assertion errors (and therefore bugs) more easy to notice. Since assertions
-thus do not always stop execution, they should never be relied upon to be the
-sole guard against conditions that really _need_ to stop execution (e.g.
-security guarantees should never be enforced only by `assert()`).
+pointers; they use NULL or the ERR_PTR mechanism to report failure.
 
 Headers and includes
 ---------------
@@ -1065,7 +1002,7 @@ The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
 <https://duckduckgo.com/?q=isbn+0-13-110362-8> or
-<https://www.google.com/search?q=isbn+0-13-110362-8>
+<https://www.google.com/search?q=isbn+0-13-110362-8.
 
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.

Documentation/contributing/gerrit_guidelines.md

@@ -53,10 +53,7 @@ it's implemented, should restart the wait period.
 a recently-introduced issue (build, boot or OS-level compatibility, not
 necessarily identified by coreboot.org facilities). Its commit message
 has to explain what change introduced the problem and the nature of
-the problem so that the emergency need becomes apparent. Avoid stating
-something like "fix build error" in the commit summary, describe what
-the commit does instead, just like any other commit. In addition, it is
-recommended to reference the commit that introduced the issue. The change
+the problem so that the emergency need becomes apparent. The change
 itself should be as limited in scope and impact as possible to make it
 simple to assess the impact. Such a change can be merged early with 3
 Code-Review+2. For emergency fixes that affect a single project (SoC,

Documentation/contributing/project_ideas.md

@@ -87,7 +87,7 @@ across architectures.
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
+to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
 yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a

Documentation/coreboot_logo.svg

@@ -1,40 +0,0 @@
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-     style="stroke-width:1.89259;fill:#ffffff" />
-</svg>

Documentation/distributions.md

@@ -8,15 +8,6 @@ and those providing after-market firmware to extend the usefulness of devices.
 
 ## Hardware shipping with coreboot
 
-### NovaCustom laptops
-
-[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
-[Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
-[3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
-Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
-and the firmware is equipped with important security features such as measured
-boot, verified boot, TPM integration and UEFI Secure Boot.
-
 ### ChromeOS Devices
 
 All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
@@ -37,15 +28,15 @@ firmware binaries on [GitHub](https://pcengines.github.io).
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
 built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
+use Tianocore as the payload and include an NVRAM option to disable the
+Intel Management Engine.
 
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and
 servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
+distribution of coreboot, EDK2, and System76 firmware applications.
 
 ### Purism
 
@@ -63,20 +54,11 @@ provides ready-made firmware images for supported devices: those which can be
 built entirely from source code. Their copy of the coreboot repository is
 therefore stripped of all devices that require binary components to boot.
 
-
-### Dasharo
-
-[Dasharo](https://dasharo.com/) is an open-source based firmware distribution
-focusing on clean and simple code, long-term maintenance, transparent
-validation, privacy-respecting implementation, liberty for the owners, and
-trustworthiness for all.
-
-
 ### MrChromebox
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

Documentation/doxygen/Doxyfile.coreboot_platform

@@ -0,0 +1,319 @@
+# Doxyfile 1.8.11
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING      = UTF-8
+PROJECT_NAME           = "coreboot for $(DOXYGEN_PLATFORM)"
+PROJECT_NUMBER         =
+PROJECT_BRIEF          = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
+PROJECT_LOGO           = Documentation/coreboot_logo.png
+OUTPUT_DIRECTORY       = $(DOXYGEN_OUTPUT_DIR)
+CREATE_SUBDIRS         = YES
+ALLOW_UNICODE_NAMES    = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       =
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = YES
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+QT_AUTOBRIEF           = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                =
+TCL_SUBST              =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+OPTIMIZE_FOR_FORTRAN   = NO
+OPTIMIZE_OUTPUT_VHDL   = NO
+EXTENSION_MAPPING      =
+MARKDOWN_SUPPORT       = YES
+AUTOLINK_SUPPORT       = YES
+BUILTIN_STL_SUPPORT    = NO
+CPP_CLI_SUPPORT        = NO
+SIP_SUPPORT            = NO
+IDL_PROPERTY_SUPPORT   = YES
+DISTRIBUTE_GROUP_DOC   = NO
+GROUP_NESTED_COMPOUNDS = NO
+SUBGROUPING            = YES
+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS  = NO
+TYPEDEF_HIDES_STRUCT   = NO
+LOOKUP_CACHE_SIZE      = 0
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = NO
+EXTRACT_PACKAGE        = NO
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+EXTRACT_ANON_NSPACES   = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = YES
+HIDE_SCOPE_NAMES       = NO
+HIDE_COMPOUND_REFERENCE= NO
+SHOW_INCLUDE_FILES     = YES
+SHOW_GROUPED_MEMB_INC  = NO
+FORCE_LOCAL_INCLUDES   = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES       = NO
+SORT_BY_SCOPE_NAME     = NO
+STRICT_PROTO_MATCHING  = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_FILES             = YES
+SHOW_NAMESPACES        = YES
+FILE_VERSION_FILTER    =
+LAYOUT_FILE            =
+CITE_BIB_FILES         =
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_AS_ERROR          = NO
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           =
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = $(DOXYFILES)
+INPUT_ENCODING         = UTF-8
+FILE_PATTERNS          =
+RECURSIVE              = NO
+EXCLUDE                =
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXCLUDE_SYMBOLS        =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       =
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+FILTER_SOURCE_PATTERNS =
+USE_MDFILE_AS_MAINPAGE =
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = NO
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+REFERENCES_LINK_SOURCE = YES
+SOURCE_TOOLTIPS        = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = YES
+CLANG_ASSISTED_PARSING = NO
+CLANG_OPTIONS          =
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = YES
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_EXTRA_STYLESHEET  =
+HTML_EXTRA_FILES       =
+HTML_COLORSTYLE_HUE    = 220
+HTML_COLORSTYLE_SAT    = 100
+HTML_COLORSTYLE_GAMMA  = 80
+HTML_TIMESTAMP         = NO
+HTML_DYNAMIC_SECTIONS  = NO
+HTML_INDEX_NUM_ENTRIES = 100
+GENERATE_DOCSET        = NO
+DOCSET_FEEDNAME        = "Doxygen documentation"
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+DOCSET_PUBLISHER_NAME  = Publisher
+GENERATE_HTMLHELP      = NO
+CHM_FILE               =
+HHC_LOCATION           =
+GENERATE_CHI           = NO
+CHM_INDEX_ENCODING     =
+BINARY_TOC             = NO
+TOC_EXPAND             = NO
+GENERATE_QHP           = NO
+QCH_FILE               =
+QHP_NAMESPACE          = org.doxygen.Project
+QHP_VIRTUAL_FOLDER     = doc
+QHP_CUST_FILTER_NAME   =
+QHP_CUST_FILTER_ATTRS  =
+QHP_SECT_FILTER_ATTRS  =
+QHG_LOCATION           =
+GENERATE_ECLIPSEHELP   = NO
+ECLIPSE_DOC_ID         = org.doxygen.Project
+DISABLE_INDEX          = NO
+GENERATE_TREEVIEW      = YES
+ENUM_VALUES_PER_LINE   = 4
+TREEVIEW_WIDTH         = 250
+EXT_LINKS_IN_WINDOW    = NO
+FORMULA_FONTSIZE       = 10
+FORMULA_TRANSPARENT    = YES
+USE_MATHJAX            = NO
+MATHJAX_FORMAT         = HTML-CSS
+MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
+MATHJAX_EXTENSIONS     =
+MATHJAX_CODEFILE       =
+SEARCHENGINE           = YES
+SERVER_BASED_SEARCH    = NO
+EXTERNAL_SEARCH        = NO
+SEARCHENGINE_URL       =
+SEARCHDATA_FILE        = searchdata.xml
+EXTERNAL_SEARCH_ID     =
+EXTRA_SEARCH_MAPPINGS  =
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4wide
+EXTRA_PACKAGES         =
+LATEX_HEADER           =
+LATEX_FOOTER           =
+LATEX_EXTRA_STYLESHEET =
+LATEX_EXTRA_FILES      =
+PDF_HYPERLINKS         = NO
+USE_PDFLATEX           = NO
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+LATEX_SOURCE_CODE      = NO
+LATEX_BIB_STYLE        = plain
+LATEX_TIMESTAMP        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    =
+RTF_EXTENSIONS_FILE    =
+RTF_SOURCE_CODE        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_SUBDIR             =
+MAN_LINKS              = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_PROGRAMLISTING     = YES
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+GENERATE_DOCBOOK       = NO
+DOCBOOK_OUTPUT         = docbook
+DOCBOOK_PROGRAMLISTING = NO
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = YES
+EXPAND_ONLY_PREDEF     = YES
+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           =
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             = __attribute__(x)=
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+EXTERNAL_PAGES         = YES
+PERL_PATH              = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = YES
+MSCGEN_PATH            =
+DIA_PATH               =
+HIDE_UNDOC_RELATIONS   = NO
+HAVE_DOT               = NO
+DOT_NUM_THREADS        = 0
+DOT_FONTNAME           = Helvetica
+DOT_FONTSIZE           = 10
+DOT_FONTPATH           =
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = YES
+UML_LIMIT_NUM_FIELDS   = 10
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = YES
+CALLER_GRAPH           = YES
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+INTERACTIVE_SVG        = NO
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DIAFILE_DIRS           =
+PLANTUML_JAR_PATH      =
+PLANTUML_INCLUDE_PATH  =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = YES
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES

Documentation/drivers/cbfs_smbios.md

@@ -1,143 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS Serial Number
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information and type 2 Baseboard Information called Serial Number. It
-is a null-terminated string field assumed to be unique per platform. Certain
-mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
-data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
-provide an option to populate the Serial Numbers from CBFS for boards that
-can't generate the it from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `Serial number in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the serial number:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
-```
-
-Where `serial_file.txt` is the unterminated string representation of the SMBIOS
-type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
-partitions you will have to specify the RW regions where the file is going to
-be added too. By default the RW CBFS partitions are truncated, so the files
-would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the Serial Number from running system (if it exists) using one
-of the following commands:
-
-```shell
-# Type 1
-echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
-# OR Type 2
-echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
-```
-
-Ensure the file does not end with whitespaces like LF and/or CR. The above
-commands will not add any whitespaces. The driver automatically terminates the
-Serial Number with the NULL character. If the CBFS file is not present, the
-driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
-option.
-
-Please note that this driver provides `smbios_mainboard_serial_number` hook
-overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
-build option. If you wish to populate only type 2 Serial Number field your
-board code needs to implement `smbios_system_serial_number`, otherwise the weak
-implementation of `smbios_system_serial_number` will call
-`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
-implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
-has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
-if the board does not implement its own `smbios_system_serial_number`.
-
-There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
-populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
-implementation (returns empty string). If you wish to populate type 3 Serial
-Number, your board code should override the default
-`smbios_chassis_serial_number` weak implementation.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt

Documentation/drivers/dptf.md

@@ -43,7 +43,7 @@ This policy monitors the temperature of participants and controls fans to spin
 at varying speeds. These speeds are defined by the platform, and will be enabled
 depending on the various temperatures reported by participants.
 
-## Note about units
+# Note about units
 
 ACPI uses unusual units for specifying various physical measurements. For
 example, temperatures are specified in 10ths of a degree K, and time is measured
@@ -69,7 +69,7 @@ data was a 0). The following Methods were removed:
 2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
    specified in the devicetree entries or by calling the DPTF acpigen API).
 
-## ACPI Tables
+# ACPI Tables
 
 DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
 application. We will discuss the more important ones here.
@@ -108,7 +108,7 @@ various informational properties.
 This table describes performance states supported by a participant (typically
 the battery charger).
 
-## ACPI Methods
+# ACPI Methods
 
 The Active and Passive policies also provide for short Methods to define
 different kinds of temperature thresholds.
@@ -141,7 +141,7 @@ a "graceful shutdown".
 
 These are optional, and are enabled by selecting the Critical Policy.
 
-## How to use the devicetree entries
+# How to use the devicetree entries
 
 The `drivers/intel/dptf` chip driver is organized into several sections:
 - Policies
@@ -151,7 +151,7 @@ The `drivers/intel/dptf` chip driver is organized into several sections:
 The Policies section (`policies.active`, `policies.passive`, and
 `policies.critical`) is where the components of each policy are defined.
 
-### Active Policy
+## Active Policy
 
 Each Active Policy is defined in terms of 4 parts:
 1) A Source (this is implicitly defined as TFN1, the system fan)
@@ -182,7 +182,7 @@ the CPU's active cooling capability). When the CPU temperature first crosses
 rest of the table (note that it *must* be defined from highest temperature/
 percentage on down to the lowest).
 
-### Passive Policy
+## Passive Policy
 
 Each Passive Policy is defined in terms of 5 parts:
 1) Source - The device that can be throttled
@@ -201,7 +201,7 @@ This example sets up a policy to begin throttling the charger performance when
 temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
 The Priority is defaulted to 100 in this case.
 
-### Critical Policy
+## Critical Policy
 
 Each Critical Policy is defined in terms of 3 parts:
 1) Source - A device that can trigger a critical event
@@ -218,7 +218,7 @@ register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
 This example sets up a policy wherein ACPI will cause the system to shutdown
 (in a "graceful" manner) when the CPU temperature reaches 75C.
 
-### Power Limits
+## Power Limits
 
 Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
 that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
@@ -244,7 +244,7 @@ This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
 over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
 increments of 200 mW.
 
-### Charger Performance
+## Charger Performance
 
 The battery charger can be a large contributor of unwanted heat in a system that
 has one. Controlling the rate of charging is another tool that DPTF uses to enact
@@ -266,7 +266,7 @@ register "controls.charger_perf[3]" = "{   8,  500 }"
 In this example, when DPTF decides to throttle the charger, it has four different
 performance states to choose from.
 
-### Fan Performance
+## Fan Performance
 
 When using DPTF, the system fan (`TFN1`) is the device responsible for actively
 cooling the other temperature sensors on the mainboard. A fan speed table can be
@@ -298,21 +298,21 @@ increment of 10 percentage points. This is common when specifying fine-grained
 control of the fan, wherein DPTF will interpolate between the percentages in the
 table for a given temperature threshold.
 
-### Options
+## Options
 
-#### Fan
+### Fan
 1) Fine-grained control - a boolean (see Fan Performance section above)
 2) Step-size - Recommended minimum step size (in percentage points) to adjust
    the fan speed when using fine-grained control (ranges from 1 - 9).
 3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
    fan device if a low fan speed is detected.
 
-#### Temperature sensors
+### Temperature sensors
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
 
-### OEM Variables
+## OEM Variables
 Platform vendors can define an array of OEM-specific values as OEM variables
 to be used under DPTF policy. There are total six OEM variables available.
 These can be used in AP policy for more specific actions. These OEM variables

Documentation/drivers/dt_entries.md

@@ -1,309 +0,0 @@
-# Driver Devicetree Entries
-
-Let's take a look at an example entry from
-``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
-
-```
-device pci 15.0 on
-	chip drivers/i2c/generic
-		register "hid" = ""ELAN0000""
-		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
-		register "wake" = "GPE0_DW0_21"
-		device i2c 15 on end
-	end
-end # I2C #0
-```
-
-When this entry is processed during ramstage, it will create a device in the
-ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
-generation routines in coreboot actually generate the raw bytecode that
-represents the device's structure, but looking at ASL code is easier to
-understand; see below for what the disassembled bytecode looks like:
-
-```
-Scope (\_SB.PCI0.I2C0)
-{
-    Device (D015)
-    {
-        Name (_HID, "ELAN0000")  // _HID: Hardware ID
-        Name (_UID, Zero)  // _UID: Unique ID
-        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
-        Method (_STA, 0, NotSerialized)  // _STA: Status
-        {
-            Return (0x0F)
-        }
-        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-        {
-            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-            {
-                0x0000002D,
-            }
-        })
-        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
-        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
-        {
-            0x15, // GPE #21
-            0x03  // Sleep state S3
-        })
-    }
-}
-```
-
-You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
-names/methods in the Device's scope.
-
-## Utilizing a device driver
-
-The device driver must be enabled for your build.  There will be a CONFIG option
-in the Kconfig file in the directory that the driver is in (e.g.,
-``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
-CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
-mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
-to be compiled into your build.
-
-## Diving into the above example:
-
-Let's take a look at how the devicetree language corresponds to the generated
-ASL.
-
-First, note this:
-
-```
-    chip drivers/i2c/generic
-```
-
-This means that the device driver we're using has a corresponding structure,
-located at ``src/drivers/i2c/generic/chip.h``, named **struct
-drivers_i2c_generic_config** and it contains many properties you can specify to
-be included in the ACPI table.
-
-### hid
-
-```
-    register "hid" = ""ELAN0000""
-```
-
-This corresponds to **const char \*hid** in the struct.  In the ACPI ASL, it
-translates to:
-
-```
-    Name (_HID, "ELAN0000") // _HID: Hardware ID
-```
-
-under the device.  **This property is used to match the device to its driver
-during enumeration in the OS.**
-
-### desc
-
-```
-    register "desc" = ""ELAN Touchpad""
-```
-
-corresponds to **const char \*desc** and in ASL:
-
-```
-    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
-```
-
-### irq
-
-It also adds the interrupt,
-
-```
-    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-    {
-        0x0000002D,
-    }
-```
-
-which comes from:
-
-```
-    register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-```
-
-The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
-means it is a level-triggered interrupt as opposed to
-edge-triggered; active low means the interrupt is triggered when the signal is
-low).
-
-Also note that the IRQ names are SoC-specific, and you will need to
-find the names in your SoC's header file.  The ACPI_* macros are defined in
-``src/arch/x86/include/acpi/acpi_device.h``.
-
-Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
-This is often done in a mainboard-specific file named ``gpio.c``.
-
-AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
-GPIO controller needs to be used directly. You can do this by setting the
-`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
-
-i.e.,
-```
-register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
-```
-
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
-mainboards in the tree to implement this are google/skyrim and google/guybrush.
-This feature has also been used in downstream forks without issue for some time
-now on several other boards.
-
-### wake
-
-The last register is:
-
-```
-    register "wake" = "GPE0_DW0_21"
-```
-
-which indicates that the method of waking the system using the touchpad will be
-through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
-this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
-elsewhere in the devicetree.
-
-### device
-
-The last bit of the definition of that device includes:
-
-```
-    device i2c 15 on end
-```
-
-which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
-meaning it will be exposed in the ACPI table.  The PCI device that the
-controller is located in determines which I2C bus the device is expected to be
-found on.  In this example, this is I2C bus 0.  This also determines the ACPI
-"Scope" that the device names and methods will live under, in this case
-"\_SB.PCI0.I2C0".
-
-## Wake sources
-
-The ACPI spec defines two methods to describe how a device can wake the system.
-Only one of these methods should be used, otherwise duplicate wake events will
-be generated.
-
-### Using GPEs as a wake source
-
-The `wake` property specified above is used to tell the ACPI subsystem that the
-device can use a GPE to wake the system. The OS can control whether to enable
-or disable the wake source by unmasking/masking off the GPE.
-
-The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
-generally done by a mainboard specific `gpio.c` file that defines the GPIO
-using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
-`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
-file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
-`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
-GPEs (the rest are available as `tier-2` GPEs).
-
-Windows has a large caveat when using this method. If you use the `gpio_irq`
-property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
-to define a `GPE`, Windows will
-[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
-complaining about an invalid ACPI configuration.
-> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
-
-In order to avoid this error, you should use the `irq` property instead. AMD
-platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
-feasible. The other option is to use a wake capable GPIO as described below.
-
-### Using GPIO interrupts as a wake source
-
-The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
-`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
-`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
-
-This method has a few caveats:
-* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
-  the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
-  system. Instead you need to use the `gpio_irq` property, or a `GPE` as
-  described above.
-* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
-  means the platform specific GPIO controller driver must implement the
-  `irq_set_wake` callback. For AMD systems this wasn't
-  [implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
-  until linux v5.15. If the controller doesn't define this callback, it's
-  possible for the firmware to manually set the `wake` bit on the GPIO. This is
-  often done in a mainboard-specific file named `gpio.c`. This is not
-  recommended because then it's not possible for the OS to disable the wake
-  source.
-* As of
-  [linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
-  the ACPI subsystem doesn't take the interrupt `wake` bit into account when
-  deciding on which power state to put the device in before suspending the
-  system. This means that if you define a power resource for a device via
-  `has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
-  device into D3Cold. i.e., power off the device.
-
-## Other auto-generated names
-
-(see [ACPI specification
-6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
-for more details on ACPI methods)
-
-### _S0W (S0 Device Wake State)
-\_S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
-D3Hot means the `PR3` power resources are still on and the device is still
-responsive on the bus. For i2c devices this is generally the same state as `D0`.
-
-### \_PRW (Power Resources for Wake)
-\_PRW indicates the power resources and events required for wake.  There are no
-dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
-as well as the deepest sleep state supporting waking the system (3), which is
-S3.
-
-### \_STA (Status)
-The \_STA method is generated automatically, and its values, 0xF, indicates the
-following:
-
-    Bit [0] – Set if the device is present.
-    Bit [1] – Set if the device is enabled and decoding its resources.
-    Bit [2] – Set if the device should be shown in the UI.
-    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
-
-### \_CRS (Current resource settings)
-The \_CRS method is generated automatically, as the driver knows it is an I2C
-controller, and so specifies how to configure the controller for proper
-operation with the touchpad.
-
-```
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                    0x00, ResourceConsumer, , Exclusive, )
-```
-
-## Notes
-
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)

Documentation/drivers/index.md

@@ -4,14 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code across platforms.
 
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
-
 * [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
 * [SoundWire](soundwire.md)
+* [SMMSTOREv2](smmstorev2.md)
 * [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)

Documentation/drivers/ipmi_kcs.md

@@ -42,15 +42,6 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/retimer.md

@@ -1,6 +1,6 @@
 # USB4 Retimers
 
-## Introduction
+# Introduction
 As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
 newer revisions of the spec), it becomes more difficult to maintain signal
 integrity for longer traces. Devices such as retimers and redrivers can be used
@@ -17,7 +17,7 @@ by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
 this is a digital component, it may have firmware.
 
 
-## Driver Usage
+# Driver Usage
 
 Some operating systems may have the ability to update firmware on USB4 retimers,
 and ultimately will need some way to power the device on and off so that its new

Documentation/drivers/smmstorev2.md

@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
+EDK2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

Documentation/external_docs.md

@@ -1,114 +0,0 @@
-# External Resources
-
-This is a list of resources that could be useful to coreboot developers.
-These are not endorsed or officially recommended by the coreboot project,
-but simply listed here in the hopes that someone will find something
-useful.
-
-Please add any helpful or informational links and sections as you see fit.
-
-## Articles
-
-* External Interrupts in the x86 system.
-  * [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
-  * [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
-  * [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
-* System address map initialization in x86/x64 architecture.
-  * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
-  * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
-  * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
-* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
-
-
-## General Information
-
-* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
-* [Interface BUS](http://www.interfacebus.com/)
-* Open course material for a variety of topics such as assembly, firmware,
-  security, debugging, and more.
-  * [Open Security Training](https://opensecuritytraining.info/Training.html),
-  * [Open Security Training 2](https://p.ost2.fyi/)
-
-
-## Firmware Specifications & Information
-
-* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
-* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
-* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
-
-
-### ACPI
-
-* [ACPI Specs](https://uefi.org/acpi/specs)
-* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
-* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
-* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
-
-
-### Security
-
-* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
-
-
-## Hardware information
-
-* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
-* [Sandpile](https://www.sandpile.org/)
-* [CPU-World](https://www.cpu-world.com/index.html)
-* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
-
-
-### Hardware Specifications & Standards
-
-* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
-* [eMMC](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
-* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
-  [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
-* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
-* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
-* [Memory](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
-* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
-* [PCI / PCIe / M.2](https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED)
-* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
-* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
-* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
-* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
-* [USB](https://www.usb.org/documents) - USB Implementers Forum
-* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
-
-
-### Chip Vendor Documentation
-
-* AMD
-  * [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
-  * [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
-* ARM
-  * [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
-* Intel
-  * [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
-  * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
-  * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
-  * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
-
-* Rockchip
-  * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
-
-
-## Software
-
- * [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
- * [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
- * [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
- * [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
- * [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
- * [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
-* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
-* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
-
-
-## Infrastructure software
-
-* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
-* [GNU Make](https://www.gnu.org/software/make/manual/)

Documentation/getting_started/architecture.md

@@ -3,7 +3,7 @@
 ## Overview
 ![][architecture]
 
-[architecture]: comparison_coreboot_uefi.svg
+[architecture]: comparision_coreboot_uefi.svg
 
 ## Stages
 coreboot consists of multiple stages that are compiled as separate binaries and

Documentation/getting_started/devicetree.md

@@ -1,87 +0,0 @@
-# Adding new devices to a device tree
-
-## Introduction
-
-ACPI exposes a platform-independent interface for operating systems to perform
-power management and other platform-level functions.  Some operating systems
-also use ACPI to enumerate devices that are not immediately discoverable, such
-as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
-the way that coreboot uses the concept of a "device tree" to generate ACPI
-tables for usage by the operating system.
-
-## Devicetree and overridetree (if applicable)
-
-For mainboards that are organized around a "reference board" or "baseboard"
-model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
-typically a devicetree.cb file that all boards share, and any differences for a
-specific board ("variant") are captured in the overridetree.cb file.  Any
-settings changed in the overridetree take precedence over those in the main
-devicetree.  Note, not all mainboards will have the devicetree/overridetree
-distinction, and may only have a devicetree.cb file.  Or you can always just
-write the ASL (ACPI Source Language) code yourself.
-
-### Naming and referencing devices
-
-When declaring a device, it can optionally be given an alias that can be
-referred to elsewhere. This is particularly useful to declare a device in one
-device tree while allowing its configuration to be more easily changed in an
-overlay. For instance, the AMD Picasso SoC definition
-(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
-by default:
-
-```
-chip soc/amd/picasso
-	device domain 0 on
-		...
-		device pci 00.2 alias iommu off end
-		...
-	end
-end
-```
-
-A device based on this SoC can override the configuration for the IOMMU without
-duplicating addresses, as in
-`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
-
-```
-chip soc/amd/picasso
-	device domain 0
-		...
-		device ref iommu on end
-		...
-	end
-end
-```
-
-In this example the override simply enables the IOMMU, but it could also
-set additional properties (or even add child devices) inside the IOMMU `device`
-block.
-
----
-
-It is important to note that devices that use `device ref` syntax to override
-previous definitions of a device by alias must be placed at **exactly the same
-location in the device tree** as the original declaration. If not, this will
-actually create another device rather than overriding the properties of the
-existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
-were written as follows:
-
-```
-chip soc/amd/picasso
-	# NOTE: not inside domain 0!
-	device ref iommu on end
-end
-```
-
-Then this would leave the SoC's IOMMU disabled, and instead create a new device
-with no properties as a direct child of the SoC.
-
-## Device drivers
-
-Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
-
-## Notes
-
- - **All fields that are left unspecified in the devicetree are initialized to
-   zero.**

Documentation/getting_started/index.md

@@ -6,4 +6,3 @@
 * [Kconfig](kconfig.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
-* [Adding devices to a device tree](devicetree.md)

Documentation/ifdtool/layout.md

@@ -2,7 +2,7 @@
 
 A coreboot image for an Intel SoC contains two separate definitions of the
 layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and
-sizes of various regions of flash and the [coreboot FMAP](../../lib/flashmap.md).
+sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md).
 
 The FMAP should define all of the of the regions defined by the IFD to ensure
 that those regions are accounted for by coreboot and will not be accidentally
@@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 +------------+------------------+-----------+-------------------------------------------+
 | 4          | Platform Data    | SI_PDR    |                                           |
 +------------+------------------+-----------+-------------------------------------------+
-| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this     |
+| 8          | EC Firmware      | SI_EC     | Most Chrome OS devices do not use this    |
 |            |                  |           | region; EC firmware is stored in BIOS     |
 |            |                  |           | region of flash                           |
 +------------+------------------+-----------+-------------------------------------------+

Documentation/index.md

@@ -5,11 +5,6 @@ It is built from Markdown files in the
 [Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
 directory in the source code.
 
-## Spelling of coreboot
-
-The correct spelling of coreboot is completely in lower case characters and in
-one word without a space between the two parts.
-
 ## Purpose of coreboot
 
 coreboot is a project to develop open source boot firmware for various
@@ -26,7 +21,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, edk2, which provides UEFI services,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 
@@ -194,8 +189,5 @@ Contents:
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
 * [Project infrastructure & services](infrastructure/index.md)
-* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
-* [Acronyms & Definitions](acronyms.md)
-* [External Resources](external_docs.md)
 * [Documentation License](documentation_license.md)

Documentation/infrastructure/builders.md

@@ -41,33 +41,25 @@ can run into "out of storage space" errors.
 #### Current Build Machines
 
 To give an idea of what a suitable build machine might be, currently the
-coreboot project has 6 active jenkins build machines.
+coreboot project has 4 active jenkins build machines.
 
 These times are taken from the week of Feb 21 - Feb 28, 2022
 
 * Congenialbuilder - 128 threads, 256GiB RAM
-  * Coverity Builds, Toolchain builds, Scanbuild-builds
-  * Fastest Passing coreboot gerrit build: 6 min, 47 sec
-  * Slowest Passing coreboot gerrit build: 14 min
+  *  Fastest Passing coreboot gerrit build: 6 min, 47 sec
+  *  Slowest Passing coreboot gerrit build: 14 min
 
-* Gleefulbuilder - 64 threads, 64GiB RAM
-  * Fastest Passing coreboot gerrit build: 10 min
-  * Slowest Passing coreboot gerrit build: 46 min
+* Gleefulbuilder - 64 thread, 64GiB RAM
+  *  Fastest Passing coreboot gerrit build: 10 min
+  *  Slowest Passing coreboot gerrit build: 46 min
 
 * Fabulousbuilder - 64 threads, 64GiB RAM
-  * Fastest Passing coreboot gerrit build: 7 min, 56 sec
-  * Slowest Passing coreboot gerrit build: 56 min (No ccache)
+  *  Fastest Passing coreboot gerrit build: 7 min, 56 sec
+  *  Slowest Passing coreboot gerrit build: 56 min (No ccache)
 
 * Ultron (9elements) - 48 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 12 min
-  * Slowest Passing coreboot gerrit build: 58 min
-
-* Bob - 64 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 7 min
-  * Slowest Passing coreboot gerrit build: 34 min
-
-* Pokeybuilder - 32 Threads, 96GiB RAM
-  * Runs coreboot-checkpatch and other lighter builds
+  *  Fastest Passing coreboot gerrit build: 12
+  *  Slowest Passing coreboot gerrit build: 58 min
 
 
 ### Jenkins Builds
@@ -77,18 +69,7 @@ for a number of different projects - coreboot, flashrom, memtest86+,
 em100, etc.  Many of these have builders for their current master branch
 as well as Gerrit and [Coverity](coverity.md) builds.
 
-
-#### Long builds - over 90 minutes on congenialbuilder
-There are a few builds that take a long time even on the fastest
-machines.  These tasks run overnight in the US timezones.
-* coreboot_coverity - 9 to 12 hours
-* coreboot_scanbuild - ~3 hours
-* coreboot_toolchain - ~1 hour 45 minutes
-
-
-#### All builds
-
-You can see all the builds in the main jenkins interface:
+You can see all the builds here:
 [https://qa.coreboot.org/](https://qa.coreboot.org/)
 
 Most of the time on the builders is taken up by the coreboot master and
@@ -110,8 +91,8 @@ hour.
 
 On a system with 32 cores, it was tested with this command:
 
-```sh
-stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
+```
+$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
 ```
 
 You can watch the temperature with the sensors package or with ‘acpi -t’
@@ -121,8 +102,8 @@ You can check for thermal throttling by running this command and seeing
 if the values go down on any of the cores after it's been running for a
 while.
 
-```sh
-while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
+```
+$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
 ```
 
 If the machine throttles or resets, you probably need to upgrade the
@@ -161,7 +142,7 @@ These instructions keep changing, so just check the latest information.
 
 As a regular user - *Not root*, run:
 
-```sh
+```
 sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
 sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
 sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
@@ -177,7 +158,7 @@ To make configuration and the later commands easier, these should go in
 your shell's .rc file.  Note that you only need to set them if you're
 using something other than the default.
 
-```sh
+```
 # Set the port used on your machine to connect to jenkins.
 export COREBOOT_JENKINS_PORT=49151
 
@@ -199,13 +180,13 @@ continuing to the next step.
 
 From the coreboot directory, run
 
-```sh
+```
 make -C util/docker help
 ```
 
 This will show you the available targets and variables needed:
 
-```text
+```
 Commands for working with docker images:
   coreboot-sdk                 - Build coreboot-sdk container
   upload-coreboot-sdk          - Upload coreboot-sdk to hub.docker.com
@@ -240,7 +221,7 @@ Variables:
 
 ### Install the coreboot jenkins builder
 
-```sh
+```
 make -C util/docker docker-jenkins-server
 ```
 
@@ -271,12 +252,11 @@ the ccache gets populated, the build time will drop.
 
 
 ### How to log in to the docker instance for debugging
-
-```sh
-make -C util/docker docker-jenkins-attach
-su coreboot
-cd ~/slave-root/workspace
-bash
+```
+    $ make -C util/docker docker-jenkins-attach
+    $ su coreboot
+    $ cd ~/slave-root/workspace
+    $ bash
 ```
 
 
@@ -293,18 +273,18 @@ then update to get a fresh installation.
 
 To delete the old containers & images:
 
-```sh
-docker stop $COREBOOT_JENKINS_CONTAINER
-docker rm $COREBOOT_JENKINS_CONTAINER
-docker images # lists all existing images
-docker rmi XXXX # Use the image ID found in the above command.
+```
+$ docker stop $COREBOOT_JENKINS_CONTAINER
+$ docker rm $COREBOOT_JENKINS_CONTAINER
+$ docker images # lists all existing images
+$ docker rmi XXXX # Use the image ID found in the above command.
 ```
 
 To get and run the new coreboot-jenkins image, change the value in the
 `DOCKER_COMMIT` variable to the new image value.
 
-```sh
-make -C util/docker docker-jenkins-server
+```
+$ make -C util/docker docker-jenkins-server
 ```
 
 #### Getting ready to push the docker images
@@ -318,15 +298,15 @@ Get an admin to add the account to the coreboot team on hub.docker.com
 Make sure your credentials are configured on your host machine by
 running
 
-```sh
-docker login
+```
+$ docker login
 ```
 
 This will prompt you for your docker username, password, and your email
 address, and write out to ~/.docker/config.json.  Without this file, you
 won’t be able to push the images.
 
-#### Updating the Dockerfiles
+#### Updating the Dockerfiles:
 
 The coreboot-sdk Dockerfile will need to be updated when any additional
 dependencies are added.  Both the coreboot-sdk and the
@@ -337,15 +317,15 @@ files are stored in the coreboot repo under coreboot/util/docker.
 Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/)
 page before updating the files.
 
-#### Rebuilding the coreboot-sdk docker image to update the toolchain
+#### Rebuilding the coreboot-sdk docker image to update the toolchain:
 
-```sh
-make -C util/docker coreboot-sdk
+```
+$ make -C util/docker coreboot-sdk
 ```
 
 This takes a relatively long time.
 
-#### Test the coreboot-sdk docker image
+#### Test the coreboot-sdk docker image:
 
 There are two methods of running the docker image - interactively as a
 shell, or doing the build directly.  Running interactively as a shell is
@@ -353,44 +333,44 @@ useful for early testing, because it allows you to update the image
 (without any changes getting saved) and re-test builds.  This saves the
 time of having to rebuild the image for every issue you find.
 
-#### Running the docker image interactively
+#### Running the docker image interactively:
 
 Run:
 
-```sh
-make -C util/docker docker-jenkins-server
-make -C util/docker docker-jenkins-attach
+```
+$ make -C util/docker docker-jenkins-server
+$ make -C util/docker docker-jenkins-attach
 ```
 
-#### Running the build directly
+#### Running the build directly:
 
 From the coreboot directory:
 
-```sh
-make -C util/docker docker-build-coreboot
+```
+$ make -C util/docker docker-build-coreboot
 ```
 
 You’ll also want to test building the other projects and payloads:
 ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo,
 nvramcui, tint...
 
-#### Pushing the coreboot-sdk image to hub.docker.com for use
+#### Pushing the coreboot-sdk image to hub.docker.com for use:
 
 When you’re satisfied with the testing, push the coreboot-sdk image to
 the hub.docker.com
 
-```sh
-make -C util/docker upload-coreboot-sdk
+```
+$ make -C util/docker upload-coreboot-sdk
 ```
 
-#### Building and pushing the coreboot-jenkins-node docker image
+#### Building and pushing the coreboot-jenkins-node docker image:
 
 This docker image is pretty simple, so there’s not really any testing
 that needs to be done.
 
-```sh
-make -C util/docker coreboot-jenkins-node
-make -C util/docker upload-coreboot-jenkins-node
+```
+$ make -C util/docker coreboot-jenkins-node
+$ make -C util/docker upload-coreboot-jenkins-node
 ```
 
 ### Coverity Setup
@@ -411,7 +391,7 @@ Rename the directory from its original name
 (cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a
 symlink:
 
-```sh
+```
 ln -s cov-analysis-linux64-7.7.0.4 coverity
 ```
 

Documentation/infrastructure/services.md

@@ -16,21 +16,6 @@ all your email addresses you intend to use in the context of coreboot
 development so that commits with your email address in them are associated with
 you properly.
 
-Below is a list of its SSH host keys and fingerprints.
-```Bash
-[review.coreboot.org]:29418 ssh-rsa AAAAB3NzaC1yc2EAAAABIwAAAQEAvNDn8qGHlWM/5ndFltStlg3QTc8xvGOgyjxxZByhMZx8LVE4cfgF38WP3euq0avyFy7gAJNghHorXpYKoOzuQPn2WNi5QhyGsUhg7ZJz9hC7Z2gqxxsZF3E7rku4Uj9sN7hWx9fBngxD4z2tP4y/18FTT5XTMcC3Q2sBCOLM0XVAO5R/nb2GO3d27avy+sanKAFEwJHnZ996IoTlU8JJFyi1Y6g30dC2K75oFgCtzntxf++wvrkkKPa+CFQub8fp20shat9WwX9kXjpRjt/Yv9LgqFCaI5ztJvWXicAmbgghGVzbzz4GoSjjF9cxxJF//KTmNb4iGQqmP3Olm27xuw==
-
-[review.coreboot.org]:29418 ecdsa-sha2-nistp256 AAAAE2VjZHNhLXNoYTItbmlzdHAyNTYAAAAIbmlzdHAyNTYAAABBBBzlwf/bFejt4EEz1QmbNOfK/HN1NtdcefrRs5Gs42uGnIvjxsff+vEF3//jCTvFPadoy3DrPsbQB3ioQAcYppk=
-
-[review.coreboot.org]:29418 ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAIOC3Z32gc+1rJXhKX+SW0vESlXR/h/mhcxd+62B1PWC2
-```
-
-```Bash
-2048 SHA256:WW5prF7YE3MTnkRIxLklr9Gxddj9s5BZKUqWJF5dnTg review.coreboot.org:29418 (RSA)
-256 SHA256:IuLv/DgrBtVn36eMP1zFD0ISAl3IxIoCeiRms6UDhZc review.coreboot.org:29418 (ECDSA)
-256 SHA256:QFZieVHy8dCRl9tDib6qiwELnfa7SVU4ZWJ5VrXoC8k review.coreboot.org:29418 (ED25519)
-```
-
 ### https push access
 When using the https URLs to git repositories, you can push with the "HTTP
 Credentials" you can have Gerrit generate for you on that page. By default,

Documentation/lib/flashmap.md

@@ -4,7 +4,7 @@
 
 [Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to
 describe partitions in a flash chip. It was added to coreboot to support the
-requirements of ChromiumOS firmware but then was also used in other scenarios
+requirements of Chromium OS firmware but then was also used in other scenarios
 where precise placement of data in flash was necessary, or for data that is
 written to at runtime, as CBFS is considered too fragile for such situations.
 The Flashmap implementation inside coreboot is the de facto standard today.

Documentation/lib/fw_config.md

@@ -8,8 +8,8 @@ BIOS image to be used across a wide variety of devices which may have key differ
 otherwise similar enough to use the same coreboot build target.
 
 The initial implementation is designed to take advantage of a bitmask returned by the Embedded
-Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
-image across multiple devices by selecting various options at runtime.  See the ChromiumOS
+Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware
+image across multiple devices by selecting various options at runtime.  See the Chromium OS
 [Firmware Config][1] documentation for more information.
 
 This firmware configuration interface differs from the CMOS option interface in that this
@@ -91,7 +91,7 @@ file in CBFS use the value it contains when matching fields and options.
 
 ### Embedded Controller
 
-Google ChromeOS devices support an Embedded Controller interface for reading and writing the
+Google Chrome OS devices support an Embedded Controller interface for reading and writing the
 firmware configuration value, along with other board-specific information.  It is possible for
 coreboot to read this value at boot on systems that support this feature.
 
@@ -101,9 +101,9 @@ possible by enabling the CBFS source and coreboot will look in CBFS first for a
 before asking the embedded controller.
 
 It is also possible to adjust the value in the embedded controller *(after disabling write
-protection)* with the `ectool` command in a ChromeOS environment.
+protection)* with the `ectool` command in a Chrome OS environment.
 
-For more information on the firmware configuration field on ChromeOS devices see the Chromium
+For more information on the firmware configuration field on Chrome OS devices see the Chromium
 documentation for [Firmware Config][1] and [Board Info][2].
 
 [1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md
@@ -383,7 +383,7 @@ training.  This example expects that the default value of this `register` is set
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
+	if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED))
 		mupd->ExampleFeature = false;
 }
 ```

Documentation/mainboard/acer/g43t-am3.md

@@ -134,7 +134,7 @@ SPI_ROM1 header while the board is off and disconnected from power. There
 seems to be a diode that prevents the external programmer from powering the
 whole board.
 
-The signal assignment on the header is identical to the pinout of the flash
+The signal assigment on the header is identical to the pinout of the flash
 chip. The pinout diagram below is valid when the PCI slots are on the left
 and the CPU is on the right. Note that HOLD# and WP# must be pulled high
 (to VCC) to be able to flash the chip.

Documentation/mainboard/amd/pademelon/pademelon.md

@@ -1,80 +0,0 @@
-# Pademelon board
-
-## Specs (with Merlin Falcon SOC)
-
-* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
-  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
-* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
-  code is specific for Merlin Falcon SOC. Some specs will change if not
-  using Merlin Falcon.
-* One half mini PCI-Express slot on back side of mainboard
-* One PCI Express® 3.0 x8 slot
-* Two SATA3 ports with 6Gb/s data transfer rate
-* Two USB 2.0 ports at rear panel
-* Two USB 3.0 ports at rear panel
-* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
-* 6-channel High-Definition audio from Realtek ALC662 codec
-* One soldered down SPI flash with dediprog header
-
-## Mainboard
-
-![mainboard][pademelon]
-
-Three items are marked in this picture
-1. dediprog header
-2. memory dimms, address 0xA0 and 0xA4
-3. SATA cables connected to motherboard
-
-## Back panel
-
-![back panel][pademelon_io]
-
-* The lower serial port is UART A (debug serial)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+--------------------+
-| Type                | Value              |
-+=====================+====================+
-| Socketed flash      | no                 |
-+---------------------+--------------------+
-| Model               | Macronix MX256435E |
-+---------------------+--------------------+
-| Size                | 8 MiB              |
-+---------------------+--------------------+
-| Flash programming   | dediprog header    |
-+---------------------+--------------------+
-| Package             | SOIC-8             |
-+---------------------+--------------------+
-| Write protection    | No                 |
-+---------------------+--------------------+
-```
-
-## Technology
-
-```eval_rst
-+---------------+------------------------------+
-| Fan control   | Using fintek F81803A         |
-+---------------+------------------------------+
-| CPU           | Merlin Falcon (see reference)|
-+---------------+------------------------------+
-```
-
-## Description of pictures within this document
-
-```eval_rst
-+----------------------------+----------------------------------------+
-|pademelon.jpg               | Motherboard with components identified |
-+----------------------------+----------------------------------------+
-|pademelon_io.jpg            | Back panel picture                     |
-+----------------------------+----------------------------------------+
-```
-
-## Reference
-
-[Merlin Falcon BKDG][merlinfalcon]
-
-[merlinfalcon]: ../../../soc/amd/family15h.md
-[pademelon]: pademelon.jpg
-[pademelon_io]: pademelon_io.jpg

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -0,0 +1,80 @@
+# Padmelon board
+
+## Specs (with Merlin Falcon SOC)
+
+* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
+  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
+* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
+  code is specific for Merlin Falcon SOC. Some specs will change if not
+  using Merlin Falcon.
+* One half mini PCI-Express slot on back side of mainboard
+* One PCI Express® 3.0 x8 slot
+* Two SATA3 ports with 6Gb/s data transfer rate
+* Two USB 2.0 ports at rear panel
+* Two USB 3.0 ports at rear panel
+* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
+* 6-channel High-Definition audio from Realtek ALC662 codec
+* One soldered down SPI flash with dediprog header
+
+## Mainboard
+
+![mainboard][padmelon]
+
+Three items are marked in this picture
+1. dediprog header
+2. memory dimms, address 0xA0 and 0xA4
+3. SATA cables connected to motherboard
+
+## Back panel
+
+![back panel][padmelon_io]
+
+* The lower serial port is UART A (debug serial)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------------------+
+| Type                | Value              |
++=====================+====================+
+| Socketed flash      | no                 |
++---------------------+--------------------+
+| Model               | Macronix MX256435E |
++---------------------+--------------------+
+| Size                | 8 MiB              |
++---------------------+--------------------+
+| Flash programming   | dediprog header    |
++---------------------+--------------------+
+| Package             | SOIC-8             |
++---------------------+--------------------+
+| Write protection    | No                 |
++---------------------+--------------------+
+```
+
+## Technology
+
+```eval_rst
++---------------+------------------------------+
+| Fan control   | Using fintek F81803A         |
++---------------+------------------------------+
+| CPU           | Merlin Falcon (see reference)|
++---------------+------------------------------+
+```
+
+## Description of pictures within this document
+
+```eval_rst
++----------------------------+----------------------------------------+
+|padmelon.jpg                | Motherboard with components identified |
++----------------------------+----------------------------------------+
+|padmelon_io.jpg             | Back panel picture                     |
++----------------------------+----------------------------------------+
+```
+
+## Reference
+
+[Merlin Falcon BKDG][merlinfalcon]
+
+[merlinfalcon]: ../../../soc/amd/family15h.md
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -37,7 +37,7 @@ easy to remove and reflash.
 
 ## Working
 
-- PS/2 keyboard with SeaBIOS & edk2 (in Mint 18.3/19.1)
+- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
 
 - Rear/front headphones connector audio & mic
 
@@ -57,7 +57,7 @@ easy to remove and reflash.
        port 3        port 5         port 1             port 8
        port 4        port 6         port 2             port 7
 
-- NVME SSD boot on PCIe-x16/x8/4x slot using edk2
+- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
   (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
 
 - CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
@@ -89,7 +89,7 @@ easy to remove and reflash.
 - If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
   as IGP's UMA could be reconfigured by the blob
 
-- Using edk2 + a PCIe GPU under Windows crashes with an
+- Using TianoCore + a PCIe GPU under Windows crashes with an
   ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
   works perfectly
 
@@ -105,9 +105,9 @@ easy to remove and reflash.
 
 ## Not working
 
-- PS/2 keyboard in Win10 using edk2 (please see [Known issues])
-- PS/2 mouse using edk2
-- PCIe graphics card on Windows and edk2 (throws critical ACPI_BIOS_ERROR)
+- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
+- PS/2 mouse using Tianocore
+- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
 
 ## Native raminit compatibility
 

Documentation/mainboard/facebook/monolith.md

@@ -104,11 +104,11 @@ solution. Wires need to be connected to be able to flash using an external progr
 - SMBus
 - Initialization with FSP
 - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
-- edk2 payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
+- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
 - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
 - eMMC
 
-All of the above has been briefly tested by booting Linux from eMMC using the edk2 payload
+All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
 and LinuxBoot.
 
 SeaBios has been checked to the extend that it runs to the boot selection and provides display

Documentation/mainboard/hp/folio_9480m.md

@@ -130,7 +130,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 - Arch Linux with Linux 5.8.9
 - Memory initialization with mrc.bin version 1.6.1 Build 2
 - Graphics initialization with libgfxinit
-- Payload: SeaBIOS, edk2
+- Payload: SeaBIOS, Tianocore
 - EC firmware
   - KBC Revision 92.15 from OEM firmware version 01.33
   - KBC Revision 92.17 from OEM firmware version 01.50

Documentation/mainboard/hp/z220_sff.md

@@ -44,17 +44,8 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.
 
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
-otherwise there's not enough space near the flash.
-
-In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
-be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
-interfere.
-
-## Side note
-The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
-that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
-even interchangeable, so should do coreboot images built for them.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
 
 ## Technology
 
@@ -75,6 +66,5 @@ even interchangeable, so should do coreboot images built for them.
 ```
 
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
-[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -11,7 +11,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [G43T-AM3](acer/g43t-am3.md)
 
 ## AMD
-- [pademelon](amd/pademelon/pademelon.md)
+- [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
@@ -30,7 +30,6 @@ This section contains documentation about coreboot on specific mainboards.
 - [P8H77-V](asus/p8h77-v.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
-- [wifigo_v1](asus/wifigo_v1.md)
 
 ## Cavium
 
@@ -85,6 +84,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
+- [IceLake RVP](intel/icelake_rvp.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
@@ -145,6 +145,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
+- [Rotundu](opencellular/rotundu.md)
 
 ## PC Engines
 
@@ -179,13 +180,10 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Star Labs Systems
 
-- [LabTop Mk III](starlabs/labtop_kbl.md)
 - [LabTop Mk IV](starlabs/labtop_cml.md)
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
-- [StarBook Mk VI](starlabs/starbook_adl.md)
-- [Flashing devices](starlabs/common/flashing.md)
 
 ## Supermicro
 
@@ -201,22 +199,16 @@ The boards in this section are not real mainboards, but emulators.
 - [Bonobo Workstation 14](system76/bonw14.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
-- [Darter Pro 8](system76/darp8.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
-- [Galago Pro 6](system76/galp6.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
-- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
-- [Lemur Pro 11](system76/lemp11.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
-- [Oryx Pro 9](system76/oryp9.md)
-- [Oryx Pro 10](system76/oryp10.md)
 
 ## Texas Instruments
 

Documentation/mainboard/intel/icelake_rvp.md

@@ -0,0 +1,40 @@
+# Intel Ice Lake RVP (Reference Validation Platform)
+
+This page describes how to run coreboot on the Intel icelake_rvp board.
+
+Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+## Building coreboot
+
+* Follow build instructions mentioned in Ice Lake document
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+* The default options for this board should result in a fully working image:
+```bash
+	# echo "CONFIG_VENDOR_INTEL=y" > .config
+	# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
+	# make olddefconfig && make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```

Documentation/mainboard/kontron/mal10.md

@@ -45,7 +45,7 @@ make
 ```
 ## Payloads
 - SeaBIOS
-- edk2
+- Tianocore
 - Linux as payload
 
 ## Flashing coreboot

Documentation/mainboard/ocp/deltalake.md

@@ -26,12 +26,12 @@ host up to 4 Delta Lake servers (blades) in one sled.
 
 The Yosemite-V3 system is in mass production. Meta, Intel and partners
 jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
-solution. The OSF solution reached production quality for some use cases
-in July, 2021.
+solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
+OSF solution reached production quality for some use cases in July, 2021.
 
 ## How to build
 
-OSF code base is publicly available at
+OSF code base is public at
 https://github.com/opencomputeproject/OpenSystemFirmware
 
 Run following commands to build Delta Lake OSF image from scratch:
@@ -42,21 +42,19 @@ The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
 Linux kernel and u-root code from their upstream repo, and sync down needed
 binary blobs. [osf-builder] also provides the top level build system.
 
-Besides coreboot, the Delta Lake OSF solution includes following components:
-- FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
-  is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
-- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
-- ME ignition binary: downloaded from
+Delta Lake server OSF solution requires following binary blobs:
+- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
+  can be downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
+- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
+  coreboot.org mirrors this repo and by default the correct binary is included.
+- ME binary: Ignition binary can be downloaded from
 	https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
 - ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
 - Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
-  U-root as initramfs, is used in the joint development. It is built
+  U-root as initramfs, is used in the joint development. It can be built
   following [All about u-root].
 
-The Delta Lake OSF solution is updated periodically to newer versions of
-upstream coreboot code base and other components.
-
-## How to verify Delta Lake OSF image
+## Flashing coreboot
 
 To do in-band FW image update, use [flashrom]:
     flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
@@ -72,21 +70,6 @@ To power off/on the host:
 To connect to console through SOL (Serial Over Lan):
     sol-util slotx
 
-## How to work on coreboot for Delta Lake
-After the OSF image for Delta Lake is built and verified, under
-OpenSystemFirmware/Wiwynn/deltalake directory:
-    cd src/osf-builder/projects/craterlake/coreboot
-
-Run "git remote -v" to confirm the origin is from coreboot upstream repo.
-
-Run "git branch -v" to know the confirmed working coreboot commit ID for the
-Delta Lake OSF solution.
-
-Fetch down the tip of coreboot upstream repo, run "make" to build a new OSF
-image for Delta Lake, verify that it works.
-
-Now you are in a familiar coreboot environment, happy coding!
-
 ## Firmware configurations
 [ChromeOS VPD] is used to store most of the firmware configurations.
 RO_VPD region holds default values, while RW_VPD region holds customized

Documentation/mainboard/opencellular/rotundu.md

@@ -0,0 +1,76 @@
+# Rutundu
+
+This page describes how to run coreboot on the [Rotundu] compute board
+from [OpenCellular].
+
+## TODO
+
+* Configure UART
+* EC interface
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25Q128    |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit.
+Directly connecting a Pomona test-clip on the flash is also possible.
+
+**Closeup view of SOIC-8 flash IC**
+
+![][rotundu_flash]
+
+[rotundu_flash]: rotundu_flash.jpg
+
+**SPI header**
+
+![][rotundu_header2]
+
+[rotundu_header2]: rotundu_header2.jpg
+
+**SPI header pinout**
+
+Dediprog compatible pinout.
+
+![][rotundu_j16]
+
+[rotundu_j16]: rotundu_j16.png
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Baytrail                                   |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Rotundu]: https://github.com/Telecominfraproject/OpenCellular
+[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/purism/librem_14.md

@@ -92,7 +92,7 @@ located underneath the Wi-Fi module, below the left cooling fan.
 
  * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
  * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), and Heads payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * M.2 storage (NVMe, SATA III)

Documentation/mainboard/purism/librem_mini.md

@@ -107,7 +107,7 @@ desoldering it from the mainboard.
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
    (no libgfxinit support yet)
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe

Documentation/mainboard/starlabs/common/building.md

@@ -1,30 +0,0 @@
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-
-#### StarBook series:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-#### StarLite series:
-* Intel Flash Descriptor file (descriptor.bin)
-* IFWI Image (ifwi.rom)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image, where the last two words represent the
-series and processor i.e. `lite_glkr`:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
-make
-```

Documentation/mainboard/starlabs/common/flashing.md

@@ -16,7 +16,7 @@ fwupdmgr --version
 ```
 
 This will show the version number. **1.5.6** or greater will work.
-![fwupd version](../fwupdVersion.png)
+![fwupd version](fwupdVersion.png)
 On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
 
 ```
@@ -40,7 +40,7 @@ BIOS Lock must be disabled when switching from the standard AMI (American Megatr
 2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
 3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
 
-![Disable BIOS Lock](../BiosLock.jpg)
+![Disable BIOS Lock](BiosLock.jpg)
 
 4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
 
@@ -61,7 +61,7 @@ fwupdmgr switch-branch
 ```
 
 You can then select which branch you would like to use, by typing in the corresponding number:
-![Switch Branch](../SwitchBranch.png)
+![Switch Branch](SwitchBranch.png)
 You will be prompted to confirm, press `y` to continue or `n` to cancel.
 
 Once the switch has been completed, you will be prompted to restart.

Documentation/mainboard/starlabs/labtop_cml.md

@@ -41,7 +41,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -1,64 +0,0 @@
-# Star LabTop Mk III
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-8550u  (Kaby Lake Refresh)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 620
-    - GOP driver is recommended, VBT is provided
-    - eDP 13-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 8265 PCIe WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - USB 3.1 Gen 2 Type-C (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 8  MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glk.md

@@ -37,7 +37,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/lite_glkr.md

@@ -37,7 +37,26 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* IFWI Image (ifwi.rom)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/starbook_adl.md

@@ -1,88 +0,0 @@
-# StarBook Mk V
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-1260P (Alder Lake)
-    - Intel i3-1220P (Alder Lake)
-- EC
-    - ITE IT5570E
-    - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel® Iris® Xe Graphics
-    - GOP driver is recommended, VBT is provided
-    - eDP 14-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 2 x DDR4 SODIMM
-- Networking
-    - AX210 2230 WiFi / Bluetooth
-- Sound
-    - Realtek ALC269-VB6
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1920x1080 CCD camera
-    - USB 3.1 Gen 2 (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-    - USB 2.0 Type-A (right)
-
-## Building coreboot
-
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | W25Q256.V  |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -40,7 +40,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/system76/darp8.md

@@ -1,82 +0,0 @@
-# Syste76 Darter Pro 8 (darp8)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1240P
-  - Intel Core i7-1260P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 15.6" 1920x1080@60Hz LCD
-  - 1x HDMI
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 65W+ chargers
-  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - M.2 PCIe NVMe Gen 4 SSD
-  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 1x USB 3.2 (Gen 2) Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Winbond             |
-+---------------------+---------------------+
-| Model               | W25Q256.V           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U19) is above the left DIMM slot.

Documentation/mainboard/system76/galp6.md

@@ -1,61 +0,0 @@
-# System76 Galago Pro 6 (galp6)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1240P
-  - Intel Core i7-1260P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 90W+ chargers
-  - 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 32.49cm x 22.5cm x 1.82cm, 1.45kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U43) is left of the wireless card.

Documentation/mainboard/system76/gaze17.md

@@ -1,65 +0,0 @@
-# System76 Gazelle 17 (gaze17)
-
-The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
-
-## Specs
-
-- CPU
-  - Intel Core i5-12500H
-  - Intel Core i7-12700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options
-    - NVIDIA GeForce RTX 3050
-    - NVIDIA GeForce RTX 3050 Ti
-    - NVIDIA GeForce RTX 3060
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
-- Networking
-  - Gigabit Ethernet
-    - 3050: Realtek RTL8111H controller
-    - 3060: Onboard Intel I219-V
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6 AX201
-- Power
-  - 3050: 150W (20V, 7.5A) AC barrel adapter
-  - 3060: 180W (20V, 9A) AC barrel adapter
-      - Lite-On PA-1181-76, using a C5 power cord
-  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-- Storage
-  - 1x M.2 PCIe NVMe Gen 4 SSD
-  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The position of the flash chip depends on the variant:
-
-- 3050: U24, below the bottom DIMM slot.
-- 3060: U55, left of the PCIe 4.0 M.2 slot.

Documentation/mainboard/system76/lemp11.md

@@ -1,62 +0,0 @@
-# System76 Lemur Pro 11 (lemp11)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1235U
-  - Intel Core i7-1255U
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.0" 1920x1080@60Hz LCD
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
-  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
-- Networking
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
-  - USB-C charging, compatible with 65W+ chargers
-  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5 mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - M.2 PCIe NVMe Gen 4 SSD
-  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-A
-  - 1x USB 3.2 (Gen 1) Type-A
-- Dimensions
-    - 1.65cm x 32.2cm x 21.68cm, 1.15kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U41) is left of the DIMM slot.

Documentation/mainboard/system76/oryp10.md

@@ -1,69 +0,0 @@
-# System76 Oryx Pro 10 (oryp10)
-
-## Specs
-
-- CPU
-  - Intel Core i7-12700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
-    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
-  - eDP options:
-    - 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
-    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
-    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
-  - 80Wh 6-cell Lithium-ion battery
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1306 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
-  - 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
-
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U61) is left of the DIMM slots.

Documentation/mainboard/system76/oryp9.md

@@ -1,67 +0,0 @@
-# System76 Oryx Pro 9 (oryp9)
-
-## Specs
-
-- CPU
-  - Intel Core i7-12700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
-    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
-  - eDP options:
-    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
-    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
-  - 80Wh 6-cell Lithium-ion battery
-- Sound
-  - Realtek ALC1220 codec
-  - TI TAS5825M smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
-  - 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U61) is left of the DIMM slots.

Documentation/northbridge/intel/haswell/mrc.bin.md

@@ -3,7 +3,7 @@
 All Haswell boards supported by coreboot currently require a proprietary
 blob in order to initialise the DRAM and a few other components. The
 blob, named `mrc.bin`, largely consists of Intel's memory reference code
-(MRC), but it has been tailored specifically for ChromeOS. It is just
+(MRC), but it has been tailored specifically for Chrome OS. It is just
 under 200 KiB in size. Another name for `mrc.bin` is the system agent
 binary.
 

Documentation/northbridge/intel/sandybridge/nri_registers.md

@@ -1899,7 +1899,7 @@ Please handle with care!
 +===========+==================================================================+
 |        0:7|  PDWN_idle_counter, This defines the rank indle period in DCLK   |
 |           |  cycles that causes power-down entrance. The minimum value       |
-|           |  should be greater than or equal to the worst roundtrip time     |
+|           |  should be greater then or equal to the worst roundtrip time     |
 |           |  plus burst length.                                              |
 +-----------+------------------------------------------------------------------+
 |       8:10|  PDWN_mode, selects the mode of power-down:                      |

Documentation/payloads.md

@@ -11,23 +11,17 @@ payload or can be made to work as one.
 
 [SeaBIOS](https://www.seabios.org) is an open source implementation of
 the PCBIOS API that exists since the original IBM PC and was extended
-since. While originally written for emulators such as QEMU, it can be built
-as a coreboot payload. It supports executing Option ROMs in a more complete
-fashion than coreboot. It also supports Multiboot.
+since. While originally written for emulators such as QEMU, it can be made
+to work as a coreboot payload and all the necessary code is in SeaBIOS'
+mainline code.
 
-When chainloaded from GRUB2, the following menuentry could be used:
+## Tianocore
 
-    menuentry "SeaBIOS" --unrestricted {
-        root=(cbfsdisk)
-        multiboot /img/seabios
-        module /vgaroms/seavgabios.bin
-    }
-
-## edk2
-
-[edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,
-cross-platform firmware development environment for the UEFI and UEFI
-Platform Initialization (PI) specifications.
+[Tianocore](https://www.tianocore.org) is the open source reference
+implementation of the UEFI Specifications that modern firmware for PCs is
+based on. There were various projects in the past to make it suitable as a
+coreboot payload, but these days this function is available directly in the
+UefiPayloadPkg part of its source tree.
 
 ## GRUB2
 
@@ -57,4 +51,4 @@ updates, but only works on a limited amount of mainboards.
 For more details have a look at [heads-wiki].
 
 [Heads]: https://github.com/osresearch/heads
-[heads-wiki]: http://osresearch.net/
+[heads-wiki]: http://osresearch.net/

Documentation/releases/boards_supported_on_branches.md

@@ -1,592 +0,0 @@
-# Platforms supported on branches
-
-For one reason or another, platforms have been deleted from the master
-branch at times in the past.  Early on, there was no real policy on
-removing boards.  Now the policy is that boards will only be removed if
-they're causing issues in the tree or if they're preventing progress.
-
-This does not mean that these boards are gone forever.  The release or
-commit prior to where they were removed can be checked out, and the
-boards can still be built there and updated in a release branch if
-desired.
-
-Currently, [jenkins](https://qa.coreboot.org), our continuous
-integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-4.16, and 4.18 branches.  Builders for other branches can be created on
-request.  Likewise, some releases are only marked with tags, and
-branches would need to be created to push new code to.  These branches
-can also be created on request.
-
-Patches can be backported from the master branch to any of these other
-branches as needed. The coreboot project may take care of backporting
-critical security fixes, but other patches will need to handled by
-anyone using that release.
-
-
-## [4.18 Release](coreboot-4.18-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| amd/inagua                    | AMD_FAMILY14           | 2011-02-14 | eval      |
-| amd/olivehill                 | AMD_FAMILY16_KB        | 2013-08-05 | eval      |
-| amd/parmer                    | AMD_FAMILY15_TN        | 2012-07-22 | eval      |
-| amd/persimmon                 | AMD_FAMILY14           | 2011-02-14 | eval      |
-| amd/south_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-| amd/thatcher                  | AMD_FAMILY15_TN        | 2012-08-02 | eval      |
-| amd/union_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-| asrock/e350m1                 | AMD_FAMILY14           | 2011-02-24 | mini      |
-| asrock/imb-a180               | AMD_FAMILY16_KB        | 2013-08-27 | mini      |
-| asus/a88xm-e                  | AMD_FAMILY15_TN        | 2020-08-13 | desktop   |
-| asus/am1i-a                   | AMD_FAMILY16_KB        | 2018-01-14 | mini      |
-| asus/f2a85-m                  | AMD_FAMILY15_TN        | 2013-03-22 | desktop   |
-| bap/ode_e20XX                 | AMD_FAMILY16_KB        | 2015-05-27 | eval      |
-| biostar/a68n_5200             | AMD_FAMILY16_KB        | 2017-10-14 | eval      |
-| biostar/am1ml                 | AMD_FAMILY16_KB        | 2015-04-10 | mini      |
-| elmex/pcm205400               | AMD_FAMILY14           | 2016-09-29 | sbc       |
-| gizmosphere/gizmo2            | AMD_FAMILY16_KB        | 2014-12-09 | eval      |
-| gizmosphere/gizmo             | AMD_FAMILY14           | 2014-01-03 | half      |
-| hp/abm                        | AMD_FAMILY16_KB        | 2015-01-05 | mini      |
-| hp/pavilion_m6_1035dx         | AMD_FAMILY15_TN        | 2014-03-28 | laptop    |
-| jetway/nf81-t56n-lf           | AMD_FAMILY14           | 2014-02-16 | mini      |
-| lenovo/g505s                  | AMD_FAMILY15_TN        | 2014-11-27 | laptop    |
-| lippert/frontrunner-af        | AMD_FAMILY14           | 2013-03-02 | half      |
-| msi/ms7721                    | AMD_FAMILY15_TN        | 2016-11-22 | desktop   |
-| pcengines/apu1                | AMD_FAMILY14           | 2015-02-23 | half      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
-
-## [4.17 Release](coreboot-4.17-relnotes.md)
-No Branch or builder
-
-* No platforms maintained on this release
-
-
-## [4.16 Release](coreboot-4.16-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.15 Release](coreboot-4.15-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.14 Release](coreboot-4.14-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.13 Release](coreboot-4.13-relnotes.md)
-Tag only
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| intel/cannonlake_rvp        | INTEL_CANNONLAKE       | 2017-07-19 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-## [4.12 Release](coreboot-4.12-relnotes.md)
-
-Branch created, builder configured
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| bap/ode_e21XX               | AMD_PI_00730F01        | 2016-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/toucan-af           | AMD_FAMILY14           | 2013-03-02 | half     |
-+-----------------------------+------------------------+------------+----------+
-| ocp/sonorapass              | INTEL_COOPERLAKE_SP    | 2020-05-01 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
-
-## [4.11 Release](coreboot-4.11-relnotes.md)
-
-Branch created, builder configured
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| adi/rcc-dff                 | INTEL_FSP_RANGELEY     | 2016-06-08 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| advansus/a785e-i            | AMD_AMDFAM10           | 2011-05-07 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| amd/bettong                 | AMD_PI_00660F01        | 2015-06-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/bimini_fam10            | AMD_AMDFAM10           | 2011-01-01 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/db-ft3b-lc              | AMD_PI_00730F01        | 2016-07-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/gardenia                | AMD_STONEYRIDGE_FP4    | 2016-12-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/lamar                   | AMD_PI_00630F01        | 2015-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/mahogany_fam10          | AMD_AMDFAM10           | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/olivehillplus           | AMD_PI_00730F01        | 2014-09-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/serengeti_cheetah_fam10 | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| amd/tilapia_fam10           | AMD_AMDFAM10           | 2010-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/torpedo                 | AMD_FAMILY12           | 2011-06-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| asus/kcma-d8                | AMD_AMDFAM10           | 2016-02-05 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/kfsn4-dre              | AMD_AMDFAM10           | 2015-01-28 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/kgpe-d16               | AMD_AMDFAM10           | 2015-10-28 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/m4a785-m               | AMD_AMDFAM10           | 2010-09-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m4a785t-m              | AMD_AMDFAM10           | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m4a78-em               | AMD_AMDFAM10           | 2010-12-06 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m5a88-v                | AMD_AMDFAM10           | 2011-10-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| avalue/eax-785e             | AMD_AMDFAM10           | 2011-09-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| esd/atom15                  | INTEL_FSP_BAYTRAIL     | 2015-12-04 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| facebook/watson             | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server   |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ma785gm            | AMD_AMDFAM10           | 2012-04-23 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ma785gmt           | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ma78gm             | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| google/urara                | IMGTEC_PISTACHIO       | 2015-03-27 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| hp/dl165_g6_fam10           | AMD_AMDFAM10           | 2010-09-24 | server   |
-+-----------------------------+------------------------+------------+----------+
-| iei/kino-780am2-fam10       | AMD_AMDFAM10           | 2010-09-13 | half     |
-+-----------------------------+------------------------+------------+----------+
-| intel/bayleybay_fsp         | INTEL_FSP_BAYTRAIL     | 2014-05-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/littleplains          | INTEL_FSP_RANGELEY     | 2015-11-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/minnowmax             | INTEL_FSP_BAYTRAIL     | 2014-08-11 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| intel/mohonpeak             | INTEL_FSP_RANGELEY     | 2014-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| jetway/pa78vm5              | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms9652_fam10            | AMD_AMDFAM10           | 2010-03-01 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| ocp/monolake                | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
-| ocp/wedge100s               | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
-| opencellular/rotundu        | INTEL_FSP_BAYTRAIL     | 2018-06-26 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| siemens/mc_bdx1             | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc     |
-+-----------------------------+------------------------+------------+----------+
-| siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL     | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
-| siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL_MD  | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8dmr_fam10      | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8qme_fam10      | AMD_AMDFAM10           | 2010-02-03 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8scm_fam10      | AMD_AMDFAM10           | 2011-03-28 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2912_fam10            | AMD_AMDFAM10           | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-m850               | VIA_NANO               | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-m850               | VIA_VX900              | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.10 Release](coreboot-4.10-relnotes.md)
-Branch created
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| cubietech/cubieboard        | ALLWINNER_A10          | 2014-01-08 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.9 Release](coreboot-4.9-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| pcengines/alix1c            | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| pcengines/alix1c            | AMD_LX                 | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| pcengines/alix2d            | AMD_GEODE_LX           | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-| pcengines/alix2d            | AMD_LX                 | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
-Branch created
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| aaeon/pfm-540i_revb         | AMD_GEODE_LX           | 2011-06-29 | half     |
-+-----------------------------+------------------------+------------+----------+
-| amd/db800                   | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/dbm690t                 | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/f2950                   | AMD_GEODE_LX           | 2016-07-17 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| amd/mahogany                | AMD_AMDK8              | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/norwich                 | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/pistachio               | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/serengeti_cheetah       | AMD_AMDK8              | 2009-08-12 | server   |
-+-----------------------------+------------------------+------------+----------+
-| artecgroup/dbe61            | AMD_GEODE_LX           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| asrock/939a785gmh           | AMD_AMDK8              | 2010-04-05 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/a8n_e                  | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/a8v-e_deluxe           | AMD_AMDK8              | 2010-11-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/a8v-e_se               | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/k8v-x                  | AMD_AMDK8              | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/kfsn4-dre_k8           | AMD_AMDK8              | 2015-10-30 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/m2n-e                  | AMD_AMDK8              | 2010-12-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m2v                    | AMD_AMDK8              | 2010-11-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m2v-mx_se              | AMD_AMDK8              | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| bachmann/ot200              | AMD_GEODE_LX           | 2012-07-13 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| bcom/winnetp680             | VIA_C7                 | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| broadcom/blast              | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| digitallogic/msm800sev      | AMD_GEODE_LX           | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ga_2761gxdk        | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/m57sli             | AMD_AMDK8              | 2009-10-03 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| google/purin                | BROADCOM_CYGNUS        | 2015-04-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/rotor                | MARVELL_MVMAP2315      | 2016-09-13 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/zoombini             | INTEL_CANNONLAKE       | 2017-09-28 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| hp/dl145_g1                 | AMD_AMDK8              | 2010-08-20 | server   |
-+-----------------------------+------------------------+------------+----------+
-| hp/dl145_g3                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| iei/pcisa-lx-800-r10        | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| iei/pm-lx2-800-r10          | AMD_GEODE_LX           | 2012-10-28 | half     |
-+-----------------------------+------------------------+------------+----------+
-| iei/pm-lx-800-r11           | AMD_GEODE_LX           | 2012-07-06 | half     |
-+-----------------------------+------------------------+------------+----------+
-| intel/cougar_canyon2        | INTEL_FSP_IVYBRIDGE    | 2013-12-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/stargo2               | INTEL_FSP_IVYBRIDGE    | 2015-11-10 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| iwill/dk8_htx               | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| jetway/j7f2                 | VIA_C7                 | 2014-01-19 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| kontron/kt690               | AMD_AMDK8              | 2009-10-15 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/hurricane-lx        | AMD_GEODE_LX           | 2010-09-10 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/literunner-lx       | AMD_GEODE_LX           | 2010-09-07 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/roadrunner-lx       | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/spacerunner-lx      | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lowrisc/nexys4ddr           | LOWRISC_LOWRISC        | 2016-10-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms7135                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms7260                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms9185                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms9282                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
-| nvidia/l1_2pvv              | AMD_AMDK8              | 2009-10-07 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| siemens/sitemp_g1p1         | AMD_AMDK8              | 2011-05-11 | half     |
-+-----------------------------+------------------------+------------+----------+
-| sunw/ultra40                | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| sunw/ultra40m2              | AMD_AMDK8              | 2015-11-10 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8dme            | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8dmr            | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| technexion/tim5690          | AMD_AMDK8              | 2009-10-13 | half     |
-+-----------------------------+------------------------+------------+----------+
-| technexion/tim8690          | AMD_AMDK8              | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| traverse/geos               | AMD_GEODE_LX           | 2010-05-20 | half     |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2912                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-cn                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-m700               | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/pc2500e                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/vt8454c                 | VIA_C7                 | 2009-08-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| winent/mb6047               | AMD_AMDK8              | 2013-10-19 | half     |
-+-----------------------------+------------------------+------------+----------+
-| winent/pl6064               | AMD_GEODE_LX           | 2010-02-24 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| winnet/g170                 | VIA_C7                 | 2017-08-28 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.7 Release](coreboot-4.7-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| abit/be6-ii_v2_0            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| amd/dinar                   | AMD_FAMILY15           | 2012-02-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/rumba                   | AMD_GEODE_GX2          | 2009-08-29 | half     |
-+-----------------------------+------------------------+------------+----------+
-| asus/dsbf                   | INTEL_I5000            | 2012-07-14 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/mew-am                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/mew-vm                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| a-trend/atc-6220            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| a-trend/atc-6240            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| azza/pt-6ibd                | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| biostar/m6tba               | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| compaq/deskpro_en_sff_p600  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| dmp/vortex86ex              | DMP_VORTEX86EX         | 2013-07-05 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| ecs/p6iwp-fe                | INTEL_I82810           | 2010-06-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ga-6bxc            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ga-6bxe            | INTEL_I440BX           | 2010-05-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| hp/e_vectra_p2706t          | INTEL_I82810           | 2009-10-20 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| intel/d810e2cb              | INTEL_I82810           | 2010-06-21 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| intel/eagleheights          | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/mtarvon               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/truxton               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| iwave/iWRainbowG6           | INTEL_SCH              | 2010-12-18 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lanner/em8510               | INTEL_I855             | 2010-08-30 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| lippert/frontrunner         | AMD_GEODE_GX2          | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| mitac/6513wu                | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6119                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6147                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6156                  | INTEL_I440BX           | 2009-10-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6178                  | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| nec/powermate2000           | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| nokia/ip530                 | INTEL_I440BX           | 2010-04-19 | server   |
-+-----------------------------+------------------------+------------+----------+
-| rca/rm4100                  | INTEL_I82830           | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| soyo/sy-6ba-plus-iii        | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8qgi            | AMD_FAMILY15           | 2011-07-22 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8scm            | AMD_FAMILY15           | 2012-11-30 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/x7db8            | INTEL_I5000            | 2012-06-23 | server   |
-+-----------------------------+------------------------+------------+----------+
-| thomson/ip1000              | INTEL_I82830           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s1846                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s8226                  | AMD_FAMILY15           | 2012-10-04 | server   |
-| wyse/s50                    | AMD_GEODE_GX2          | 2010-05-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.6](coreboot-4.6-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| bifferos/bifferboard        | RDC_R8610              | 2012-03-27 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/cosmos               | MARVELL_BG4CD          | 2015-04-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/bakersport_fsp        | INTEL_FSP_BAYTRAIL     | 2014-08-11 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.5](coreboot-4.5-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| google/enguarde             | INTEL_BAYTRAIL         | 2016-09-21 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/falco                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/guado                | INTEL_BROADWELL        | 2016-01-12 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/ninja                | INTEL_BAYTRAIL         | 2016-05-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/panther              | INTEL_HASWELL          | 2014-07-12 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/peppy                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/rikku                | INTEL_BROADWELL        | 2016-06-16 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/samus                | INTEL_BROADWELL        | 2014-08-29 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/tidus                | INTEL_BROADWELL        | 2016-01-21 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.4](coreboot-4.4-relnotes.md)
-Branch created
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| google/bolt                 | INTEL_HASWELL          | 2013-12-12 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/rush                 | NVIDIA_TEGRA132        | 2015-01-26 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/rush_ryu             | NVIDIA_TEGRA132        | 2015-03-05 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/slippy               | INTEL_HASWELL          | 2013-11-24 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/amenia                | INTEL_APOLLOLAKE       | 2016-04-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.3](coreboot-4.3-relnotes.md)
-Branch created
-
-* No platforms maintained on this release
-
-
-## [4.2](coreboot-4.2-relnotes.md)
-Branch created
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| arima/hdama                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| digitallogic/adl855pc       | INTEL_I855             | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
-| ibm/e325                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| ibm/e326                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| intel/sklrvp                | INTEL_SKYLAKE          | 2015-07-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| iwill/dk8s2                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| iwill/dk8x                  | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| newisys/khepri              | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2735                  | INTEL_E7501            | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2850                  | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2875                  | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2881                  | AMD_AMDK8              | 2009-09-23 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2885                  | AMD_AMDK8              | 2009-10-08 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2891                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2892                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2895                  | AMD_AMDK8              | 2009-09-22 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s4880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s4882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.1](coreboot-4.1-relnotes.md)
-Branch Created
-
-* No platforms maintained on this release

Documentation/releases/checklist.md

@@ -4,73 +4,56 @@
 
 # coreboot Release Process
 
-This document describes our release process and all prerequisites to
-implement it successfully.
-
+This document describes our release process and all prerequisites to implement
+it successfully.
 
 ## Purpose of coreboot releases
-Our releases aren't primarily a vehicle for code that is stable across
-all boards: The logistics of testing the more than 100 boards that are
-spread out all continents (except Antarctica, probably) on a given tree
-state are prohibitive for project of our size.
+Our releases aren't primarily a vehicle for code that is stable across all
+boards: The logistics of testing the more than 100 boards that are spread out
+all continents (except Antarctica, probably) on a given tree state are
+prohibitive for project of our size.
 
-Instead, the releases are regular breakpoints that serve multiple
-purposes: They support cooperation between multiple groups (corporations
-or otherwise) in that it's easier to keep source trees synchronized
-based on a limited set of commits. They allow a quick assessment of the
-age of any given build or source tree based on its git version (4.8-1234
-was merged into master a few months after 4.8, which came out in April
-of 2018. 4.0-21718's age is harder to guess).
+Instead, the releases are regular breakpoints that serve multiple purposes:
+They support cooperation between multiple groups (corporations or otherwise)
+in that it's easier to keep source trees synchronized based on a limited set
+of commits. They allow a quick assessment of the age of any given build or
+source tree based on its git version (4.8-1234 was merged into master a few
+months after 4.8, which came out in April 2018. 4.0-21718's age is harder to
+guess).
 
-And finally we use releases to as points in time where we remove old
-code: Once we decide that a certain part of coreboot gets in the way of
-future development, we announce on the next release that we intend to
-remove that part - and everything that depends on it - after the
-following release. So removing feature FOO will be announced in release
-X for release X+1. The first commit after X+1 is fair game for such
-removal.
+And finally we use releases to as points in time where we remove old code:
+Once we decide that a certain part of coreboot gets in the way of future
+development, we announce on the next release that we intend to remove that
+part - and everything that depends on it - after the following release.
+So removing feature FOO will be announced in release X for release
+X+1. The first commit after X+1 is fair game for such removal.
 
-Together with our 3 months release horizon, this provides time to plan
+Together with our 6 months release horizon, this provides time to plan
 any migrations necessary to keep older boards in the tree by bringing
 them up to current standards.
 
-## coreboot release team
-To avoid issues of blocking the release on a single person, a release
-team has been formed. Please see the `COREBOOT RELEASES` section of the
-MAINTAINERS file for the current members.
-
-These individuals work together to make sure releases are done on time,
-follow the steps of this document, and update the release processes and
-scripts.
-
-
 ## Needed credentials & authorizations
-
-### coreboot admins only
 * Website access is required to post the release files to the website.
-
-### All release team members
-* IRC topic access is required to update the topic.
+* IRC admin access is required to update the topic.
 * Git access rights are needed to post the tag.
 * Blog post access is needed to do the blog post.
 * A PGP key is required to sign the release tarballs and git tag.
 
-Most of the steps in the release process can be done by anyone on the
-release team. Only adding the files to the website needs to be done
-by a coreboot administrator.
+This set of required credentials implies that releases can only be done
+by a coreboot admin.
 
 ## When to release
-Releases are done roughly on a 3-month schedule. If a release is
-delayed, the next release will still be 3 months after the last release.
+Releases are done roughly on a 6-month schedule, ideally around end
+of April and end of October (can be a bit earlier or delay into May
+or November).
 
+We initially followed a 3 month release schedule, but we found that to
+be more frequent than was needed, so we scaled it back to twice a year.
 
 ## Checklist
-
 ### ~2 weeks prior to release
 - [ ] Announce upcoming release to mailing list, ask people to test and
       to update release notes.
-- [ ] Start marking patches that should to go into the release with a
-      tag "coreboot_release_X.yy"
 
 ### ~1 week prior to release
 - [ ] Send reminder email to mailing list, ask for people to test,
@@ -83,53 +66,28 @@ delayed, the next release will still be 3 months after the last release.
 - [ ] Finalize release notes as much as possible
 - [ ] Prepare release notes template for following release
 - [ ] Update `Documentation/releases/index.md`
-- [ ] Check which branches need to be released. Any branch with changes
-      should get a new release. Announce these branch releases and
-      prepare release notes.
-
-### Day before release
-- [ ] Make sure patches with tags for the release are merged.
-- [ ] Announce to IRC that the release will be tomorrow and ask for
-      testing.
 - [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
       boards supported by vboot.
 
 ### Day of release
-- [ ] Review the full documentation about doing the release below.
-- [ ] Select a commit ID to base the release upon.
+- [ ] Select a commit ID to base the release upon, announce to IRC,
+      ask for testing.
 - [ ] Test the commit selected for release.
-- [ ] Submit last pre-release release notes.
-- [ ] Run the release script.
+- [ ] Submit release notes
+- [ ] Create new release notes doc template for the next version.
+- [ ] Fill in the release date, remove "Upcoming release" and other filler
+      from the current release notes.
+- [ ] Run release script.
 - [ ] Test the release from the actual release tarballs.
-- [ ] Push signed Tag to repo. *This is the actual release step.*
-      Once this patch is pushed, the release itself has been done.
-      everything after this step is packaging and delivering the
-      release.
-
+- [ ] Push signed Tag to repo.
 - [ ] Announce that the release tag is done on IRC.
-- [ ] Update the topic in the IRC channel that the release is done.
-
-- [ ] Do the final release notes - Fill in the release date, remove
-      "Upcoming release" and other filler from the current release
-      notes.
-- [ ] ADMIN: Upload release files to web server.
-- [ ] ADMIN: Upload the final release notes to the web server.
-- [ ] ADMIN: Upload crossgcc sources to web server.
-- [ ] Create coreboot-sdk and coreboot-jenkins-node docker images
-      based on the release ID and push them to dockerhub. These
-      can be used as release builders.
-
-### Week following the release
+- [ ] Upload release files to web server.
+- [ ] Also extract the release notes and place them on the web server.
+- [ ] Upload crossgcc sources to web server.
 - [ ] Update download page to point to files, push to repo.
-- [ ] Write and publish blog post with release final notes. Branch
-      releases notes should be included in the same post.
-- [ ] Remove code that was announced it was going to be removed.
-- [ ] Update `Documentation/releases/boards_supported_on_branches.md`
-
-### Creating a branch
-- [ ] Branches are named 4.xx_branch to differentiate from the tags.
-      Instructions on creating branches are listed below.
-
+- [ ] Write and publish blog post with release notes.
+- [ ] Update the topic in the IRC channel that the release is done.
+- [ ] Announce the release to the mailing list.
 
 ## Pre-Release tasks
 Announce the upcoming release to the mailing list release 2 weeks ahead
@@ -144,30 +102,29 @@ People should be encouraged to provide additions to the release notes.
 
 The final release notes will reside in coreboot's Documentation/releases
 directory, so asking for additions to that through the regular Gerrit
-process works as well. Note that git requires lots of conflict
-resolution on heavily edited text files though.
+process works as well. Note that git requires lots of conflict resolution
+on heavily edited text files though.
 
 Frequently, we will want to wait until particular things are in the
-release. Once those are in, you can select the commit ID that you want
-to use for your release. For the 4.6 release, we waited until we had
+release.  Once those are in, you can select the commit ID that you want
+to use for your release.  For the 4.6 release, we waited until we had
 time to do the release, then pulled in a few patches that we wanted
-to have in the release. The release was based on the final of those
+to have in the release.  The release was based on the final of those
 patches to be pulled in.
 
 When a release candidate has been selected, announce the commit ID to
 the #coreboot IRC channel, and request that it get some testing, just
 to make sure that everything is sane.
 
-
 ## Generate the release
 After the commit for the release has been selected and verified, run the
-release script - util/release/build-release. This will download a new
+release script - util/release/build-release.  This will download a new
 tree, checkout the commit that you specified, download the submodules,
 create a tag, then generate and sign the tarballs.
 
-**Be prepared to type in your PGP key’s passphrase.**
+Be prepared to type in your PGP key’s passphrase.
 
-```text
+````
 usage: util/release/build-release <version> [commit id] [username] [gpg key id]
 Tags a new coreboot version and creates a tar archive
 
@@ -175,41 +132,37 @@ version:    New version name to tag the tree with
 commit id:  check out this commit-id after cloning the coreboot tree
 username:   clone the tree using ssh://USERNAME - defaults to https://
 gpg key id: used to tag the version, and generate a gpg signature
-```
+````
 
-After running the script, you should have a new directory for the
-release, along with 4 files: 2 tarballs, and 2 signature files.
+After running the script, you should have a new directory for the release,
+along with 4 files - 2 tarballs, and 2 signature files.
 
-```text
+````
 drwxr-xr-x   9 martin martin      4096 Apr 30 19:57 coreboot-4.6
 -rw-r--r--   1 martin martin  29156788 Apr 30 19:58 coreboot-4.6.tar.xz
 -rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-4.6.tar.xz.sig
 -rw-r--r--   1 martin martin   5902076 Apr 30 19:58 coreboot-blobs-4.6.tar.xz
 -rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-blobs-4.6.tar.xz.sig
-```
+````
 
 Here’s the command that was used to generate the 4.6 release:
-```bash
-util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
-```
-
+````
+% util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
+````
 
 ## Test the release from the tarballs
 * Run “make what-jenkins-does” and verify that everything is building.
 * Build and test qemu
-```bash
-cp configs/config.emulation_qemu_x86_i440fx .config
-make olddefconfig
-make
-qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
-```
+  ````
+  cp configs/config.emulation_qemu_x86_i440fx .config; make olddefconfig; make
+  qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+  ````
 * Build and test any other platforms you can.
-* Compare the directory from the tarballs to the coreboot repo to make
-  sure nothing went wrong.
+* Compare the directory from the tarballs to the coreboot repo to make sure nothing went wrong.
 * Push the tag to git
 
 A good tag will look like this:
-````text
+````
 % git show 4.6
 tag 4.6
 Tagger: Martin Roth <martinroth@google.com>
@@ -230,44 +183,33 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
 ...
 ````
 
-When you used the script to generate the release, a signed tag was
-generated in the tree that was downloaded. From the coreboot-X.Y tree,
-just run: `git push origin X.Y`. In case you pushed the wrong tag
-already, you have to force push the new one.
+When you used the script to generate the release, a signed tag was generated in the
+tree that was downloaded. From the coreboot-X.Y tree, just run: `git push origin X.Y`.
+In case you pushed the wrong tag already, you have to force push the new one.
 
 You will need write access for tags to the coreboot git repo to do this.
 
-
 ## After the release is tagged in git
 Announce that the release has been tagged - this lets people know that
-they should update their trees to grab the new tag. Until they do this,
+they should update their trees to grab the new tag.  Until they do this,
 the version number in build.h will still be based on the previous tag.
 
 Copy the tarballs and .sig files generated by the script to
 the coreboot server, and put them in the release directory at
 `/srv/docker/www.coreboot.org-staticfiles/releases/`
 
-````bash
-# Update the sha256sum file
-sha256sum -b coreboot-*.tar.xz > sha256suma.txt
-
-# make sure the two new files are present (and nothing else has changed)
-diff sha256sum.txt sha256suma.txt
-
-mv sha256suma.txt sha256sum.txt
+````
+% sha256sum -b coreboot-*.tar.xz > sha256suma.txt # Update the sha256sum file
+% diff sha256sum.txt sha256suma.txt # make sure that the two new files are present (and that nothing else has changed)
+% mv sha256suma.txt sha256sum.txt
 ````
 
 People can now see the release tarballs on the website at
 <https://www.coreboot.org/releases/>
 
-The downloads page is the official place to download the releases from,
-and it needs to be updated with links to the new release tarballs and
-.sig files. It can be found at:
-<https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
-
-Here is an example commit to change it:
-<https://review.coreboot.org/c/homepage/+/19515>
+The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
 
+Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515>
 
 ## Upload crossgcc sources
 Sometimes the source files for older revisions of
@@ -277,32 +219,24 @@ sources used by the crossgcc scripts that are part of coreboot releases.
 
 Run
 
-````bash
-util/crossgcc/buildgcc -u
+````
+% util/crossgcc/buildgcc -u
 ````
 
 This will output the set of URLs that the script uses to download the
 sources. Download them yourself and copy them into the crossgcc-sources
 directory on the server.
 
-
 ## After the release is complete
-Post the final release notes on <https://blogs.coreboot.org>
-
+Post the release notes on <https://blogs.coreboot.org>
 
 ## Making a branch
 At times we will need to create a branch, generally for patch fixes.
-When making a branch, do NOT name it the same as the release tag: X.Y -
-this creates trouble when trying to check it out, as git can’t tell
-whether you want the tag or the branch. Instead, name it X.Y\_branch:
-```bash
-git checkout 4.8
-git checkout -b 4.8_branch
-git push origin 4.8_branch
-```
+When making a branch, do NOT name it the same as the release tag: X.Y - this creates trouble when trying to check it out, as git can’t tell whether you want the tag or the branch.
+Instead, name it X.Y\_branch: `git checkout 4.8; git checkout -b 4.8_branch; git push origin 4.8_branch`
 
 You can then cherry-pick changes and push them up to the branch:
-````bash
+````
 git cherry-pick c6d134988c856d0025153fb885045d995bc8c397
 git push origin HEAD:refs/for/4.8_branch
 ````

Documentation/releases/coreboot-4.15-relnotes.md

@@ -52,9 +52,9 @@ Deprecations and incompatible changes
 
 Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
 updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
-to build from upstream edk2 master. Drop the EDK2_USE_8254_TIMER Kconfig
+to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
 option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
-that we're only building from a single edk2 package/target.
+that we're only building from a single Tianocore package/target.
 
 ### Remove old lp4x and ddr4 versions of spd_tools
 

Documentation/releases/coreboot-4.16-relnotes.md

@@ -132,7 +132,7 @@ HECI based on Intel Core processors from Skylake to Alder Lake. State is
 set based on a CMOS value of `me_state`. A value of `0` will result in a
 (CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
 state of `3` (disabled). For an example CMOS layout and more info, see
-[cse.c](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/soc/intel/common/block/cse/cse.c).
+[cse.c](../../src/soc/intel/common/block/cse/cse.c).
 
 
 ### Add [AMD] apcb_v3_edit tool

Documentation/releases/coreboot-4.17-relnotes.md

@@ -1,375 +1,19 @@
-coreboot 4.17
-========================================================================
+Upcoming release - coreboot 4.17
+================================
 
-The coreboot 4.17 release was done on June 3, 2022.
+The 4.17 release is planned for May, 2022.
 
-Since the 4.16 release, we've had over 1300 new commits by around 150
-contributors.  Of those people, roughly 15 were first-time contributors.
+We are continuing the quarterly release cadence in order to enable others to
+release quarterly on a fresher version of coreboot.
 
-As always, we appreciate everyone who has contributed and done the hard
-work to make the coreboot project successful.
+Update this document with changes that should be in the release notes.
 
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
 
-Major Bugfixes in this release
-------------------------------
-* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264)
+Significant changes
+-------------------
 
-
-New Mainboards
---------------
-
-* Clevo L140MU / L141MU / L142MU
-* Dell Precision T1650
-* Google Craask
-* Google Gelarshie
-* Google Kuldax
-* Google Mithrax
-* Google Osiris
-* HP Z220 CMT Workstation
-* Star Labs LabTop Mk III (i7-8550u)
-* Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
-* Star Labs Lite Mk III (N5000)
-* Star Labs Lite Mk IV (N5030)
-
-
-Removed Mainboards
-------------------
-
-* Google Deltan
-* Google Deltaur
-
-Significant or interesting changes
-----------------------------------
-
-These changes are a few that were selected as a sampling of particularly
-interesting commits.
-
-
-### CBMEM init hooks changed
-
-Instead of having per stage x_CBMEM_INIT_HOOK, we now have only 2 hooks:
-* CBMEM_CREATION_HOOK: Used only in the first stage that creates cbmem,
-  typically romstage. For instance code that migrates data from cache
-  as ram to dram would use this hook.
-* CBMEM_READY_HOOK: Used in every stage that has cbmem. An example would
-  be initializing the cbmem console by appending to what previous stages
-  logged.
-The reason for this change is improved flexibility with regards to which
-stage initializes cbmem.
-
-
-### Payloads
-
-* SeaBIOS: Update stable release from 1.14.0 to 1.16.0
-* iPXE: Update stable release from 2019.3 to 2022.1
-* Add "GRUB2 atop SeaBIOS" aka "SeaGRUB" option, which builds GRUB2 as a
-  secondary payload for SeaBIOS with GRUB2 set as the default boot
-  entry.  This allows GRUB2 to use BIOS callbacks provided by SeaBIOS as
-  a fallback method to access hardware that the native GRUB2 payload
-  cannot access.
-* Add option to build SeaBIOS and GRUB2 as secondary payloads
-* Add new coreDOOM payload.  See commit message below.
-
-
-### payloads/external: Add support for coreDOOM payload
-
-coreDOOM is a port of DOOM to libpayload, based on the doomgeneric
-source port. It renders the game to the coreboot linear framebuffer,
-and loads WAD files from CBFS.
-
-
-### cpu/x86/smm_module_load: Rewrite setup_stub
-
-This code was hard to read as it did too much and had a lot of state
-to keep track of.
-
-It also looks like the staggered entry points were first copied and
-only later the parameters of the first stub were filled in. This
-means that only the BSP stub is actually jumping to the permanent
-smihandler. On the APs the stub would jump to wherever c_handler
-happens to point to, which is likely 0. This effectively means that on
-APs it's likely easy to have arbitrary code execution in SMM which is a
-security problem.
-
-Note: This patch fixes CVE-2022-29264 for the 4.17 release.
-
-
-### cpu/x86/smm_module_loader.c: Rewrite setup
-
-This code is much easier to read if one does not have to keep track of
-mutable variables.
-
-This also fixes the alignment code on the TSEG smihandler setup code.
-It was aligning the code upwards instead of downwards which would cause
-it to encroach a part of the save state.
-
-
-### cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub
-
-The sinkhole exploit exists in placing the lapic base such that it
-messes with GDT. This can be mitigated by checking the lapic MSR
-against the current program counter.
-
-
-### cpu/x86/64bit: Generate static page tables from an assembly file
-
-This removes the need for a tool to generate simple identity pages.
-Future patches will link this page table directly into the stages on
-some platforms so having an assembly file makes a lot of sense.
-
-This also optimizes the size of the page of each 4K page by placing
-the PDPE_table below the PDE.
-
-
-### cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
-
-This change will allow the SMI handler to write to the cbmem console
-buffer. Normally SMIs can only be debugged using some kind of serial
-port (UART). By storing the SMI logs into cbmem we can debug SMIs using
-'cbmem -1'. Now that these logs are available to the OS we could also
-verify there were no errors in the SMI handler.
-
-Since SMM can write to all of DRAM, we can't trust any pointers
-provided by cbmem after the OS has booted. For this reason we store the
-cbmem console pointer as part of the SMM runtime parameters. The cbmem
-console is implemented as a circular buffer so it will never write
-outside of this area.
-
-
-### security/tpm/crtm: Add a function to measure the bootblock on SoC level
-
-On platforms where the bootblock is not included in CBFS anymore
-because it is part of another firmware section (IFWI or a different
-CBFS), the CRTM measurement fails.
-
-This patch adds a new function to provide a way at SoC level to measure
-the bootblock. Following patches will add functionality to retrieve the
-bootblock from the SoC related location and measure it from there.
-In this way the really executed code will be measured.
-
-
-### soc/amd/common/block/psp: Add platform secure boot support
-
-Add Platform Secure Boot (PSB) enablement via the PSP if it is not
-already enabled. Upon receiving psb command, PSP will program PSB fuses
-as long as BIOS signing key token is valid.
-Refer to the AMD PSB user guide doc# 56654, Revision# 1.00.
-Unfortunately this document is only available with NDA customers.
-
-
-### drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
-
-This patch implements coreboot native debug handler to manage the FSP
-event messages.
-
-'FSP Event Handlers' feature introduced in FSP to generate event
-messages to aid in the debugging of firmware issues. This eliminates
-the need for FSP to directly write debug messages to the UART and FSP
-might not need to know the board related UART port configuration.
-Instead FSP signals the bootloader to inform it of a new debug message.
-This allows the coreboot to provide board specific methods of reporting
-debug messages, example: legacy UART or LPSS UART etc.
-
-This implementation has several advantages as:
-1. FSP relies on XIP 'DebugLib' driver even while printing FSP-S debug
-  messages, hence, without ROM being cached, post 'romstage' would
-  results into sluggish boot with FSP debug enabled.
-  This patch utilities coreboot native debug implementation which is
-  XIP during FSP-M and relocatable to DRAM based resource for FSP-S.
-
-2. This patch simplifies the FSP DebugLib implementation and remove the
-   need to have serial port library. Instead coreboot 'printk' can be
-   used for display FSP serial messages. Additionally, unifies the debug
-   library between coreboot and FSP.
-
-3. This patch is also useful to get debug prints even with FSP
-   non-serial image (refer to 'Note' below) as FSP PEIMs are now
-   leveraging coreboot debug library instead FSP 'NULL' DebugLib
-   reference for release build.
-
-4. Can optimize the FSP binary size by removing the DebugLib dependency
-   from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary
-   size is reduced by ~100KB+ and FSP-S debug library size is also
-   reduced by ~300KB+ (FSP-S debug and release binary size is exactly
-   same with this code changes). The total savings is ~400KB for each
-   FSP copy, and in case of Chrome AP firmware with 3 copies, the total
-   savings would be 400KB * 3 = ~1.2MB.
-
-Note: Need to modify FSP source code to remove 'MDEPKG_NDEBUG' as
-compilation flag for release build and generate FSP binary with non-NULL
-FSP debug wrapper module injected (to allow FSP event handler to execute
-even with FSP non-serial image) in the final FSP.fd.
-
-
-### security/tpm: Add vendor-specific tis functions to read/write TPM regs
-
-In order to abstract bus-specific logic from TPM logic, the prototype
-for two vendor-specific tis functions are added in this
-patch. tis_vendor_read() can be used to read directly from TPM
-registers, and tis_vendor_write() can be used to write directly to TPM
-registers.
-
-
-### arch/x86: Add support for catching null dereferences through debug regs
-
-This commit adds support for catching null dereferences and execution
-through x86's debug registers. This is particularly useful when running
-32-bit coreboot as paging is not enabled to catch these through page
-faults. This commit adds three new configs to support this feature:
-DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and
-DEBUG_NULL_DEREF_HALT.
-
-
-### drivers/i2c/generic: Add support for i2c device detection
-
-Add 'detect' flag which can be attached to devices which may or may not
-be present at runtime, and for which coreboot should probe the i2c bus
-to confirm device presence prior to adding an entry for it in the SSDT.
-
-This is useful for boards which may utilize touchpads/touchscreens from
-multiple vendors, so that only the device(s) present are added to the
-SSDT. This relieves the burden from the OS to detect/probe if a device
-is actually present and allows the OS to trust the ACPI _STA value.
-
-
-### util/cbmem: Add FlameGraph-compatible timestamps output
-
-Flame graphs are used to visualize hierarchical data, like call stacks.
-Timestamps collected by coreboot can be processed to resemble
-profiler-like output, and thus can be feed to flame graph generation
-tools.
-
-Generating flame graph using https://github.com/brendangregg/FlameGraph:
-```
-   cbmem -S > trace.txt
-   FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg
-```
-
-
-### src/console/Kconfig: Add option to disable loglevel prefix
-
-This patch adds an option to disable loglevel prefixes. This patch helps
-to achieve clear messages when low loglevel is used and very few
-messages are displayed on a terminal. This option also allows to
-maintain compatibility with log readers and continuous integration
-systems that depend on fixed log content.
-
-If the code contains:
-  printk(BIOS_DEBUG, "This is a debug message!\n")
-it will show as:
-  [DEBUG]  This is a debug message!
-but if the Kconfig contains:
-  CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
-the same message will show up as
-  This is a debug message!
-
-
-### util/cbmem: add an option to append timestamp
-
-Add an option to the cbmem utility that can be used to append an entry
-to the cbmem timestamp table from userspace. This is useful for
-bookkeeping of post-coreboot timing information while still being able
-to use cbmem-based tooling for processing the generated data.
-
-
-`-a | --add-timestamp ID:          append timestamp with ID\n`
-
-
-Additional changes
-------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* As always, general documentation, code cleanup, and refactoring
-* Remove doxygen config files and targets
-* Get clang compile working for all x86 platforms
-* Work on updating checkpatch to match the current Linux version
-* Timestamps: Rename timestamps to make names more consistent
-* Continue updating ACPI code to ASL 2.0
-* Remove redundant or unnecessary headers from C files
-* arch/x86/acpi_bert_storage.c: Use a common implementation
-* Postcar stage improvements
-* arch/x86/acpi: Consolidate POST code handling
-* intel/common: Enable ROM caching in ramstage
-* vendorcode/amd/agesa: Fix improper use of .data (const is important)
-* sandybridge & gm45: Support setting PCI bars above 4G
-
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the V4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the V4
-allocator.
-
-
-Plans for Code Deprecation
---------------------------
-
-
-### Intel Icelake
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever was
-the CRB board. From the looks of it the code never was ready for production as
-only engineering sample CPUIDs are supported.
-
-Thus, to reduce the maintanence overhead for the community, it is deprecated
-from this release on and support for the following components will be dropped
-with the release 4.19.
-
-  * Intel Icelake SoC
-  * Intel Icelake RVP mainboard
-
-
-### LEGACY_SMP_INIT
-
-As of release 4.18 (August 2022) we plan to deprecate LEGACY_SMP_INIT.
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-No platforms in the tree have any hardware limitations that would block
-migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
-
-
-Statistics
-----------
-
-- Total Commits: 1305
-- Average Commits per day: 13.42
-- Total lines added: 51422
-- Average lines added per commit: 39.40
-- Number of patches adding more than 100 lines: 59
-- Average lines added per small commit: 24.73
-- Total lines removed: 66206
-- Average lines removed per commit: 50.73
-- Total difference between added and removed: -14784
-- Total authors: 146
-- New authors: 17
+### Add significant changes here

Documentation/releases/coreboot-4.18-relnotes.md

@@ -1,288 +0,0 @@
-coreboot 4.18 release
-========================================================================
-
-The 4.18 release was quite late, but was completed on October 16, 2022.
-
-In the 4 months since the 4.17 release, the coreboot project has merged
-more than 1800 commits from over 200 different authors. Over 50 of those
-authors submitted their first patches.
-
-Welcome and thank you to all of our new contributors, and of course the
-work of all of the seasoned contributors is greatly appreciated.
-
-
-Significant or interesting changes
-----------------------------------
-
-### sconfig: Allow to specify device operations
-
-Currently we only have runtime mechanisms to assign device operations to
-a node in our devicetree (with one exception: the root device). The most
-common method is to map PCI IDs to the device operations with a `struct
-pci_driver`. Another accustomed way is to let a chip driver assign them.
-
-For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
-ID lists grew very large and are incredibly error-prone. Often, IDs are
-missing and sometimes IDs are added almost mechanically without checking
-the code for compatibility. Maintaining these lists in a central place
-also reduces flexibility.
-
-Now, for onboard devices it is actually unnecessary to assign the device
-operations at runtime. We already know exactly what operations should be
-assigned. And since we are using chipset devicetrees, we have a perfect
-place to put that information.
-
-This patch adds a simple mechanism to `sconfig`. It allows us to speci-
-fy operations per device, e.g.
-
-device pci 00.0 alias system_agent on
-	ops system_agent_ops
-end
-
-The operations are given as a C identifier. In this example, we simply
-assume that a global `struct device_operations system_agent_ops` exists.
-
-
-### Set touchpads to use detect (vs probed) flag
-
-Historically, ChromeOS devices have worked around the problem of OEMs
-using several different parts for touchpads/touchscreens by using a
-ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
-to indicate that the device may or may not be present, and that the
-driver should probe to confirm device presence.
-
-Since release 4.18, coreboot  supports detection for i2c devices at
-runtime when creating the device entries for the ACPI/SSDT tables,
-rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
-in the tree from using the 'probed' flag to the 'detect' flag.
-
-Touchscreens require more involved power sequencing, which will be done
-at some future time, after which they will switch over as well.
-
-
-### Add SBOM (Software Bill of Materials) Generation
-
-Firmware is typically delivered as one large binary image that gets
-flashed. Since this final image consists of binaries and data from a
-vast number of different people and companies, it's hard to determine
-what all the small parts included in it are. The goal of the software
-bill of materials (SBOM) is to take a firmware image and make it easy to
-find out what it consists of and where those pieces came from.
-
-Basically, this answers the question, who supplied the code that's
-running on my system right now? For example, buyers of a system can use
-an SBOM to perform an automated vulnerability check or license analysis,
-both of which can be used to evaluate risk in a product. Furthermore,
-one can quickly check to see if the firmware is subject to a new
-vulnerability included in one of the software parts (with the specified
-version) of the firmware.
-
-Further reference:
-https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
-
-- Add Makefile.inc to generate and build coswid tags
-- Add templates for most payloads, coreboot, intel-microcode,
-  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
-  intel ME and compiler (gcc,clang,other)
-- Add Kconfig entries to optionally supply a path to CoSWID tags
-  instead of using the default CoSWID tags
-- Add CBFS entry called SBOM to each build via Makefile.inc
-- Add goswid utility tool to generate SBOM data
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Allocator v4 is not yet ready, but received significant work.
-* Console: create an [smbus console driver](https://doc.coreboot.org/technotes/console.html)
-* pciexp_device: Numerous updates and fixes
-* Update checkpatch to match Linux v5.19
-* Continue updating ACPI to ASL 2.0 syntax
-* arch/x86: Add a common romstage entry point
-* Documentation: Add a list of [acronyms](https://doc.coreboot.org/acronyms.html)
-* Start hooking up ops in devicetree
-* Large amounts of general code cleanup and improvement, as always
-* Work to make sure all files have licenses
-
-
-Payloads
---------
-
-### EDK II (TianoCore)
-
-coreboot uses TianoCore interchangeably with EDK II, and whilst the
-meaning is generally clear, it's not the payload it uses.
-Consequentially, TianoCore has been renamed to EDK II (2).
-
-The option to use the already deprecated CorebootPayloadPkg has been
-removed.
-
-Recent changes to both coreboot and EDK means that UefiPayloadPkg seems
-to work on all hardware. It has been tested on:
-
-* Intel Core 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 8th, 9th, 10th,
-  11th and 12th generation processors
-* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
-* AMD Stoney Ridge and Picasso
-
-CorebootPayloadPkg can still be found [here](https://github.com/MrChromebox/edk2/tree/coreboot_fb).
-
-The recommended option to use is `EDK2_UEFIPAYLOAD_MRCHROMEBOX` as
-`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SoC.
-
-
-New Mainboards
---------------
-
-* AMD Birman
-* AMD Pademelon renamed from Padmelon
-* Google Evoker
-* Google Frostflow
-* Google Gaelin4ADL
-* Google Geralt
-* Google Joxer
-* Google Lisbon
-* Google Magikarp
-* Google Morthal
-* Google Pujjo
-* Google Rex 0
-* Google Shotzo
-* Google Skolas
-* Google Tentacruel
-* Google Winterhold
-* Google Xivu
-* Google Yaviks
-* Google Zoglin
-* Google Zombie
-* Google Zydron
-* MSI PRO Z690-A WIFI DDR4
-* Siemens MC APL7
-
-
-Removed Mainboards
-------------------
-
-* Google Brya4ES
-
-
-Updated SoCs
-------------
-
-* Added Intel Meteor Lake
-* Added Mediatek Mt8188
-* Renamed AMD Sabrina to Mendocino
-* Added AMD Morgana
-
-
-Plans for Code Deprecation
---------------------------
-
-### LEGACY_SMP_INIT
-
-Legacy SMP init will be removed from the coreboot master branch
-immediately following this release. Anyone looking for the latest
-version of the code should find it on the 4.18 branch or tag.
-
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the v4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the v4
-allocator.
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from commit d2d9021543 to f4c97ea131
------------------------------------------------
-
-- Total Commits: 1822
-- Average Commits per day: 13.38
-- Total lines added: 150578
-- Average lines added per commit: 82.64
-- Number of patches adding more than 100 lines: 128
-- Average lines added per small commit: 38.44
-- Total lines removed: 33849
-- Average lines removed per commit: 18.58
-- Total difference between added and removed: 116729
-- Total authors: 202
-- New authors: 52
-
-
-Known Issues
-------------
-
-A couple of issues were discovered immediately following the release
-that will be fixed in a follow-on point release in the upcoming weeks.
-
-A pair of changes ([CB:67754](https://review.coreboot.org/67754) and
-[CB:67662](https://review.coreboot.org/67662)) which merged shortly
-before the 4.18 release have created an issue on Intel Apollo Lake
-platform boards which prevents SMM/SMI from functioning; this affects
-only Apollo Lake (but not Gemini Lake) devices.
-See [CB:68599](https://review.coreboot.org/68599) for the fix.
-
-Another issue applies to all Intel-based boards with onboard I2C TPMs
-when verified boot is not enabled. The I2C buses don’t get initialized
-until after the TPM, causing timeouts, TPM initialization failures, and
-long boot times.  See [CB:68550](https://review.coreboot.org/68550) for
-the fix.

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,233 +0,0 @@
-Upcoming release - coreboot 4.19
-========================================================================
-
-The 4.19 release is planned for the 16th of January 2023.
-
-Since the last release, the coreboot project has merged over 1600
-commits from over 150 authors. Of those authors, around 25 were
-first-time committers to the coreboot project.
-
-As always, we are very grateful to all of the contributors for helping
-to keep the project going. The coreboot project is different from many
-open source projects in that we need to keep constantly updating the
-codebase to stay relevant with the latest processors and technologies.
-It takes constant effort to just stay afloat, let alone improve the
-codebase. Thank you very much to everyone who has contributed, both in
-this release and in previous times.
-
-The 4.20 release is planned for the 20th of April, 2023.
-
-
-Significant or interesting changes
-----------------------------------
-
-
-### Show all Kconfig options in saved config file; compress same
-
-The coreboot build system automatically adds a 'config' file to CBFS
-that lists the exact Kconfig configuration that the image was built
-with. This is useful to reproduce a build after the fact or to check
-whether support for a specific feature is enabled in the image.
-
-This file has been generated using the 'savedefconfig' Kconfig command,
-which generates the minimal .config file that is needed to produce the
-required config in a coreboot build. This is fine for reproduction, but
-bad when you want to check if a certain config was enabled, since many
-options get enabled by default or pulled in through another option's
-'select' statement and thus don't show up in the defconfig.
-
-Instead coreboot now includes a larger .config instead. In order to save
-some space, all of the comments disabling options are removed from the
-file, except for those included in the defconfig.
-
-We can also LZMA compress the file since it is never read by firmware
-itself and only intended for later re-extraction via cbfstool, which
-always has LZMA support included.
-
-
-### Toolchain updates
-
-* Upgrade LLVM from 15.0.0 to 15.0.6
-* Upgrade CMake from 3.24.2 to 3.25.0
-* Upgrade IASL from 20220331 to 20221020
-* Upgrade MPFR from 4.1.0 to 4.1.1
-
-
-### Finished the conversion to ASL 2.0 syntax
-
-Until recently, coreboot still contained lots of code using the legacy
-ASL syntax. However, all ASL code was ported over to make use of the ASL
-2.0 syntax and from this point on new ASL code should make use of it.
-
-
-Additional coreboot changes
----------------------------
-
-* Significant work was done to enable and build-test clang builds.
-* Added touchscreen power sequencing and runtime detection.
-* A number of patches were added to clean up and improve SMBIOS.
-* Work is in progress to unify and extend coreboot post codes.
-* Clean up for header includes is in progress with help from IWYU.
-* IOAPIC code has been reworked.
-* Support was added to superiotool for the NCT6687D-W chip.
-* Work is progressing to switch return values to enum cb_err instead of
-  bool or other pass/fail indicators.
-* Clang builds are now working for most boards and are being
-  build-tested.
-* 64-bit coreboot support is in progress and is working on a number of
-  platforms.
-* A driver for EC used on various Clevo laptops was added.
-* Native Intel Lynxpoint code was added to replace the MRC.bin.
-* Work continued for the process of adding ops structures to the
-  devicetree.
-* The crossgcc tool can now download the source packages, which are
-  needed to build the coreboot toolchain, from coreboot’s own mirror if
-  desired.
-* A document with useful external resources related to firmware
-  development was added at Documentation/external_docs.md.
-
-
-New Mainboards
---------------
-
-* AMD: Mayan for Phoenix SoC
-* GIGABYTE: GA-H61M-DS2
-* Google: Crystaldrift
-* Google: Gladios
-* Google: Dibbi
-* Google: Gaelin
-* Google: Marasov
-* Google: Markarth
-* Google: Omnigul
-* Google: Voltorb
-* Intel: Meteorlake-P RVP
-* MSI: PRO Z690-A (WIFI)
-* Siemens: MC_EHL3
-* Star Labs: StarBook Mk VI (i3-1220P and i7-1260P)
-* System76: darp8
-* System76: galp6
-
-
-Removed Mainboards
-------------------
-
-* AMD: Inagua
-* AMD: Olive Hill
-* AMD: Parmer
-* AMD: Persimmon
-* AMD: Southstation
-* AMD: Thatcher
-* AMD: Unionstation
-* ASROCK: E350M1
-* ASROCK: IMB-A180
-* ASUS: A88XM-E
-* ASUS: AM1I-A
-* ASUS: F2A85-M
-* ASUS: F2A85-M LE
-* ASUS: F2A85-M PRO
-* BAP: ODE_e20xx
-* Biostar: A68N-5200
-* Biostar: AM1ML
-* ELMEX: pcm205400
-* ELMEX: pcm205401
-* GizmoSphere: Gizmo
-* GizmoSphere: Gizmo2
-* Google: Morthal
-* HP: ABM
-* HP: Pavilion m6 1035dx
-* Jetway: NF81_T56N_LF
-* Lenovo: AMD G505s
-* LiPPERT: FrontRunner-AF aka ADLINK CoreModule2-GF
-* LiPPERT: Toucan-AF aka cExpress-GFR (+W83627DHG SIO)
-* MSI: MS-7721 (FM2-A75MA-E35)
-* PC Engines: APU1
-
-
-Updated SoCs
-------------
-
-* Added soc/amd/glinda
-* Renamed soc/amd/morgana to soc/amd/phoenix
-* Removed cpu/amd/agesa/family14
-* Removed cpu/amd/agesa/family15tn
-* Removed cpu/amd/agesa/family16kb
-
-
-Updated Chipsets
-----------------
-
-* Removed northbridge/amd/agesa/family14
-* Removed northbridge/amd/agesa/family15tn
-* Removed northbridge/amd/agesa/family16kb
-* Removed southbridge/amd/agesa/hudson
-* Removed southbridge/amd/cimx/sb800
-
-
-Payloads
---------
-
-* Updated GRUB from 2.04 to 2.06
-* Updated SeaBIOS 1.16.0 to 1.16.1
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained and the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of the
-code, it was never ready for production as only engineering sample
-CPUIDs are supported.
-
-Intel Icelake code will be removed following 4.19 and any maintenance
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed. Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintenance overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.18 to the 4.19 release
---------------------------------------------
-
-- Total Commits: 1608
-- Average Commits per day: 17.39
-- Total lines added: 93786
-- Average lines added per commit: 58.32
-- Number of patches adding more than 100 lines: 80
-- Average lines added per small commit: 38.54
-- Total lines removed: 768014
-- Total difference between added and removed: -674228
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-
-| #   | Subject                                                         |
-|-----|-----------------------------------------------------------------|
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-| 446 | Optiplex 9010 No Post                                           |
-| 445 | Thinkpad X200 wifi issue                                        |
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-| 427 | x200: Two battery charging issues                               |
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-| 412 | x230 reboots on suspend                                         |
-| 393 | T500 restarts rather than waking up from suspend                |
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |

Documentation/releases/coreboot-4.20-relnotes.md

@@ -1,67 +0,0 @@
-Upcoming release - coreboot 4.20
-========================================================================
-
-The 4.20 release is planned for the 20th of April 2023.
-
-
-The 4.21 release is planned for around the 17th of July, 2023
-
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-* This document may also be edited at the google doc copy:
-  https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
-
-Significant or interesting changes
-----------------------------------
-
-### Add changes that need a full description here
-
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-have so far failed.  The only user of this SoC ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.19 to the 4.20 release
---------------------------------------------
-
-* To be filled in immediately before the release by the release team
-
-
-Significant Known and Open Issues
----------------------------------
-
-* To be filled in immediately before the release by the release team
-

Documentation/releases/coreboot-4.6-relnotes.md

@@ -55,15 +55,15 @@ is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
 
 ### UEFI support: A long road to go
 
-coreboot can be used with the edk2 UEFI implementation which
+coreboot can be used with the Tianocore EDK2 UEFI implementation which
 is open source and available at Github. Sadly it is not currently
 integrated into the coreboot build. This has several reasons:
 
-* edk2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
-* Incompatibilities with code inside the edk2 which has not been updated.
+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the EDK2 which has not been updated.
 
 We started to make progress with the integration into our sources and
-the hope is that by the end of the summer, we finally support the edk2
+the hope is that by the end of the summer, we finally support the EDK2
 payload out-of-the- box. See the current patch state at
 http://review.coreboot.org/#/c/15057/