mb/system76: Use default GMA brightness levels

This reverts commit 1f81af52a4 ("mb/system76: Add custom backlight
levels for Intel GMA").

Defaulting to 40% can make the screen hard to read as System76's
firmware setup uses white text on a gray background.

Change-Id: I13ab3797319c4db6e800737a3f4e4344e3b588f3
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.gitmodules

@@ -1,70 +1,70 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk
 [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
 	path = src/vendorcode/amd/opensil/genoa_poc/opensil
-	url = ../opensil_genoa_poc.git
+	url = https://review.coreboot.org/opensil_genoa_poc.git

AUTHORS

@@ -39,9 +39,7 @@ Alexandru Gagniuc
 Alexey Buyanov
 Alexey Vazhnov
 Alice Sell
-Alicja Michalska
 Allen-KH Cheng
-Alper Nebi Yasak
 Amanda Hwang
 American Megatrends International, LLC
 Amersel
@@ -64,7 +62,6 @@ Anna Karaś
 Annie Chen
 Anton Kochkov
 Ao Zhong
-Appukuttan V K
 Arashk Mahshidfar
 Arec Kao
 Ariel Fang
@@ -96,7 +93,6 @@ Bora Guvendik
 Boris Barbulovski
 Boris Mittelberg
 Brandon Breitenstein
-Brandon Weeks
 Brian Norris
 Bryant Ou
 Carl-Daniel Hailfinger
@@ -105,7 +101,6 @@ Caveh Jalali
 Cavium Inc.
 Chao Gui
 Chen-Tsung Hsieh
-Chen. Gang C
 Chia-Ling Hou
 Chien-Chih Tseng
 Chris Wang
@@ -133,7 +128,6 @@ Da Lao
 Daisuke Nojiri
 Damien Zammit
 Dan Callaghan
-Dan Campbell
 Daniel Campello
 Daniel Gröber
 Daniel Kang
@@ -187,7 +181,6 @@ Eltan B.V
 Eltan B.V.
 Elyes Haouas
 Eran Mitrani
-Eren Peng
 Eric Biederman
 Eric Lai
 Eric Peers
@@ -201,16 +194,13 @@ Evan Green
 Evgeny Zinoviev
 Fabian Groffen
 Fabian Kunkel
-Fabian Meyer
 Fabio Aiuto
 Fabrice Bellard
 Facebook, Inc.
-Fei Yan
 Felix Friedlander
 Felix Held
 Felix Singer
 Fengquan Chen
-Filip Lewiński
 Flora Fu
 Florian Laufenböck
 Francois Toguo Fotso
@@ -224,7 +214,7 @@ Free Software Foundation, Inc.
 Freescale Semiconductor, Inc.
 Furquan Shaikh
 Gaggery Tsai
-Gang C Chen
+Gang C Chen 
 Garmin Chang
 Gary Jennejohn
 George Trudeau
@@ -244,7 +234,6 @@ HardenedLinux
 Harsha B R
 Harshit Sharma
 Henry C Chen
-Herbert Wu
 Hewlett Packard Enterprise Development LP
 Hewlett-Packard Development Company, L.P.
 Himanshu Sahdev
@@ -297,7 +286,6 @@ Jason Zhao
 jason-ch chen
 Jason-jh Lin
 Jay Patel
-Jean Lucas
 Jeff Chase
 Jeff Daly
 Jeff Li
@@ -319,7 +307,6 @@ Jitao Shi
 Joe Pillow
 Joe Tessler
 Joel Kitching
-Joel Linn
 Joey Peng
 Johanna Schander
 John Su
@@ -338,7 +325,6 @@ Jordan Crouse
 Jörg Mische
 Joseph Smith
 Josie Nordrum
-Juan José García-Castro Crespo
 Julia Tsai
 Julian Schroeder
 Julian Stecklina
@@ -351,7 +337,6 @@ Kangheui Won
 Kapil Porwal
 Karol Zmyslowski
 Karthik Ramasubramanian
-Kei Hiroyoshi
 Keith Hui
 Keith Packard
 Kenneth Chan
@@ -382,11 +367,9 @@ Lawrence Chang
 Leah Rowe
 Lean Sheng Tan
 Lei Wen
-Lennart Eichhorn
 Lenovo Group Ltd
 Leo Chou
 Li-Ta Lo
-Li1 Feng
 Liam Flaherty
 Libra Li
 Libretrend LDA
@@ -414,7 +397,6 @@ Marc Bertens
 Marc Jones
 Marco Chen
 Marek Kasiewicz
-Marek Maślanka
 Marek Vasut
 Mario Scheithauer
 Marius Gröger
@@ -483,12 +465,10 @@ Myles Watson
 Nancy.Lin
 Naresh Solanki
 Nathan Lu
-Naveen R. Iyer
 Neill Corlett
 Network Appliance Inc.
 Nicholas Chin
 Nicholas Sielicki
-Nicholas Sudsgaard
 Nick Barker
 Nick Chen
 Nick Vaccaro
@@ -522,7 +502,6 @@ Paul Fagerburg
 Paul Menzel
 Paul2 Huang
 Paulo Alcantara
-Pavan Holla
 Pavel Sayekat
 Paz Zcharya
 PC Engines GmbH
@@ -541,7 +520,6 @@ Philipp Deppenwiese
 Philipp Hug
 Piotr Kleinschmidt
 Po Xu
-Poornima Tom
 Prasad Malisetty
 Prashant Malani
 Pratik Vishwakarma
@@ -551,7 +529,6 @@ Protectli
 Purism SPC
 Purism, SPC
 Qii Wang
-Qinghong Zeng
 Qualcomm Technologies, Inc.
 Quanta Computer INC
 Raihow Shi
@@ -595,7 +572,6 @@ Robinson P. Tryon
 Rockchip, Inc.
 Rocky Phagura
 Roger Lu
-Roger Wang
 Roja Rani Yarubandi
 Romain Lievin
 Roman Zippel
@@ -769,14 +745,12 @@ Wojciech Macek
 Wolfgang Denk
 Won Chung
 Wonkyu Kim
-Wuxy
+Wuxy 
-Xiang W
 Xin Ji
 Xixi Chen
 Xuxin Xiong
 YADRO
 Yan Liu
-Yang Wu
 Yann Collet
 Yaroslav Kurlaev
 YH Lin
@@ -793,7 +767,6 @@ Yuanliding
 Yuchen He
 Yuchen Huang
 Yunlong Jia
-Yuval Peress
 Zachary Yedidia
 Zanxi Chen
 Zhanyong Wang
@@ -803,11 +776,10 @@ Zhi7 Li
 Zhiqiang Ma
 Zhixing Ma
 Zhiyong Tao
-Zhongtian Wu
+zhongtian wu
 Zhuohao Lee
 Ziang Wang
 Zoey Wu
 Zoltan Baldaszti
 小田喜陽彦
-忧郁沙茶
 陳建宏

Documentation/Makefile.sphinx

@@ -1,20 +1,60 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-# Minimal makefile for Sphinx documentation
+# Makefile for Sphinx documentation
 #
 
-# You can set these variables from the command line, and also
+# You can set these variables from the command line.
-# from the environment for the first two.
+SPHINXOPTS        ?=
-SPHINXOPTS    ?=
+SPHINXBUILD       = sphinx-build
-SPHINXBUILD   ?= sphinx-build
+SPHINXAUTOBUILD   = sphinx-autobuild
-SPHINXAUTOBUILD = sphinx-autobuild
+PAPER             =
-SOURCEDIR     = .
+BUILDDIR          = _build
-BUILDDIR      = _build
 
-# Put it first so that "make" without argument is like "make help".
+# Internal variables.
+PAPEROPT_a4     = -D latex_paper_size=a4
+PAPEROPT_letter = -D latex_paper_size=letter
+ALLSPHINXOPTS   = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
+# the i18n builder cannot share the environment and doctrees with the others
+I18NSPHINXOPTS  = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
+
+.PHONY: help
 help:
-	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+	@echo "Please use \`make <target>' where <target> is one of"
+	@echo "  html       to make standalone HTML files"
+	@echo "  dirhtml    to make HTML files named index.html in directories"
+	@echo "  singlehtml to make a single large HTML file"
+	@echo "  pickle     to make pickle files"
+	@echo "  json       to make JSON files"
+	@echo "  htmlhelp   to make HTML files and a HTML help project"
+	@echo "  qthelp     to make HTML files and a qthelp project"
+	@echo "  applehelp  to make an Apple Help Book"
+	@echo "  devhelp    to make HTML files and a Devhelp project"
+	@echo "  epub       to make an epub"
+	@echo "  epub3      to make an epub3"
+	@echo "  latex      to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
+	@echo "  latexpdf   to make LaTeX files and run them through pdflatex"
+	@echo "  latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
+	@echo "  text       to make text files"
+	@echo "  man        to make manual pages"
+	@echo "  texinfo    to make Texinfo files"
+	@echo "  info       to make Texinfo files and run them through makeinfo"
+	@echo "  gettext    to make PO message catalogs"
+	@echo "  changes    to make an overview of all changed/added/deprecated items"
+	@echo "  xml        to make Docutils-native XML files"
+	@echo "  pseudoxml  to make pseudoxml-XML files for display purposes"
+	@echo "  linkcheck  to check all external links for integrity"
+	@echo "  doctest    to run all doctests embedded in the documentation (if enabled)"
+	@echo "  coverage   to run coverage check of the documentation (if enabled)"
+	@echo "  dummy      to check syntax errors of document sources"
 
-.PHONY: help Makefile.sphinx
+.PHONY: clean
+clean:
+	rm -rf $(BUILDDIR)
+
+.PHONY: html
+html:
+	$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
+	@echo
+	@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
 
 .PHONY: livehtml
 livehtml:
@@ -23,7 +63,172 @@ livehtml:
 	@echo
 	$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
 
-# Catch-all target: route all unknown targets to Sphinx using the new
+.PHONY: dirhtml
-# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+dirhtml:
-%: Makefile.sphinx
+	$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
-	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+	@echo
+	@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
+
+.PHONY: singlehtml
+singlehtml:
+	$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
+	@echo
+	@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
+
+.PHONY: pickle
+pickle:
+	$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
+	@echo
+	@echo "Build finished; now you can process the pickle files."
+
+.PHONY: json
+json:
+	$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
+	@echo
+	@echo "Build finished; now you can process the JSON files."
+
+.PHONY: htmlhelp
+htmlhelp:
+	$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
+	@echo
+	@echo "Build finished; now you can run HTML Help Workshop with the" \
+	      ".hhp project file in $(BUILDDIR)/htmlhelp."
+
+.PHONY: qthelp
+qthelp:
+	$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp
+	@echo
+	@echo "Build finished; now you can run "qcollectiongenerator" with the" \
+	      ".qhcp project file in $(BUILDDIR)/qthelp, like this:"
+	@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/coreboot.qhcp"
+	@echo "To view the help file:"
+	@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/coreboot.qhc"
+
+.PHONY: applehelp
+applehelp:
+	$(SPHINXBUILD) -b applehelp $(ALLSPHINXOPTS) $(BUILDDIR)/applehelp
+	@echo
+	@echo "Build finished. The help book is in $(BUILDDIR)/applehelp."
+	@echo "N.B. You won't be able to view it unless you put it in" \
+	      "~/Library/Documentation/Help or install it in your application" \
+	      "bundle."
+
+.PHONY: devhelp
+devhelp:
+	$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp
+	@echo
+	@echo "Build finished."
+	@echo "To view the help file:"
+	@echo "# mkdir -p $$HOME/.local/share/devhelp/coreboot"
+	@echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/coreboot"
+	@echo "# devhelp"
+
+.PHONY: epub
+epub:
+	$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
+	@echo
+	@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
+
+.PHONY: epub3
+epub3:
+	$(SPHINXBUILD) -b epub3 $(ALLSPHINXOPTS) $(BUILDDIR)/epub3
+	@echo
+	@echo "Build finished. The epub3 file is in $(BUILDDIR)/epub3."
+
+.PHONY: latex
+latex:
+	$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
+	@echo
+	@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
+	@echo "Run \`make' in that directory to run these through (pdf)latex" \
+	      "(use \`make latexpdf' here to do that automatically)."
+
+.PHONY: latexpdf
+latexpdf:
+	$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
+	@echo "Running LaTeX files through pdflatex..."
+	$(MAKE) -C $(BUILDDIR)/latex all-pdf
+	@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
+
+.PHONY: latexpdfja
+latexpdfja:
+	$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
+	@echo "Running LaTeX files through platex and dvipdfmx..."
+	$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
+	@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
+
+.PHONY: text
+text:
+	$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
+	@echo
+	@echo "Build finished. The text files are in $(BUILDDIR)/text."
+
+.PHONY: man
+man:
+	$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
+	@echo
+	@echo "Build finished. The manual pages are in $(BUILDDIR)/man."
+
+.PHONY: texinfo
+texinfo:
+	$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
+	@echo
+	@echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
+	@echo "Run \`make' in that directory to run these through makeinfo" \
+	      "(use \`make info' here to do that automatically)."
+
+.PHONY: info
+info:
+	$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
+	@echo "Running Texinfo files through makeinfo..."
+	make -C $(BUILDDIR)/texinfo info
+	@echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
+
+.PHONY: gettext
+gettext:
+	$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
+	@echo
+	@echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
+
+.PHONY: changes
+changes:
+	$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
+	@echo
+	@echo "The overview file is in $(BUILDDIR)/changes."
+
+.PHONY: linkcheck
+linkcheck:
+	$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
+	@echo
+	@echo "Link check complete; look for any errors in the above output " \
+	      "or in $(BUILDDIR)/linkcheck/output.txt."
+
+.PHONY: doctest
+doctest:
+	$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
+	@echo "Testing of doctests in the sources finished, look at the " \
+	      "results in $(BUILDDIR)/doctest/output.txt."
+
+.PHONY: coverage
+coverage:
+	$(SPHINXBUILD) -b coverage $(ALLSPHINXOPTS) $(BUILDDIR)/coverage
+	@echo "Testing of coverage in the sources finished, look at the " \
+	      "results in $(BUILDDIR)/coverage/python.txt."
+
+.PHONY: xml
+xml:
+	$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
+	@echo
+	@echo "Build finished. The XML files are in $(BUILDDIR)/xml."
+
+.PHONY: pseudoxml
+pseudoxml:
+	$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
+	@echo
+	@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
+
+.PHONY: dummy
+dummy:
+	$(SPHINXBUILD) -b dummy $(ALLSPHINXOPTS) $(BUILDDIR)/dummy
+	@echo
+	@echo "Build finished. Dummy builder generates no files."

Documentation/acpi/index.md

@@ -5,34 +5,18 @@ backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and
 upwards.
 
 
-```{toctree}
+- [SSDT UID generation](uid.md)
-:maxdepth: 1
-
-SSDT UID generation <uid.md>
-```
 
 ## GPIO
 
-```{toctree}
+- [GPIO toggling in ACPI AML](gpio.md)
-:maxdepth: 1
-
-GPIO toggling in ACPI AML <gpio.md>
-```
 
 ## Windows-specific ACPI documentation
 
-```{toctree}
+- [Windows-specific documentation](windows.md)
-:maxdepth: 1
-
-Windows-specific documentation <windows.md>
-```
 
 ##  ACPI specification - Useful links
 
-```{toctree}
+- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
-:maxdepth: 1
+- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
-
+- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
-ACPI Specification 6.5 <https://uefi.org/specs/ACPI/6.5/index.html>
-ASL 2.0 Syntax <https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions>
-Predefined ACPI Names <https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names>
-```

Documentation/acronyms.md

@@ -1141,8 +1141,4 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 
 ## References:
-```{toctree}
+* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf)
-:maxdepth: 1
-
-AMD Glossary of terms <https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf>
-```

Documentation/arch/index.md

@@ -5,15 +5,7 @@ architectures.
 
 ## RISC-V
 
-```{toctree}
+- [RISC-V documentation](riscv/index.md)
-:maxdepth: 1
-
-RISC-V documentation <riscv/index.md>
-```
 
 ## x86
-```{toctree}
+- [x86 documentation](x86/index.md)
-:maxdepth: 1
-
-x86 documentation <x86/index.md>
-```

Documentation/arch/x86/index.md

@@ -2,14 +2,12 @@
 
 This section contains documentation about coreboot on x86 architecture.
 
-```{toctree}
+* [x86 PAE support](pae.md)
-:maxdepth: 1
-
-x86 PAE support <pae.md>
-```
 
 ## State of x86_64 support
-Some SOCs now support 64bit mode. Search for HAVE_X86_64_SUPPORT in Kconfig.
+At the moment there's only experimental x86_64 support.
+The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support
+*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*.
 
 In order to add support for x86_64 the following assumptions were made:
 * The CPU supports long mode
@@ -17,6 +15,7 @@ In order to add support for x86_64 the following assumptions were made:
 * All code that is to be run must be below 4GiB in physical memory
 * The high dword of pointers is always zero
 * The reference implementation is qemu
+* The CPU supports 1GiB hugepages
 * x86 payloads are loaded below 4GiB in physical memory and are jumped
   to in *protected mode*
 
@@ -44,12 +43,8 @@ Basic support for x86_64 has been implemented for QEMU mainboard target.
 
 ## Reference implementation
 The reference implementation is
-```{toctree}
+* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md)
-:maxdepth: 1
+* [QEMU Q35](../../mainboard/emulation/qemu-q35.md)
-
-QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md>
-QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
-```
 
 ## TODO
 * Identity map memory above 4GiB in ramstage
@@ -59,6 +54,7 @@ QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
 1. Fine grained page tables for SMM:
    * Must not have execute and write permissions for the same page.
    * Must allow only that TSEG pages can be marked executable
+   * Must reside in SMRAM
 2. Support 64bit PCI BARs above 4GiB
 3. Place and run code above 4GiB
 
@@ -66,10 +62,13 @@ QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
 * Fix compilation errors
 * Test how well CAR works with x86_64 and paging
 * Improve mode switches
+* Test libgfxinit / VGA Option ROMs / FSP
 
-## Known problems on real hardware
+## Known bugs on real hardware
 
-Running VGA rom directly fails. Yabel works fine though.
+According to Intel x86_64 mode hasn't been validated in CAR environments.
+Until now it could be verified on various Intel platforms and no issues have
+been found.
 
 ## Known bugs on KVM enabled qemu
 

Documentation/community/index.md

@@ -1,10 +1,6 @@
 # Community
 
-```{toctree}
+* [Code of Conduct](code_of_conduct.md)
-:maxdepth: 1
+* [Language style](language_style.md)
-
+* [Community forums](forums.md)
-Code of Conduct <code_of_conduct.md>
+* [coreboot at conferences](conferences.md)
-Language style <language_style.md>
-Community forums <forums.md>
-coreboot at conferences <conferences.md>
-```

Documentation/conf.py

@@ -1,34 +1,46 @@
-# Configuration file for the Sphinx documentation builder.
+# -*- coding: utf-8 -*-
-#
-# For the full list of built-in configuration values, see the documentation:
-# https://www.sphinx-doc.org/en/master/usage/configuration.html
-
-# -- Project information -----------------------------------------------------
-# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
-
 import subprocess
+from recommonmark.parser import CommonMarkParser
+import sphinx
 
-project = 'coreboot'
+# Get Sphinx version
-copyright = 'CC-by 4.0 the coreboot project'
+major = 0
-author = 'the coreboot project'
+minor = 0
+patchlevel = 0
+version = sphinx.__version__.split(".")
+if len(version) > 1:
+	major = int(version[0])
+	minor = int(version[1])
+	if len(version) > 2:
+		patchlevel = int(version[2])
 
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# The suffix(es) of source filenames.
+source_suffix = ['.md']
+
+# The master toctree document.
+master_doc = 'index'
+
+# General information about the project.
+project = u'coreboot'
+copyright = u'CC-by 4.0 the coreboot project'
+author = u'the coreboot project'
+
+# The version info for the project you're documenting, acts as replacement for
+# |version| and |release|, also used in various other places throughout the
+# built documents.
+#
+# The full version, including alpha/beta/rc tags.
 release = subprocess.check_output(('git', 'describe')).decode("utf-8")
 # The short X.Y version.
 version = release.split("-")[0]
 
-
+extensions = []
-# -- General configuration ---------------------------------------------------
+# Load recommonmark, supported since 1.8+
-# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
+if major >= 2 or (major == 1 and minor >= 8):
-
+    extensions += ['recommonmark']
-extensions = ["myst_parser"]
-
-myst_heading_anchors = 5
-
-templates_path = ['_templates']
-exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
-
-# The name of the Pygments (syntax highlighting) style to use.
-pygments_style = 'sphinx'
 
 # Try to load DITAA
 try:
@@ -45,11 +57,62 @@ else:
 # Usually you set "language" from the command line for these cases.
 language = 'en'
 
-# -- Options for HTML output -------------------------------------------------
+# List of patterns, relative to source directory, that match files and
-# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
+# directories to ignore when looking for source files.
+# This patterns also effect to html_static_path and html_extra_path
+exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
 
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = 'sphinx'
+
+# A list of ignored prefixes for module index sorting.
+# modindex_common_prefix = []
+
+# If true, keep warnings as "system message" paragraphs in the built documents.
+# keep_warnings = False
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = False
+
+
+# -- Options for HTML output ----------------------------------------------
+
+# The theme to use for HTML and HTML Help pages.  See the documentation for
+# a list of builtin themes.
+#
 html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']
+
 html_css_files = [
     'theme_overrides.css',  # override wide tables in RTD theme
 ]
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = 'corebootdoc'
+
+enable_auto_toc_tree = True
+
+class MyCommonMarkParser(CommonMarkParser):
+    # remove this hack once upstream RecommonMark supports inline code
+    def visit_code(self, mdnode):
+        from docutils import nodes
+        n = nodes.literal(mdnode.literal, mdnode.literal)
+        self.current_node.append(n)
+
+def setup(app):
+    from recommonmark.transform import AutoStructify
+    # Load recommonmark on old Sphinx
+    if major == 1 and minor < 8:
+        app.add_source_parser('.md', MyCommonMarkParser)
+
+    app.add_config_value('recommonmark_config', {
+        'enable_auto_toc_tree': True,
+        'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
+        'enable_eval_rst': True,
+        'url_resolver': lambda url: '/' + url
+    }, True)
+    app.add_transform(AutoStructify)

Documentation/contributing/gerrit_guidelines.md

@@ -395,8 +395,8 @@ Gerrit user roles
 There are a few relevant roles a user can have on Gerrit:
 
 - The anonymous user can check out source code.
-- A registered user can also comment and give "+1" code reviews.
+- A registered user can also comment and give "+1" and "-1" code reviews.
-- A reviewer can give "-1" and "+2" code reviews.
+- A reviewer can also give "+2" code reviews.
 - A core developer can also give "-2" (that is, blocking) code reviews
   and submit changes.
 

Documentation/contributing/index.md

@@ -1,11 +1,7 @@
 # Contributing
 
-```{toctree}
+* [Coding Style](coding_style.md)
-:maxdepth: 1
+* [Gerrit Guidelines](gerrit_guidelines.md)
-
+* [Project Ideas](project_ideas.md)
-Coding Style <coding_style.md>
+* [Documentation Ideas](documentation_ideas.md)
-Gerrit Guidelines <gerrit_guidelines.md>
+* [Google Summer of Code](gsoc.md)
-Project Ideas <project_ideas.md>
-Documentation Ideas <documentation_ideas.md>
-Google Summer of Code <gsoc.md>
-```

Documentation/drivers/index.md

@@ -8,14 +8,10 @@ For details on how to connect device drivers to a mainboard, see [Driver Devicet
 
 Some of the drivers currently available include:
 
-```{toctree}
+* [Intel DPTF](dptf.md)
-:maxdepth: 1
+* [IPMI KCS](ipmi_kcs.md)
-
+* [SMMSTORE](smmstore.md)
-Intel DPTF <dptf.md>
+* [SMMSTOREv2](smmstorev2.md)
-IPMI KCS <ipmi_kcs.md>
+* [SoundWire](soundwire.md)
-SMMSTORE <smmstore.md>
+* [USB4 Retimer](retimer.md)
-SMMSTOREv2 <smmstorev2.md>
+* [CBFS SMBIOS hooks](cbfs_smbios.md)
-SoundWire <soundwire.md>
-USB4 Retimer <retimer.md>
-CBFS SMBIOS hooks <cbfs_smbios.md>
-```

Documentation/drivers/smmstore.md

@@ -128,11 +128,7 @@ data or modify the currently running kernel.*
 
 ## External links
 
-```{toctree}
+* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
-:maxdepth: 1
-
-A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
-```
 Note, this differs significantly from coreboot's implementation.
 
 [SMM]: ../security/smm.md

Documentation/drivers/smmstorev2.md

@@ -124,9 +124,25 @@ additional calling arguments are passed via `%ebx`.
 **NOTE**: The size of the struct entries are in the native word size of
 smihandler. This means 32 bits in almost all cases.
 
-#### - SMMSTORE_CMD_INIT_DEPRECATED = 4
+#### - SMMSTORE_CMD_INIT = 4
 
-Unused, returns SMMSTORE_REG_UNSUPPORTED.
+This installs the communication buffer to use and thus enables the
+SMMSTORE handler. This command can only be executed once and is done
+by the firmware. Calling this function at runtime has no effect.
+
+The additional parameter buffer `%ebx` contains a pointer to the
+following struct:
+
+```C
+struct smmstore_params_init {
+	uint32_t com_buffer;
+	uint32_t com_buffer_size;
+} __packed;
+```
+
+INPUT:
+- `com_buffer`: Physical address of the communication buffer (CBMEM)
+- `com_buffer_size`: Size in bytes of the communication buffer
 
 #### - SMMSTORE_CMD_RAW_READ = 5
 
@@ -199,11 +215,7 @@ running kernel.
 
 ## External links
 
-```{toctree}
+* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
-:maxdepth: 1
-
-A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
-```
 Note that this differs significantly from coreboot's implementation.
 
 [SMM]: ../security/smm.md

Documentation/external_docs.md

@@ -17,21 +17,13 @@ Please add any helpful or informational links and sections as you see fit.
   * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
   * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
   * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
-```{toctree}
+* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
-:maxdepth: 1
-
-Boot Guard and PSB have user-hostile defaults <https://mjg59.dreamwidth.org/58424.html>
-```
 
 
 ## General Information
 
-```{toctree}
+* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
-:maxdepth: 1
+* [Interface BUS](http://www.interfacebus.com/)
-
-OS Dev <https://wiki.osdev.org/Categorized_Main_Page>
-Interface BUS <http://www.interfacebus.com/>
-```
 
 ## OpenSecurityTraining2
 
@@ -51,14 +43,10 @@ modified works back to the community.
 Below is a list of currently available courses that can help understand the
 inner workings of coreboot and other firmware-related topics:
 
-```{toctree}
+* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-:maxdepth: 1
+* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-
+* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-coreboot design principles and boot process <https://ost2.fyi/Arch4031>
+* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-x86-64 Assembly <https://ost2.fyi/Arch1001>
-x86-64 OS Internals <https://ost2.fyi/Arch2001>
-x86-64 Intel Firmware Attack & Defense <https://ost2.fyi/Arch4001>
-```
 
 There are [additional security courses](https://p.ost2.fyi/courses) at the site
 as well (such as
@@ -66,79 +54,47 @@ as well (such as
 
 ## Firmware Specifications & Information
 
-```{toctree}
+* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
-:maxdepth: 1
+* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
-
+* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
-System Management BIOS - SMBIOS <https://www.dmtf.org/standards/smbios>
-Desktop and Mobile Architecture for System Hardware - DASH <https://www.dmtf.org/standards/dash>
-PNP BIOS <https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf>
-```
 
 
 ### ACPI
 
-```{toctree}
+* [ACPI Specs](https://uefi.org/acpi/specs)
-:maxdepth: 1
+* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
-
+* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
-ACPI Specs <https://uefi.org/acpi/specs>
+* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
-ACPI in Linux <https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf>
-ACPI 5 Linux <https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf>
-ACPI 6 Linux <https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf>
-```
 
 
 ### Security
 
-```{toctree}
+* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
-:maxdepth: 1
-
-Intel Boot Guard <https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard>
-```
 
 
 ## Hardware information
 
-```{toctree}
+* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
-:maxdepth: 1
+* [Sandpile](https://www.sandpile.org/)
-
+* [CPU-World](https://www.cpu-world.com/index.html)
-WikiChip <https://en.wikichip.org/wiki/WikiChip>
+* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
-Sandpile <https://www.sandpile.org/>
-CPU-World <https://www.cpu-world.com/index.html>
-CPU-Upgrade <https://www.cpu-upgrade.com/index.html>
-```
 
 
 ### Hardware Specifications & Standards
 
 * [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
-```{toctree}
+* [eMMC](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-:maxdepth: 1
-
-eMMC <https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED>
-```
 * [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
 * [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
   [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
 * [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
-```{toctree}
+* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
-:maxdepth: 1
+* [Memory](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-
-I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED>
-Memory <https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED>
-```
 * [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
 * [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
-```{toctree}
+* [PCI / PCIe / M.2](https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED)
-:maxdepth: 1
-
-PCI / PCIe / M.2 <https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED>
-```
 * [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
-```{toctree}
+* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
-:maxdepth: 1
-
-SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED>
-```
 * [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
 * [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
 * [USB](https://www.usb.org/documents) - USB Implementers Forum
@@ -177,9 +133,5 @@ SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN RE
 
 ## Infrastructure software
 
-```{toctree}
+* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
-:maxdepth: 1
+* [GNU Make](https://www.gnu.org/software/make/manual/)
-
-Kconfig <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>
-GNU Make <https://www.gnu.org/software/make/manual/>
-```

Documentation/getting_started/build_system.md

@@ -75,7 +75,7 @@ $(call add_intermediate, add_mrc_data)
 
 Note that the second line must start with a tab, not spaces.
 
-```{eval-rst}
+```eval_rst
 See also :doc:`../tutorial/managing_local_additions`.
 ```
 

Documentation/getting_started/gpio.md

@@ -167,7 +167,7 @@ could cause catastrophic failures, up to and including your mainboard!
 As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
 supports four different types of GPIO reset as:
 
-```{eval-rst}
+```eval_rst
 +------------------------+----------------+-------------+-------------+
 |                        |                |         PAD Reset ?       |
 + PAD Reset Config       + Platform Reset +-------------+-------------+

Documentation/getting_started/index.md

@@ -1,14 +1,10 @@
 # Getting Started
 
-```{toctree}
+* [coreboot architecture](architecture.md)
-:maxdepth: 1
+* [Build System](build_system.md)
-
+* [Submodules](submodules.md)
-coreboot architecture <architecture.md>
+* [Kconfig](kconfig.md)
-Build System <build_system.md>
+* [Writing Documentation](writing_documentation.md)
-Submodules <submodules.md>
+* [Setting up GPIOs](gpio.md)
-Kconfig <kconfig.md>
+* [Adding devices to a device tree](devicetree.md)
-Writing Documentation <writing_documentation.md>
+* [Frequently Asked Questions](faq.md)
-Setting up GPIOs <gpio.md>
-Adding devices to a device tree <devicetree.md>
-Frequently Asked Questions <faq.md>
-```

Documentation/getting_started/kconfig.md

@@ -11,12 +11,8 @@ configuration front end in coreboot today.
 
 The official Kconfig source and documentation is kept at kernel.org:
 
-```{toctree}
+- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig)
-:maxdepth: 1
+- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
-
-Kconfig source <https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig>
-Kconfig Language Documentation <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt>
-```
 
 The advantage to using Kconfig is that it allows users to easily select the
 high level features of the project to be enabled or disabled at build time.

Documentation/gfx/display-panel.md

@@ -22,7 +22,7 @@ the power sequence timing parameters, which are usually named T[N] and also
 referenced in Intel's respective registers listing. You need the values for
 `PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`:
 
-```{eval-rst}
+```eval_rst
 +-----------------------------+---------------------------------------+-----+
 | Intel docs                  | devicetree.cb                         | eDP |
 +-----------------------------+---------------------------------------+-----+

Documentation/index.md

@@ -170,38 +170,34 @@ for example OpenBSD, is probably the closest cousin of our approach.
 
 Contents:
 
-```{toctree}
+* [Getting Started](getting_started/index.md)
-:maxdepth: 1
+* [Tutorial](tutorial/index.md)
-
+* [Contributing](contributing/index.md)
-Getting Started <getting_started/index.md>
+* [Community](community/index.md)
-Tutorial <tutorial/index.md>
+* [Payloads](payloads.md)
-Contributing <contributing/index.md>
+* [Distributions](distributions.md)
-Community <community/index.md>
+* [Technotes](technotes/index.md)
-Payloads <payloads.md>
+* [ACPI](acpi/index.md)
-Distributions <distributions.md>
+* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
-Technotes <technotes/index.md>
+* [Display panel](gfx/display-panel.md)
-ACPI <acpi/index.md>
+* [CPU Architecture](arch/index.md)
-Native Graphics Initialization with libgfxinit <gfx/libgfxinit.md>
+* [Platform independent drivers](drivers/index.md)
-Display panel <gfx/display-panel.md>
+* [Northbridge](northbridge/index.md)
-CPU Architecture <arch/index.md>
+* [System on Chip](soc/index.md)
-Platform independent drivers <drivers/index.md>
+* [Mainboard](mainboard/index.md)
-Northbridge <northbridge/index.md>
+* [Payloads](lib/payloads/index.md)
-System on Chip <soc/index.md>
+* [Libraries](lib/index.md)
-Mainboard <mainboard/index.md>
+* [Options](lib/option.md)
-Payloads <lib/payloads/index.md>
+* [Security](security/index.md)
-Libraries <lib/index.md>
+* [SuperIO](superio/index.md)
-Options <lib/option.md>
+* [Vendorcode](vendorcode/index.md)
-Security <security/index.md>
+* [Utilities](util.md)
-SuperIO <superio/index.md>
+* [Software Bill of Materials](sbom/sbom.md)
-Vendorcode <vendorcode/index.md>
+* [Project infrastructure & services](infrastructure/index.md)
-Utilities <util.md>
+* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
-Software Bill of Materials <sbom/sbom.md>
+* [Release notes](releases/index.md)
-Project infrastructure & services <infrastructure/index.md>
+* [Acronyms & Definitions](acronyms.md)
-Boards supported in each release directory <releases/boards_supported_on_branches.md>
+* [External Resources](external_docs.md)
-Release notes <releases/index.md>
+* [Documentation License](documentation_license.md)
-Acronyms & Definitions <acronyms.md>
-External Resources <external_docs.md>
-Documentation License <documentation_license.md>
-```
 
 [Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Documentation/

Documentation/infrastructure/builders.md

@@ -93,19 +93,11 @@ You can see all the builds in the main jenkins interface:
 Most of the time on the builders is taken up by the coreboot main and
 coreboot gerrit builds.
 
-```{toctree}
+* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
-:maxdepth: 1
-
-coreboot gerrit build <https://qa.coreboot.org/job/coreboot-gerrit/>
-```
 ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
 
 
-```{toctree}
+* [coreboot main build](https://qa.coreboot.org/job/coreboot/)
-:maxdepth: 1
-
-coreboot main build <https://qa.coreboot.org/job/coreboot/>
-```
  ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
 
 

Documentation/infrastructure/index.md

@@ -4,17 +4,9 @@ This section contains documentation about our infrastructure
 
 ## Services
 
-```{toctree}
+* [Project services](services.md)
-:maxdepth: 1
+* [Administrator's handbook](admin.md)
-
-Project services <services.md>
-Administrator's handbook <admin.md>
-```
 
 ## Jenkins builders and builds
-```{toctree}
+* [Setting up Jenkins build machines](builders.md)
-:maxdepth: 1
+* [Coverity Scan integration](coverity.md)
-
-Setting up Jenkins build machines <builders.md>
-Coverity Scan integration <coverity.md>
-```

Documentation/lib/index.md

@@ -3,11 +3,7 @@
 This section contains documentation about coreboot internal technical
 information and libraries.
 
-```{toctree}
+- [Flashmap and Flashmap Descriptor](flashmap.md)
-:maxdepth: 1
+- [ABI data consumption](abi-data-consumption.md)
-
+- [Timestamps](timestamp.md)
-Flashmap and Flashmap Descriptor <flashmap.md>
+- [Firmware Configuration Interface](fw_config.md)
-ABI data consumption <abi-data-consumption.md>
-Timestamps <timestamp.md>
-Firmware Configuration Interface <fw_config.md>
-```

Documentation/lib/payloads/index.md

@@ -8,8 +8,4 @@ selected mainboard.
 
 ## FIT
 
-```{toctree}
+- [uImage.FIT support](fit.md)
-:maxdepth: 1
-
-uImage.FIT support <fit.md>
-```

Documentation/mainboard/acer/g43t-am3.md

@@ -5,7 +5,7 @@ Acer models Aspire M3800, Aspire M5800 and possibly more.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | Intel G43 (called x4x in coreboot code)          |
 +------------------+--------------------------------------------------+
@@ -69,7 +69,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +-------------------+---------------------+
 | Type              | Value               |
 +===================+=====================+
@@ -122,7 +122,7 @@ $ sudo flashrom \
   -w coreboot.rom
 ```
 
-```{eval-rst}
+```eval_rst
 In addition to the information here, please see the
 :doc:`../../tutorial/flashing_firmware/index`.
 ```

Documentation/mainboard/amd/pademelon/pademelon.md

@@ -33,7 +33,7 @@ Three items are marked in this picture
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------+
 | Type                | Value              |
 +=====================+====================+
@@ -53,7 +53,7 @@ Three items are marked in this picture
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +---------------+------------------------------+
 | Fan control   | Using fintek F81803A         |
 +---------------+------------------------------+
@@ -63,7 +63,7 @@ Three items are marked in this picture
 
 ## Description of pictures within this document
 
-```{eval-rst}
+```eval_rst
 +----------------------------+----------------------------------------+
 |pademelon.jpg               | Motherboard with components identified |
 +----------------------------+----------------------------------------+

Documentation/mainboard/asrock/h110m-dvs.md

@@ -11,7 +11,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
 
 FSP Information:
 
-```{eval-rst}
+```eval_rst
 +-----------------------------+-------------------+-------------------+
 | FSP Project Name            | Directory         | Specification     |
 +-----------------------------+-------------------+-------------------+
@@ -114,7 +114,7 @@ facing towards the bottom of the board.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Skylake/Kaby Lake (LGA1151)                |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asrock/h77pro4-m.md

@@ -5,7 +5,7 @@ Bridge and Ivy Bridge CPUs.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+
@@ -71,7 +71,7 @@ extlinux
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -115,7 +115,7 @@ $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
 The use of `--noverify-all` is required since the Management Engine
 region is not readable even by the host.
 
-```{eval-rst}
+```eval_rst
 In addition to the information here, please see the
 :doc:`../../tutorial/flashing_firmware/index`.
 ```

Documentation/mainboard/asrock/h81m-hds.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
 
 ## Required proprietary blobs
 
-```{eval-rst}
+```eval_rst
 Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
 ```
 
@@ -75,7 +75,7 @@ facing towards the bottom of the board.
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS.
 
-```{eval-rst}
+```eval_rst
 Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 ```
 
@@ -111,7 +111,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/haswell/index`     |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/a88xm-e.md

@@ -14,7 +14,7 @@ and their GPU is [Sea Islands] (GCN2-based).
 
 A10 Richland is recommended for the best performance and working IOMMU.
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | A88XM-E          |                                                  |
 +------------------+--------------------------------------------------+
@@ -36,7 +36,7 @@ A10 Richland is recommended for the best performance and working IOMMU.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+

Documentation/mainboard/asus/f2a85-m.md

@@ -15,7 +15,7 @@ Both "Trinity" and "Richland" desktop processing units are working,
 the CPU architecture in these CPUs/APUs is [Piledriver],
 and their GPU is [TeraScale 3] (VLIW4-based).
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | F2A85-M          |                                                  |
 +------------------+--------------------------------------------------+
@@ -35,7 +35,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
 +------------------+--------------------------------------------------+
 ```
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | F2A85-M LE       |                                                  |
 +------------------+--------------------------------------------------+
@@ -55,7 +55,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
 +------------------+--------------------------------------------------+
 ```
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | F2A85-M PRO      |                                                  |
 +------------------+--------------------------------------------------+
@@ -77,7 +77,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+

Documentation/mainboard/asus/p2b-ls.md

@@ -10,7 +10,7 @@ This page describes how to run coreboot on the ASUS P2B-LS mainboard.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+---------------------------+
 | Type                | Value                     |
 +=====================+===========================+
@@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | Intel I440BX                                     |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p3b-f.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the ASUS P3B-F mainboard.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+---------------------------+
 | Type                | Value                     |
 +=====================+===========================+
@@ -88,7 +88,7 @@ for only CPU models that the board will actually be run with.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | Intel I440BX                                     |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p5q.md

@@ -32,7 +32,7 @@ This page describes how to run coreboot on the [ASUS P5Q] desktop board.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +-------------------+----------------+
 | Type              | Value          |
 +===================+================+
@@ -56,7 +56,7 @@ You can flash coreboot into your motherboard using [this guide].
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+---------------------------------------------------+
 | Northbridge      | Intel P45 (called x4x in coreboot code)           |
 +------------------+---------------------------------------------------+

Documentation/mainboard/asus/p8c_ws.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+----------------+
 | Type                | Value          |
 +=====================+================+
@@ -69,7 +69,7 @@ flash externally.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p8h61-m_lx.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M LX].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -84,7 +84,7 @@ region is not readable even by the host.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p8h61-m_pro.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M Pro].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -78,7 +78,7 @@ region is not readable even by the host.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p8h77-v.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+----------------+
 | Type                | Value          |
 +=====================+================+
@@ -56,7 +56,7 @@ work. The flash chip is socketed, so it's easy to remove and reflash.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p8z77-m.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+----------------+
 | Type                | Value          |
 +=====================+================+
@@ -112,7 +112,7 @@ therefore they currently do nothing under coreboot.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M PRO]
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+----------------+
 | Type                | Value          |
 +=====================+================+
@@ -143,7 +143,7 @@ easy to remove and reflash.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p8z77-v.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-V].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+----------------+
 | Type                | Value          |
 +=====================+================+
@@ -86,7 +86,7 @@ See [Asus Wi-Fi Go! v1].
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/wifigo_v1.md

@@ -8,7 +8,7 @@ through a proprietary 16-1 pin connector.
 I managed to grope the most pinout of the proprietary connector.
 See [Mini PCIe pinout] for more info.
 
-```{eval-rst}
+```eval_rst
 +------------+----------+-----------+------------+----------+-----------+
 | WIFIGO Pin | Usage    | mPCIe pin | WIFIGO Pin | Usage    | mPCIe pin |
 +============+==========+===========+============+==========+===========+

Documentation/mainboard/cavium/cn8100_sff_evb.md

@@ -17,7 +17,7 @@
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+----------------+
 | Type                | Value          |
 +=====================+================+
@@ -58,7 +58,7 @@
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +---------------+----------------------------------------+
 | SoC           | :doc:`../../soc/cavium/cn81xx/index`   |
 +---------------+----------------------------------------+

Documentation/mainboard/clevo/n130wu/index.md

@@ -2,7 +2,7 @@
 
 ## Hardware
 ### Technology
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------+
 | CPU              | Intel i7-8550U                 |
 +------------------+--------------------------------+
@@ -15,7 +15,7 @@
 ```
 
 ### Flash chip
-```{eval-rst}
+```eval_rst
 +---------------------+-----------------+
 | Type                | Value           |
 +=====================+=================+

Documentation/mainboard/dell/optiplex_9010.md

@@ -6,7 +6,7 @@ This page describes how to run coreboot on Dell OptiPlex 9010 SFF.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------+---------------------------------------------------------------+
 | CPU        | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge)       |
 +------------+---------------------------------------------------------------+
@@ -28,7 +28,7 @@ More specifications on [Dell OptiPlex 9010 specifications].
 
 ## Required proprietary blobs
 
-```{eval-rst}
+```eval_rst
 +------------------+---------------------------------+---------------------+
 | Binary file      | Apply                           | Required / Optional |
 +==================+=================================+=====================+
@@ -50,7 +50,7 @@ signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------------+
 | Type                | Value                    |
 +=====================+==========================+

Documentation/mainboard/emulation/qemu-riscv.md

@@ -3,9 +3,6 @@
 ## Building coreboot and running it in QEMU
 
 - Configure coreboot and run `make` as usual
-
+- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
-Run QEMU
+  convert coreboot to an ELF that QEMU can load
-```
+- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`
-qemu-system-riscv64 -M virt -m 1G -nographic -bios build/coreboot.rom \
-                    -drive if=pflash,file=./build/coreboot.rom,format=raw
-```

Documentation/mainboard/facebook/fbg1701.md

@@ -63,7 +63,7 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | SoC              | Intel Atom Processor N3710                       |
 +------------------+--------------------------------------------------+

Documentation/mainboard/facebook/monolith.md

@@ -14,7 +14,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
 
 FSP Information:
 
-```{eval-rst}
+```eval_rst
 +-----------------------------+-------------------+-------------------+
 | FSP Project Name            | Directory         | Specification     |
 +-----------------------------+-------------------+-------------------+
@@ -116,7 +116,7 @@ output.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | SoC              | Intel Kaby Lake U                                |
 +------------------+--------------------------------------------------+

Documentation/mainboard/foxconn/d41s.md

@@ -14,7 +14,7 @@ The default options for this board should result in a fully working image:
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+--------+
 | Type                | Value  |
 +=====================+========+
@@ -56,7 +56,7 @@ To do this gently take the SPI flash out of its socket and flash with your progr
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+------------------+
 | Northbridge      | Intel Pinevew    |
 +------------------+------------------+

Documentation/mainboard/gigabyte/ga-g41m-es2l.md

@@ -6,7 +6,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Type             | Value                                            |
 +==================+==================================================+
@@ -30,7 +30,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
 
 ## Preparation
 
-```{eval-rst}
+```eval_rst
 For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
 ```
 
@@ -140,7 +140,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 In addition to the information here, please see the
 :doc:`../../tutorial/flashing_firmware/index`.
 ```

Documentation/mainboard/gigabyte/ga-h61m-s2pv.md

@@ -5,7 +5,7 @@ from [Gigabyte].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -59,7 +59,7 @@ However, this makes DualBIOS unable to recover from a bad flash for some reason.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/2170p.md

@@ -74,7 +74,7 @@ The EHCI debug port is the left USB3 port.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/2560p.md

@@ -80,7 +80,7 @@ Schematic of this laptop can be found on [Lab One].
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/8760w.md

@@ -7,7 +7,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -66,7 +66,7 @@ clip to read and flash the chip.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+-------------------------+
 | Type                | Value                   |
 +=====================+=========================+
@@ -128,7 +128,7 @@ as otherwise there's not enough space near the flash.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/compaq_8300_usdt.md

@@ -5,7 +5,7 @@ from [HP].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+-------------+
 | Type                | Value       |
 +=====================+=============+
@@ -42,7 +42,7 @@ Wake on LAN is active works great.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/elitebook_820_g2.md

@@ -124,7 +124,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+-----------------------------+
 | SoC              | Intel Broadwell             |
 +------------------+-----------------------------+

Documentation/mainboard/hp/folio_9480m.md

@@ -138,7 +138,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+-----------------------------+
 | CPU              | Intel Haswell-ULT           |
 +------------------+-----------------------------+

Documentation/mainboard/hp/pro_3500_series.md

@@ -1,103 +0,0 @@
-# HP Pro 3500 Series
-
-This page describes how to run coreboot on the [Pro 3500 Series]
-desktop from [HP].
-
-## State
-
-All peripherals should work. Automatic fan control as well as S3 are
-working. The board was tested to boot Linux and Windows. EHCI debug
-is untested. When using MrChromebox edk2 with secure boot build in, the
-board will hang on each boot for about 20 seconds before continuing.
-With disabled ME, the SuperIO will not get CPU temperatures via PECI and
-therefore the automatic fan control will not increase the fan speed.
-
-## Flashing coreboot
-
-```{eval_rst}
-+---------------------+-------------------------+
-| Type                | Value                   |
-+=====================+=========================+
-| Socketed flash      | No                      |
-+---------------------+-------------------------+
-| Model               | W25Q64FVSIG             |
-+---------------------+-------------------------+
-| Size                | 8 MiB                   |
-+---------------------+-------------------------+
-| In circuit flashing | Yes                     |
-+---------------------+-------------------------+
-| Package             | SOIC-8                  |
-+---------------------+-------------------------+
-| Write protection    | See below               |
-+---------------------+-------------------------+
-| Dual BIOS feature   | No                      |
-+---------------------+-------------------------+
-| Internal flashing   | Yes                     |
-+---------------------+-------------------------+
-```
-
-### Flash layout
-The original layout of the flash should look like this:
-```
-00000000:00000fff fd
-00400000:007fffff bios
-00001000:003fffff me
-00fff000:00000fff gbe
-00fff000:00000fff pd
-```
-
-### Internal programming
-
-The SPI flash can be accessed using [flashrom] (although it reports as
-"N25Q064..3E", it works fine).
-
-With a missing FDO jumper, `fd` region is read-only, `bios` region is
-read-write and `me` region is locked. Vendor firmware will additionally
-protect the flash chip. After shorting the FDO jumper (E2) full
-read-write access is granted.
-
-Do **NOT shutdown** the operating system **after flashing** coreboot
-from the vendor firmware! This will brick your device because the bios
-region will be modified on shutdown. Cut the AC power or do a restart
-from the OS.
-
-**Position of FDO jumper (E2) close to the F_USB3**
-![][pro_3500_jumper]
-
-[pro_3500_jumper]: pro_3500_series_jumper.avif
-
-### External programming
-
-External programming with an SPI adapter and [flashrom] does work, but
-it powers the whole southbridge complex. The average current will be
-400mA but spikes may be higher. Connect the power to the flash or the
-programming header next to the flash otherwise programming is unstable.
-The supply needs to quickly reach 3V3 or else the chip is also unstable
-until cleanly power cycled.
-
-**Position of SOIC-8 flash and pin-header near ATX power connector**
-![][pro_3500_flash]
-
-[pro_3500_flash]: pro_3500_series_flash.avif
-
-## Technology
-
-```{eval_rst}
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x (bd82h61)                                |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| SuperIO          | IT8779E (identifies as IT8772F via register)     |
-+------------------+--------------------------------------------------+
-| EC               | Fixed function as part of SuperIO                |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel ME                                         |
-+------------------+--------------------------------------------------+
-```
-
-[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089
-[HP]: https://www.hp.com/
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/z220_sff.md

@@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+-------------+
 | Type                | Value       |
 +=====================+=============+
@@ -58,7 +58,7 @@ even interchangeable, so should do coreboot images built for them.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/index.md

@@ -4,393 +4,240 @@ This section contains documentation about coreboot on specific mainboards.
 
 ## 51NB
 
-```{toctree}
+- [X210](51nb/x210.md)
-:maxdepth: 1
-
-X210 <51nb/x210.md>
-```
 
 ## Acer
 
-```{toctree}
+- [G43T-AM3](acer/g43t-am3.md)
-:maxdepth: 1
-
-G43T-AM3 <acer/g43t-am3.md>
-```
 
 ## AMD
-```{toctree}
+- [pademelon](amd/pademelon/pademelon.md)
-:maxdepth: 1
-
-pademelon <amd/pademelon/pademelon.md>
-```
 
 ## ASRock
 
-```{toctree}
+- [H77 Pro4-M](asrock/h77pro4-m.md)
-:maxdepth: 1
+- [H81M-HDS](asrock/h81m-hds.md)
-
+- [H110M-DVS](asrock/h110m-dvs.md)
-H77 Pro4-M <asrock/h77pro4-m.md>
-H81M-HDS <asrock/h81m-hds.md>
-H110M-DVS <asrock/h110m-dvs.md>
-```
 
 ## ASUS
 
-```{toctree}
+- [A88XM-E](asus/a88xm-e.md)
-:maxdepth: 1
+- [F2A85-M](asus/f2a85-m.md)
-
+- [P2B-LS](asus/p2b-ls.md)
-A88XM-E <asus/a88xm-e.md>
+- [P3B-F](asus/p3b-f.md)
-F2A85-M <asus/f2a85-m.md>
+- [P5Q](asus/p5q.md)
-P2B-LS <asus/p2b-ls.md>
+- [P8C WS](asus/p8c_ws.md)
-P3B-F <asus/p3b-f.md>
+- [P8H61-M LX](asus/p8h61-m_lx.md)
-P5Q <asus/p5q.md>
+- [P8H61-M Pro](asus/p8h61-m_pro.md)
-P8C WS <asus/p8c_ws.md>
+- [P8H77-V](asus/p8h77-v.md)
-P8H61-M LX <asus/p8h61-m_lx.md>
+- [P8Z77-M](asus/p8z77-m.md)
-P8H61-M Pro <asus/p8h61-m_pro.md>
+- [P8Z77-M Pro](asus/p8z77-m_pro.md)
-P8H77-V <asus/p8h77-v.md>
+- [P8Z77-V](asus/p8z77-v.md)
-P8Z77-M <asus/p8z77-m.md>
+- [wifigo_v1](asus/wifigo_v1.md)
-P8Z77-M Pro <asus/p8z77-m_pro.md>
-P8Z77-V <asus/p8z77-v.md>
-wifigo_v1 <asus/wifigo_v1.md>
-```
 
 ## Cavium
 
-```{toctree}
+- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
-:maxdepth: 1
-
-CN81XX EVB SFF <cavium/cn8100_sff_evb.md>
-```
 
 ## Clevo
 
-```{toctree}
+- [N130WU / N131WU](clevo/n130wu/index.md)
-:maxdepth: 1
-
-N130WU / N131WU <clevo/n130wu/index.md>
-```
 
 ## Dell
 
-```{toctree}
+- [OptiPlex 9010 SFF](dell/optiplex_9010.md)
-:maxdepth: 1
-
-OptiPlex 9010 SFF <dell/optiplex_9010.md>
-```
 
 ## Emulation
 
 The boards in this section are not real mainboards, but emulators.
 
-```{toctree}
+- [Spike RISC-V emulator](emulation/spike-riscv.md)
-:maxdepth: 1
+- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
-
+- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
-Spike RISC-V emulator <emulation/spike-riscv.md>
+- [QEMU x86 Q35](emulation/qemu-q35.md)
-QEMU RISC-V emulator <emulation/qemu-riscv.md>
+- [QEMU x86 PC](emulation/qemu-i440fx.md)
-QEMU AArch64 emulator <emulation/qemu-aarch64.md>
+- [QEMU POWER9](emulation/qemu-power9.md)
-QEMU x86 Q35 <emulation/qemu-q35.md>
-QEMU x86 PC <emulation/qemu-i440fx.md>
-QEMU POWER9 <emulation/qemu-power9.md>
-```
 
 ## Facebook
 
-```{toctree}
+- [FBG-1701](facebook/fbg1701.md)
-:maxdepth: 1
+- [Monolith](facebook/monolith.md)
-
-FBG-1701 <facebook/fbg1701.md>
-Monolith <facebook/monolith.md>
-```
 
 ## Foxconn
 
-```{toctree}
+- [D41S](foxconn/d41s.md)
-:maxdepth: 1
-
-D41S <foxconn/d41s.md>
-```
 
 ## Gigabyte
 
-```{toctree}
+- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md)
-:maxdepth: 1
+- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
-
-GA-G41M-ES2L <gigabyte/ga-g41m-es2l.md>
-GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
-```
 
 ## HP
 
-```{toctree}
+- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
-:maxdepth: 1
+- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
-
+- [Z220 Workstation SFF](hp/z220_sff.md)
-Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
-Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
-Pro 3500 Series <hp/pro_3500_series.md>
-Z220 Workstation SFF <hp/z220_sff.md>
-```
 
 ### EliteBook series
 
-```{toctree}
+- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
-:maxdepth: 1
+- [HP Sure Start](hp/hp_sure_start.md)
-
+- [EliteBook 2170p](hp/2170p.md)
-HP Laptops with KBC1126 EC <hp/hp_kbc1126_laptops.md>
+- [EliteBook 2560p](hp/2560p.md)
-HP Sure Start <hp/hp_sure_start.md>
+- [EliteBook 8760w](hp/8760w.md)
-EliteBook 2170p <hp/2170p.md>
+- [EliteBook Folio 9480m](hp/folio_9480m.md)
-EliteBook 2560p <hp/2560p.md>
+- [EliteBook 820 G2](hp/elitebook_820_g2.md)
-EliteBook 8760w <hp/8760w.md>
-EliteBook Folio 9480m <hp/folio_9480m.md>
-EliteBook 820 G2 <hp/elitebook_820_g2.md>
-```
 
 ## Intel
 
-```{toctree}
+- [DG43GT](intel/dg43gt.md)
-:maxdepth: 1
+- [DQ67SW](intel/dq67sw.md)
-
+- [KBLRVP11](intel/kblrvp11.md)
-DG43GT <intel/dg43gt.md>
-DQ67SW <intel/dq67sw.md>
-KBLRVP11 <intel/kblrvp11.md>
-```
 
 ## Kontron
 
-```{toctree}
+- [mAL-10](kontron/mal10.md)
-:maxdepth: 1
-
-mAL-10 <kontron/mal10.md>
-```
 
 ## Lenovo
 
-```{toctree}
+- [Mainboard codenames](lenovo/codenames.md)
-:maxdepth: 1
+- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
-
+- [R60](lenovo/r60.md)
-Mainboard codenames <lenovo/codenames.md>
+- [T4xx common](lenovo/t4xx_series.md)
-Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md>
+- [X2xx common](lenovo/x2xx_series.md)
-R60 <lenovo/r60.md>
+- [vboot](lenovo/vboot.md)
-T4xx common <lenovo/t4xx_series.md>
-X2xx common <lenovo/x2xx_series.md>
-vboot <lenovo/vboot.md>
-```
 
 ### GM45 series
 
-```{toctree}
+- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
-:maxdepth: 1
+- [X301](lenovo/x301.md)
-
-X200 / T400 / T500 / X301 common <lenovo/montevina_series.md>
-X301 <lenovo/x301.md>
-```
 
 ### Arrandale series
 
-```{toctree}
+- [T410](lenovo/t410.md)
-:maxdepth: 1
-
-T410 <lenovo/t410.md>
-```
 
 ### Sandy Bridge series
 
-```{toctree}
+- [T420](lenovo/t420.md)
-:maxdepth: 1
+- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md)
-
+- [X1](lenovo/x1.md)
-T420 <lenovo/t420.md>
-T420 / T520 / X220 / T420s / W520 common <lenovo/Sandy_Bridge_series.md>
-X1 <lenovo/x1.md>
-```
 
 ### Ivy Bridge series
 
-```{toctree}
+- [T430](lenovo/t430.md)
-:maxdepth: 1
+- [T530 / W530](lenovo/w530.md)
-
+- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
-T430 <lenovo/t430.md>
+- [T431s](lenovo/t431s.md)
-T530 / W530 <lenovo/w530.md>
+- [X230s](lenovo/x230s.md)
-T430 / T530 / X230 / W530 common <lenovo/Ivy_Bridge_series.md>
+- [Internal flashing](lenovo/ivb_internal_flashing.md)
-T431s <lenovo/t431s.md>
-X230s <lenovo/x230s.md>
-Internal flashing <lenovo/ivb_internal_flashing.md>
-```
 
 ### Haswell series
 
-```{toctree}
+- [T440p](lenovo/t440p.md)
-:maxdepth: 1
-
-T440p <lenovo/t440p.md>
-```
 
 ## Libretrend
 
-```{toctree}
+- [LT1000](libretrend/lt1000.md)
-:maxdepth: 1
-
-LT1000 <libretrend/lt1000.md>
-```
 
 ## MSI
 
-```{toctree}
+- [MS-7707](msi/ms7707/ms7707.md)
-:maxdepth: 1
-
-MS-7707 <msi/ms7707/ms7707.md>
-```
 
 ## OCP
 
-```{toctree}
+- [Delta Lake](ocp/deltalake.md)
-:maxdepth: 1
+- [Tioga Pass](ocp/tiogapass.md)
-
-Delta Lake <ocp/deltalake.md>
-Tioga Pass <ocp/tiogapass.md>
-```
 
 ## Open Cellular
 
-```{toctree}
+- [Elgon](opencellular/elgon.md)
-:maxdepth: 1
-
-Elgon <opencellular/elgon.md>
-```
 
 ## PC Engines
 
-```{toctree}
+- [APU1](pcengines/apu1.md)
-:maxdepth: 1
+- [APU2](pcengines/apu2.md)
-
-APU1 <pcengines/apu1.md>
-APU2 <pcengines/apu2.md>
-```
 
 ## Portwell
 
-```{toctree}
+- [PQ7-M107](portwell/pq7-m107.md)
-:maxdepth: 1
-
-PQ7-M107 <portwell/pq7-m107.md>
-```
 
 ## Prodrive
 
-```{toctree}
+- [Hermes](prodrive/hermes.md)
-:maxdepth: 1
-
-Hermes <prodrive/hermes.md>
-```
 
 ## Purism
 
-```{toctree}
+- [Librem 14](purism/librem_14.md)
-:maxdepth: 1
+- [Librem Mini](purism/librem_mini.md)
-
-Librem 14 <purism/librem_14.md>
-Librem Mini <purism/librem_mini.md>
-```
 
 ## Protectli
 
-```{toctree}
+- [FW2B / FW4B](protectli/fw2b_fw4b.md)
-:maxdepth: 1
+- [FW6A / FW6B / FW6C](protectli/fw6.md)
-
+- [VP2420](protectli/vp2420.md)
-FW2B / FW4B <protectli/fw2b_fw4b.md>
+- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
-FW6A / FW6B / FW6C <protectli/fw6.md>
-VP2420 <protectli/vp2420.md>
-VP4630 / VP4650 / VP4670 <protectli/vp46xx.md>
-```
 
 ## Roda
 
-```{toctree}
+- [RK9 Flash Header](roda/rk9/flash_header.md)
-:maxdepth: 1
-
-RK9 Flash Header <roda/rk9/flash_header.md>
-```
 
 ## SiFive
 
-```{toctree}
+- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
-:maxdepth: 1
-
-SiFive HiFive Unleashed <sifive/hifive-unleashed.md>
-```
 
 ## Star Labs Systems
 
-```{toctree}
+- [LabTop Mk III](starlabs/labtop_kbl.md)
-:maxdepth: 1
+- [LabTop Mk IV](starlabs/labtop_cml.md)
-
+- [StarLite Mk III](starlabs/lite_glk.md)
-LabTop Mk III <starlabs/labtop_kbl.md>
+- [StarLite Mk IV](starlabs/lite_glkr.md)
-LabTop Mk IV <starlabs/labtop_cml.md>
+- [StarBook Mk V](starlabs/starbook_tgl.md)
-StarLite Mk III <starlabs/lite_glk.md>
+- [StarBook Mk VI](starlabs/starbook_adl.md)
-StarLite Mk IV <starlabs/lite_glkr.md>
+- [Flashing devices](starlabs/common/flashing.md)
-StarBook Mk V <starlabs/starbook_tgl.md>
-StarBook Mk VI <starlabs/starbook_adl.md>
-Flashing devices <starlabs/common/flashing.md>
-```
 
 ## Supermicro
 
-```{toctree}
+- [X9SAE](supermicro/x9sae.md)
-:maxdepth: 1
+- [X10SLM+-F](supermicro/x10slm-f.md)
-
+- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
-X9SAE <supermicro/x9sae.md>
+- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
-X10SLM+-F <supermicro/x10slm-f.md>
-X11 LGA1151 series <supermicro/x11-lga1151-series/x11-lga1151-series.md>
-Flashing using the BMC <supermicro/flashing_on_vendorbmc.md>
-```
 
 ## System76
 
-```{toctree}
+- [Adder Workstation 1](system76/addw1.md)
-:maxdepth: 1
+- [Adder Workstation 2](system76/addw2.md)
-
+- [Adder Workstation 3](system76/addw3.md)
-Adder Workstation 1 <system76/addw1.md>
+- [Bonobo Workstation 14](system76/bonw14.md)
-Adder Workstation 2 <system76/addw2.md>
+- [Bonobo Workstation 15](system76/bonw15.md)
-Adder Workstation 3 <system76/addw3.md>
+- [Darter Pro 6](system76/darp6.md)
-Bonobo Workstation 14 <system76/bonw14.md>
+- [Darter Pro 7](system76/darp7.md)
-Bonobo Workstation 15 <system76/bonw15.md>
+- [Darter Pro 8](system76/darp8.md)
-Darter Pro 6 <system76/darp6.md>
+- [Darter Pro 9](system76/darp9.md)
-Darter Pro 7 <system76/darp7.md>
+- [Galago Pro 4](system76/galp4.md)
-Darter Pro 8 <system76/darp8.md>
+- [Galago Pro 5](system76/galp5.md)
-Darter Pro 9 <system76/darp9.md>
+- [Galago Pro 6](system76/galp6.md)
-Galago Pro 4 <system76/galp4.md>
+- [Galago Pro 7](system76/galp7.md)
-Galago Pro 5 <system76/galp5.md>
+- [Gazelle 15](system76/gaze15.md)
-Galago Pro 6 <system76/galp6.md>
+- [Gazelle 16](system76/gaze16.md)
-Galago Pro 7 <system76/galp7.md>
+- [Gazelle 17](system76/gaze17.md)
-Gazelle 15 <system76/gaze15.md>
+- [Gazelle 18](system76/gaze18.md)
-Gazelle 16 <system76/gaze16.md>
+- [Lemur Pro 9](system76/lemp9.md)
-Gazelle 17 <system76/gaze17.md>
+- [Lemur Pro 10](system76/lemp10.md)
-Gazelle 18 <system76/gaze18.md>
+- [Lemur Pro 11](system76/lemp11.md)
-Lemur Pro 9 <system76/lemp9.md>
+- [Lemur Pro 12](system76/lemp12.md)
-Lemur Pro 10 <system76/lemp10.md>
+- [Oryx Pro 5](system76/oryp5.md)
-Lemur Pro 11 <system76/lemp11.md>
+- [Oryx Pro 6](system76/oryp6.md)
-Lemur Pro 12 <system76/lemp12.md>
+- [Oryx Pro 7](system76/oryp7.md)
-Oryx Pro 5 <system76/oryp5.md>
+- [Oryx Pro 8](system76/oryp8.md)
-Oryx Pro 6 <system76/oryp6.md>
+- [Oryx Pro 9](system76/oryp9.md)
-Oryx Pro 7 <system76/oryp7.md>
+- [Oryx Pro 10](system76/oryp10.md)
-Oryx Pro 8 <system76/oryp8.md>
+- [Oryx Pro 11](system76/oryp11.md)
-Oryx Pro 9 <system76/oryp9.md>
+- [Serval Workstation 13](system76/serw13.md)
-Oryx Pro 10 <system76/oryp10.md>
-Oryx Pro 11 <system76/oryp11.md>
-Serval Workstation 13 <system76/serw13.md>
-```
 
 ## Texas Instruments
 
-```{toctree}
+- [Beaglebone Black](ti/beaglebone-black.md)
-:maxdepth: 1
-
-Beaglebone Black <ti/beaglebone-black.md>
-```
 
 ## UP
 
-```{toctree}
+- [Squared](up/squared/index.md)
-:maxdepth: 1
-
-Squared <up/squared/index.md>
-```

Documentation/mainboard/intel/dg43gt.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [Intel DG43GT] desktop.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -79,7 +79,7 @@ The layout of the header is:
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+---------------------------------------------------+
 | Northbridge      | Intel G43 (called x4x in coreboot code)           |
 +------------------+---------------------------------------------------+

Documentation/mainboard/intel/dq67sw.md

@@ -4,7 +4,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+
@@ -67,7 +67,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -104,7 +104,7 @@ the PCI configuration space of the LPC Interface Bridge, is set.
 It is possible to program the chip is to attach an external programmer
 with an SOIC-8 clip.
 
-```{eval-rst}
+```eval_rst
 Another way is to boot the vendor firmware in UEFI mode and exploit the
 unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
 :doc:`../lenovo/ivb_internal_flashing`.
@@ -126,7 +126,7 @@ The boot script contains an entry that writes 0x02 to memory at address
 Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
 prevents this by making it write a 0 instead.
 
-```{eval-rst}
+```eval_rst
 After suspending and resuming the board, the BIOS region can be flashed with
 a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
 so the `--noverify-all` flag is necessary. Please refer to the

Documentation/mainboard/intel/kblrvp11.md

@@ -23,7 +23,7 @@
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -65,7 +65,7 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+---------------------------------------------------+
 | CPU              | Kaby lake H (i7-7820EQ)                           |
 +------------------+---------------------------------------------------+

Documentation/mainboard/kontron/mal10.md

@@ -6,7 +6,7 @@ processors.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+----------------------------------+
 | COMe Type        | mini pin-out type 10             |
 +------------------+----------------------------------+

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -3,7 +3,7 @@
 This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md).
 
 ## Flashing coreboot
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------------------+
 | Type                | Value                          |
 +=====================+================================+
@@ -37,7 +37,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
   exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
 * ROM chip size should be set to 12MiB.
 
-```{eval-rst}
+```eval_rst
 Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
 ```
 

Documentation/mainboard/lenovo/Sandy_Bridge_series.md

@@ -1,7 +1,7 @@
 # Lenovo Sandy Bridge series
 
 ## Flashing coreboot
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------+
 | Type                | Value              |
 +=====================+====================+

Documentation/mainboard/lenovo/codenames.md

@@ -1,6 +1,6 @@
 # Lenovo mainboard codenames
 
-```{eval-rst}
+```eval_rst
 .. csv-table::
    :header: "Marketing name", "Development codename"
    :file: codenames.csv

Documentation/mainboard/lenovo/ivb_internal_flashing.md

@@ -19,11 +19,7 @@ that was discovered and fixed later.
 
 - USB drive (in case you need to downgrade BIOS)
 - Linux install that (can be) loaded in UEFI mode
-```{toctree}
+- [CHIPSEC](https://github.com/chipsec/chipsec)
-:maxdepth: 1
-
-CHIPSEC <https://github.com/chipsec/chipsec>
-```
 
 ## BIOS versions
 
@@ -31,7 +27,7 @@ Below is a table of BIOS versions that are vulnerable enough for our
 goals, per model. The version number means that you need to downgrade to
 that or earlier version.
 
-```{eval-rst}
+```eval_rst
 +------------+--------------+
 | Model      | BIOS version |
 +============+==============+

Documentation/mainboard/lenovo/montevina_series.md

@@ -20,7 +20,7 @@ touch any other regions:
 
 ## Installing without ME firmware
 
-```{eval-rst}
+```eval_rst
 .. Note::
    **ThinkPad R500** has slightly different flash layout (it doesn't have
    ``gbe`` region), so the process would be a little different for that model.
@@ -51,7 +51,7 @@ your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
 Pick the layout according to your chip size from the table below and save it to
 the `new_layout.txt` file:
 
-```{eval-rst}
+```eval_rst
 +---------------------------+---------------------------+---------------------------+
 | 4 MiB chip                | 8 MiB chip                | 16 MiB chip               |
 +===========================+===========================+===========================+
@@ -102,7 +102,7 @@ $ make
 If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
 `flreg1_limit` in the `ifd-x200.set` file according to following table:
 
-```{eval-rst}
+```eval_rst
 +-----------------+-------+-------+--------+
 |                 | 4 MiB | 8 MiB | 16 MiB |
 +=================+=======+=======+========+
@@ -144,7 +144,7 @@ Then build coreboot and flash whole `build/coreboot.rom` to the chip.
 
 The flash layouts of the OEM firmware are as follows:
 
-```{eval-rst}
+```eval_rst
 +---------------------------------+---------------------------------+
 | 4 MiB chip                      | 8 MiB chip                      |
 +=================================+=================================+

Documentation/mainboard/lenovo/t410.md

@@ -5,7 +5,7 @@
 * TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB)
 
 ## Flashing instructions
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------------------+
 | Type                | Value                          |
 +=====================+================================+

Documentation/mainboard/libretrend/lt1000.md

@@ -10,7 +10,7 @@ Librebox).
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+
@@ -98,7 +98,7 @@ The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not
 sold yet). More details on [baseboard site]. Unfortunately the board manual is
 not publicly available.
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i7-6500U                              |
 +------------------+--------------------------------------------------+

Documentation/mainboard/msi/ms7707/ms7707.md

@@ -9,7 +9,7 @@
 * IME 7.0.4.1197
 
 ## Flash chip (Winbond 25Q32BV)
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------+
 | Type                | Value              |
 +=====================+====================+

Documentation/mainboard/ocp/deltalake.md

@@ -200,7 +200,7 @@ and [u-root] as initramfs.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------------+---------------------------------------------+
 | Processor (1 socket)   | Intel Cooper Lake Scalable Processor        |
 +------------------------+---------------------------------------------+

Documentation/mainboard/ocp/tiogapass.md

@@ -80,7 +80,7 @@ u-root.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------------+---------------------------------------------+
 | Processor (2 sockets)  | Intel Skylake Scalable Processor LGA3647    |
 +------------------------+---------------------------------------------+

Documentation/mainboard/opencellular/elgon.md

@@ -9,7 +9,7 @@ from [OpenCellular].
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+
@@ -69,7 +69,7 @@ Dediprog compatible pinout.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +---------------+----------------------------------------+
 | SoC           | :doc:`../../soc/cavium/cn81xx/index`   |
 +---------------+----------------------------------------+

Documentation/mainboard/pcengines/apu1.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on PC Engines APU1 platform.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------+--------------------------------------------------------+
 | CPU        | AMD G series T40E APU                                  |
 +------------+--------------------------------------------------------+
@@ -23,7 +23,7 @@ This page describes how to run coreboot on PC Engines APU1 platform.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------------+
 | Type                | Value                    |
 +=====================+==========================+

Documentation/mainboard/pcengines/apu2.md

@@ -4,7 +4,7 @@ This page describes how to run coreboot on PC Engines APU2 platform.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------+---------------------------------------------------------------+
 | CPU        | AMD G series GX-412TC                                         |
 +------------+---------------------------------------------------------------+
@@ -25,7 +25,7 @@ This page describes how to run coreboot on PC Engines APU2 platform.
 
 To build working coreboot image some blobs are needed.
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+
@@ -41,7 +41,7 @@ blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP*
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+--------------------------+
 | Type                | Value                    |
 +=====================+==========================+

Documentation/mainboard/portwell/pq7-m107.md

@@ -61,7 +61,7 @@ serial/video/pcie ports might be available.
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | SoC              | Intel Atom Processor N3710                       |
 +------------------+--------------------------------------------------+

Documentation/mainboard/prodrive/hermes.md

@@ -32,7 +32,7 @@ The board features:
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | CoffeeLake + CoffeeLake R (Core + Xeon)          |
 +------------------+--------------------------------------------------+

Documentation/mainboard/protectli/fw2b_fw4b.md

@@ -9,7 +9,7 @@ This page describes how to run coreboot on the [Protectli FW2B] and
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+
@@ -91,7 +91,7 @@ connected via [FE1.1 USB 2.0 hub].
 
 - FW2B:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Celeron J3060                              |
 +------------------+--------------------------------------------------+
@@ -107,7 +107,7 @@ connected via [FE1.1 USB 2.0 hub].
 
 - FW4B:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Celeron J3160                              |
 +------------------+--------------------------------------------------+

Documentation/mainboard/protectli/fw6.md

@@ -9,7 +9,7 @@ This page describes how to run coreboot on the [Protectli FW6].
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+
@@ -92,7 +92,7 @@ used SoC.
 
 - FW6A:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Celeron 3865U                              |
 +------------------+--------------------------------------------------+
@@ -106,7 +106,7 @@ used SoC.
 
 - FW6B:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i3-7100U                              |
 +------------------+--------------------------------------------------+
@@ -120,7 +120,7 @@ used SoC.
 
 - FW6C:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i5-7200U                              |
 +------------------+--------------------------------------------------+

Documentation/mainboard/protectli/vp2420.md

@@ -10,7 +10,7 @@ This page describes how to run coreboot on the [Protectli VP2420].
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+
@@ -66,7 +66,7 @@ MX25L12835F - [datasheet][MX25L12835F].
 
 ## Technology
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Celeron J6412                              |
 +------------------+--------------------------------------------------+
@@ -80,12 +80,8 @@ MX25L12835F - [datasheet][MX25L12835F].
 
 ## Useful links
 
-```{toctree}
+- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
-:maxdepth: 1
+- [VP2420 Product Page](https://protectli.com/product/vp2420/)
-
+- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-VP2420 Hardware Overview <https://protectli.com/kb/vp2400-series-hardware-overview/>
+- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
-VP2420 Product Page <https://protectli.com/product/vp2420/>
+- [flashrom](https://flashrom.org/Flashrom)
-Protectli TPM module <https://protectli.com/product/tpm-module/>
-MX25L12835F <https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf>
-flashrom <https://flashrom.org/Flashrom>
-```

Documentation/mainboard/protectli/vp46xx.md

@@ -10,7 +10,7 @@ This page describes how to run coreboot on the [Protectli VP46xx].
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+
@@ -84,7 +84,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
 
 - VP4630:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i3-10110U                             |
 +------------------+--------------------------------------------------+
@@ -98,7 +98,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
 
 - VP4650:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i5-10210U                             |
 +------------------+--------------------------------------------------+
@@ -112,7 +112,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
 
 - VP4670:
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i7-10810U                             |
 +------------------+--------------------------------------------------+
@@ -126,13 +126,9 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
 
 ## Useful links
 
-```{toctree}
+- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
-:maxdepth: 1
+- [VP4630 Product Page](https://protectli.com/product/vp4630/)
-
+- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-VP4600 Hardware Overview <https://protectli.com/kb/vp4600-hardware-overview/>
-VP4630 Product Page <https://protectli.com/product/vp4630/>
-Protectli TPM module <https://protectli.com/product/tpm-module/>
-```
 
 [Protectli VP46xx]: https://protectli.com/vault-6-port/
 [MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf

Documentation/mainboard/purism/librem_14.md

@@ -2,7 +2,7 @@
 
 This page describes how to run coreboot on the [Purism Librem 14].
 
-```{eval-rst}
+```eval_rst
 +------------------+------------------------------------------------------+
 | CPU              | Intel Core i7-10710U                                 |
 +------------------+------------------------------------------------------+
@@ -23,7 +23,7 @@ This page describes how to run coreboot on the [Purism Librem 14].
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+

Documentation/mainboard/purism/librem_mini.md

@@ -2,7 +2,7 @@
 
 This page describes how to run coreboot on the [Purism Librem Mini].
 
-```{eval-rst}
+```eval_rst
 +------------------+--------------------------------------------------+
 | CPU              | Intel Core i7-8565U/8665U (v1)                   |
 |                  | Intel Core i7-10510U      (v2)                   |
@@ -25,7 +25,7 @@ This page describes how to run coreboot on the [Purism Librem Mini].
 To build a minimal working coreboot image some blobs are required (assuming
 only the BIOS region is being modified).
 
-```{eval-rst}
+```eval_rst
 +-----------------+---------------------------------+---------------------+
 | Binary file     | Apply                           | Required / Optional |
 +=================+=================================+=====================+

Documentation/mainboard/starlabs/labtop_cml.md

@@ -45,7 +45,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -42,7 +42,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+

Documentation/mainboard/starlabs/lite_glk.md

@@ -41,7 +41,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+

Documentation/mainboard/starlabs/lite_glkr.md

@@ -41,7 +41,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 
 ## Flashing coreboot
 
-```{eval-rst}
+```eval_rst
 +---------------------+------------+
 | Type                | Value      |
 +=====================+============+