mb/system76/tgl: Update VBTs to version 250

Commit 4c7e97b26a ("Update fsp submodule to upstream master branch")
included an update to the VBT from 240 to 250, breaking parsing of
existing VBTs.

After that commit, the VBT was parsed as (from gaze16-3060-b):

    [DEBUG]  PCI: 00:02.0 init
    [INFO ]  GMA: Found VBT in CBFS
    [INFO ]  GMA: Found valid VBT in CBFS
    [INFO ]  framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
    [INFO ]                     x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000
    [DEBUG]  PCI: 00:02.0 init finished in 6 msecs

When the expected output is:

    [DEBUG]  PCI: 00:00:02.0 init
    [INFO ]  GMA: Found VBT in CBFS
    [INFO ]  GMA: Found valid VBT in CBFS
    [INFO ]  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
    [INFO ]                     x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000
    [DEBUG]  PCI: 00:00:02.0 init finished in 6 msecs

Generate blobs for the new version using Intel Display Configuration
Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs.

(For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.)

Tested on all affected systems:

- darp7
- galp5
- gaze16-3050
- gaze16-3060
- gaze16-3060-b
- lemp10
- oryp8

Tested:

- Boot splash displays on screen again
- Firmware setup menu is rendered, at correct resolution

Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Daniel Sutton <daniel@system76.com>
Tested-by: Jacob Kauffmann <jacob@system76.com>

.gitmodules

@@ -1,70 +1,70 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = https://review.coreboot.org/blobs.git
+	url = ../blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = https://review.coreboot.org/nvidia-cbootimage.git
+	url = ../nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = https://review.coreboot.org/vboot.git
+	url = ../vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = https://review.coreboot.org/arm-trusted-firmware.git
+	url = ../arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = https://review.coreboot.org/chrome-ec.git
+	url = ../chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = https://review.coreboot.org/libhwbase.git
+	url = ../libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = https://review.coreboot.org/libgfxinit.git
+	url = ../libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = https://review.coreboot.org/fsp.git
+	url = ../fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = https://review.coreboot.org/opensbi.git
+	url = ../opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = https://review.coreboot.org/intel-microcode.git
+	url = ../intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = https://review.coreboot.org/ffs.git
+	url = ../ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = https://review.coreboot.org/amd_blobs
+	url = ../amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = https://review.coreboot.org/cmocka.git
+	url = ../cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = https://review.coreboot.org/qc_blobs.git
+	url = ../qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = https://review.coreboot.org/9esec-security-tooling.git
+	url = ../9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = https://review.coreboot.org/STM
+	url = ../STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = https://review.coreboot.org/goswid.git
+	url = ../goswid
 	branch = trunk
 [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
 	path = src/vendorcode/amd/opensil/genoa_poc/opensil
-	url = https://review.coreboot.org/opensil_genoa_poc.git
+	url = ../opensil_genoa_poc.git

AUTHORS

@@ -39,9 +39,7 @@ Alexandru Gagniuc
 Alexey Buyanov
 Alexey Vazhnov
 Alice Sell
-Alicja Michalska
 Allen-KH Cheng
-Alper Nebi Yasak
 Amanda Hwang
 American Megatrends International, LLC
 Amersel
@@ -64,7 +62,6 @@ Anna Karaś
 Annie Chen
 Anton Kochkov
 Ao Zhong
-Appukuttan V K
 Arashk Mahshidfar
 Arec Kao
 Ariel Fang
@@ -96,7 +93,6 @@ Bora Guvendik
 Boris Barbulovski
 Boris Mittelberg
 Brandon Breitenstein
-Brandon Weeks
 Brian Norris
 Bryant Ou
 Carl-Daniel Hailfinger
@@ -105,7 +101,6 @@ Caveh Jalali
 Cavium Inc.
 Chao Gui
 Chen-Tsung Hsieh
-Chen. Gang C
 Chia-Ling Hou
 Chien-Chih Tseng
 Chris Wang
@@ -133,7 +128,6 @@ Da Lao
 Daisuke Nojiri
 Damien Zammit
 Dan Callaghan
-Dan Campbell
 Daniel Campello
 Daniel Gröber
 Daniel Kang
@@ -187,7 +181,6 @@ Eltan B.V
 Eltan B.V.
 Elyes Haouas
 Eran Mitrani
-Eren Peng
 Eric Biederman
 Eric Lai
 Eric Peers
@@ -201,16 +194,13 @@ Evan Green
 Evgeny Zinoviev
 Fabian Groffen
 Fabian Kunkel
-Fabian Meyer
 Fabio Aiuto
 Fabrice Bellard
 Facebook, Inc.
-Fei Yan
 Felix Friedlander
 Felix Held
 Felix Singer
 Fengquan Chen
-Filip Lewiński
 Flora Fu
 Florian Laufenböck
 Francois Toguo Fotso
@@ -224,7 +214,7 @@ Free Software Foundation, Inc.
 Freescale Semiconductor, Inc.
 Furquan Shaikh
 Gaggery Tsai
-Gang C Chen
+Gang C Chen 
 Garmin Chang
 Gary Jennejohn
 George Trudeau
@@ -244,7 +234,6 @@ HardenedLinux
 Harsha B R
 Harshit Sharma
 Henry C Chen
-Herbert Wu
 Hewlett Packard Enterprise Development LP
 Hewlett-Packard Development Company, L.P.
 Himanshu Sahdev
@@ -297,7 +286,6 @@ Jason Zhao
 jason-ch chen
 Jason-jh Lin
 Jay Patel
-Jean Lucas
 Jeff Chase
 Jeff Daly
 Jeff Li
@@ -319,7 +307,6 @@ Jitao Shi
 Joe Pillow
 Joe Tessler
 Joel Kitching
-Joel Linn
 Joey Peng
 Johanna Schander
 John Su
@@ -338,7 +325,6 @@ Jordan Crouse
 Jörg Mische
 Joseph Smith
 Josie Nordrum
-Juan José García-Castro Crespo
 Julia Tsai
 Julian Schroeder
 Julian Stecklina
@@ -351,7 +337,6 @@ Kangheui Won
 Kapil Porwal
 Karol Zmyslowski
 Karthik Ramasubramanian
-Kei Hiroyoshi
 Keith Hui
 Keith Packard
 Kenneth Chan
@@ -382,11 +367,9 @@ Lawrence Chang
 Leah Rowe
 Lean Sheng Tan
 Lei Wen
-Lennart Eichhorn
 Lenovo Group Ltd
 Leo Chou
 Li-Ta Lo
-Li1 Feng
 Liam Flaherty
 Libra Li
 Libretrend LDA
@@ -414,7 +397,6 @@ Marc Bertens
 Marc Jones
 Marco Chen
 Marek Kasiewicz
-Marek Maślanka
 Marek Vasut
 Mario Scheithauer
 Marius Gröger
@@ -483,12 +465,10 @@ Myles Watson
 Nancy.Lin
 Naresh Solanki
 Nathan Lu
-Naveen R. Iyer
 Neill Corlett
 Network Appliance Inc.
 Nicholas Chin
 Nicholas Sielicki
-Nicholas Sudsgaard
 Nick Barker
 Nick Chen
 Nick Vaccaro
@@ -522,7 +502,6 @@ Paul Fagerburg
 Paul Menzel
 Paul2 Huang
 Paulo Alcantara
-Pavan Holla
 Pavel Sayekat
 Paz Zcharya
 PC Engines GmbH
@@ -541,7 +520,6 @@ Philipp Deppenwiese
 Philipp Hug
 Piotr Kleinschmidt
 Po Xu
-Poornima Tom
 Prasad Malisetty
 Prashant Malani
 Pratik Vishwakarma
@@ -551,7 +529,6 @@ Protectli
 Purism SPC
 Purism, SPC
 Qii Wang
-Qinghong Zeng
 Qualcomm Technologies, Inc.
 Quanta Computer INC
 Raihow Shi
@@ -595,7 +572,6 @@ Robinson P. Tryon
 Rockchip, Inc.
 Rocky Phagura
 Roger Lu
-Roger Wang
 Roja Rani Yarubandi
 Romain Lievin
 Roman Zippel
@@ -769,14 +745,12 @@ Wojciech Macek
 Wolfgang Denk
 Won Chung
 Wonkyu Kim
-Wuxy
+Wuxy 
-Xiang W
 Xin Ji
 Xixi Chen
 Xuxin Xiong
 YADRO
 Yan Liu
-Yang Wu
 Yann Collet
 Yaroslav Kurlaev
 YH Lin
@@ -793,7 +767,6 @@ Yuanliding
 Yuchen He
 Yuchen Huang
 Yunlong Jia
-Yuval Peress
 Zachary Yedidia
 Zanxi Chen
 Zhanyong Wang
@@ -803,11 +776,10 @@ Zhi7 Li
 Zhiqiang Ma
 Zhixing Ma
 Zhiyong Tao
-Zhongtian Wu
+zhongtian wu
 Zhuohao Lee
 Ziang Wang
 Zoey Wu
 Zoltan Baldaszti
 小田喜陽彦
-忧郁沙茶
 陳建宏

Documentation/releases/coreboot-24.05-relnotes.md

@@ -1,76 +1,37 @@
-coreboot 24.05 release
+Upcoming release - coreboot 24.05
 ========================================================================
 
-The coreboot project is pleased to announce the release of coreboot version
+The 24.05 release is scheduled for Mid May, 2024
-24.05. This update represents three months of hard work and commitment from our
-community. With over 20 new members and contributions from more than a hundred
-fifty other people in coding, reviewing patches, and other areas, this release
-showcases the strength of our collaborative efforts.
 
-With this release, coreboot has expanded its support, adding 25 new platforms or
-variants and 2 new processors, further demonstrating our dedication to offering
-flexible and adaptable firmware solutions. From laptops and servers to embedded
-devices, coreboot 24.05 is designed to enhance a variety of hardware platforms
-with its strong features.
 
-We are grateful to all the contributors who have made this release possible.
+Update this document with changes that should be in the release notes.
-Your expertise and collaborative efforts continue to propel the coreboot project
-forward. We value the participation of everyone in the community, from long-time
-developers to those new to the project, and encourage you to explore the new
-opportunities that coreboot 24.05 offers.
 
-Our next release will be 24.08, scheduled for mid-August.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
 
 
 
 Significant or interesting changes
 ----------------------------------
 
-### Mark 64-bit support as stable
+* Add changes that need a full description here
 
-A significant amount of work has gone into fully supporting 64-bit coreboot
+* This section should have full descriptions and can or should have
-builds. There are still additional pieces that are happening, but with SMM
+  a link to the referenced commits.
-holding page tables itself, we can consider SMM support stable and safe enough
-for general use.
-
-
-### security/tpm: support compiling in multiple TPM drivers
-
-Previously, boards could only be built with code supporting TPM 1.x or TPM 2.x
-specifications. This has been updated with code allowing both to be built in
-simultaneously, allowing the system to query the TPM. For systems with
-soldered-down TPMs or firmware TPM solutions, it’s still possible to specify a
-single TPM version so that the code for the other version isn’t included.
-
-
-### arch/arm64: Add EL1/EL2/EL3 support for arm64
-
-Previously, arch/arm64 required coreboot to run on EL3 due to EL3 register
-access. This might be an issue when, for example, one boots into TF-A first and
-drops into EL2 for coreboot afterwards.
-
-This patch aims at making arch/arm64 more versatile by removing the current EL3
-constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3.
-
-The strategy is to add a Kconfig option (ARM64_CURRENT_EL) which allows us to
-specify coreboot's EL upon entry. Based on that, we access the appropriate ELx
-registers. So, for example, when running coreboot on EL1, we would not access
-vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults
-when accessing higher-EL registers.
 
 
 
 Additional coreboot changes
 ---------------------------
 
-* util/smmstoretool: support processing ROMs
+The following are changes across a number of patches, or changes worth
-* cpu/x86: Link page tables in stage if possible
+noting, but not needing a full description.
-* lib/lzmadecode: Allow for 8 byte reads on 64bit to speed up decompression
+
-* mb/lenovo/*: Set VR12 PSI to fix crash
+* Changes that only need a line or two of description go here.
-* Numerous fixes for clang support
-* Ongoing code cleanup
-* Docs: Replace Recommonmark with MyST Parser. For changes, see the commit
-  message in https://review.coreboot.org/73158
 
 
 
@@ -79,29 +40,11 @@ Changes to external resources
 
 ### Toolchain updates
 
-* util/kconfig: Uprev to Linux 6.8's kconfig
-* crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
-* util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
-* crossgcc: Upgrade binutils from 2.41 to 2.42
-* util/crossgcc/buildgcc: Use Intel mirror for ACPICA
-
 
 ### Git submodule pointers
 
-- amd_blobs: Update from commit id 64cdd7c8ef to ae5fc7d277 (1 commits)
-- arm-trusted-firmware: Update from commit id 17bef2248d to 48f1bc9f52 (517
-  commits)
-- cmocka: Update from commit id 8931845c35 to 8be3737209 (32 commits)
-- fsp: Update from commit id 507ef01cce to cc6399e8c7 (14 commits)
-- intel-microcode: Update from commit id ece0d294a2 to 41af345005 (1 commit)
-- vboot: Update from commit id 3d37d2aafe to 09fcd2184f (27 commits)
 
-
+### External payloads
-#### External payloads
-
-* payloads/U-Boot: Upgrade from U-Boot v2023.07 to v2024.4
-* payloads/edk2: Add Kconfig options for LAPIC timer & UFS support
-* payloads/Kconfig: Add flat binary as payload option
 
 
 
@@ -109,155 +52,42 @@ Platform Updates
 ----------------
 
 ### Added mainboards:
-
+* To be filled in immediately before the release by the release team
-* AMD BirmanPlus for Glinda SoC
-* AMD BirmanPlus for Phoenix SoC
-* ASROCK Z97 Extreme6
-* Dell OptiPlex 7020/9020 MT
-* Dell OptiPlex 7020/9020 SFF
-* Framework Azalea (Framework 13 AMD 7040)
-* Google Brox EC ISH
-* Google Bujia
-* Google Glassway
-* Google Greenbayupoc
-* Google Kyogre
-* Google Lotso
-* Google Nova
-* Google Pujjoga
-* Google Riven
-* Google Skitty
-* Google Squirtle
-* Google Sundance
-* Google Tivviks
-* Google Trulo
-* Google Veluza
-* Google Wugtrio
-* Google Yavista
-* HP Pro 3500 Series
-* Lenovo ThinkCentre M700 / M900 Tiny
-* Lenovo ThinkCentre M710s
-* Raptor Computing Systems Talos II
-* SiFive HiFive Unmatched
 
 
 ### Removed Mainboards
-
+* To be filled in immediately before the release by the release team
-* Intel Alderlake-M RVP
-* Intel Alderlake-M RVP with Chrome EC
 
 
 ### Updated SoCs
-
+* To be filled in immediately before the release by the release team
-* Added src/soc/ibm/power9
-* Added src/soc/intel/xeon_sp/gnr
-* Added src/soc/sifive/fu740
 
 
 
-Statistics from the 24.02 to the 24.05 release
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 4.22 to the 24.02 release
 --------------------------------------------
+* To be filled in immediately before the release by the release team
 
-* Total Commits: 739
-* Average Commits per day: 8.64
-* Total lines added: 304721
-* Average lines added per commit: 412.34
-* Number of patches adding more than 100 lines: 60
-* Average lines added per small commit: 37.74
-* Total lines removed: 16195
-* Average lines removed per commit: 21.91
-* Total difference between added and removed: 288526
-* Total authors: 131
-* New authors: 23
 
 
 Significant Known and Open Issues
 ---------------------------------
 
-## coreboot-wide or architecture-wide issues
+Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+* To be filled in immediately before the release by the release team
 
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 522 | 'region_overlap()' issues due to an integer overflow.           |
-+-----+-----------------------------------------------------------------+
-| 519 | make gconfig - could not find glade file                        |
-+-----+-----------------------------------------------------------------+
-| 518 | make xconfig - g++: fatal error: no input files                 |
-+-----+-----------------------------------------------------------------+
-```
-
-
-## Payload-specific issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-```
-
-
-## Platform-specific issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx    |
-+-----+-----------------------------------------------------------------+
-| 517 | lenovo x230 boot stuck with connected external monitor          |
-+-----+-----------------------------------------------------------------+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-```
 
 
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Website: https://www.coreboot.org
+* Main Web site: https://www.coreboot.org
 * Downloads: https://coreboot.org/downloads.html
 * Source control: https://review.coreboot.org
 * Documentation: https://doc.coreboot.org

Documentation/releases/coreboot-24.08-relnotes.md

@@ -1,100 +0,0 @@
-Upcoming release - coreboot 24.08
-========================================================================
-
-The 24.08 release is scheduled for Mid Aug, 2024
-
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-
-
-Significant or interesting changes
-----------------------------------
-
-* Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain updates
-
-* Upgrade ACPICA from 20230628 to 20240321
-* Upgrade CMake from 3.28.3 to 3.29.3
-* Upgrade nasm from 2.16.01 to 2.16.03
-* Upgrade LLVM from 17.0.6 to 18.1.6
-* Upgrade GCC from 13.2 to 14.1.0
-
-### Git submodule pointers
-
-
-### External payloads
-
-
-
-Platform Updates
-----------------
-
-### Added mainboards:
-* To be filled in immediately before the release by the release team
-
-
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
-
-
-### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Statistics from the 24.05 to the 24.08 release
---------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-* To be filled in immediately before the release by the release team
-
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/index.md

@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-24.08 - August 2024 <coreboot-24.08-relnotes.md>
+24.05 - May 2024 <coreboot-24.05-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,7 +22,6 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
-24.05  - May 2024 <coreboot-24.05-relnotes.md>
 24.02  - February 2024 <coreboot-24.02-relnotes.md>
 4.22   - November 2023 <coreboot-4.22-relnotes.md>
 4.21   - August 2023 <coreboot-4.21-relnotes.md>

Documentation/security/vboot/list_vboot.md

@@ -4,8 +4,6 @@
 - Birman for Phoenix SoC using FSP
 - Birman for Phoenix SoC using openSIL
 - Birman for Glinda SoC
-- BirmanPlus for Phoenix SoC
-- BirmanPlus for Glinda SoC
 - Chausie
 - Majolica
 - Mayan for Phoenix SoC
@@ -37,9 +35,6 @@
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
 - Brox
-- Brox EC ISH
-- Lotso
-- Greenbayupoc
 - Agah
 - Anahera
 - Anahera4ES
@@ -58,7 +53,6 @@
 - Gimble
 - Gimble4ES
 - Gladios
-- Glassway
 - Gothrax
 - Hades
 - Kano
@@ -80,14 +74,11 @@
 - Quandiso
 - Redrix
 - Redrix4ES
-- Riven
 - Skolas
 - Skolas4ES
 - Taeko
 - Taeko4ES
 - Taniks
-- Tivviks
-- Trulo
 - Uldren
 - Vell
 - Volmar
@@ -96,29 +87,19 @@
 - Yavilla
 - Zydron
 - Xol
-- Nova
-- Bujia
-- Yavista
-- Sundance
-- Pujjoga
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
-- Kyogre
-- Ponyta
-- Squirtle
 - Steelix
 - Voltorb
-- Chinchou
+- Ponyta
 - Krabby
-- Magikarp
-- Skitty
 - Tentacruel
-- Veluza
+- Magikarp
+- Chinchou
 - Starmie
-- Wugtrio
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -324,6 +305,8 @@
 - Alderlake-P RVP
 - Alderlake-P RVP with Chrome EC
 - Alderlake-P RVP with Microchip EC
+- Alderlake-M RVP
+- Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
 - Raptorlake silicon with Alderlake-P RVP
@@ -382,7 +365,6 @@
 - ThinkPad X230
 - ThinkPad X230t
 - ThinkPad X230s
-- ThinkPad X230 eDP Mod (2K/FHD)
 - ThinkPad X60 / X60s / X60t
 
 ## MSI

configs/builder/config.intel.crb.avc

@@ -1,50 +0,0 @@
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc
-
-#
-# [RO] Board Configurations
-#
-CONFIG_VENDOR_INTEL=y
-CONFIG_BOARD_INTEL_AVENUECITY_CRB=y
-
-CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
-CONFIG_CONFIGURABLE_RAMSTAGE=y
-
-CONFIG_NO_GFX_INIT=y
-
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_PAYLOAD_LINUX=y
-
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_CONSOLE_SERIAL_115200=y
-
-#
-# [RW] IFWI Ingredients
-#
-CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb"
-CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/"
-
-CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage"
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-
-#
-# [RW] Debug Settings
-#
-CONFIG_CONSOLE_POST=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
-
-CONFIG_VERIFY_HOBS=y
-CONFIG_DISPLAY_MTRRS=y
-
-CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
-CONFIG_DISPLAY_FSP_HEADER=y
-
-CONFIG_HAVE_DEBUG_GPIO=y
-CONFIG_DEBUG_GPIO=y

configs/builder/config.intel.crb.bnc

@@ -1,50 +0,0 @@
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc
-
-#
-# [RO] Board Configurations
-#
-CONFIG_VENDOR_INTEL=y
-CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y
-
-CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
-CONFIG_CONFIGURABLE_RAMSTAGE=y
-
-CONFIG_NO_GFX_INIT=y
-
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_PAYLOAD_LINUX=y
-
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_CONSOLE_SERIAL_115200=y
-
-#
-# [RW] IFWI Ingredients
-#
-CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb"
-CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
-
-CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage"
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-
-#
-# [RW] Debug Settings
-#
-CONFIG_CONSOLE_POST=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
-
-CONFIG_VERIFY_HOBS=y
-CONFIG_DISPLAY_MTRRS=y
-
-CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
-CONFIG_DISPLAY_FSP_HEADER=y
-
-CONFIG_HAVE_DEBUG_GPIO=y
-CONFIG_DEBUG_GPIO=y

configs/config.protectli_vp4630_vp4650

@@ -0,0 +1,13 @@
+CONFIG_VENDOR_PROTECTLI=y
+CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_SMMSTORE_SIZE=0x40000
+CONFIG_TPM2=y
+CONFIG_POST_IO_PORT=0x80
+CONFIG_PAYLOAD_EDK2=y
+CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
+CONFIG_EDK2_BOOT_TIMEOUT=6
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
+CONFIG_EDK2_SD_MMC_TIMEOUT=10
+CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.protectli_vp4670

@@ -1,5 +1,5 @@
 CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP46XX=y
+CONFIG_BOARD_PROTECTLI_VP4670=y
 CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_SMMSTORE_SIZE=0x40000
 CONFIG_TPM2=y

payloads/external/LinuxBoot/Makefile

@@ -33,7 +33,7 @@ endif
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
 
-build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage build/initramfs | build
+build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build
 	cp $< $@
 
 else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)

payloads/external/Makefile.mk

@@ -381,7 +381,6 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT)
 	CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \
 	CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \
 	CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \
-	CONFIG_PXE_TRUST_CMD=$(CONFIG_PXE_TRUST_CMD) \
 	MFLAGS= MAKEFLAGS=
 
 # LinuxBoot

payloads/external/edk2/Makefile

@@ -37,8 +37,6 @@ BUILD_STR += -s
 endif
 endif
 
-BUILD_STR += -D BUILD_ARCH=X64
-
 #
 # EDK II (edk2/master) has the following build options relevant to coreboot:
 #

payloads/external/iPXE/Kconfig

@@ -108,16 +108,7 @@ config IPXE_HAS_HTTPS
 	  Enable HTTPS protocol, which allows you to encrypt all communication
 	  with a web server and to verify the server's identity
 
-config PXE_TRUST_CMD
-	bool "Enable TRUST commands"
-	default y
-	help
-	  Enable imgverify and imgtrust commands, which allow you to verify
-	  digital signature of file prior loading it, and restrict to loading
-	  trusted files only.
-
 endif # BUILD_IPXE
-
 endmenu
 
 endif # PXE

payloads/external/iPXE/Makefile

@@ -52,9 +52,6 @@ endif
 ifeq ($(CONFIG_IPXE_HAS_HTTPS),y)
 	sed -i'' 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h"
 endif
-ifeq ($(CONFIG_PXE_TRUST_CMD),y)
-	sed -i'' 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h"
-endif
 
 build: config $(CONFIG_SCRIPT)
 ifeq ($(CONFIG_HAS_SCRIPT),y)

payloads/libpayload/Kconfig

@@ -106,22 +106,17 @@ menu "Architecture Options"
 
 choice
         prompt "Target Architecture"
-        default ARCH_X86_32
+        default ARCH_X86
 
 config ARCH_ARM
         bool "ARM"
         help
           Support the ARM architecture
 
-config ARCH_X86_32
+config ARCH_X86
-        bool "x86_32"
+        bool "x86"
         help
-          Support the x86_32 architecture
+          Support the x86 architecture
-
-config ARCH_X86_64
-        bool "x86_64"
-        help
-          Support the x86_64 architecture
 
 config ARCH_ARM64
         bool "ARM64"
@@ -138,12 +133,6 @@ config ARCH_MOCK
 
 endchoice
 
-config ARCH_X86
-	bool
-	default y if ARCH_X86_32 || ARCH_X86_64
-	help
-	  Support the x86 architecture
-
 config MULTIBOOT
 	bool "Multiboot header support"
 	depends on ARCH_X86

payloads/libpayload/Makefile

@@ -118,8 +118,7 @@ ARCH-y := $(ARCHDIR-y)
 # override here.
 ARCH-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCH-$(CONFIG_LP_ARCH_ARM64)   := arm64
-ARCH-$(CONFIG_LP_ARCH_X86_32)  := x86_32
+ARCH-$(CONFIG_LP_ARCH_X86)     := x86_32
-ARCH-$(CONFIG_LP_ARCH_X86_64)  := x86_64
 ARCH-$(CONFIG_LP_ARCH_MOCK)    := mock
 
 # Five cases where we don't need fully populated $(obj) lists:

payloads/libpayload/Makefile.mk

@@ -56,6 +56,7 @@ classes-$(CONFIG_LP_REMOTEGDB) += libgdb
 classes-$(CONFIG_LP_VBOOT_LIB) += vboot_fw
 classes-$(CONFIG_LP_VBOOT_LIB) += tlcl
 libraries := $(classes-y)
+classes-y += head.o
 
 subdirs-y := arch/$(ARCHDIR-y)
 subdirs-y += crypto libc drivers libpci gdb
@@ -96,7 +97,7 @@ $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) $(obj)/libpayload.config
 	cmp $@ $< 2>/dev/null || cp $< $@
 
 library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a
-lib: $$(library-targets) $(obj)/libpayload.ldscript
+lib: $$(library-targets) $(obj)/head.o
 
 extract_nth=$(word $(1), $(subst |, ,$(2)))
 
@@ -115,16 +116,17 @@ $(obj)/%.a: $$(%-objs)
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
 	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
 
-$(obj)/libpayload.ldscript: arch/$(ARCHDIR-y)/libpayload.ldscript $(obj)/libpayload-config.h
+$(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o
-	@printf "  LDSCRIPT  $@\n"
+	printf "    CP         $(subst $(CURDIR)/,,$(@))\n"
-	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -P -x assembler-with-cpp -undef -o $@ $<
+	cp $^ $@
 
 install: real-target
 	printf "    INSTALL    $(DESTDIR)/libpayload/lib\n"
 	install -m 755 -d $(DESTDIR)/libpayload/lib
 	install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/
-	install -m 644 $(obj)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
+	install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
 	install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
+	install -m 644 $(obj)/head.o $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
 	printf "    INSTALL    $(DESTDIR)/libpayload/include\n"
 	install -m 755 -d $(DESTDIR)/libpayload/include
 	find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \;

payloads/libpayload/arch/arm/Makefile.mk

@@ -29,7 +29,7 @@
 CFLAGS += -mthumb -march=armv7-a
 arm_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
 
-libc-y += head.S
+head.o-y += head.S
 libc-y += eabi_compat.c
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
@@ -44,4 +44,5 @@ libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S
 libgdb-y += gdb.c
 
 # Add other classes here when you put assembly files into them!
+head.o-S-ccopts += $(arm_asm_flags)
 libc-S-ccopts += $(arm_asm_flags)

payloads/libpayload/arch/arm64/Makefile.mk

@@ -29,7 +29,7 @@
 CFLAGS += -march=armv8-a
 arm64_asm_flags =
 
-libc-y += head.S
+head.o-y += head.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
 libc-y += virtual.c
@@ -42,4 +42,5 @@ libc-y += mmu.c
 libgdb-y += gdb.c
 
 # Add other classes here when you put assembly files into them!
-libc-S-ccopts += $(arm64_asm_flags)
+ head.o-S-ccopts += $(arm64_asm_flags)
+ libc-S-ccopts += $(arm64_asm_flags)

payloads/libpayload/arch/mock/Makefile.mk

@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
+head.o-y += head.c
+
 libc-y += virtual.c
 
 CFLAGS += -Wno-address-of-packed-member

payloads/libpayload/arch/mock/head.c

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file is empty on purpose. It should not be used. */

payloads/libpayload/arch/x86/Makefile.mk

@@ -27,26 +27,16 @@
 ##
 
 ifneq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y)
-ifeq ($(CONFIG_LP_ARCH_X86_64),y)
-CFLAGS += -mpreferred-stack-boundary=4
-else
 CFLAGS += -mpreferred-stack-boundary=2
 endif
-endif
 
-libc-$(CONFIG_LP_ARCH_X86_32)  += head.S
+head.o-y += head.S
-libc-$(CONFIG_LP_ARCH_X86_64)  += head_64.S
-libc-$(CONFIG_LP_ARCH_X86_64) += pt.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
-libc-y += virtual.c
+libc-y += exec.S virtual.c
 libc-y += selfboot.c cache.c
-libc-y += exception.c
+libc-y += exception_asm.S exception.c
 libc-y += delay.c
-libc-$(CONFIG_LP_ARCH_X86_32) += exec.c
-libc-$(CONFIG_LP_ARCH_X86_32) += exec.S
-libc-$(CONFIG_LP_ARCH_X86_32) += exception_asm.S
-libc-$(CONFIG_LP_ARCH_X86_64) += exception_asm_64.S
 
 # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed.
 libc-$(CONFIG_LP_GPL) += string.c

payloads/libpayload/arch/x86/exception.c

@@ -34,13 +34,7 @@
 
 #define IF_FLAG				(1 << 9)
 
-#if CONFIG(LP_ARCH_X86_64)
+u32 exception_stack[0x400] __attribute__((aligned(8)));
-#define REGISTER_FMT "0x%016zx"
-#else
-#define REGISTER_FMT "0x%08zx"
-#endif
-
-u8 exception_stack[0x400] __aligned(16);
 
 static interrupt_handler handlers[256];
 
@@ -149,27 +143,17 @@ static void dump_exception_state(void)
 		break;
 	}
 	printf("\n");
-	printf("REG_IP:    " REGISTER_FMT "\n", exception_state->regs.reg_ip);
+	printf("EIP:    0x%08x\n", exception_state->regs.eip);
-	printf("REG_FLAGS: " REGISTER_FMT "\n", exception_state->regs.reg_flags);
-	printf("REG_AX:    " REGISTER_FMT "\n", exception_state->regs.reg_ax);
-	printf("REG_BX:    " REGISTER_FMT "\n", exception_state->regs.reg_bx);
-	printf("REG_CX:    " REGISTER_FMT "\n", exception_state->regs.reg_cx);
-	printf("REG_DX:    " REGISTER_FMT "\n", exception_state->regs.reg_dx);
-	printf("REG_SP:    " REGISTER_FMT "\n", exception_state->regs.reg_sp);
-	printf("REG_BP:    " REGISTER_FMT "\n", exception_state->regs.reg_bp);
-	printf("REG_SI:    " REGISTER_FMT "\n", exception_state->regs.reg_si);
-	printf("REG_DI:    " REGISTER_FMT "\n", exception_state->regs.reg_di);
-#if CONFIG(LP_ARCH_X86_64)
-	printf("REG_R8:    0x%016zx\n", exception_state->regs.reg_r8);
-	printf("REG_R9:    0x%016zx\n", exception_state->regs.reg_r9);
-	printf("REG_R10:    0x%016zx\n", exception_state->regs.reg_r10);
-	printf("REG_R11:    0x%016zx\n", exception_state->regs.reg_r11);
-	printf("REG_R12:    0x%016zx\n", exception_state->regs.reg_r12);
-	printf("REG_R13:    0x%016zx\n", exception_state->regs.reg_r13);
-	printf("REG_R14:    0x%016zx\n", exception_state->regs.reg_r14);
-	printf("REG_R15:    0x%016zx\n", exception_state->regs.reg_r15);
-#endif
 	printf("CS:     0x%04x\n", exception_state->regs.cs);
+	printf("EFLAGS: 0x%08x\n", exception_state->regs.eflags);
+	printf("EAX:    0x%08x\n", exception_state->regs.eax);
+	printf("ECX:    0x%08x\n", exception_state->regs.ecx);
+	printf("EDX:    0x%08x\n", exception_state->regs.edx);
+	printf("EBX:    0x%08x\n", exception_state->regs.ebx);
+	printf("ESP:    0x%08x\n", exception_state->regs.esp);
+	printf("EBP:    0x%08x\n", exception_state->regs.ebp);
+	printf("ESI:    0x%08x\n", exception_state->regs.esi);
+	printf("EDI:    0x%08x\n", exception_state->regs.edi);
 	printf("DS:     0x%04x\n", exception_state->regs.ds);
 	printf("ES:     0x%04x\n", exception_state->regs.es);
 	printf("SS:     0x%04x\n", exception_state->regs.ss);
@@ -180,7 +164,7 @@ static void dump_exception_state(void)
 void exception_dispatch(void)
 {
 	die_if(exception_state->vector >= ARRAY_SIZE(handlers),
-	       "Invalid vector %zu\n", exception_state->vector);
+	       "Invalid vector %u\n", exception_state->vector);
 
 	u8 vec = exception_state->vector;
 
@@ -200,7 +184,7 @@ void exception_dispatch(void)
 	       vec);
 
 	dump_exception_state();
-	dump_stack(exception_state->regs.reg_sp, 512);
+	dump_stack(exception_state->regs.esp, 512);
 	/* We don't call apic_eoi because we don't want to ack the interrupt and
 	   allow another interrupt to wake the processor. */
 	halt();
@@ -213,10 +197,6 @@ success:
 
 void exception_init(void)
 {
-	/* TODO: Add exception init code for x64, currently only supporting 32-bit code */
-	if (CONFIG(LP_ARCH_X86_64))
-		return;
-
 	exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
 	exception_init_asm();
 }
@@ -226,17 +206,6 @@ void set_interrupt_handler(u8 vector, interrupt_handler handler)
 	handlers[vector] = handler;
 }
 
-#if CONFIG(LP_ARCH_X86_64)
-static uint64_t eflags(void)
-{
-	uint64_t eflags;
-	asm volatile(
-		"pushfq\n\t"
-		"popq %0\n\t"
-	: "=rm" (eflags));
-	return eflags;
-}
-#else
 static uint32_t eflags(void)
 {
 	uint32_t eflags;
@@ -246,7 +215,6 @@ static uint32_t eflags(void)
 	: "=rm" (eflags));
 	return eflags;
 }
-#endif
 
 void enable_interrupts(void)
 {

payloads/libpayload/arch/x86/exception_asm_64.S

@@ -1,221 +0,0 @@
-/*
- *
- * Copyright 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-	.align 16
-	.global exception_stack_end
-exception_stack_end:
-	.quad 0
-	.global exception_state
-exception_state:
-	.quad 0
-
-/* Some temporary variables which are used while saving exception state. */
-vector:
-	.quad 0
-error_code:
-	.quad 0
-old_rsp:
-	.quad 0
-old_rax:
-	.quad 0
-
-	.align 16
-
-/*
- * Each exception vector has a small stub associated with it which sets aside
- * the error code, if any, records which vector we entered from, and calls
- * the common exception entry point. Some exceptions have error codes and some
- * don't, so we have a macro for each type.
- */
-
-	.macro stub num
-exception_stub_\num:
-	movq	$0, error_code
-	movq	$\num, vector
-	jmp	exception_common
-	.endm
-
-	.macro stub_err num
-exception_stub_\num:
-	pop	error_code
-	movq	$\num, vector
-	jmp	exception_common
-	.endm
-
-	.altmacro
-	.macro	user_defined_stubs from, to
-	stub	\from
-	.if	\to-\from
-	user_defined_stubs	%(from+1),\to
-	.endif
-	.endm
-
-	stub 0
-	stub 1
-	stub 2
-	stub 3
-	stub 4
-	stub 5
-	stub 6
-	stub 7
-	stub_err 8
-	stub 9
-	stub_err 10
-	stub_err 11
-	stub_err 12
-	stub_err 13
-	stub_err 14
-	stub 15
-	stub 16
-	stub_err 17
-	stub 18
-	stub 19
-	stub 20
-	stub 21
-	stub 22
-	stub 23
-	stub 24
-	stub 25
-	stub 26
-	stub 27
-	stub 28
-	stub 29
-	stub_err 30
-	stub 31
-	/* Split the macro so we avoid a stack overflow. */
-	user_defined_stubs 32, 63
-	user_defined_stubs 64, 127
-	user_defined_stubs 128, 191
-	user_defined_stubs 192, 255
-
-exception_common:
-
-	/* Return from the exception. */
-	iretl
-
-/*
- * We need segment selectors for the IDT, so we need to know where things are
- * in the GDT. We set one up here which is pretty standard and largely copied
- * from coreboot.
- */
-	.align 16
-gdt:
-	/* selgdt 0, unused */
-	.word 0x0000, 0x0000
-	.byte 0x00, 0x00, 0x00, 0x00
-
-	/* selgdt 8, unused */
-	.word 0x0000, 0x0000
-	.byte 0x00, 0x00, 0x00, 0x00
-
-	/* selgdt 0x10, flat 4GB code segment */
-	.word 0xffff, 0x0000
-	.byte 0x00, 0x9b, 0xcf, 0x00
-
-	/* selgdt 0x18, flat 4GB data segment */
-	.word 0xffff, 0x0000
-	.byte	0x00, 0x92, 0xcf, 0x00
-
-	/* selgdt 0x20, flat x64 code segment */
-	.word	0xffff, 0x0000
-	.byte	0x00, 0x9b, 0xaf, 0x00
-gdt_end:
-
-/* GDT pointer for use with lgdt */
-.global gdt_ptr
-gdt_ptr:
-	.word	gdt_end - gdt - 1
-	.quad	gdt
-
-	/*
-	 * Record the target and construct the actual entry at init time. This
-	 * is necessary because the linker doesn't want to construct the entry
-	 * for us.
-	 */
-	.macro interrupt_gate target
-	.quad \target
-	.quad \target
-	.endm
-
-	.altmacro
-	.macro	user_defined_gates from, to
-	interrupt_gate	exception_stub_\from
-	.if	\to-\from
-	user_defined_gates	%(from+1),\to
-	.endif
-	.endm
-
-	.align 16
-	.global	idt
-idt:
-	interrupt_gate exception_stub_0
-	interrupt_gate exception_stub_1
-	interrupt_gate exception_stub_2
-	interrupt_gate exception_stub_3
-	interrupt_gate exception_stub_4
-	interrupt_gate exception_stub_5
-	interrupt_gate exception_stub_6
-	interrupt_gate exception_stub_7
-	interrupt_gate exception_stub_8
-	interrupt_gate exception_stub_9
-	interrupt_gate exception_stub_10
-	interrupt_gate exception_stub_11
-	interrupt_gate exception_stub_12
-	interrupt_gate exception_stub_13
-	interrupt_gate exception_stub_14
-	interrupt_gate exception_stub_15
-	interrupt_gate exception_stub_16
-	interrupt_gate exception_stub_17
-	interrupt_gate exception_stub_18
-	interrupt_gate exception_stub_19
-	interrupt_gate exception_stub_20
-	interrupt_gate exception_stub_21
-	interrupt_gate exception_stub_22
-	interrupt_gate exception_stub_23
-	interrupt_gate exception_stub_24
-	interrupt_gate exception_stub_25
-	interrupt_gate exception_stub_26
-	interrupt_gate exception_stub_27
-	interrupt_gate exception_stub_28
-	interrupt_gate exception_stub_29
-	interrupt_gate exception_stub_30
-	interrupt_gate exception_stub_31
-	user_defined_gates 32, 63
-	user_defined_gates 64, 127
-	user_defined_gates 128, 191
-	user_defined_gates 192, 255
-idt_end:
-
-/* IDT pointer for use with lidt */
-idt_ptr:
-	.word idt_end - idt - 1
-	.quad idt
-
-	.global exception_init_asm
-exception_init_asm:
-	ret

payloads/libpayload/arch/x86/gdb.c

@@ -15,7 +15,6 @@
 #include <exception.h>
 #include <gdb.h>
 #include <libpayload.h>
-#include <stddef.h>
 
 static const u8 type_to_signal[] = {
 	[EXC_DE]  = GDB_SIGFPE,
@@ -54,15 +53,12 @@ void gdb_arch_init(void)
 
 void gdb_arch_enter(void)
 {
-	u8 *stack_pointer;
+	u32 *esp;
-#if CONFIG(LP_ARCH_X86_64)
+
-	asm volatile ("movq %%rsp, %0" : "=r"(stack_pointer));
+	asm volatile ("mov %%esp, %0" : "=r"(esp) );
-#else
-	asm volatile ("mov %%esp, %0" : "=r"(stack_pointer));
-#endif
 
 	/* Avoid reentrant exceptions, just call the hook if in one already. */
-	if (stack_pointer >= exception_stack && stack_pointer <= exception_stack_end)
+	if (esp >= exception_stack && esp <= exception_stack_end)
 		gdb_exception_hook(EXC_BP);
 	else
 		asm volatile ("int3");
@@ -70,12 +66,12 @@ void gdb_arch_enter(void)
 
 int gdb_arch_set_single_step(int on)
 {
-	const size_t tf_bit = 1 << 8;
+	const u32 tf_bit = 1 << 8;
 
 	if (on)
-		exception_state->regs.reg_flags |= tf_bit;
+		exception_state->regs.eflags |= tf_bit;
 	else
-		exception_state->regs.reg_flags &= ~tf_bit;
+		exception_state->regs.eflags &= ~tf_bit;
 
 	return 0;
 }

payloads/libpayload/arch/x86/head.S

@@ -29,7 +29,7 @@
 
 	.code32
 	.global _entry
-	.section .text._entry
+	.text
 	.align 4
 
 /*
@@ -38,14 +38,37 @@
  * change anything.
  */
 _entry:
+	jmp _init
 
-	/* Add multiboot header and jump around it when building with multiboot support. */
+	.align 4
-#if CONFIG(LP_MULTIBOOT)
+
-	#include "multiboot_header.inc"
+#define MB_MAGIC 0x1BADB002
-#endif
+#define MB_FLAGS 0x00010003
+
+mb_header:
+	.long MB_MAGIC
+	.long MB_FLAGS
+	.long -(MB_MAGIC + MB_FLAGS)
+	.long mb_header
+	.long _start
+	.long _edata
+	.long _end
+	.long _init
+
+/*
+ * This function saves off the previous stack and switches us to our
+ * own execution environment.
+ */
+_init:
 	/* No interrupts, please. */
 	cli
 
+#if CONFIG(LP_MULTIBOOT)
+	/* Store EAX and EBX */
+	movl %eax, loader_eax
+	movl %ebx, loader_ebx
+#endif
+
 	/* save pointer to coreboot tables */
 	movl 4(%esp), %eax
 	movl %eax, cb_header_ptr

payloads/libpayload/arch/x86/head_64.S

@@ -1,141 +0,0 @@
-/*
- *
- * Copyright (C) 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#define IA32_EFER	0xC0000080
-#define  EFER_LME	(1 << 8)
-
-	.code32
-	.global _entry
-	.section .text._entry
-	.align 4
-
-/*
- * WARNING: Critical Code Section - 32/64-bit Compatibility
- * This code between `_entry` and `jnz _init64` is executed during system initialization.
- * It MUST function correctly regardless of whether the system is booting in:
- *   - 32-bit protected mode
- *   - 64-bit long mode
- * To achieve this, ONLY use instructions that produce identical binary output in both modes.
- * Thoroughly test ALL modifications to this section in BOTH 32-bit and 64-bit boot
- * environments.
- */
-
-_entry:
-
-	/* Add multiboot header and jump around it when building with multiboot support. */
-#if CONFIG(LP_MULTIBOOT)
-	#include "multiboot_header.inc"
-#endif
-	/* No interrupts, please. */
-	cli
-
-	movl $IA32_EFER, %ecx
-	rdmsr
-	testl $EFER_LME, %eax
-	jnz _init64
-
-	lgdt %cs:gdt_ptr
-
-	/* save pointer to coreboot tables */
-	movl 4(%esp), %eax
-	/*
-	 * NOTE: coreboot tables has passed over the top of the stack
-	 * while calling in protected mode.
-	 */
-	movl %eax, cb_header_ptr
-
-	call init_page_table
-	movl $pm4le, %eax
-
-	/* load identity mapped page tables */
-	movl %eax, %cr3
-
-	/* enable PAE */
-	movl %cr4, %eax
-	btsl $5, %eax
-	movl %eax, %cr4
-
-	/* enable long mode */
-	movl $(IA32_EFER), %ecx
-	rdmsr
-	btsl $8, %eax
-	wrmsr
-
-	/* enable paging */
-	movl %cr0, %eax
-	btsl $31, %eax
-	movl %eax, %cr0
-
-	/* Jump to selgdt 0x20, flat x64 code segment */
-	ljmp $0x20, $_entry64
-
-.code64
-.align 16
-_init64:
-	movabs	$gdt_ptr, %rax
-	lgdt	(%rax)
-
-	/*
-	 * Note: The `cb_header_ptr` has passed as the first argument
-	 * to the x86-64 calling convention.
-	 */
-	movq %rdi, cb_header_ptr
-
-	call init_page_table
-	movq $pm4le, %rax
-
-	/* load identity mapped page tables */
-	movq %rax, %cr3
-
-_entry64:
-	/* Store current stack pointer and set up new stack. */
-	movq %rsp, %rax
-	movabs	$_estack, %rsp
-
-	push %rax
-
-	fninit
-	movq %cr0, %rax
-	andq $0xFFFFFFFFFFFFFFFB, %rax	/* clear EM */
-	orq $0x00000022, %rax	/* set MP, NE */
-	movq %rax, %cr0
-
-	movq %cr4, %rax
-	orq $0x00000600, %rax	/* set OSFXSR, OSXMMEXCPT */
-	movq %rax, %cr4
-
-	/* Let's rock. */
-	call start_main
-
-	/* %rax has the return value - pass it on unmolested */
-_leave:
-	/* Restore old stack. */
-	pop %rsp
-
-	/* Return to the original context. */
-	ret

payloads/libpayload/arch/x86/libpayload.ldscript

@@ -26,13 +26,8 @@
  * SUCH DAMAGE.
  */
 
-#if CONFIG(LP_ARCH_X86_64)
-OUTPUT_FORMAT(elf64-x86-64)
-OUTPUT_ARCH(x86_64)
-#else
 OUTPUT_FORMAT(elf32-i386)
 OUTPUT_ARCH(i386)
-#endif
 
 ENTRY(_entry)
 

payloads/libpayload/arch/x86/multiboot_header.inc

@@ -1,54 +0,0 @@
-/*
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
- * Copyright (C) 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#define MB_MAGIC 0x1BADB002
-#define MB_FLAGS 0x00010003
-
-	jmp _init
-
-/*
- * Note: The Multiboot standard requires Multiboot header to be placed
- * below 0x2000 in the resulting image.  See:
- * http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
- */
-mb_header:
-	.long MB_MAGIC
-	.long MB_FLAGS
-	.long -(MB_MAGIC + MB_FLAGS)
-	.long mb_header
-	.long _start
-	.long _edata
-	.long _end
-	.long _init
-
-_init:
-	/* Store EAX and EBX */
-	movl %eax, loader_eax
-	movl %ebx, loader_ebx

payloads/libpayload/arch/x86/pt.S

@@ -1,149 +0,0 @@
-/*
- *
- * Copyright 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * For reference see "AMD64 Architecture Programmer's Manual Volume 2",
- * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4
- *
- * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty
- */
-
-.section .bss
-#define _PRES (1ULL << 0)
-#define _RW   (1ULL << 1)
-#define _US   (1ULL << 2)
-#define _A    (1ULL << 5)
-#define _D    (1ULL << 6)
-#define _PS   (1ULL << 7)
-
-.section .bss.pm4le
-.global pm4le
-.align 4096
-pm4le:
-.skip 8
-
-.section .bss.main_page_table
-.global main_page_table
-.align 4096
-main_page_table:
-.skip 8192
-
-.section .bss.extra_page_table
-.global extra_page_table
-.align 4096
-extra_page_table:
-.skip 32
-
-/*
- * WARNING: 32-bit/64-bit Mode Compatibility for Page Table Initialization
- * This `init_page_table` function is designed to work in both 32-bit protected
- * mode AND 64-bit long mode.
- *
- * Key Considerations:
- * - Assembly Instructions:  Use ONLY instructions that have the SAME binary representation
- *                           in both 32-bit and 64-bit modes.
- * - `.code64` Directive:  We're compiling with `.code64` to ensure the assembler uses
- *                         the correct 64-bit version of instructions (e.g., `inc`).
- * - Register Notation:
- *     - Use 64-bit register names (like `%rsi`) for register-indirect addressing to avoid
- *       incorrect address size prefixes.
- *     - It's safe to use `%esi` with `mov` instructions, as the high 32 bits are zeroed
- *       in 64-bit mode.
- *
- * IMPORTANT:
- * Thoroughly test ANY changes to this function in BOTH 32-bit and 64-bit boot environments.
- */
-
-.code64
-.section .text.init_page_table
-.globl init_page_table
-.type init_page_table, @function
-
-init_page_table:
-	mov $0x80000001, %eax
-	cpuid
-	test $(1 << 26), %edx
-	jnz setup_1gb
-
-setup_2mb:
-	mov $2048, %edi
-	mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
-	mov $0, %ecx
-	mov $main_page_table, %esi
-
-loop_2mb:
-	mov %eax, (%rsi, %rcx, 8)
-	mov $0, 4(%rsi, %rcx, 8)
-	add $0x200000, %eax
-	inc %ecx
-	cmp %edi, %ecx
-	jb loop_2mb
-
-	mov $4, %edi
-	mov $main_page_table, %eax
-	add $(_PRES + _RW + _US + _A), %eax
-	mov $0, %ecx
-	mov $extra_page_table, %esi
-
-fill_extra_page_table:
-	mov %eax, (%rsi, %rcx, 8)
-	mov $0, 4(%rsi, %rcx, 8)
-	add $4096, %eax
-	inc %ecx
-	cmp %edi, %ecx
-	jb fill_extra_page_table
-
-	mov $extra_page_table, %eax
-	jmp leave
-
-setup_1gb:
-	mov $512, %edi
-	mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
-	mov $0, %ebx
-	mov $0, %ecx
-	mov $main_page_table, %esi
-
-loop_1gb:
-	mov %eax, (%rsi, %rcx, 8)
-	mov %ebx, 4(%rsi, %rcx, 8)
-	add $0x40000000, %eax
-	cmp $0x40000000, %eax
-	ja no_overflow_1gb
-	inc %ebx
-no_overflow_1gb:
-	inc %ecx
-	cmp %edi, %ecx
-	jb loop_1gb
-
-	mov $main_page_table, %eax
-
-leave:
-	or $(_PRES + _RW + _US + _A), %eax
-	mov %eax, pm4le
-
-	ret

payloads/libpayload/arch/x86/string.c

@@ -81,16 +81,6 @@ void *memcpy(void *dest, const void *src, size_t n)
 {
 	unsigned long d0, d1, d2;
 
-#if CONFIG(LP_ARCH_X86_64)
-	asm volatile(
-		"rep ; movsq\n\t"
-		"mov %4,%%rcx\n\t"
-		"rep ; movsb\n\t"
-		: "=&c" (d0), "=&D" (d1), "=&S" (d2)
-		: "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
-		: "memory"
-	);
-#else
 	asm volatile(
 		"rep ; movsl\n\t"
 		"movl %4,%%ecx\n\t"
@@ -99,7 +89,6 @@ void *memcpy(void *dest, const void *src, size_t n)
 		: "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
 		: "memory"
 	);
-#endif
 
 	return dest;
 }

payloads/libpayload/bin/lpgcc

@@ -74,34 +74,34 @@ else
 fi
 
 if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
-  _ARCHDIR=arm
+  _ARCHINCDIR=$_INCDIR/arm
+  _ARCHLIBDIR=$_LIBDIR/arm
   _ARCHEXTRA=""
-
+  _ARCH=arm
 fi
 if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
-  _ARCHDIR=arm64
+  _ARCHINCDIR=$_INCDIR/arm64
+  _ARCHLIBDIR=$_LIBDIR/arm64
   _ARCHEXTRA=""
+  _ARCH=arm64
 fi
 if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
-  _ARCHDIR=x86
+  _ARCHINCDIR=$_INCDIR/x86
-  if [ "$CONFIG_LP_ARCH_X86_32" = "y" ]; then
+  _ARCHLIBDIR=$_LIBDIR/x86
-    _ARCHEXTRA="-m32 "
+  _ARCHEXTRA="-m32 "
-  else
+  _ARCH=x86
-    _ARCHEXTRA="-m64 "
-  fi
 fi
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
-  _ARCHDIR=mock
+  _ARCHINCDIR=$_INCDIR/mock
+  _ARCHLIBDIR=$_LIBDIR/mock
   _ARCHEXTRA=""
+  _ARCH=mock
 fi
 
-_ARCHINCDIR=$_INCDIR/$_ARCHDIR
-_ARCHLIBDIR=$_LIBDIR/$_ARCHDIR
-
 if [ -f $_LIBDIR/libpayload.ldscript ]; then
 	_LDDIR=$_LIBDIR
-elif [ -f $BASE/../arch/$_ARCHDIR/libpayload.ldscript ]; then
+elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then
-	_LDDIR=$BASE/../arch/$_ARCHDIR
+	_LDDIR=$BASE/../arch/$_ARCH
 fi
 # Host arch should youse default linker script
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
@@ -126,10 +126,13 @@ CMDLINE=
 
 while [ $# -gt 0 ]; do
 	case $1 in
-	    -m32|-fno-stack-protector|-m64)
+	    -m32|-fno-stack-protector)
 		shift
 		continue
 		;;
+	    -m64)
+		error "Invalid option --64 - only 32 bit architectures are supported"
+		;;
 	    -c)
 		DOLINK=0
 		;;
@@ -202,6 +205,14 @@ if [ $DOLINK -eq 0 ]; then
     $DEFAULT_CC $CMDLINE $_CFLAGS
 else
     _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
+    if [ -f $_ARCHLIBDIR/head.o ]; then
+	    HEAD_O=$_ARCHLIBDIR/head.o
+    elif [ -f $_OBJ/head.o ]; then
+	    HEAD_O=$_OBJ/head.o
+    else
+	    echo "Could not find head.o"
+	    exit 1
+    fi
 
     if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] &&
        grep -q fix-cortex-a53-843419 $_XCOMPILE; then
@@ -213,8 +224,13 @@ else
     _LDFLAGS="$_LDFLAGS -Wl,--defsym=CONFIG_LP_STACK_SIZE=$CONFIG_LP_STACK_SIZE"
 
     if [ $DEBUGME -eq 1 ]; then
-	echo "$DEFAULT_CC $_LDFLAGS $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
+	echo "$DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
     fi
 
-    $DEFAULT_CC $_LDFLAGS $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
+    # Note: $_ARCHLIBDIR/head.o must be the first object being linked, because it
+    # contains a Multiboot header.  The Multiboot standard requires this
+    # header to be placed below 0x2000 in the resulting image.  See:
+    # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
+
+    $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
 fi

payloads/libpayload/drivers/storage/ahci_common.c

@@ -66,7 +66,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
 			    u8 *const user_buf, const size_t len,
 			    const int out)
 {
-	if ((uintptr_t)user_buf & 1) {
+	if ((u32)user_buf & 1) {
 		printf("ahci: Odd buffer pointer (%p).\n", user_buf);
 		if (dev->buf) /* orphaned buffer */
 			free(dev->buf - *(dev->buf - 1));
@@ -76,7 +76,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
 		dev->user_buf = user_buf;
 		dev->write_back = !out;
 		dev->buflen = len;
-		if ((uintptr_t)dev->buf & 1) {
+		if ((u32)dev->buf & 1) {
 			dev->buf[0] = 1;
 			dev->buf += 1;
 		} else {

payloads/libpayload/drivers/usb/uhci.c

@@ -274,7 +274,7 @@ uhci_stop(hci_t *controller)
 
 #define UHCI_SLEEP_TIME_US 30
 #define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US)
-#define GET_TD(x) ((void *)(((unsigned long)(x))&~0xf))
+#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
 
 static td_t *
 wait_for_completed_qh(hci_t *controller, qh_t *qh)

payloads/libpayload/include/x86/arch/exception.h

@@ -29,7 +29,6 @@
 #ifndef _ARCH_EXCEPTION_H
 #define _ARCH_EXCEPTION_H
 
-#include <stddef.h>
 #include <stdint.h>
 
 void exception_init_asm(void);
@@ -39,28 +38,20 @@ void disable_interrupts(void);
 /** Returns 1 if interrupts are enabled. */
 int interrupts_enabled(void);
 
-#if CONFIG(LP_ARCH_X86_64)
+struct exception_state
-struct exception_state {
+{
 	/* Careful: x86/gdb.c currently relies on the size and order of regs. */
 	struct {
-		size_t reg_ax;
+		u32 eax;
-		size_t reg_bx;
+		u32 ecx;
-		size_t reg_cx;
+		u32 edx;
-		size_t reg_dx;
+		u32 ebx;
-		size_t reg_si;
+		u32 esp;
-		size_t reg_di;
+		u32 ebp;
-		size_t reg_bp;
+		u32 esi;
-		size_t reg_sp;
+		u32 edi;
-		size_t reg_r8;
+		u32 eip;
-		size_t reg_r9;
+		u32 eflags;
-		size_t reg_r10;
-		size_t reg_r11;
-		size_t reg_r12;
-		size_t reg_r13;
-		size_t reg_r14;
-		size_t reg_r15;
-		size_t reg_ip;
-		size_t reg_flags;
 		u32 cs;
 		u32 ss;
 		u32 ds;
@@ -68,39 +59,13 @@ struct exception_state {
 		u32 fs;
 		u32 gs;
 	} regs;
-	size_t error_code;
+	u32 error_code;
-	size_t vector;
+	u32 vector;
 } __packed;
-#else
-struct exception_state {
-	/* Careful: x86/gdb.c currently relies on the size and order of regs. */
-	struct {
-		size_t reg_ax;
-		size_t reg_cx;
-		size_t reg_dx;
-		size_t reg_bx;
-		size_t reg_sp;
-		size_t reg_bp;
-		size_t reg_si;
-		size_t reg_di;
-		size_t reg_ip;
-		size_t reg_flags;
-		u32 cs;
-		u32 ss;
-		u32 ds;
-		u32 es;
-		u32 fs;
-		u32 gs;
-	} regs;
-	size_t error_code;
-	size_t vector;
-} __packed;
-#endif
-
 extern struct exception_state *exception_state;
 
-extern u8 exception_stack[];
+extern u32 exception_stack[];
-extern u8 *exception_stack_end;
+extern u32 *exception_stack_end;
 
 enum {
 	EXC_DE = 0, /* Divide by zero */

payloads/libpayload/libc/Makefile.mk

@@ -29,7 +29,7 @@
 
 libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c
 libc-$(CONFIG_LP_LIBC) += memory.c ctype.c lib.c libgcc.c
-libc-$(CONFIG_LP_LIBC) += rand.c time.c
+libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c
 libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c
 libc-$(CONFIG_LP_LIBC) += args.c
 libc-$(CONFIG_LP_LIBC) += strlcpy.c

payloads/libpayload/libc/exec.c

@@ -29,10 +29,8 @@
 #include <libpayload-config.h>
 #include <libpayload.h>
 
-#if CONFIG(LP_ARCH_X86_32)
+#if CONFIG(LP_ARCH_X86)
 extern void i386_do_exec(long addr, int argc, char **argv, int *ret);
-#else
-#error "exec does not currently support x86_64."
 #endif
 
 /**
@@ -47,7 +45,7 @@ int exec(long addr, int argc, char **argv)
 {
 	int val = -1;
 
-#if CONFIG(LP_ARCH_X86_32)
+#if CONFIG(LP_ARCH_X86)
 	i386_do_exec(addr, argc, argv, &val);
 #endif
 	return val;

payloads/libpayload/vboot/Makefile.mk

@@ -15,8 +15,7 @@ vboot-fixup-includes = $(filter -I$(coreboottop)/%, $(1)) \
 		       $(filter-out -I$(coreboottop)/%,$(1)))))
 
 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_32) := x86
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_64) := x86_64
 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
 
 ifneq ($(CONFIG_LP_ARCH_MOCK),)

src/Kconfig

@@ -918,9 +918,8 @@ config GENERATE_PIRQ_TABLE
 	  If unsure, say Y.
 
 config GENERATE_SMBIOS_TABLES
-	depends on ARCH_X86 || ARCH_ARM64
+	depends on ARCH_X86
 	bool "Generate SMBIOS tables"
-	default n if ARCH_ARM64
 	default y
 	help
 	  Generate SMBIOS tables for this board.

src/acpi/acpi_apic.c

@@ -11,7 +11,7 @@ static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 {
 	lapic->type = LOCAL_APIC; /* Local APIC structure */
 	lapic->length = sizeof(acpi_madt_lapic_t);
-	lapic->flags = ACPI_MADT_LAPIC_ENABLED;
+	lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
 	lapic->processor_id = cpu;
 	lapic->apic_id = apic;
 
@@ -23,7 +23,7 @@ static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 api
 	lapic->type = LOCAL_X2APIC; /* Local APIC structure */
 	lapic->reserved = 0;
 	lapic->length = sizeof(acpi_madt_lx2apic_t);
-	lapic->flags = ACPI_MADT_LAPIC_ENABLED;
+	lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
 	lapic->processor_id = cpu;
 	lapic->x2apic_id = apic;
 
@@ -127,12 +127,17 @@ static int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride)
 
 	ioapic_get_sci_pin(&gsi, &irq, &flags);
 
-	/* In systems without 8259, the SCI_INT field in the FADT contains the SCI GSI number
-	   instead of the 8259 IRQ number */
 	if (!CONFIG(ACPI_HAVE_PCAT_8259))
 		irq = gsi;
 
-	return acpi_create_madt_irqoverride(irqoverride, MP_BUS_ISA, irq, gsi, flags);
+	irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */
+	irqoverride->length = sizeof(acpi_madt_irqoverride_t);
+	irqoverride->bus = MP_BUS_ISA;
+	irqoverride->source = irq;
+	irqoverride->gsirq = gsi;
+	irqoverride->flags = flags;
+
+	return irqoverride->length;
 }
 
 static unsigned long acpi_create_madt_ioapic_gsi0_default(unsigned long current)
@@ -229,7 +234,7 @@ unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current)
 	madt->lapic_addr = cpu_get_lapic_addr();
 
 	if (CONFIG(ACPI_HAVE_PCAT_8259))
-		madt->flags |= ACPI_MADT_PCAT_COMPAT;
+		madt->flags |= 1;
 
 	if (CONFIG(ACPI_COMMON_MADT_LAPIC))
 		current = acpi_create_madt_lapics_with_nmis(current);

src/acpi/acpigen.c

@@ -14,7 +14,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/soundwire.h>
-#include <stdio.h>
 #include <types.h>
 
 static char *gencurrent;

src/acpi/acpigen_dptf.c

@@ -4,7 +4,6 @@
 #include <acpi/acpigen_dptf.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include <stdio.h>
 
 /* Defaults */
 #define DEFAULT_RAW_UNIT		"ma"

src/acpi/acpigen_usb.c

@@ -5,7 +5,6 @@
 #include <acpi/acpigen.h>
 #include <acpi/acpigen_usb.h>
 #include <device/device.h>
-#include <stdio.h>
 
 static const char *power_role_to_str(enum usb_typec_power_role power_role)
 {

src/acpi/device.c

@@ -8,7 +8,6 @@
 #include <acpi/acpigen_pci.h>
 #include <device/device.h>
 #include <stdlib.h>
-#include <stdio.h>
 #include <types.h>
 #include <crc_byte.h>
 

src/arch/arm64/Makefile.mk

@@ -30,9 +30,6 @@ bootblock-y += eabi_compat.c
 decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 bootblock-y += transition.c transition_asm.S
-ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
-bootblock-y += smc.c smc_asm.S
-endif
 
 decompressor-y += memset.S
 bootblock-y += memset.S
@@ -72,9 +69,6 @@ verstage-y += memcpy.S
 verstage-y += memmove.S
 
 verstage-y += transition.c transition_asm.S
-ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
-verstage-y += smc.c smc_asm.S
-endif
 
 endif # CONFIG_ARCH_VERSTAGE_ARM64
 
@@ -94,9 +88,6 @@ romstage-y += memmove.S
 romstage-y += ramdetect.c
 romstage-y += romstage.c
 romstage-y += transition.c transition_asm.S
-ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
-romstage-y += smc.c smc_asm.S
-endif
 
 rmodules_arm64-y += memset.S
 rmodules_arm64-y += memcpy.S
@@ -118,7 +109,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
 ramstage-y += div0.c
 ramstage-y += eabi_compat.c
 ramstage-y += boot.c
-ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
 ramstage-y += tables.c
 ramstage-y += ramdetect.c
 ramstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
@@ -127,9 +117,6 @@ ramstage-y += memcpy.S
 ramstage-y += memmove.S
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c
 ramstage-y += transition.c transition_asm.S
-ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
-ramstage-y += smc.c smc_asm.S
-endif
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += dma.c

src/arch/arm64/include/armv8/arch/smc.h

@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef ARM_ARM64_SMC_H
-#define ARM_ARM64_SMC_H
-
-#include <types.h>
-
-uint64_t smc(uint32_t function_id, uint64_t arg1, uint64_t arg2, uint64_t arg3,
-		uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7);
-
-#define smc_call0(function_id)			smc(function_id, 0, 0, 0, 0, 0, 0, 0)
-#define smc_call1(function_id, a1)		smc(function_id, a1, 0, 0, 0, 0, 0, 0)
-#define smc_call2(function_id, a1, a2)		smc(function_id, a1, a2, 0, 0, 0, 0, 0)
-#define smc_call3(function_id, a1, a2, a3)	smc(function_id, a1, a2, a3, 0, 0, 0, 0)
-
-/* Documented in https://developer.arm.com/documentation/den0022/ */
-enum psci_return_values {
-	PSCI_SUCCESS = 0,
-	PSCI_NOT_SUPPORTED = -1,
-	PSCI_INVALID_PARAMETERS = -2,
-	PSCI_DENIED = -3,
-	PSCI_ALREADY_ON = -4,
-	PSCI_ON_PENDING = -5,
-	PSCI_INTERNAL_FAILURE = -6,
-	PSCI_NOT_PRESENT = -7,
-	PSCI_DISABLED = -8,
-	PSCI_INVALID_ADDRESS = -9,
-};
-
-/* PSCI functions */
-#define PSCI_VERSION		0x84000000
-#define PSCI_FEATURES		0x8400000a
-
-/* Documented in https://developer.arm.com/documentation/den0028/ */
-enum smccc_return_values {
-	SMC_SUCCESS = 0,
-	SMC_NOT_SUPPORTED = -1,
-	SMC_NOT_REQUIRED = -2,
-	SMC_INVALID_PARAMETER = -3,
-};
-
-/* SMCCC functions */
-#define SMCCC_VERSION		0x80000000
-#define SMCCC_ARCH_FEATURES	0x80000001
-#define SMCCC_ARCH_SOC_ID	0x80000002
-#define  SMCCC_GET_SOC_VERSION	0
-#define  SMCCC_GET_SOC_REVISION	1
-
-uint8_t smccc_supports_arch_soc_id(void);
-enum cb_err smccc_arch_soc_id(uint32_t *jep106code, uint32_t *soc_revision);
-
-#endif /* ARM_ARM64_SMC_H */

src/arch/arm64/smbios.c

@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/cache.h>
-#include <arch/lib_helpers.h>
-#include <arch/smc.h>
-#include <console/console.h>
-#include <smbios.h>
-#include <stdio.h>
-
-static void smbios_processor_id(u32 *processor_id)
-{
-	uint32_t jep106code, soc_revision;
-	uint64_t midr_el1;
-
-	if (smccc_supports_arch_soc_id()) {
-		smccc_arch_soc_id(&jep106code, &soc_revision);
-		processor_id[0] = jep106code;
-		processor_id[1] = soc_revision;
-	} else {
-		midr_el1 = raw_read_midr_el1();
-		processor_id[0] = midr_el1;
-		processor_id[1] = 0;
-	}
-}
-
-static int smbios_processor_manufacturer(u8 *start)
-{
-	char midr_el1_implementer;
-	char buf[32];
-
-	// [31:24] - Implementer code
-	midr_el1_implementer = (raw_read_midr_el1() & 0xff000000) >> 24;
-
-	snprintf(buf, sizeof(buf), "CPU implementer %x", midr_el1_implementer);
-	return smbios_add_string(start, buf);
-}
-
-static int smbios_processor_name(u8 *start)
-{
-	uint16_t midr_el1_partnumber;
-	char buf[32];
-
-	// [15:4] - PartNum
-	midr_el1_partnumber = (raw_read_midr_el1() & 0xfff0) >> 4;
-
-	snprintf(buf, sizeof(buf), "ARMv8 Processor rev %d", midr_el1_partnumber);
-	return smbios_add_string(start, buf);
-}
-
-#define MAX_CPUS_ENABLED(cpus) (cpus > 0xff ? 0xff : cpus)
-
-/* NOTE: Not handling big.LITTLE clusters. Consider using MP services (not yet) or the DSU. */
-int smbios_write_type4(unsigned long *current, int handle)
-{
-	static unsigned int cnt = 0;
-	char buf[8];
-	uint16_t characteristics = 0;
-	unsigned int cpu_voltage;
-
-	struct smbios_type4 *t = smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION,
-						    sizeof(*t), handle);
-
-	snprintf(buf, sizeof(buf), "CPU%d", cnt++);
-	t->socket_designation = smbios_add_string(t->eos, buf);
-
-	smbios_processor_id(t->processor_id);
-	t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
-	t->processor_version = smbios_processor_name(t->eos);
-	t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
-	t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
-	t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
-
-	smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);
-	t->core_count = MAX_CPUS_ENABLED(t->core_count2);
-	t->thread_count = MAX_CPUS_ENABLED(t->thread_count2);
-	/* Assume we always enable all cores */
-	t->core_enabled = t->core_count;
-	t->core_enabled2 = t->core_count2;
-	t->l1_cache_handle = 0xffff;
-	t->l2_cache_handle = 0xffff;
-	t->l3_cache_handle = 0xffff;
-	t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number());
-	t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED;
-	t->processor_upgrade = PROCESSOR_UPGRADE_UNKNOWN;
-
-	t->external_clock = smbios_processor_external_clock();
-	if (t->external_clock == 0)
-		t->external_clock = (raw_read_cntfrq_el0() / 1000 / 1000);
-
-	t->current_speed = smbios_cpu_get_current_speed_mhz();
-
-	/* This field identifies a capability for the system, not the processor itself. */
-	t->max_speed = smbios_cpu_get_max_speed_mhz();
-
-	/* TODO: Are "Enhanced Virtualization" (by EL2) and "Power/Performance Control" supported? */
-	characteristics |= PROCESSOR_64BIT_CAPABLE;
-	characteristics |= BIT(5); /* Execute Protection */
-
-	if (t->core_count > 1)
-		characteristics |= PROCESSOR_MULTI_CORE;
-	if (t->thread_count > 1)
-		characteristics |= BIT(4); /* BIT4: Hardware Thread */
-	if (smccc_supports_arch_soc_id())
-		characteristics |= BIT(9); /* Arm64 SoC ID */
-
-	t->processor_characteristics = characteristics | smbios_processor_characteristics();
-
-	cpu_voltage = smbios_cpu_get_voltage();
-	if (cpu_voltage > 0)
-		t->voltage = 0x80 | cpu_voltage;
-
-	const int len = smbios_full_table_len(&t->header, t->eos);
-	*current += len;
-	return len;
-}
-
-int smbios_write_type7_cache_parameters(unsigned long *current,
-					int *handle,
-					int *max_struct_size,
-					struct smbios_type4 *type4)
-{
-	enum cache_level level = CACHE_L1;
-	int h;
-	int len = 0;
-
-	while (1) {
-		enum smbios_cache_type type;
-		struct cache_info info;
-
-		const u8 cache_type = cpu_get_cache_type(level);
-		/* No more caches in the system */
-		if (!cache_type)
-			break;
-
-		switch (cache_type) {
-		case CACHE_INSTRUCTION:
-			type = SMBIOS_CACHE_TYPE_INSTRUCTION;
-			cpu_get_cache_info(level, cache_type, &info);
-			break;
-		case CACHE_DATA:
-			type = SMBIOS_CACHE_TYPE_DATA;
-			cpu_get_cache_info(level, cache_type, &info);
-			break;
-		case CACHE_SEPARATE:
-			type = SMBIOS_CACHE_TYPE_DATA;
-			cpu_get_cache_info(level, CACHE_DATA, &info);
-			h = (*handle)++;
-			update_max(len, *max_struct_size, smbios_write_type7(current, h,
-				   level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity),
-				   type, info.size, info.size));
-
-			type = SMBIOS_CACHE_TYPE_INSTRUCTION;
-			cpu_get_cache_info(level, CACHE_INSTRUCTION, &info);
-			break;
-		case CACHE_UNIFIED:
-			type = SMBIOS_CACHE_TYPE_UNIFIED;
-			cpu_get_cache_info(level, cache_type, &info);
-			break;
-		default:
-			type = SMBIOS_CACHE_TYPE_UNKNOWN;
-			info.size = info.associativity = 0;
-			break;
-		}
-
-		h = (*handle)++;
-		update_max(len, *max_struct_size, smbios_write_type7(current, h,
-			   level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity),
-			   type, info.size, info.size));
-
-		if (type4) {
-			switch (level) {
-			case 1:
-				type4->l1_cache_handle = h;
-				break;
-			case 2:
-				type4->l2_cache_handle = h;
-				break;
-			case 3:
-				type4->l3_cache_handle = h;
-				break;
-			default:
-				break;
-			}
-		}
-
-		level++;
-	}
-
-	return len;
-}

src/arch/arm64/smc.c

@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/smc.h>
-#include <console/console.h>
-#include <types.h>
-
-/* Assumes at least a PSCI implementation is present */
-uint8_t smccc_supports_arch_soc_id(void)
-{
-	static uint8_t supported = 0xff;
-	uint64_t smc_ret;
-
-	if (supported != 0xff)
-		return supported;
-
-	// PSCI_FEATURES mandatory from PSCI 1.0
-	smc_ret = smc_call0(PSCI_VERSION);
-	if (smc_ret < 0x10000)
-		goto fail;
-
-	smc_ret = smc_call1(PSCI_FEATURES, SMCCC_VERSION);
-	if (smc_ret == PSCI_NOT_SUPPORTED)
-		goto fail;
-
-	// SMCCC_ARCH_FEATURES supported from SMCCC 1.1
-	smc_ret = smc_call0(SMCCC_VERSION);
-	if (smc_ret < 0x10001)
-		goto fail;
-
-	smc_ret = smc_call1(SMCCC_ARCH_FEATURES, SMCCC_ARCH_SOC_ID);
-	if (smc_ret != SMC_SUCCESS)
-		goto fail;
-
-	supported = 1;
-	return supported;
-
-fail:
-	supported = 0;
-	return supported;
-}
-
-enum cb_err smccc_arch_soc_id(uint32_t *jep106code, uint32_t *soc_revision)
-{
-	uint64_t smc_ret;
-
-	if (jep106code == NULL || soc_revision == NULL)
-		return CB_ERR_ARG;
-
-	smc_ret = smc_call1(SMCCC_ARCH_SOC_ID, SMCCC_GET_SOC_VERSION);
-	if (smc_ret != SMC_INVALID_PARAMETER)
-		*jep106code = smc_ret;
-	else
-		*jep106code = -1;
-
-	smc_ret = smc_call1(SMCCC_ARCH_SOC_ID, SMCCC_GET_SOC_REVISION);
-	if (smc_ret != SMC_INVALID_PARAMETER)
-		*soc_revision = smc_ret;
-	else
-		*soc_revision = -1;
-
-	if (*jep106code == -1 || *soc_revision == -1) {
-		printk(BIOS_ERR, "SMCCC_ARCH_SOC_ID failed!\n");
-		return CB_ERR;
-	} else
-		return CB_SUCCESS;
-}

src/arch/arm64/smc_asm.S

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/asm.h>
-
-ENTRY(smc)
-	/* W0, X1-X7 passed as arguments. Function ID is always W0. */
-	smc	#0
-	ret			/* X0 passed back as return value */
-ENDPROC(smc)

src/arch/arm64/tables.c

@@ -6,9 +6,6 @@
 #include <boot/tables.h>
 #include <bootmem.h>
 #include <cbmem.h>
-#include <console/console.h>
-#include <smbios.h>
-#include <string.h>
 #include <symbols.h>
 
 static void write_acpi_table(void)
@@ -21,40 +18,10 @@ static void write_acpi_table(void)
 	printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", acpi_end - acpi_start);
 }
 
-static void write_smbios_table(void)
-{
-	unsigned long smbios_begin, smbios_end;
-
-#define MAX_SMBIOS_SIZE (32 * KiB)
-
-	smbios_begin = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE);
-	if (!smbios_begin) {
-		printk(BIOS_ERR, "Out of memory for SMBIOS tables\n");
-		return;
-	}
-
-	/*
-	 * Clear the entire region to ensure the unused space doesn't
-	 * contain garbage from a previous boot, like stale table
-	 * signatures that could be found by the OS.
-	 */
-	memset((void *)smbios_begin, 0, MAX_SMBIOS_SIZE);
-
-	smbios_end = smbios_write_tables(smbios_begin);
-
-	if (smbios_end > (smbios_begin + MAX_SMBIOS_SIZE))
-		printk(BIOS_ERR, "Increase SMBIOS size\n");
-
-	printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", smbios_end - smbios_begin);
-}
-
 void arch_write_tables(uintptr_t coreboot_table)
 {
 	if (CONFIG(HAVE_ACPI_TABLES))
 		write_acpi_table();
-
-	if (CONFIG(GENERATE_SMBIOS_TABLES))
-		write_smbios_table();
 }
 
 void bootmem_arch_add_ranges(void)

src/arch/riscv/include/vm.h

@@ -3,6 +3,7 @@
 #ifndef _VM_H
 #define _VM_H
 
+#include <string.h>
 #include <stdint.h>
 #include <arch/encoding.h>
 

src/arch/x86/Makefile.mk

@@ -253,6 +253,7 @@ ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c
 ramstage-y += boot.c
 ramstage-y += post.c
 ramstage-y += c_start.S
+ramstage-y += c_exit.S
 ramstage-y += cpu.c
 ramstage-y += cpu_common.c
 ramstage-$(CONFIG_DEBUG_HW_BREAKPOINTS) += breakpoint.c

src/arch/x86/acpi.c

@@ -12,8 +12,7 @@ static u16 acpi_sci_int(void)
 
 	ioapic_get_sci_pin(&gsi, &irq, &flags);
 
-	/* In systems without 8259, the SCI_INT field in the FADT contains the SCI GSI number
+	/* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */
-	   instead of the 8259 IRQ number */
 	if (!CONFIG(ACPI_HAVE_PCAT_8259))
 		return gsi;
 

src/arch/x86/boot.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/boot/boot.h>
 #include <arch/cpu.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
-#include <mode_switch.h>
 #include <program_loading.h>
 #include <symbols.h>
 #include <assert.h>
@@ -26,7 +26,7 @@ void arch_prog_run(struct prog *prog)
 	const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog));
 
 	/* On x86 coreboot payloads expect to be called in protected mode */
-	protected_mode_call_1arg((void *)(uintptr_t)entry, arg);
+	protected_mode_jump(entry, arg);
 #else
 #if ENV_X86_64
 	void (*doit)(void *arg);

src/arch/x86/c_exit.S

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/ram_segs.h>
+#include <cpu/x86/cr.h>
+
+#if ENV_X86_64
+
+	/*
+	 * Functions to handle mode switches from long mode to protected
+	 * mode.
+	 */
+.text
+.code64
+	.section ".text.protected_mode_jump", "ax", @progbits
+	.globl protected_mode_jump
+protected_mode_jump:
+
+	push %rbp
+	mov %rsp, %rbp
+
+	/* Arguments to stack */
+	push	%rdi
+	push	%rsi
+
+	#include <cpu/x86/64bit/exit32.inc>
+
+	movl	-8(%ebp), %eax	/* Function to call */
+	movl	-16(%ebp), %ebx	/* Argument 0 */
+
+	/* Align the stack */
+	andl	$0xFFFFFFF0, %esp
+	subl	$12, %esp
+	pushl	%ebx	/* Argument 0 */
+
+	jmp	*%eax
+#endif

src/arch/x86/include/arch/boot/boot.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef X86_BOOT_H
+#define X86_BOOT_H
+
+#include <types.h>
+/*
+ * Jump to function in protected mode.
+ * @arg func_ptr           Function to jump to in protected mode
+ * @arg                    Argument to pass to called function
+ *
+ * @noreturn
+ */
+void protected_mode_jump(uint32_t func_ptr, uint32_t argument);
+
+#endif /* X86_BOOT_H */

src/arch/x86/smbios.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <string.h>
 #include <smbios.h>
 #include <console/console.h>
 #include <arch/cpu.h>
 #include <cpu/x86/name.h>
-#include <stdio.h>
 
 static int smbios_cpu_vendor(u8 *start)
 {
@@ -68,7 +68,7 @@ static int get_socket_type(void)
 
 unsigned int __weak smbios_processor_family(struct cpuid_result res)
 {
-	return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486;
+	return (res.eax > 0) ? 0x0c : 0x6;
 }
 
 static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)
@@ -126,7 +126,7 @@ int smbios_write_type4(unsigned long *current, int handle)
 	t->processor_manufacturer = smbios_cpu_vendor(t->eos);
 	t->processor_version = smbios_processor_name(t->eos);
 	t->processor_family = smbios_processor_family(res);
-	t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
+	t->processor_type = 3; /* System Processor */
 	/*
 	 * If CPUID leaf 11 is available, calculate "core count" by dividing
 	 * SMT_ID (logical processors in a core) by Core_ID (number of cores).

src/console/vsprintf.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/vtxprintf.h>
-#include <stdio.h>
+#include <string.h>
 
 struct vsnprintf_context {
 	char *str_buf;

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -190,26 +190,17 @@ static void configure_c_states(struct device *dev)
 
 		/* C3 Interrupt Response Time Limit */
 		msr.hi = 0;
-		if (IS_IVY_CPU(cpu_get_cpuid()))
+		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
-			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x3b;
-		else
-			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
 		wrmsr(MSR_PKGC3_IRTL, msr);
 
 		/* C6 Interrupt Response Time Limit */
 		msr.hi = 0;
-		if (IS_IVY_CPU(cpu_get_cpuid()))
+		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
-			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
-		else
-			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
 		wrmsr(MSR_PKGC6_IRTL, msr);
 
 		/* C7 Interrupt Response Time Limit */
 		msr.hi = 0;
-		if (IS_IVY_CPU(cpu_get_cpuid()))
+		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
-			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x57;
-		else
-			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
 		wrmsr(MSR_PKGC7_IRTL, msr);
 
 		/* Primary Plane Current Limit (Icc) */

src/cpu/x86/pae/pgtbl.c

@@ -100,97 +100,6 @@ void paging_disable_pae(void)
 	write_cr4(cr4);
 }
 
-/*
- * Prepare PAE pagetables that identity map the whole 32-bit address space using
- * 2 MiB pages. The PAT are set to all cacheable, but MTRRs still apply. CR3 is
- * loaded and PAE is enabled by this function.
- *
- * Requires a scratch memory for pagetables.
- *
- * @param pgtbl     Where pagetables reside, must be 4 KiB aligned and 20 KiB in
- *                  size.
- *                  Content at physical address isn't preserved.
- * @return 0 on success, 1 on error
- */
-int init_pae_pagetables(void *pgtbl)
-{
-	struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl;
-	struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp;
-
-	printk(BIOS_DEBUG, "%s: Using address %p for page tables\n",
-	       __func__, pgtbl_buf);
-
-	/* Cover some basic error conditions */
-	if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB)) {
-		printk(BIOS_ERR, "%s: Invalid alignment\n", __func__);
-		return 1;
-	}
-
-	paging_disable_pae();
-
-	/* Point the page directory pointers at the page directories. */
-	memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp));
-
-	pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES;
-	pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES;
-	pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES;
-	pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES;
-
-	/* Identity map the whole 32-bit address space */
-	for (size_t i = 0; i < 2048; i++) {
-		pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW;
-		pd[i].addr_hi = 0;
-	}
-
-	paging_enable_pae_cr3((uintptr_t)pdp);
-
-	return 0;
-}
-
-/*
- * Map single 2 MiB page in pagetables created by init_pae_pagetables().
- *
- * The function does not check if the page was already non identity mapped,
- * this allows callers to reuse one page without having to explicitly unmap it
- * between calls.
- *
- * @param pgtbl     Where pagetables created by init_pae_pagetables() reside.
- *                  Content at physical address is preserved except for single
- *                  entry corresponding to vmem_addr.
- * @param paddr     Physical memory address to map. Function prints a warning if
- *                  it isn't aligned to 2 MiB.
- * @param vmem_addr Where the virtual non identity mapped page resides, must
- *                  be at least 2 MiB in size. Function prints a warning if it
- *                  isn't aligned to 2 MiB.
- *                  Content at physical address is preserved.
- * @return 0 on success, 1 on error
- */
-void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr)
-{
-	struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl;
-	struct pde *pd;
-
-	if (!IS_ALIGNED(paddr, s2MiB)) {
-		printk(BIOS_WARNING, "%s: Aligning physical address to 2MiB\n",
-		       __func__);
-		paddr = ALIGN_DOWN(paddr, s2MiB);
-	}
-
-	if (!IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) {
-		printk(BIOS_WARNING, "%s: Aligning virtual address to 2MiB\n",
-		       __func__);
-		vmem_addr = (void *)ALIGN_DOWN((uintptr_t)vmem_addr, s2MiB);
-	}
-
-	/* Map a page using PAE at virtual address vmem_addr. */
-	pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT];
-	pd->addr_lo = paddr | PDE_PS | PDE_PRES | PDE_RW;
-	pd->addr_hi = paddr >> 32;
-
-	/* Update page tables */
-	asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory");
-}
-
 /*
  * Use PAE to map a page and then memset it with the pattern specified.
  * In order to use PAE pagetables for virtual addressing are set up and reloaded
@@ -221,18 +130,22 @@ void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr)
 int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 	       void *vmem_addr)
 {
+	struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl;
 	ssize_t offset;
-	const uintptr_t pgtbl_s = (uintptr_t)pgtbl;
-	const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table);
 
 	printk(BIOS_DEBUG, "%s: Using virtual address %p as scratchpad\n",
 	       __func__, vmem_addr);
+	printk(BIOS_DEBUG, "%s: Using address %p for page tables\n",
+	       __func__, pgtbl_buf);
 
 	/* Cover some basic error conditions */
-	if (!IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) {
+	if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB) ||
+	    !IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) {
 		printk(BIOS_ERR, "%s: Invalid alignment\n", __func__);
 		return 1;
 	}
+	const uintptr_t pgtbl_s = (uintptr_t)pgtbl_buf;
+	const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table);
 
 	if (OVERLAP(dest, dest + length, pgtbl_s, pgtbl_e)) {
 		printk(BIOS_ERR, "%s: destination overlaps page tables\n",
@@ -247,12 +160,31 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 		return 1;
 	}
 
-	if (init_pae_pagetables(pgtbl))
+	paging_disable_pae();
-		return 1;
+
+	struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp;
+	/* Point the page directory pointers at the page directories. */
+	memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp));
+
+	pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES;
+	pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES;
+	pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES;
+	pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES;
 
 	offset = dest - ALIGN_DOWN(dest, s2MiB);
 	dest = ALIGN_DOWN(dest, s2MiB);
 
+	/* Identity map the whole 32-bit address space */
+	for (size_t i = 0; i < 2048; i++) {
+		pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW;
+		pd[i].addr_hi = 0;
+	}
+
+	/* Get pointer to PD that's not identity mapped */
+	pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT];
+
+	paging_enable_pae_cr3((uintptr_t)pdp);
+
 	do {
 		const size_t len = MIN(length, s2MiB - offset);
 
@@ -260,7 +192,11 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 		 * Map a page using PAE at virtual address vmem_addr.
 		 * dest is already 2 MiB aligned.
 		 */
-		pae_map_2M_page(pgtbl, dest, vmem_addr);
+		pd->addr_lo = dest | PDE_PS | PDE_PRES | PDE_RW;
+		pd->addr_hi = dest >> 32;
+
+		/* Update page tables */
+		asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory");
 
 		printk(BIOS_SPEW, "%s: Clearing %llx[%lx] - %zx\n", __func__,
 		       dest + offset, (uintptr_t)vmem_addr + offset, len);
@@ -277,6 +213,69 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 	return 0;
 }
 
+#if ENV_RAMSTAGE
+void *map_2M_page(unsigned long page)
+{
+	struct pde {
+		uint32_t addr_lo;
+		uint32_t addr_hi;
+	} __packed;
+	struct pg_table {
+		struct pde pd[2048];
+		struct pde pdp[512];
+	} __packed;
+
+	static struct pg_table pgtbl[CONFIG_MAX_CPUS]
+		__attribute__((aligned(4096)));
+	static unsigned long mapped_window[CONFIG_MAX_CPUS];
+	int index;
+	unsigned long window;
+	void *result;
+	int i;
+	index = cpu_index();
+	if (index < 0)
+		return MAPPING_ERROR;
+	window = page >> 10;
+	if (window != mapped_window[index]) {
+		paging_disable_pae();
+		if (window > 1) {
+			struct pde *pd, *pdp;
+			/* Point the page directory pointers at the page
+			 * directories
+			 */
+			memset(&pgtbl[index].pdp, 0, sizeof(pgtbl[index].pdp));
+			pd = pgtbl[index].pd;
+			pdp = pgtbl[index].pdp;
+			pdp[0].addr_lo = ((uintptr_t)&pd[512*0])|1;
+			pdp[1].addr_lo = ((uintptr_t)&pd[512*1])|1;
+			pdp[2].addr_lo = ((uintptr_t)&pd[512*2])|1;
+			pdp[3].addr_lo = ((uintptr_t)&pd[512*3])|1;
+			/* The first half of the page table is identity mapped
+			 */
+			for (i = 0; i < 1024; i++) {
+				pd[i].addr_lo = ((i & 0x3ff) << 21) | 0xE3;
+				pd[i].addr_hi = 0;
+			}
+			/* The second half of the page table holds the mapped
+			 * page
+			 */
+			for (i = 1024; i < 2048; i++) {
+				pd[i].addr_lo = ((window & 1) << 31)
+					| ((i & 0x3ff) << 21) | 0xE3;
+				pd[i].addr_hi = (window >> 1);
+			}
+			paging_enable_pae_cr3((uintptr_t)pdp);
+		}
+		mapped_window[index] = window;
+	}
+	if (window == 0)
+		result = (void *)(page << 21);
+	else
+		result = (void *)(0x80000000 | ((page & 0x3ff) << 21));
+	return result;
+}
+#endif
+
 void paging_set_nxe(int enable)
 {
 	msr_t msr = rdmsr(IA32_EFER);
@@ -341,3 +340,177 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name)
 
 	return 0;
 }
+
+static void *get_pdpt_addr(void)
+{
+	if (preram_symbols_available())
+		return _pdpt;
+	return (void *)(uintptr_t)read_cr3();
+}
+
+static uint64_t pde_pat_flags(int pat)
+{
+	switch (pat) {
+	case PAT_UC:
+		return 0 | PDE_PCD | PDE_PWT;
+	case PAT_WC:
+		return 0 | 0 | PDE_PWT;
+	case PAT_WT:
+		return PDE_PAT | PDE_PCD | PDE_PWT;
+	case PAT_WP:
+		return PDE_PAT | 0 | PDE_PWT;
+	case PAT_WB:
+		return 0 | 0 | 0;
+	case PAT_UC_MINUS:
+		return 0 | PDE_PCD | 0;
+	default:
+		printk(BIOS_ERR, "PDE PAT defaulting to WB: %x\n", pat);
+		return pde_pat_flags(PAT_WB);
+	}
+}
+
+static uint64_t pde_page_flags(int pat)
+{
+	uint64_t flags = PDE_PS | PDE_PRES | PDE_RW | PDE_A | PDE_D;
+
+	return flags | pde_pat_flags(pat);
+}
+
+static uint64_t pte_pat_flags(int pat)
+{
+	switch (pat) {
+	case PAT_UC:
+		return 0 | PTE_PCD | PTE_PWT;
+	case PAT_WC:
+		return 0 | 0 | PTE_PWT;
+	case PAT_WT:
+		return PTE_PAT | PTE_PCD | PTE_PWT;
+	case PAT_WP:
+		return PTE_PAT | 0 | PTE_PWT;
+	case PAT_WB:
+		return 0 | 0 | 0;
+	case PAT_UC_MINUS:
+		return 0 | PTE_PCD | 0;
+	default:
+		printk(BIOS_ERR, "PTE PAT defaulting to WB: %x\n", pat);
+		return pte_pat_flags(PAT_WB);
+	}
+}
+
+static uint64_t pte_page_flags(int pat)
+{
+	uint64_t flags = PTE_PRES | PTE_RW | PTE_A | PTE_D;
+	return flags | pte_pat_flags(pat);
+}
+
+/* Identity map an address. This function does not handle splitting or adding
+ * new pages to the page tables. It's assumed all the page tables are already
+ * seeded with the correct amount and topology. */
+static int identity_map_one_page(uintptr_t base, size_t size, int pat,
+				int commit)
+{
+	uint64_t (*pdpt)[4];
+	uint64_t pdpte;
+	uint64_t (*pd)[512];
+	uint64_t pde;
+
+	pdpt = get_pdpt_addr();
+
+	pdpte = (*pdpt)[(base >> PDPTE_IDX_SHIFT) & PDPTE_IDX_MASK];
+
+	/* No page table page allocation. */
+	if (!(pdpte & PDPTE_PRES))
+		return -1;
+
+	pd = (void *)(uintptr_t)(pdpte & PDPTE_ADDR_MASK);
+
+	/* Map in a 2MiB page. */
+	if (size == s2MiB) {
+		if (!commit)
+			return 0;
+		pde = base;
+		pde |= pde_page_flags(pat);
+		(*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK] = pde;
+		return 0;
+	}
+
+	if (size == s4KiB) {
+		uint64_t (*pt)[512];
+		uint64_t pte;
+
+		pde = (*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK];
+
+		/* No page table page allocation. */
+		if (!(pde & PDE_PRES)) {
+			printk(BIOS_ERR, "Cannot allocate page table for pde %p\n",
+				(void *)base);
+			return -1;
+		}
+
+		/* No splitting pages */
+		if (pde & PDE_PS) {
+			printk(BIOS_ERR, "Cannot split pde %p\n", (void *)base);
+			return -1;
+		}
+
+		if (!commit)
+			return 0;
+
+		pt = (void *)(uintptr_t)(pde & PDE_ADDR_MASK);
+		pte = base;
+		pte |= pte_page_flags(pat);
+		(*pt)[(base >> PTE_IDX_SHIFT) & PTE_IDX_MASK] = pte;
+
+		return 0;
+	}
+
+	return -1;
+}
+
+static int _paging_identity_map_addr(uintptr_t base, size_t size, int pat,
+					int commit)
+{
+	while (size != 0) {
+		size_t map_size;
+
+		map_size = IS_ALIGNED(base, s2MiB) ? s2MiB : s4KiB;
+		map_size = MIN(size, map_size);
+
+		if (identity_map_one_page(base, map_size, pat, commit) < 0)
+			return -1;
+
+		base += map_size;
+		size -= map_size;
+	}
+
+	return 0;
+}
+
+static int paging_is_enabled(void)
+{
+	return !!(read_cr0() & CR0_PG);
+}
+
+int paging_identity_map_addr(uintptr_t base, size_t size, int pat)
+{
+	if (!paging_is_enabled()) {
+		printk(BIOS_ERR, "Paging is not enabled.\n");
+		return -1;
+	}
+
+	if (!IS_ALIGNED(base, s2MiB) && !IS_ALIGNED(base, s4KiB)) {
+		printk(BIOS_ERR, "base %p is not aligned.\n", (void *)base);
+		return -1;
+	}
+
+	if (!IS_ALIGNED(size, s2MiB) && !IS_ALIGNED(size, s4KiB)) {
+		printk(BIOS_ERR, "size %zx is not aligned.\n", size);
+		return -1;
+	}
+
+	/* First try without committing. If success commit. */
+	if (_paging_identity_map_addr(base, size, pat, 0))
+		return -1;
+
+	return _paging_identity_map_addr(base, size, pat, 1);
+}

src/cpu/x86/smm/smm_module_loader.c

@@ -11,7 +11,6 @@
 #include <device/mmio.h>
 #include <rmodule.h>
 #include <smmstore.h>
-#include <stdio.h>
 #include <string.h>
 #include <types.h>
 

src/device/Kconfig

@@ -846,18 +846,18 @@ config VGA_BIOS_ID
 	depends on VGA_BIOS
 	default "1106,3230"
 	help
-	  The comma-separated PCI vendor and device ID that would associate
+	  The comma-separated PCI vendor and device ID with optional revision if that
-	  your vBIOS to your video card.
+	  feature is enabled that would associate your vBIOS to your video card.
 
-	  Example: 1106,3230
+	  Example: 1106,3230 or 1106,3230,a3
 
 	  In the above example 1106 is the PCI vendor ID (in hex, but without
 	  the "0x" prefix) and 3230 specifies the PCI device ID of the
-	  video card (also in hex, without "0x" prefix).
+	  video card (also in hex, without "0x" prefix). a3 specifies the revision.
 
 	  This ID needs to match the PCI VID and DID in the VGA BIOS file's
 	  header and also needs to match the value returned by map_oprom_vendev
-	  if the remapping feature is used.
+	  or map_oprom_vendev_rev if the remapping feature is used.
 
 	  Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 
@@ -879,17 +879,23 @@ config VGA_BIOS_SECOND_ID
 	string "Graphics device PCI IDs"
 	depends on VGA_BIOS_SECOND
 	help
-	  The comma-separated PCI vendor and device ID that would associate
+	  The comma-separated PCI vendor and device ID with optional revision if that
-	  your vBIOS to your video card.
+	  feature is enabled that would associate your vBIOS to your video card.
 
-	  Example: 1106,3230
+	  Example: 1106,3230 or 1106,3230,a3
 
 	  In the above example 1106 is the PCI vendor ID (in hex, but without
 	  the "0x" prefix) and 3230 specifies the PCI device ID of the
-	  video card (also in hex, without "0x" prefix).
+	  video card (also in hex, without "0x" prefix). a3 specifies the revision.
 
 	  Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 
+config CHECK_REV_IN_OPROM_NAME
+	def_bool n
+	help
+	  Select this in the platform BIOS or chipset if the option rom has a revision
+	  that needs to be checked when searching CBFS.
+
 config VGA_BIOS_DGPU
 	bool "Add a discrete VGA BIOS image"
 	depends on VGA_BIOS

src/device/device_util.c

@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <types.h>
@@ -777,7 +776,7 @@ void show_all_devs_resources(int debug_level, const char *msg)
 	}
 }
 
-const struct resource *resource_range_idx(struct device *dev, unsigned long index,
+const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
 				uint64_t base, uint64_t size, unsigned long flags)
 {
 	struct resource *resource;
@@ -786,13 +785,8 @@ const struct resource *resource_range_idx(struct device *dev, unsigned long inde
 
 	resource = new_resource(dev, index);
 	resource->base = base;
-
+	resource->size = size;
-	if (flags & IORESOURCE_FIXED)
+	resource->flags = IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
-		resource->size = size;
-	if (flags & IORESOURCE_BRIDGE)
-		resource->limit = base + size - 1;
-
-	resource->flags = IORESOURCE_ASSIGNED;
 	resource->flags |= flags;
 
 	printk(BIOS_SPEW, "dev: %s, index: 0x%lx, base: 0x%llx, size: 0x%llx\n",

src/device/pci_rom.c

@@ -6,13 +6,13 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <stdio.h>
 #include <string.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <acpi/acpigen.h>
 
 /* Rmodules don't like weak symbols. */
+void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; }
 u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
 
 void vga_oprom_preload(void)
@@ -39,26 +39,34 @@ static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 	return cbfs_map(name, NULL);
 }
 
+static void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev)
+{
+	char name[20] = "pciXXXX,XXXX,XX.rom";
+
+	snprintf(name, sizeof(name), "pci%04hx,%04hx,%02hhx.rom", vendor, device, rev);
+
+	return cbfs_map(name, NULL);
+}
+
 struct rom_header *pci_rom_probe(const struct device *dev)
 {
 	struct rom_header *rom_header = NULL;
 	struct pci_data *rom_data;
+	u8 rev = pci_read_config8(dev, PCI_REVISION_ID);
+	u8 mapped_rev = rev;
 	u32 vendev = (dev->vendor << 16) | dev->device;
 	u32 mapped_vendev = vendev;
 
 	/* If the ROM is in flash, then don't check the PCI device for it. */
-	mapped_vendev = map_oprom_vendev(vendev);
+	if (CONFIG(CHECK_REV_IN_OPROM_NAME)) {
-	rom_header = cbfs_boot_map_optionrom(mapped_vendev >> 16, mapped_vendev & 0xffff);
+		map_oprom_vendev_rev(&mapped_vendev, &mapped_rev);
-
+		rom_header = cbfs_boot_map_optionrom_revision(mapped_vendev >> 16,
-	/* Handle the case of VGA_BIOS_ID not being set to the remapped PCI ID. This is a
+							      mapped_vendev & 0xffff,
-	   workaround that should be removed once the underlying issue is fixed. */
+							      mapped_rev);
-	if (!rom_header && vendev != mapped_vendev) {
+	} else {
-		rom_header = cbfs_boot_map_optionrom(vendev >> 16, vendev & 0xffff);
+		mapped_vendev = map_oprom_vendev(vendev);
-		if (rom_header) {
+		rom_header = cbfs_boot_map_optionrom(mapped_vendev >> 16,
-			printk(BIOS_NOTICE, "VGA_BIOS_ID should be the remapped PCI ID "
+						     mapped_vendev & 0xffff);
-					    "%04hx,%04hx in the VBIOS file\n",
-			       mapped_vendev >> 16, mapped_vendev & 0xffff);
-		}
 	}
 
 	if (rom_header) {

src/drivers/acpi/thermal_zone/thermal_zone.c

@@ -5,8 +5,8 @@
 #include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <stdio.h>
 #include <stdlib.h>
+#include <string.h>
 
 #include "chip.h"
 

src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c

@@ -3,8 +3,7 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpigen.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
-
 #include "chip.h"
 #include <console/console.h>
 

src/drivers/generic/gpio_keys/gpio_keys.c

@@ -3,7 +3,7 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpigen.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
 
 #include "chip.h"
 

src/drivers/gfx/nvidia/Kconfig

@@ -1,38 +0,0 @@
-config DRIVERS_GFX_NVIDIA
-	bool
-	default n
-	help
-	  Support for NVIDIA Optimus graphics
-
-config DRIVERS_GFX_NVIDIA_BRIDGE
-	hex "PCI bridge for the GPU device"
-	default 0x01
-	depends on DRIVERS_GFX_NVIDIA
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	depends on DRIVERS_GFX_NVIDIA
-	bool
-	default n
-	help
-	  Support for NVIDIA Dynamic Boost
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
-	int "Total processor power offset from default TGP in watts"
-	default 45
-	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	help
-	  This identifies the available power for the CPU or GPU boost
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
-	int "Minimum TGP offset from default TGP in watts"
-	default 0
-	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	help
-	  This is used to transfer power from the GPU to the CPU
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
-	int "Maximum TGP offset from default TGP in watts"
-	default 0
-	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	help
-	  This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.mk

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
-
-ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
-
-// Memory mapped PCI express config space
-OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
-
-Field (PCIC, ByteAcc, NoLock, Preserve) {
-	PVID,   16,
-	PDID,   16,
-
-	Offset (0x248),
-		,   7,
-	L23E,   1,      /* L23_Rdy Entry Request */
-	L23R,   1,      /* L23_Rdy to Detect Transition */
-
-	Offset (0xC20),
-		,   4,
-	P0AP,   2,      /* Additional power savings */
-
-	Offset (0xC38),
-		,   3,
-	P0RM,   1,      /* Robust squelch mechanism */
-}
-
-// Enter L23
-Method (DL23, 0, Serialized) {
-	Printf("      GPU PORT DL23 START")
-
-	L23E = 1
-	Sleep (16)
-	Local0 = 0
-	While (L23E) {
-		If ((Local0 > 4)) {
-			Break
-		}
-
-		Sleep (16)
-		Local0++
-	}
-
-	P0RM = 1
-	P0AP = 3
-
-	Printf("      GPU PORT DL23 FINISH")
-}
-
-// Exit L23
-Method (L23D, 0, Serialized) {
-	Printf("      GPU PORT L23D START")
-
-	L23R = 1
-	Sleep (16)
-	Local0 = 0
-	While (L23R) {
-		If ((Local0 > 4)) {
-			Break
-		}
-
-		Sleep (16)
-		Local0++
-	}
-
-	P0RM = 0
-	P0AP = 0
-
-	Printf("      GPU PORT L23D FINISH")
-}
-
-// Main power resource
-PowerResource (PWRR, 0, 0) {
-	Name (_STA, 1)
-
-	Method (_ON, 0, Serialized) {
-		Printf("GPU PORT PWRR._ON")
-
-		^^DEV0._ON()
-
-		_STA = 1
-	}
-
-	Method (_OFF, 0, Serialized) {
-		Printf("GPU PORT PWRR._OFF")
-
-		^^DEV0._OFF()
-
-		_STA = 0
-	}
-}
-
-// Power resources for entering D0
-Name (_PR0, Package () { PWRR })
-
-// Power resources for entering D3
-Name (_PR3, Package () { PWRR })
-
-#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define NV_ERROR_SUCCESS 0x0
-#define NV_ERROR_UNSPECIFIED 0x80000001
-#define NV_ERROR_UNSUPPORTED 0x80000002
-
-#include "gps.asl"
-#include "nvjt.asl"
-
-Method (_DSM, 4, Serialized) {
-	Printf("GPU _DSM")
-	If (Arg0 == ToUUID (JT_DSM_GUID)) {
-		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
-			Return (NVJT(Arg2, Arg3))
-		} Else {
-			Printf("  Unsupported JT revision: %o", SFST(Arg1))
-			Return (NV_ERROR_UNSUPPORTED)
-		}
-	} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
-		If (ToInteger(Arg1) == GPS_REVISION_ID) {
-			Return (GPS(Arg2, Arg3))
-		} Else {
-			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
-			Return (NV_ERROR_UNSUPPORTED)
-		}
-	} Else {
-		Printf("  Unsupported GUID: %o", IDST(Arg0))
-		Return (NV_ERROR_UNSPECIFIED)
-	}
-}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
-#define GPS_REVISION_ID 0x00000200
-#define GPS_FUNC_SUPPORT 0x00000000
-#define GPS_FUNC_PSHARESTATUS 0x00000020
-#define GPS_FUNC_PSHAREPARAMS 0x0000002A
-
-Method(GPS, 2, Serialized) {
-	Printf("  GPU GPS")
-	Switch(ToInteger(Arg0)) {
-		Case(GPS_FUNC_SUPPORT) {
-			Printf("    Supported Functions")
-			Return(ITOB(
-				(1 << GPS_FUNC_SUPPORT) |
-				(1 << GPS_FUNC_PSHARESTATUS) |
-				(1 << GPS_FUNC_PSHAREPARAMS)
-			))
-		}
-		Case(GPS_FUNC_PSHARESTATUS) {
-			Printf("    Power Share Status")
-			Return(ITOB(0))
-		}
-		Case(GPS_FUNC_PSHAREPARAMS) {
-			Printf("    Power Share Parameters")
-
-			CreateField(Arg1, 0, 4, QTYP) // Query type
-
-			Name(GPSP, Buffer(36) { 0x00 })
-			CreateDWordField(GPSP, 0, RSTS) // Response status
-			CreateDWordField(GPSP, 4, VERS) // Version
-
-			// Set query type of response
-			RSTS = QTYP
-			// Set version of response
-			VERS = 0x00010000
-
-			Switch(ToInteger(QTYP)) {
-				Case(0) {
-					Printf("      Request Current Information")
-					// No required information
-					Return(GPSP)
-				}
-				Case(1) {
-					Printf("      Request Supported Fields")
-					// Support GPU temperature field
-					RSTS |= (1 << 8)
-					Return(GPSP)
-				}
-				Case(2) {
-					Printf("      Request Current Limits")
-					// No required limits
-					Return(GPSP)
-				}
-				Default {
-					Printf("      Unknown Query: %o", SFST(QTYP))
-					Return(NV_ERROR_UNSUPPORTED)
-				}
-			}
-		}
-		Default {
-			Printf("    Unsupported function: %o", SFST(Arg0))
-			Return(NV_ERROR_UNSUPPORTED)
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (DEV0) {
-	Name(_ADR, 0x00000000)
-
-	#include "utility.asl"
-	#include "dsm.asl"
-	#include "power.asl"
-}
-
-#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
-Scope (\_SB) {
-	Device(NPCF) {
-		#include "utility.asl"
-		#include "nvpcf.asl"
-	}
-}
-#endif

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -1,152 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
-#define JT_REVISION_ID_MIN 0x00000100
-#define JT_REVISION_ID_MAX 0x00000200
-#define JT_FUNC_SUPPORT 0x00000000
-#define JT_FUNC_CAPS 0x00000001
-#define JT_FUNC_POWERCONTROL 0x00000003
-
-//TODO: SMI traps and EGIN/XCLM
-#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
-#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
-#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
-#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
-#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
-
-#define JT_DFGC_NONE 0 // Handle request immediately
-#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
-//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
-
-// Deferred GC6 enter/exit until D3-cold (saved DFGC)
-Name(DFEN, 0)
-
-// Deferred GC6 enter control (saved GPC)
-Name(DFCI, 0)
-
-// Deferred GC6 exit control (saved GPCX)
-Name(DFCO, 0)
-
-Method (NVJT, 2, Serialized) {
-	Printf("  GPU NVJT")
-	Switch (ToInteger(Arg0)) {
-		Case (JT_FUNC_SUPPORT) {
-			Printf("    Supported Functions")
-			Return(ITOB(
-				(1 << JT_FUNC_SUPPORT) |
-				(1 << JT_FUNC_CAPS) |
-				(1 << JT_FUNC_POWERCONTROL)
-			))
-		}
-		Case (JT_FUNC_CAPS) {
-			Printf("    Capabilities")
-			Return(ITOB(
-				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
-				(1 << 1) | // NVSR disabled
-				(2 << 3) | // Panel power and backlight are on the suspend rail
-				(0 << 5) | // self-refresh controller remains powered while panel is powered
-				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
-				(0 << 8) | // Combined power rail for all GPUs
-				(0 << 10) | // External SPI ROM
-				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
-				(0 << 12) | // Supports notify on GC6 state done
-				(1 << 13) | // Support deferred GC6
-				(1 << 14) | // Support fine-grained root port control
-				(2 << 15) | // GC6 version is GC6-R
-				(0 << 17) | // GC6 exit ISR is not supported
-				(0 << 18) | // GC6 self wakeup not supported
-				(JT_REVISION_ID_MAX << 20) // Highest revision supported
-			))
-		}
-		Case (JT_FUNC_POWERCONTROL) {
-			Printf("    Power Control: %o", SFST(Arg1))
-
-			CreateField (Arg1, 0, 3, GPC) // GPU power control
-			CreateField (Arg1, 4, 1, PPC) // Panel power control
-			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
-			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
-
-			// Save deferred GC6 request
-			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
-				DFEN = DFGC
-				DFCI = GPC
-				DFCO = GPCX
-			}
-
-			// Buffer to cache current state
-			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
-			CreateField (JTBF, 0, 3, CGCS) // Current GC state
-			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
-			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
-
-			// If doing deferred GC6 request, return now
-			If (ToInteger(DFGC) != 0) {
-				CGCS = 1
-				CGPS = 1
-				Return (JTBF)
-			}
-
-			// Apply requested state
-			Switch (ToInteger(GPC)) {
-				Case (JT_GPC_GSS) {
-					Printf("    Get current GPU GCx sleep status")
-					//TODO: include transitions!
-					If (GTXS(DGPU_RST_N)) {
-						// GPU powered on
-						CGCS = 1
-						CGPS = 1
-					} ElseIf (GTXS(DGPU_PWR_EN)) {
-						// GPU powered off, GC6
-						CGCS = 3
-						CGPS = 0
-					} Else {
-						// GPU powered off, D3 cold
-						CGCS = 2
-						CGPS = 0
-					}
-				}
-				Case (JT_GPC_EGNS) {
-					Printf("    Enter GC6 without self-refresh")
-					GC6I()
-					CPSS = 1
-				}
-				Case (JT_GPC_EGIS) {
-					Printf("    Enter GC6 with self-refresh")
-					GC6I()
-					If (ToInteger(PPC) == 0) {
-						CPSS = 0
-					}
-				}
-				Case (JT_GPC_XGXS) {
-					Printf("    Exit GC6 and stop self-refresh")
-					GC6O()
-
-					CGCS = 1
-					CGPS = 1
-					If (ToInteger(PPC) != 0) {
-						CPSS = 0
-					}
-				}
-				Case (JT_GPC_XGIS) {
-					Printf("    Exit GC6 for self-refresh update")
-					GC6O()
-
-					CGCS = 1
-					CGPS = 1
-					If (ToInteger(PPC) != 0) {
-						CPSS = 0
-					}
-				}
-				Default {
-					Printf("    Unsupported GPU power control: %o", SFST(GPC))
-				}
-			}
-
-			Return (JTBF)
-		}
-		Default {
-			Printf("    Unsupported function: %o", SFST(Arg0))
-			Return (NV_ERROR_UNSUPPORTED)
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/common/nvpcf.asl

@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
-#define NVPCF_REVISION_ID 0x00000200
-#define NVPCF_ERROR_SUCCESS 0x0
-#define NVPCF_ERROR_GENERIC 0x80000001
-#define NVPCF_ERROR_UNSUPPORTED 0x80000002
-#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
-#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
-#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
-
-Name(_HID, "NVDA0820")
-
-Name(_UID, "NPCF")
-
-Method(_DSM, 4, Serialized) {
-	Printf("NVPCF _DSM")
-	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
-		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
-			Return(NPCF(Arg2, Arg3))
-		} Else {
-			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
-			Return(NVPCF_ERROR_GENERIC)
-		}
-	} Else {
-		Printf("  Unsupported GUID: %o", IDST(Arg0))
-		Return(NVPCF_ERROR_GENERIC)
-	}
-}
-
-Method(NPCF, 2, Serialized) {
-	Printf("  NVPCF NPCF")
-	Switch(ToInteger(Arg0)) {
-		Case(NVPCF_FUNC_GET_SUPPORTED) {
-			Printf("    Supported Functions")
-			Return(ITOB(
-				(1 << NVPCF_FUNC_GET_SUPPORTED) |
-				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
-				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
-			))
-		}
-		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
-			Printf("    Get Static Config")
-			Return(Buffer(14) {
-				// Device table header
-				0x20, 0x03, 0x01,
-				// Intel + NVIDIA
-				0x00,
-				// Controller table header
-				0x23, 0x04, 0x05, 0x01,
-				// Dynamic boost controller
-				0x01,
-				// Supports DC
-				0x01,
-				// Reserved
-				0x00, 0x00, 0x00,
-				// Checksum
-				0xAD
-			})
-		}
-		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
-			Printf("    Update Dynamic Boost")
-
-			CreateField(Arg1, 0x28, 2, ICMD) // Input command
-
-			Name(PCFP, Buffer(49) {
-				// Table version
-				0x23,
-				// Table header size
-				0x05,
-				// Size of common status in bytes
-				0x10,
-				// Size of controller entry in bytes
-				0x1C,
-				// Other fields filled in later
-			})
-			CreateByteField(PCFP, 0x04, CCNT) // Controller count
-			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
-			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
-			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
-
-			Switch(ToInteger(ICMD)) {
-				Case(0) {
-					Printf("      Get Controller Params")
-					// Number of controllers
-					CCNT = 1
-					// AC total processor power offset from default TGP in 1/8 watt units
-					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
-					// AC maximum TGP offset from default TGP in 1/8 watt units
-					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
-					// AC minimum TGP offset from default TGP in 1/8 watt units
-					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
-					Printf("PCFP: %o", SFST(PCFP))
-					Return(PCFP)
-				}
-				Case(1) {
-					Printf("      Set Controller Status")
-					//TODO
-					Printf("PCFP: %o", SFST(PCFP))
-					Return(PCFP)
-				}
-				Default {
-					Printf("      Unknown Input Command: %o", SFST(ICMD))
-					Return(NV_ERROR_UNSUPPORTED)
-				}
-			}
-		}
-		Default {
-			Printf("    Unsupported function: %o", SFST(Arg0))
-			Return(NVPCF_ERROR_UNSUPPORTED)
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -1,120 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-//TODO: evaluate sleeps
-
-OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
-Field (PCIC, DwordAcc, NoLock, Preserve) {
-	Offset (0x40),
-	SSID, 32, // Subsystem vendor and product ID
-}
-
-// Enter GC6
-Method(GC6I, 0, Serialized) {
-	Printf("    GPU GC6I START")
-
-	// Enter L23
-	^^DL23()
-	Sleep(5)
-
-	// Put GPU into reset
-	Printf("      Put GPU into reset")
-	CTXS(DGPU_RST_N)
-	Sleep(5)
-
-	Printf("    GPU GC6I FINISH")
-}
-
-// Exit GC6
-Method(GC6O, 0, Serialized) {
-	Printf("    GPU GC6O START")
-
-	// Bring GPU out of reset
-	Printf("      Bring GPU out of reset")
-	STXS(DGPU_RST_N)
-	Sleep(5)
-
-	// Exit L23
-	^^L23D()
-	Sleep(5)
-
-	Printf("    GPU GC6O FINISH")
-}
-
-Method (_ON, 0, Serialized) {
-	Printf("  GPU _ON START")
-
-	If (DFEN == JT_DFGC_DEFER) {
-		Switch (ToInteger(DFCO)) {
-			Case (JT_GPC_XGXS) {
-				Printf("    Exit GC6 and stop self-refresh")
-				GC6O()
-			}
-			Default {
-				Printf("    Unsupported DFCO: %o", SFST(DFCO))
-			}
-		}
-		DFEN = JT_DFGC_NONE
-	} Else {
-		Printf("    Standard RTD3 power on")
-		STXS(DGPU_PWR_EN)
-		Sleep(5)
-		GC6O()
-	}
-
-	Printf("  GPU _ON FINISH")
-}
-
-Method (_OFF, 0, Serialized) {
-	Printf("  GPU _OFF START")
-
-	If (DFEN == JT_DFGC_DEFER) {
-		Switch (ToInteger(DFCI)) {
-			Case (JT_GPC_EGNS) {
-				Printf("    Enter GC6 without self-refresh")
-				GC6I()
-			}
-			Case (JT_GPC_EGIS) {
-				Printf("    Enter GC6 with self-refresh")
-				GC6I()
-			}
-			Default {
-				Printf("    Unsupported DFCI: %o", SFST(DFCI))
-			}
-		}
-		DFEN = JT_DFGC_NONE
-	} Else {
-		Printf("    Standard RTD3 power off")
-		GC6I()
-		CTXS(DGPU_PWR_EN)
-		Sleep(5)
-	}
-
-	Printf("  GPU _OFF FINISH")
-}
-
-// Main power resource
-PowerResource (PWRR, 0, 0) {
-	Name (_STA, 1)
-
-	Method (_ON, 0, Serialized) {
-		Printf("GPU PWRR._ON")
-
-		// Restore SSID
-		^^SSID = DGPU_SSID
-		Printf("  Restore SSID: %o", SFST(^^SSID))
-
-		_STA = 1
-	}
-
-	Method (_OFF, 0, Serialized) {
-		Printf("GPU PWRR._OFF")
-
-		_STA = 0
-	}
-}
-
-// Power resources for entering D0
-Name (_PR0, Package () { PWRR })
-
-// Power resources for entering D3
-Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Convert a byte to a hex string, trimming extra parts
-Method (BHEX, 1) {
-	Local0 = ToHexString(Arg0)
-	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
-}
-
-// UUID to string
-Method (IDST, 1) {
-	Local0 = ""
-	Fprintf(
-		Local0,
-		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
-		BHEX(DerefOf(Arg0[3])),
-		BHEX(DerefOf(Arg0[2])),
-		BHEX(DerefOf(Arg0[1])),
-		BHEX(DerefOf(Arg0[0])),
-		BHEX(DerefOf(Arg0[5])),
-		BHEX(DerefOf(Arg0[4])),
-		BHEX(DerefOf(Arg0[7])),
-		BHEX(DerefOf(Arg0[6])),
-		BHEX(DerefOf(Arg0[8])),
-		BHEX(DerefOf(Arg0[9])),
-		BHEX(DerefOf(Arg0[10])),
-		BHEX(DerefOf(Arg0[11])),
-		BHEX(DerefOf(Arg0[12])),
-		BHEX(DerefOf(Arg0[13])),
-		BHEX(DerefOf(Arg0[14])),
-		BHEX(DerefOf(Arg0[15]))
-	)
-	Return (Local0)
-}
-
-// Safe hex conversion, checks type first
-Method (SFST, 1) {
-	Local0 = ObjectType(Arg0)
-	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
-		Return (ToHexString(Arg0))
-	} Else {
-		Return (Concatenate("Type: ", Arg0))
-	}
-}
-
-// Convert from 4-byte buffer to 32-bit integer
-Method (BTOI, 1) {
-	Return(
-		DerefOf(Arg0[0]) |
-		(DerefOf(Arg0[1]) << 8) |
-		(DerefOf(Arg0[2]) << 16) |
-		(DerefOf(Arg0[3]) << 24)
-	)
-}
-
-// Convert from 32-bit integer to 4-byte buffer
-Method (ITOB, 1) {
-	Local0 = Buffer(4) { 0, 0, 0, 0 }
-	Local0[0] = Arg0 & 0xFF
-	Local0[1] = (Arg0 >> 8) & 0xFF
-	Local0[2] = (Arg0 >> 16) & 0xFF
-	Local0[3] = (Arg0 >> 24) & 0xFF
-	Return (Local0)
-}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
-
-// Port mapped PCI express config space
-OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
-
-Field (PCIC, AnyAcc, NoLock, Preserve) {
-	Offset(0x52),  /* LSTS - Link Status Register */
-	, 13,
-	LASX, 1,       /* 0, Link Active Status */
-
-	Offset(0x60),  /* RSTS - Root Status Register */
-	, 16,
-	PSPX, 1,       /* 16,  PME Status */
-
-	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
-	, 30,
-	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
-	PMEX, 1,       /* 31,  Power Management SCI Enable */
-
-	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
-	SCB0, 1,       /* Scratch bit 0 */
-
-	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
-	, 2,
-	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
-	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
-}
-
-Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
-	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
-	, 30,
-	HPSX, 1,       /* 30,  Hot Plug SCI Status */
-	PMSX, 1        /* 31,  Power Management SCI Status */
-}
-
-// Enter L23
-Method (DL23, 0, Serialized) {
-	Printf("      GPU PORT DL23 START")
-
-	L23E = 1
-	Sleep (16)
-	Local0 = 0
-	While (L23E) {
-		If ((Local0 > 4)) {
-			Break
-		}
-
-		Sleep (16)
-		Local0++
-	}
-	SCB0 = 1
-
-	Printf("      GPU PORT DL23 FINISH")
-}
-
-// Exit L23
-Method (L23D, 0, Serialized) {
-	Printf("      GPU PORT L23D START")
-
-	If ((SCB0 == 1)) {
-		L23R = 1
-		Local0 = 0
-		While (L23R) {
-			If ((Local0 > 4)) {
-				Break
-			}
-			Sleep (16)
-			Local0++
-		}
-
-		SCB0 = 0
-		Local0 = 0
-		While ((LASX == 0)) {
-			If ((Local0 > 8)) {
-				Break
-			}
-			Sleep (16)
-			Local0++
-		}
-	}
-
-	Printf("      GPU PORT L23D FINISH")
-}
-
-Method (HPME, 0, Serialized) {
-	Printf("  GPU PORT HPME START")
-
-	If (PMSX == 1) {
-		Printf("    Notify GPU driver of PME SCI")
-		Notify(DEV0, 0x2)
-		Printf("    Clear PME SCI")
-		PMSX = 1
-		Printf("    Consume PME notification")
-		PSPX = 1
-	}
-
-	Printf("  GPU PORT HPME FINISH")
-}
-
-// Main power resource
-PowerResource (PWRR, 0, 0) {
-	Name (_STA, 1)
-
-	Method (_ON, 0, Serialized) {
-		Printf("GPU PORT PWRR._ON")
-
-		HPME();
-		If (PMEX == 1) {
-			Printf("  Disable power management SCI")
-			PMEX = 0
-		}
-
-		^^DEV0._ON()
-
-		_STA = 1
-	}
-
-	Method (_OFF, 0, Serialized) {
-		Printf("GPU PORT PWRR._OFF")
-
-		^^DEV0._OFF()
-
-		If (PMEX == 0) {
-			Printf("  Enable power management SCI")
-			PMEX = 1
-			HPME()
-		}
-
-		_STA = 0
-	}
-}
-
-// Power resources for entering D0
-Name (_PR0, Package () { PWRR })
-
-// Power resources for entering D3
-Name (_PR3, Package () { PWRR })
-
-#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
-#define _DRIVERS_GFX_NVIDIA_CHIP_H_
-
-struct drivers_gfx_nvidia_config {
-	/* TODO: Set GPIOs in devicetree? */
-};
-
-#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
-#define _DRIVERS_GFX_NVIDIA_GPU_H_
-
-#include <stdbool.h>
-
-struct nvidia_gpu_config {
-	/* GPIO for GPU_PWR_EN */
-	unsigned int power_gpio;
-	/* GPIO for GPU_RST# */
-	unsigned int reset_gpio;
-	/* Enable or disable GPU power */
-	bool enable;
-};
-
-void nvidia_set_power(const struct nvidia_gpu_config *config);
-
-#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "chip.h"
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
-
-static void nvidia_read_resources(struct device *dev)
-{
-	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
-
-	pci_dev_read_resources(dev);
-
-	// Find all BARs on GPU, mark them above 4g if prefetchable
-	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
-		struct resource *res = probe_resource(dev, bar);
-
-		if (res) {
-			if (res->flags & IORESOURCE_PREFETCH) {
-				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
-				res->flags |= IORESOURCE_ABOVE_4G;
-			} else {
-				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
-			}
-		} else {
-			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
-		}
-	}
-}
-
-static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
-{
-	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations nvidia_device_ops_pci = {
-	.set_subsystem = nvidia_set_subsystem,
-};
-
-static struct device_operations nvidia_device_ops = {
-	.read_resources   = nvidia_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-#if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables = pci_rom_write_acpi_tables,
-	.acpi_fill_ssdt    = pci_rom_ssdt,
-#endif
-	.init             = pci_dev_init,
-	.ops_pci          = &nvidia_device_ops_pci,
-
-};
-
-static void nvidia_enable(struct device *dev)
-{
-	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
-		return;
-
-	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
-		return;
-
-	dev->ops = &nvidia_device_ops;
-}
-
-struct chip_operations drivers_gfx_nvidia_ops = {
-	.name = "NVIDIA Optimus Graphics Device",
-	.enable_dev = nvidia_enable
-};

src/drivers/gfx/nvidia/romstage.c

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <gpio.h>
-#include "chip.h"
-#include "gpu.h"
-
-void nvidia_set_power(const struct nvidia_gpu_config *config)
-{
-	if (!config->power_gpio || !config->reset_gpio) {
-		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
-		return;
-	}
-
-	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
-	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
-
-	gpio_set(config->reset_gpio, 0);
-	mdelay(10);
-
-	if (config->enable) {
-		gpio_set(config->power_gpio, 1);
-		mdelay(25);
-		gpio_set(config->reset_gpio, 1);
-	} else {
-		gpio_set(config->power_gpio, 0);
-	}
-
-	mdelay(10);
-}

src/drivers/i2c/cs35l53/cs35l53.c

@@ -6,7 +6,6 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/generic/generic.c

@@ -7,8 +7,7 @@
 #include <device/i2c_simple.h>
 #include <device/device.h>
 #include <gpio.h>
-#include <stdio.h>
+#include <string.h>
-
 #include "chip.h"
 
 #if CONFIG(HAVE_ACPI_TABLES)

src/drivers/i2c/gpiomux/bus/bus.c

@@ -4,7 +4,7 @@
 #include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
 
 #include "chip.h"
 

src/drivers/i2c/gpiomux/mux/mux.c

@@ -4,7 +4,7 @@
 #include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
 
 #include "chip.h"
 

src/drivers/i2c/hid/hid.c

@@ -4,8 +4,7 @@
 #include <acpi/acpi_device.h>
 #include <assert.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
-
 #include "chip.h"
 #include <gpio.h>
 #include <console/console.h>

src/drivers/i2c/max98390/max98390.c

@@ -7,7 +7,6 @@
 #include <device/device.h>
 #include <identity.h>
 #include <stdint.h>
-#include <stdio.h>
 #include <vendorcode/google/dsm_calib.h>
 #include "chip.h"
 

src/drivers/i2c/max98396/max98396.c

@@ -5,7 +5,6 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/rt1011/rt1011.c

@@ -6,7 +6,6 @@
 #include <device/i2c.h>
 #include <device/device.h>
 #include <stdint.h>
-#include <stdio.h>
 #include <vendorcode/google/dsm_calib.h>
 #include "chip.h"
 

src/drivers/i2c/rt5645/rt5645.c

@@ -4,8 +4,6 @@
 #include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <stdio.h>
-
 #include "chip.h"
 
 #define RT5645_ACPI_NAME	"RT58"

src/drivers/i2c/sx9310/sx9310.c

@@ -5,8 +5,7 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
-
 #include "chip.h"
 
 #define I2C_SX9310_ACPI_ID	"STH9310"

src/drivers/i2c/sx9324/sx9324.c

@@ -5,8 +5,7 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
-
 #include "chip.h"
 
 #define I2C_SX9324_ACPI_ID	"STH9324"

src/drivers/i2c/sx9360/sx9360.c

@@ -5,8 +5,7 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <stdio.h>
+#include <string.h>
-
 #include "chip.h"
 
 #define I2C_SX9360_ACPI_ID	"STH9360"

src/drivers/i2c/tpm/cr50.c

@@ -498,7 +498,7 @@ tpm_result_t tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t d
 	if (rc)
 		return rc;
 
-	printk(BIOS_DEBUG, "GSC TPM 2.0 (i2c %u:0x%02x id %#x)\n",
+	printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id %#x)\n",
 	       bus, dev_addr, did_vid >> 16);
 
 	if (tpm_first_access_this_boot()) {

src/drivers/intel/dptf/dptf.c

@@ -5,7 +5,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <intelblocks/pmc_ipc.h>
-#include <stdio.h>
 #include <soc/dptf.h>
 #include <soc/pci_devs.h>
 #include "chip.h"

src/drivers/intel/dtbt/Kconfig

@@ -1,4 +0,0 @@
-config DRIVERS_INTEL_DTBT
-	def_bool n
-	help
-	  Support for discrete Thunderbolt controllers

src/drivers/intel/dtbt/Makefile.mk

@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c