Documentation/security/vboot: Update 4.15 vboot supported boards

Update list of boards that support vboot.

Change-Id: Id5d4d18202bf85c5ba407efd690eee5cba88a8a7
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58975
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/community/index.md

@@ -1,7 +0,0 @@
-# Community
-
-* [Code of Conduct](code_of_conduct.md)
-* [Language style](language_style.md)
-* [Community forums](forums.md)
-* [Project services](services.md)
-* [coreboot at conferences](conferences.md)

Documentation/community/services.md

@@ -1,6 +1,6 @@
 # Accounts on coreboot.org
 
-There are a number of places where you can benefit from creating an account
+There are a number of places where you can benefit from creaating an account
 in our community. Since there is no single sign-on system in place (at this
 time), they come with their own setup routines.
 

Documentation/contributing/gsoc.md

@@ -1,249 +0,0 @@
-# Google Summer of Code
-
-
-## Contacts
-
-If you are interested in participating in GSoC as a contributor or mentor,
-please have a look at our [community forums] and reach out to us. Working closely
-with the community is highly encouraged, as we've seen that our most successful
-contributors are generally very involved.
-
-Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
-2022. Please feel free to reach out to them directly if you have any questions.
-
-
-## Why work on coreboot for GSoC?
-
-  * coreboot offers you the opportunity to work with various architectures
-    right on the iron. coreboot supports both current and older silicon for a
-    wide variety of chips and technologies.
-
-  * coreboot has a worldwide developer and user base.
-
-  * We are a very passionate team, so you will interact directly with the
-    project initiators and project leaders.
-
-  * We have a large, helpful community. coreboot has some extremely talented
-    and helpful experts in firmware involved in the project. They are ready to
-    assist and mentor contributors participating in GSoC.
-
-  * One of the last areas where open source software is not common is firmware.
-    Running proprietary firmware can have severe effects on user's freedom and
-    security. coreboot has a mission to change that by providing a common
-    framework for initial hardware initialization and you can help us succeed.
-
-
-## Contributor requirements & commitments
-
-Google Summer of Code is a significant time commitment for you. Medium-sized
-projects are estimated to take 175 hours, while large-sized projects are
-estimated to take 350 hours. Depending on the project size, this means we
-expect you to work roughly half-time or full-time on your project during the
-three months of coding. We expect to be able to see this level of effort in the
-results.
-
-The standard program duration is 12 weeks and in consultation with the mentor
-it can be extended up to 22 weeks. Please keep in mind that the actual number
-of hours you spend on the project highly depends on your skills and previous
-experience.
-
-Make sure that your schedule (exams, courses, day job) gives you a sufficient
-amount of spare time. If this is not the case, then you should not apply.
-
-
-### Before applying
-
-  * Join the [mailing list] and our other [community forums]. Introduce yourself
-    and mention that you are a prospective GSoC contributor. Ask questions and
-    discuss the project that you are considering. Community involvement is a
-    key component of coreboot development.
-
-  * You accept our [Code of Conduct] and [Language style].
-
-  * Demonstrate that you can work with the coreboot codebase.
-
-    * Look over some of the development processes guidelines: [Getting started],
-      [Tutorial], [Flashing firmware tutorial] and [Coding style].
-
-    * Download, build and boot coreboot in QEMU or on real hardware. Please email
-      your serial output results to the [mailing list].
-
-    * Look through some patches on Gerrit to get an understanding of the review
-      process and common issues.
-
-    * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check Easy projects or ask for simple tasks on the [mailing list] or on our
-      other [community forums] if you need ideas.
-
-
-### During the program
-
-  * To pass and to be paid by Google requires that you meet certain milestones.
-
-    * First, you must be in good standing with the community before the official
-      start of the program. We expect you to post some design emails to the
-      [mailing list], and get feedback on them, both before applying, and during
-      the "community bonding period" between acceptance and official start.
-
-    * You must have made progress and committed significant code before the
-      mid-term point and by the final.
-
-    * We require that accepted contributors to maintain a blog, where you are
-      expected to write about your project *WEEKLY*. This is a way to measure
-      progress and for the community at large to be able to help you. GSoC is
-      *NOT* a private contract between your mentor and you.
-
-  * You must be active in the community on IRC and the [mailing list].
-
-  * You are expected to work on development publicly, and to push commits to the
-    project on a regular basis. Depending on the project and what your mentor
-    agrees to, these can be published directly to the project or to a public
-    repository such as Gitlab or Github. If you are not publishing directly to
-    the project codebase, be aware that we do not want large dumps of code that
-    need to be rushed to meet the mid-term and final goals.
-
-We don't expect our contributors to be experts in our problem domain, but we
-don't want you to fail because some basic misunderstanding was in your way of
-completing the task.
-
-
-## Projects
-
-There are many development tasks available in coreboot. We prepared some ideas
-for Summer of Code projects. These are projects that we think can be managed in
-the timeline of GSoC, and they cover areas where coreboot is trying to reach
-new users and new use cases.
-
-Of course your application does not have to be based on any of the ideas listed.
-It is entirely possible that you have a great idea that we just didn't think of
-yet. Please let us know!
-
-The blog posts related to previous GSoC projects might give some insights to
-what it is like to be a coreboot GSoC contributor.
-
-
-## coreboot Summer of Code Application
-
-coreboot welcomes contributors from all backgrounds and levels of experience.
-
-Your application should include a complete project proposal. You should
-document that you have the knowledge and the ability to complete your proposed
-project. This may require a little research and understanding of coreboot prior
-to sending your application. The community and coreboot project mentors are your
-best resource in fleshing out your project ideas and helping with a project
-timeline. We recommend that you get feedback and recommendations on your
-proposal before the application deadline.
-
-Please complete the standard GSoC application and project proposal. Provide the
-following information as part of your application. Make sure to provide multiple
-ways of communicating in case your equipment (such as a laptop) is lost,
-damaged, or stolen, or in case of a natural disaster that disrupts internet
-service. You risk automatically failing if your mentor cannot contact you and if
-you cannot provide updates according to GSoC deadlines.
-
-**Personal Information**
-
-  * Name
-
-  * Email and contact options (IRC, Matrix, …)
-
-  * Phone number (optional, but recommended)
-
-  * Timezone, Usual working hours (UTC)
-
-  * School / University, Degree Program, expected graduation date
-
-  * Short bio / Overview of your background
-
-  * What are your other time commitments? Do you have a job, classes, vacations?
-    When and how long?
-
-**Software experience**
-
-If applicable, please provide the following information:
-
-  * Portfolio, Website, blog, microblog, Github, Gitlab, ...
-
-  * Links to one or more patches submitted
-
-  * Links to posts on the [mailing list] with the serial output of your build.
-
-  * Please comment on your software and firmware experience.
-
-  * Have you contributed to an open source project? Which one? What was your
-    experience?
-
-  * What was your experience while building and running coreboot? Did you have
-    problems?
-
-**Your project**
-
-  * Provide an overview of your project (in your own words).
-
-  * Provide a breakdown of your project in small specific weekly goals. Think
-    about the potential timeline.
-
-  * How will you accomplish this goal? What is your working style?
-
-  * Explain what risks or potential problems your project might experience.
-
-  * What would you expect as a minimum level of success?
-
-  * Do you have a stretch goal?
-
-**Other**
-
-  * Resume (optional)
-
-
-### Advice on how to apply
-
-  * [GSoC Contributor Guide]
-
-  * The Drupal project has a great page on how to write an GSoC application.
-
-  * Secrets for GSoC success: [2]
-
-
-## Mentors
-
-Each accepted project will have at least one mentor. We will match mentors and
-contributors based on the project and experience level. If possible, we also
-will try to match their time zones.
-
-Mentors are expected to stay in frequent contact with the contributor and
-provide guidance such as code reviews, pointers to useful documentation, etc.
-This should generally be a time commitment of several hours per week.
-
-Some projects might have more than one mentor, who can serve as a backup. They
-are expected to coordinate with each other and a contributor on a regular basis,
-and keep track of the contributor process. They should be able to take over
-mentoring duty if one of the mentors is unavailable (vacations, sickness,
-emergencies).
-
-
-### Volunteering to be a mentor
-
-If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide].
-This will give you a better idea of expectations, and where to go for help.
-After that, contact Org Admins (see coreboot contacts section above).
-
-The following coreboot developers have volunteered to be GSoC 2022 mentors.
-Please stop by in our community forums and say hi to them and ask them
-questions.
-
-  * Tim Wawrzynczak
-  * Raul Rangel
-  * Ron Minnich
-
-
-[community forums]: ../community/forums.md
-[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
-[Getting started]: ../getting_started/index.md
-[Tutorial]: ../tutorial/index.md
-[Flashing firmware tutorial]: ../flash_tutorial/index.md
-[Coding style]: coding_style.md
-[Code of Conduct]: ../community/code_of_conduct.md
-[Language style]: ../community/language_style.md
-[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
-[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor

Documentation/contributing/index.md

@@ -1,6 +0,0 @@
-# Contributing
-
-* [Coding Style](coding_style.md)
-* [Project Ideas](project_ideas.md)
-* [Documentation Ideas](documentation_ideas.md)
-* [Google Summer of Code](gsoc.md)

Documentation/distributions.md

@@ -24,13 +24,6 @@ ships with coreboot and support upstream maintenance for the devices through a
 third party, [3mdeb](https://3mdeb.com). They provide current and tested
 firmware binaries on [GitHub](https://pcengines.github.io).
 
-### Star Labs
-
-[Star Labs](https://starlabs.systems/) offers a range of laptops designed and
-built specifically for Linux that are available with coreboot firmware. They
-use Tianocore as the payload and include an NVRAM option to disable the
-Intel Management Engine.
-
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and

Documentation/getting_started/gerrit_guidelines.md

@@ -193,10 +193,8 @@ the wip flag:
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
 private changes, so that only explicitly added reviewers will see them. These
-sorts of patches are frequently posted as ideas or RFCs for the community to
-look at. Note that private changes can still be fetched from Gerrit by anybody
-who knows their commit ID, so don't use this for sensitive changes. To push
-a private change, use the command:
+sorts of patches are frequently posted as ideas or RFCs for the community
+to look at. To push a private change, use the command:
         git push origin HEAD:refs/for/master%private
 
 * Multiple push options can be combined:

Documentation/getting_started/gpio.md

@@ -162,53 +162,6 @@ The first is configuring a pin as an output, when it was designed to be an
 input. There is a real risk in this case of short-circuiting a component which
 could cause catastrophic failures, up to and including your mainboard!
 
-### Intel SoCs
-
-As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
-supports four different types of GPIO reset as:
-
-| PAD   Reset Config                              | Platform Reset | GPP | GPD |
-|-------------------------------------------------|----------------|-----|-----|
-| 00 - Power Good (GPP: RSMRST,  GPD: DSW_PWROK)  | Warm Reset     | N   | N   |
-|                                                 | Cold Reset     | N   | N   |
-|                                                 | S3/S4/S5       | N   | N   |
-|                                                 | Global Reset   | N   | N   |
-|                                                 | Deep Sx        | Y   | N   |
-|                                                 | G3             | Y   | N   |
-| 01 - Deep                                       | Warm Reset     | Y   | Y   |
-|                                                 | Cold Reset     | Y   | Y   |
-|                                                 | S3/S4/S5       | N   | N   |
-|                                                 | Global Reset   | Y   | Y   |
-|                                                 | Deep Sx        | Y   | Y   |
-|                                                 | G3             | Y   | Y   |
-| 10 - Host Reset/PLTRST                          | Warm Reset     | Y   | Y   |
-|                                                 | Cold Reset     | Y   | Y   |
-|                                                 | S3/S4/S5       | Y   | Y   |
-|                                                 | Global Reset   | Y   | Y   |
-|                                                 | Deep Sx        | Y   | Y   |
-|                                                 | G3             | Y   | Y   |
-| 11 - Resume Reset (GPP: Reserved,  GPD: RSMRST) | Warm Reset     | -   | N   |
-|                                                 | Cold Reset     | -   | N   |
-|                                                 | S3/S4/S5       | -   | N   |
-|                                                 | Global Reset   | -   | N   |
-|                                                 | Deep Sx        | -   | Y   |
-|                                                 | G3             | -   | Y   |
-
-Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
-specific register fields in the PAD configuration register.
-
-The Pad Config Lock registers reset type is default hardcoded to **Power Good** and
-it's **not** configurable by GPIO PAD DW0.PadRstCfg. Hence, it may appear that for a GPP,
-the Pad Reset Config (DW0 Bit 31) is configured differently from `Power Good`.
-
-This would create confusion where the Pad configuration is returned to its `default`
-value but remains `locked`, this would prevent software to reprogram the GPP.
-Additionally, this means software can't rely on GPIOs being reset by PLTRST# or Sx entry.
-
-Hence, as per GPIO BIOS Writers Guide (BWG) it's recommended to change the Pad Reset
-Configuration for lock GPP as `Power Good` so that pad configuration and lock bit are
-always in sync and can be reset at the same time.
-
 ## Soft Straps
 
 Soft straps, that can be configured by the vendor in the Intel Flash Image Tool

Documentation/index.md

@@ -168,8 +168,14 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Tutorial](tutorial/index.md)
-* [Contributing](contributing/index.md)
-* [Community](community/index.md)
+* [Coding Style](contributing/coding_style.md)
+* [Project Ideas](contributing/project_ideas.md)
+* [Documentation Ideas](contributing/documentation_ideas.md)
+* [Code of Conduct](community/code_of_conduct.md)
+* [Language style](community/language_style.md)
+* [Community forums](community/forums.md)
+* [Project services](community/services.md)
+* [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
 * [Technotes](technotes/index.md)

Documentation/mainboard/acer/g43t-am3.md

@@ -1,177 +0,0 @@
-# Acer G43T-AM3
-
-The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the
-Acer models Aspire M3800, Aspire M5800 and possibly more.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel G43 (called x4x in coreboot code)          |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel ICH10R (called i82801jx in coreboot code)  |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 775                                          |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1066                                    |
-+------------------+--------------------------------------------------+
-| SuperIO          | ITE IT8720F                                      |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82567V-2 Gigabit Ethernet                  |
-+------------------+--------------------------------------------------+
-```
-
-There is no serial port. Serial console output is possible by soldering
-to a point at the corresponding Super I/O pin and patching the
-mainboard-specific code accordingly.
-
-## Status
-
-### Working
-
-Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
-(linux-4.19.50).
-
-+ Intel Core 2 processors at up to FSB 1333
-+ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
-+ Integrated graphics (libgfxinit)
-+ HDMI and VGA ports
-+ Both PCI slots
-+ Both PCI-e slots
-+ USB (8 internal, 4 external)
-+ All six SATA ports
-+ Onboard Ethernet
-+ Onboard sound card with output on the rear stereo connector
-+ PS/2 mouse and keyboard
-    + With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500
-    + With FILO it works without further settings
-+ Temperature readings from the Super I/O (including the CPU temperature
-  via PECI)
-+ Super I/O EC automatic fan control
-+ S3 suspend/resume
-+ Poweroff
-
-### Not working
-
-+ DDR3 memory with 512Mx8 chips (G43 limitation)
-+ 4x4GB of DDR3 memory (works, but showed a single bit error within one
-  pass of Memtest86+ 5.01)
-+ Super I/O voltage reading conversions
-
-### Untested
-
-+ Other audio jacks or the front panel header
-+ S/PDIF output
-+ On-board Firewire
-+ Wake-on-LAN
-
-## Flashing coreboot
-
-```eval_rst
-+-------------------+---------------------+
-| Type              | Value               |
-+===================+=====================+
-| Socketed flash    | No                  |
-+-------------------+---------------------+
-| Model             | Macronix MX25L1605D |
-+-------------------+---------------------+
-| Size              | 2 MiB               |
-+-------------------+---------------------+
-| Package           | 8-Pin SOP           |
-+-------------------+---------------------+
-| Write protection  | No                  |
-+-------------------+---------------------+
-| Dual BIOS feature | No                  |
-+-------------------+---------------------+
-| Internal flashing | Yes                 |
-+-------------------+---------------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-```
-00000000:00001fff fd
-00100000:001fffff bios
-00006000:000fffff me
-00002000:00005fff gbe
-```
-
-In general, flashing is possible internally and from an external header. It
-might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E`
-is the correct one, not `MX25L1605`.
-
-### Internal flashing
-
-Internal access to the flash chip is unrestricted. When installing coreboot,
-only the BIOS region should be updated by passing the `--ifd` and `-i bios`
-parameters to flashrom. A full backup is advisable.
-
-Here is an example:
-
-```
-$ sudo flashrom \
-  -p internal \
-  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
-  -r backup.rom
-$ sudo flashrom \
-  -p internal \
-  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
-  --ifd -i bios \
-  -w coreboot.rom
-```
-
-```eval_rst
-In addition to the information here, please see the
-:doc:`../../flash_tutorial/index`.
-```
-
-### External flashing
-
-The SPI flash chip on this board can be flashed externally through the
-SPI_ROM1 header while the board is off and disconnected from power. There
-seems to be a diode that prevents the external programmer from powering the
-whole board.
-
-The signal assigment on the header is identical to the pinout of the flash
-chip. The pinout diagram below is valid when the PCI slots are on the left
-and the CPU is on the right. Note that HOLD# and WP# must be pulled high
-(to VCC) to be able to flash the chip.
-
-                +---+---+
-     SPI_CSn <- | x | x | -> VCC
-                +---+---+
-    SPI_MISO <- | x | x | -> HOLDn
-                +---+---+
-         WPn <- | x | x | -> SPI_CLK
-                +---+---+
-         GND <- | x | x | -> SPI_MOSI
-                +---+---+
-
-## Intel Management Engine
-
-The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE
-jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash
-Descriptor Security Override Strap" to be set. This disables the ME and also
-disables any read/write restrictions to the flash chip that may be set in the
-Intel Flash Descriptor (IFD) (none on this board). Note that changing this
-jumper only comes into effect when starting the board from a shutdown or
-suspend state, not during normal operation.
-
-To completely remove the ME blob from the flash image and to decrease the size
-of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can
-be used with the `-t`, `-r` and `-S` options.
-
-## Fan control
-
-There are two fan connectors that can be controlled individually. CPU_FAN
-can only control a fan by a PWM signal and SYS_FAN only by voltage. See
-the mainboard's `devicetree.cb` file for how coreboot configures the Super
-I/O to control the fans.
-
-## Variants
-
-Various similar mainboards exist, like the Acer Q45T-AM. During a discussion
-in #coreboot on IRC, ECS was suspected to be the original designer of this
-series of mainboards. They have similar models such as the ECS G43T-WM.

Documentation/mainboard/asrock/h77pro4-m.md

@@ -1,174 +0,0 @@
-# ASRock H77 Pro4-M
-
-The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy
-Bridge and Ivy Bridge CPUs.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel H77 (bd82x6x)                              |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 1155                                         |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1600                                    |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6776                                  |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC892                                   |
-+------------------+--------------------------------------------------+
-| Network          | Realtek RTL8111E                                 |
-+------------------+--------------------------------------------------+
-| Serial           | Internal header (RS-232)                         |
-+------------------+--------------------------------------------------+
-```
-
-## Status
-
-Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
-(linux-4.19.50).
-
-### Working
-
-- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
-- Native RAM initialization with four DIMMs
-- PS/2 combined port (mouse or keyboard)
-- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
-- PCIe graphics in the PEG slot
-- All three additional PCIe slots
-- All rear and internal USB2 ports
-- All rear and internal USB3 ports
-- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
-- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
-- Rear eSATA connector (multiplexed with one ASM1061 port)
-- Gigabit Ethernet
-- Console output on the serial port
-- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
-extlinux
-- Internal flashing with flashrom-1.2, see
-[Internal Programming](#internal-programming)
-- External flashing with flashrom-1.2 and a Raspberry Pi 1
-- S3 suspend/resume from either Linux or Windows 10
-- Poweroff
-
-### Not working
-
-- Booting from the two SATA ports provided by the ASM1061
-- Automatic fan control with the NCT6776D Super I/O
-
-### Untested
-
-- EHCI debug
-- S/PDIF audio
-- Other audio jacks than the green one, and the front panel header
-- Parallel port
-- Infrared/CIR
-- Wakeup from anything but the power button
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | yes        |
-+---------------------+------------+
-| Model               | W25Q64.V   |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | DIP-8      |
-+---------------------+------------+
-| Write protection    | no         |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-```
-00000000:00000fff fd
-00200000:007fffff bios
-00001000:001fffff me
-```
-
-### Internal programming
-
-The main SPI flash can be accessed using flashrom. By default, only
-the BIOS region of the flash is writable. If you wish to change any
-other region (Management Engine or flash descriptor), then an external
-programmer is required.
-
-The following command may be used to flash coreboot:
-
-```
-$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
-```
-
-The use of `--noverify-all` is required since the Management Engine
-region is not readable even by the host.
-
-```eval_rst
-In addition to the information here, please see the
-:doc:`../../flash_tutorial/index`.
-```
-
-## Hardware monitoring and fan control
-
-There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share
-a single fan tachometer input on the Super I/O while some dedicated logic
-selects which one is allowed to reach it. Two GPIO pins on the Super I/O are
-used to control that logic. The firmware has to set them; coreboot selects
-CPU_FAN1 by default, but the user can change that setting if it was built with
-CONFIG_USE_OPTION_TABLE:
-
-```
-$ sudo nvramtool -e cpu_fan_header
-[..]
-$ sudo nvramtool -w cpu_fan_header=CPU_FAN2
-$ sudo nvramtool -w cpu_fan_header=None
-$ sudo nvramtool -w cpu_fan_header=Both
-```
-
-The setting will take effect after a reboot. Selecting and connecting both fan
-headers is possible but the Super I/O will report wrong fan speeds.
-
-Currently there is no automatic, OS-independent fan control, but a software
-like `fancontrol` from the lm-sensors package can be used instead.
-
-## Serial port header
-
-Serial port 1, provided by the Super I/O, is exposed on a pin header. The
-RS-232 signals are assigned to the header so that its pin numbers map directly
-to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
-work, check if your bracket expects a different assignment. Also don't try to
-connect it directly to a device that operates at TTL levels - it would need a
-level converter like a MAX232.
-
-Here is a top view of the serial port header found on this board:
-
-                 +---+---+
-             N/C |   | 9 | RI  -> pin 9
-                 +---+---+
-    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
-                 +---+---+
-    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
-                 +---+---+
-    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
-                 +---+---+
-    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
-                 +---+---+
-
-## eSATA
-
-The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share
-the same controller port on the ASM1061. Attaching an eSATA drive causes a
-multiplexer chip to disconnect the internal port from the SATA controller and
-connect the eSATA port instead. This can be seen on GP23 of the Super I/O
-GPIOs: it is '0' when something is connected to the eSATA port and '1'
-otherwise.

Documentation/mainboard/emulation/qemu-power9.md

@@ -1,52 +0,0 @@
-# QEMU PPC64 emulator
-This page describes how to build and run coreboot for QEMU/PPC64.
-
-## Building coreboot
-```bash
-make defconfig KBUILD_DEFCONFIG=configs/config.emulation_qemu_power9
-make
-```
-
-This builds coreboot with no payload.
-
-## Payloads
-You can configure ELF or `skiboot` payload via `make menuconfig`. In either case
-you might need to adjust "ROM chip size" and make it large enough to accommodate
-the payload (see how much space it needs in the error you get if it doesn't
-fit).
-
-## Running coreboot in QEMU
-```bash
-qemu-system-ppc64 -M powernv,hb-mode=on \
-                  -cpu power9 \
-                  -bios build/coreboot.rom \
-                  -drive file=build/coreboot.rom,if=mtd \
-                  -serial stdio \
-                  -display none
-```
-
-- The default CPU in QEMU for AArch64 is a 604. You specify a suitable
-PowerPC CPU via `-cpu power9`.
-- By default Hostboot mode is off and needs to be turned on to run coreboot
-as a firmware rather than like an OS.
-- `-bios` specifies initial program (bootloader should suffice, but whole image
-works fine too).
-- `-drive` specifies image for emulated flash device.
-
-## Running with a kernel
-Loading `skiboot` (built automatically by coreboot or otherwise) allows
-specifying kernel and root file system to be run.
-
-```bash
-qemu-system-ppc64 -M powernv,hb-mode=on \
-                  -cpu power9 \
-                  -bios build/coreboot.rom \
-                  -drive file=build/coreboot.rom,if=mtd \
-                  -serial stdio \
-                  -display none \
-                  -kernel zImage \
-                  -initrd initrd.cpio.xz
-```
-
-- Specify path to your kernel via `-kernel`.
-- Specify path to your rootfs via `-initrd`.

Documentation/mainboard/facebook/fbg1701.md

@@ -5,7 +5,10 @@ This page describes how to run coreboot on the Facebook FBG1701.
 FBG1701 are assembled with different onboard memory modules:
 	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
 	Rev 1.1 and 1.2	Onboard Micron MT41K512M16HA-125A memory
-	Rev 1.3 and 1.4 Onboard Kingston B5116ECMDXGGB memory
+	Rev 1.3	Onboard Kingston B5116ECMDXGGB memory
+
+Use make menuconfig to configure `onboard memory manufacturer Samsung` in
+Mainboard menu.
 
 ## Required blobs
 

Documentation/mainboard/index.md

@@ -6,16 +6,11 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [X210](51nb/x210.md)
 
-## Acer
-
-- [G43T-AM3](acer/g43t-am3.md)
-
 ## AMD
 - [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
-- [H77 Pro4-M](asrock/h77pro4-m.md)
 - [H81M-HDS](asrock/h81m-hds.md)
 - [H110M-DVS](asrock/h110m-dvs.md)
 
@@ -177,10 +172,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
 
-## Star Labs Systems
-
-- [StarBook Mk V](starlabs/starbook_tgl.md)
-
 ## Supermicro
 
 - [X10SLM+-F](supermicro/x10slm-f.md)
@@ -197,7 +188,6 @@ The boards in this section are not real mainboards, but emulators.
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Gazelle 15](system76/gaze15.md)
-- [Gazelle 16](system76/gaze16.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Oryx Pro 5](system76/oryp5.md)

Documentation/mainboard/ocp/deltalake.md

@@ -7,16 +7,7 @@ Delta Lake server platform.
 
 OCP Delta Lake server platform is a component of multi-host server system
 Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design
-spec] were [OCP] accepted.
-
-On the other hand, Wiwynn's Yosemite-V3 system and Delta Lake server product
-along with its OSF implementation, which is based on FSP/coreboot/LinuxBoot
-stack, was [OCP] accepted; For details, check:
-- [The OCP blog]
-- [The Wiwynn Press Release]
-- [The Wiwynn's Yosemite-V3 product in OCP market place]
-Wiwynn and 9Elements formed a partnership to offer the Wiwynn's Yosemite-V3
-product and OSF for it.
+spec] were contributed to [OCP].
 
 Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
 Intel Cooper Lake Scalable Processor was launched in Q2 2020.
@@ -24,7 +15,7 @@ Intel Cooper Lake Scalable Processor was launched in Q2 2020.
 Yosemite-V3 has multiple configurations. Depending on configurations, it may
 host up to 4 Delta Lake servers (blades) in one sled.
 
-The Yosemite-V3 system is in mass production. Meta, Intel and partners
+The Yosemite-V3 system is in mass production. Facebook, Intel and partners
 jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
 solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
 OSF solution reached production quality for some use cases in July, 2021.
@@ -196,9 +187,6 @@ and [u-root] as initramfs.
 [OCP]: https://www.opencompute.org
 [Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specification-1v05-pdf
 [Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf
-[The OCP blog]: https://www.opencompute.org/blog/open-system-firmware-for-ocp-server-deltalake-is-published
-[The Wiwynn Press Release]: https://www.prnewswire.com/news-releases/wiwynn-successfully-implemented-open-system-firmware-on-its-ocp-yosemite-v3-server-301417374.html?tc=eml_cleartime
-[The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server
 [osf-builder]: https://github.com/facebookincubator/osf-builder
 [OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -1,154 +0,0 @@
-# StarBook Mk V
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-1165G7 (Tiger Lake)
-    - Intel i3-1110G4 (Tiger Lake)
-- EC
-    - ITE IT5570E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel® Iris® Xe Graphics
-    - GOP driver is recommended, VBT is provided
-    - eDP 14-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 2 x DDR4 SODIMM
-- Networking
-    - AX201 2230 WiFi / Bluetooth
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - Thunderbolt 4.0 (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-    - USB 2.0 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 16 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-#### **Requirements:**
-
-* fwupd version 1.5.6 or later
-* The battery must be charged to at least 30%
-* The charger must be connected (either USB-C or DC Jack)
-* BIOS Lock must be disabled
-* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)
-
-**fwupd 1.5.6 or later**
-To check the version of **fwupd** you have installed, open a terminal window and enter the below command:
-
-```
-fwupdmgr --version
-```
-
-This will show the version number. **1.5.6** or greater will work.
-![fwupd version](fwupdVersion.png)
-On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
-
-```
-sudo add-apt-repository ppa:starlabs/ppa
-sudo apt update
-sudo apt install fwupd
-```
-
-On Manjaro:
-
-```
-sudo pacman -Sy fwupd-git flashrom-starlabs
-```
-
-Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.
-
-**Disable BIOS Lock**
-BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:
-
-1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
-2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
-3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
-
-![Disable BIOS Lock](BiosLock.jpg)
-
-4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
-
-#### **Switching Branch**
-
-Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
-
-First, check for new firmware files with the below terminal command:
-
-```
-fwupdmgr refresh --force
-```
-
-Then, to change branch, enter the below terminal command:
-
-```
-fwupdmgr switch-branch
-```
-
-You can then select which branch you would like to use, by typing in the corresponding number:
-![Switch Branch](SwitchBranch.png)
-You will be prompted to confirm, press `y` to continue or `n` to cancel.
-
-Once the switch has been completed, you will be prompted to restart.
-
-The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.
-
-You can switch branch at any time.

Documentation/mainboard/system76/gaze16.md

@@ -1,87 +0,0 @@
-# System76 Gazelle 16 (gaze16)
-
-## Specs
-
-- CPU
-  - Intel Core i7-11800H
-- Chipset
-  - Intel HM570
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options
-    - NVIDIA GeForce RTX 3050
-    - NVIDIA GeForce RTX 3050 Ti
-    - NVIDIA GeForce RTX 3060
-  - eDP displays
-    - 15.6" 1920x1080@144Hz LCD (AUO B156HAN08.4)
-    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
-  - External outputs
-    - RTX 3050/3050 Ti
-      - 1x HDMI
-      - 1x Mini DisplayPort 1.4
-    - RTX 3060
-      - 1x HDMI
-      - 1x Mini DisplayPort 1.2
-      - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-    - Either onboard Intel I219-V or Realtek RTL8111H controller
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6 AX200/AX201
-- Power
-  - RTX 3050/3050 Ti
-    - 150W AC barrel adapter
-      - Included: Chicony A17-150P2A, using a C5 power cord
-  - RTX 3060
-    - 180W AC barrel adapter
-      - Included: Chicony A17-180P4A, using a C5 power cord
-  - 48.96Wh 4-cell battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 1x M.2 PCIe NVMe Gen 4 SSD
-  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - SD card reader
-    - Realtek RTS5227S on RTX 3050/3050 Ti models
-    - Realtek OZ711LV2 on RTX 3060 models
-- USB
-  - 1x USB 3.2 Gen 2 Type-C
-    - Supports DisplayPort over USB-C on RTX 3060 models only
-    - Does not support USB-C charging (USB-PD) or Thunderbolt
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 3.2 Gen 1 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
-  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B127D           |
-+---------------------+---------------------+
-| Size                | 16 MiB              |
-+---------------------+---------------------+
-| Package             | SOIC-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U51 on 3050 variant, U52 on 3060 variant) is left of the top DIMM slot.

Documentation/mainboard/system76/oryp8.md

@@ -10,14 +10,14 @@
   - ITE IT570E running [System76 EC](https://github.com/system76/ec)
 - Graphics
   - dGPU options
-    - NVIDIA GeForce RTX 3070
-    - NVIDIA GeForce RTX 3080
+    - NVIDIA GeForce RTX 3070 (Max-Q)
+    - NVIDIA GeForce RTX 3080 (Max-Q)
   - eDP options
-    - 15.6" 1920x1080@144Hz LCD
-    - 17.3" 1920x1080@144Hz LCD
-  - 1x HDMI
-  - 1x Mini DisplayPort
-  - 1x DisplayPort over USB-C
+    - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
+    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
 - Memory
   - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
 - Networking
@@ -26,13 +26,13 @@
     - Intel Wi-Fi 6 AX200/AX201
 - Power
   - 180W (19.5V, 9.23A) AC barrel adapter
-    - Lite-On PA-1181-16
+    - Lite-On PA-1181-16, using a C5 power cord
   - 73Wh 3-cell battery
 - Sound
   - Realtek ALC1220 codec
   - TI TAS5825M smart amp
   - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
+  - Combined 3.5mm headphone & microphone jack
   - Combined 3.5mm microphone & S/PDIF jack
   - HDMI, mDP, USB-C DP audio
 - Storage
@@ -41,6 +41,9 @@
 - USB
   - 1x USB Type-C with Thunderbolt 4
   - 3x USB 3.0 Type-A
+- Dimensions
+  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
+  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
 
 ## Flashing coreboot
 

Documentation/releases/coreboot-4.14-relnotes.md

@@ -142,7 +142,7 @@ primarily to serve the needs of the server market.
 
 coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
 This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
+generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
 or the latest generation [2] on market.
 
 With this release, the codebase for multiple generations of Xeon-SP

Documentation/releases/coreboot-4.15-relnotes.md

@@ -1,7 +1,7 @@
-coreboot 4.15
+Upcoming release - coreboot 4.15
 ================================
 
-coreboot 4.15 was released on November 5th, 2021.
+The 4.15 release is planned for November 5th, 2021.
 
 Since 4.14 there have been more than 2597 new commits by more than 219 developers.
 Of these, over 73 contributed to coreboot for the first time.

Documentation/releases/coreboot-4.16-relnotes.md

@@ -1,340 +1,19 @@
-coreboot 4.16
-========================================================================
+Upcoming release - coreboot 4.16
+================================
 
-The 4.16 release was done on February 25th, 2022.
+The 4.16 release is planned for Februrary, 2022. 
 
-Since 4.15 there have been more than 1770 new commits by more than 170
-developers.  Of these, more than 35 contributed to coreboot for the
-first time.
+We are increasing the frequency of releases in order to enable others to release quarterly on
+a fresher version of coreboot.
 
-Welcome to the project!
+Update this document with changes that should be in the release notes.
 
-Thank you to all the developers who continue to make coreboot the
-great open source firmware project that it is.
-
-New mainboards:
----------------
-* Acer Aspire VN7-572G
-* AMD Chausie
-* ASROCK H77 Pro4-M
-* ASUS P8Z77-M
-* Emulation QEMU power9
-* Google Agah
-* Google Anahera4ES
-* Google Banshee
-* Google Beadrix
-* Google Brya4ES
-* Google Crota
-* Google Dojo
-* Google Gimble4ES
-* Google Herobrine_Rev0
-* Google Kingler
-* Google Kinox
-* Google Krabby
-* Google Moli
-* Google Nereid
-* Google Nivviks
-* Google Primus4ES
-* Google Redrix4ES
-* Google Skyrim
-* Google Taeko4ES
-* Google Taniks
-* Google Vell
-* Google Volmar
-* Intel Alderlake-N RVP
-* Prodrive Atlas
-* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
-* System76 gaze16 3050
-* System76 gaze16 3060
-* System76 gaze16 3060-b
-
-Removed mainboards:
--------------------
-* Google ->  Corsola
-* Google ->  Nasher
-* Google ->  Stryke
-
-Added processors:
------------------
-* src/cpu/power9
-* src/soc/amd/sabrina
-
-Submodule Updates
------------------
-* /3rdparty/amd_blobs (6 commits)
-* /3rdparty/arm-trusted-firmware (965 commits)
-* /3rdparty/blobs (30 commits)
-* /3rdparty/chromeec (2212 commits)
-* /3rdparty/intel-microcode (1 commits)
-* /3rdparty/qc_blobs (13 commits)
-* /3rdparty/vboot (44 commits)
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the v4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the v4
-allocator.
-
-Plans for Code Deprecation
---------------------------
-As of release 4.18 (November 2022) we plan to deprecate LEGACY_SMP_INIT.
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-A few things are lacking in PARALLEL_MP init:
-- Support for !CONFIG_SMP on single core systems. It's likely easy to
-  extend PARALLEL_MP or write some code that just does CPU detection on
-  the BSP CPU.
-- Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC
-  showed that it's not that hard to do with PARALLEL_MP
-  https://review.coreboot.org/c/coreboot/+/58700
-
-No platforms in the tree have any hardware limitations that would block
-migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
 
 Significant changes
 -------------------
-This is, of course, not a complete list of all changes in the 4.16
-coreboot release, but a sampling of some of the more interesting and
-significant changes.
 
-### Option to disable Intel Management Engine
-Disable the Intel (Converged Security) Management Engine ((CS)ME) via
-HECI based on Intel Core processors from Skylake to Alder Lake. State is
-set based on a CMOS value of `me_state`. A value of `0` will result in a
-(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
-state of `3` (disabled). For an example CMOS layout and more info, see
-[cse.c](../../src/soc/intel/common/block/cse/cse.c).
-
-
-### Add [AMD] apcb_v3_edit tool
-apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
-up to 16 SPDs into an existing APCB. The APCB must have a magic number
-at the top of each SPD slot.
-
-
-### Allow enable/disable ME via CMOS
-Add .enable method that will set the CSME state. The state is based on
-the new CMOS option me_state, with values of 0 and 1. The method is very
-stable when switching between different firmware platforms.
-
-This method should not be used in combination with USE_ME_CLEANER.
-
-State 1 will result in:
-ME: Current Working State   : 4
-ME: Current Operation State : 1
-ME: Current Operation Mode  : 3
-ME: Error Code              : 2
-
-State 0 will result in:
-ME: Current Working State   : 5
-ME: Current Operation State : 1
-ME: Current Operation Mode  : 0
-ME: Error Code              : 0
-
-
-### Move LAPIC configuration to MP init
-Implementation for setup_lapic() did two things -- call enable_lapic()
-and virtual_wire_mode_init().
-
-In PARALLEL_MP case enable_lapic() was redundant as it was already
-executed prior to initialize_cpu() call.  For the !PARALLEL_MP case
-enable_lapic() is added to AP CPUs.
-
-
-### Add ANSI escape sequences for highlighting
-Add ANSI escape sequences to highlight a log line based on its loglevel
-to the output of "interactive" consoles that are meant to be displayed
-on a terminal (e.g. UART). This should help make errors and warnings
-stand out better among the usual spew of debug messages. For users whose
-terminal or use case doesn't support these sequences for some reason (or
-who simply don't like them), they can be disabled with a Kconfig.
-
-While ANSI escape sequences can be used to add color, minicom (the
-presumably most common terminal emulator for UART endpoints?) doesn't
-support color output unless explicitly enabled (via -c command line
-flag), and other terminal emulators may have similar restrictions, so in
-an effort to make this as widely useful by default as possible I have
-chosen not to use color codes and implement this highlighting via
-bolding, underlining and inverting alone (which seem to go through in
-all cases). If desired, support for separate color highlighting could be
-added via Kconfig later.
-
-
-### Add cbmem_dump_console
-This function is similar to cbmem_dump_console_to_uart except it uses
-the normally configured consoles. A console_paused flag was added to
-prevent the cbmem console from writing to itself.
-
-
-### Add coreboot-configurator
-A simple GUI to change CMOS settings in coreboot's CBFS, via the
-nvramtool utility.  Testing on Debian, Ubuntu and Manjaro with coreboot
-4.14+, but should work with any distribution or coreboot release that
-has an option table. For more info, please check the
-[README](https://web.archive.org/web/20220225194308/https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/coreboot-configurator/README.md).
-
-
-### Update live ISO configs to NixOS 21.11
-Update configs so that they work with NixOS 21.11. Drop `iasl` package
-since it was replaced with `acpica-tools`.
-
-
-### Move to U-Boot v2021.10
-Move to building the latest U-Boot.
-
-
-### Support systems with >128 cores
-Each time the spinlock is acquired a byte is decreased and then the
-sign of the byte is checked. If there are more than 128 cores the sign
-check will overflow. An easy fix is to increase the word size of the
-spinlock acquiring and releasing.
-
-
-### Add [samsung] sx9360 [proximity sensor] driver
-Add driver for setting up Semtech sx9360 SAR sensor.
-The driver is based on sx9310.c. The core of the driver is the same, but
-the bindings are slightly different.
-
-Registers are documented [in the kernel tree:](https://web.archive.org/web/20220225182803/https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/)
-Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
-
-
-### Add driver for Genesys Logic [SD Controller] GL9750
-The device is a PCIe Gen1 to SD 3.0 card reader controller to be
-used in the Chromebook. The datasheet name is GL9750S and the revision
-is 01.
-
-The patch disables ASPM L0s.
-
-
-### Add support for Realtek RT8125
-The Realtek RT8168 and RT8125 have a similar programming interface,
-therefore add the PCI device ID for the RT8125 into driver for support.
-
-
-### Add Fibocom 5G WWAN ACPI support
-Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
-PXSX._RST is invoked on driver removal.
-
-build dependency:
-  soc/intel/common/block/pcie/rtd3
-
-This driver will use the rtd3 methods for the same parent in the device
-tree. The rtd3 chip needs to be added on the same root port in the
-devicetree separately.
-
-
-### Fix bug in vr_config
-The `cpu_get_power_max()` function returns the TDP in milliwatts, but
-the vr_config code interprets the value in watts. Divide the value by
-1000 to fix this.
-
-This also fixes an integer overflow when `cpu_get_power_max()` returns
-a value greater than 65535 (UINT16_MAX).
-
-
-### Make mixed topology work
-When using a mixed memory topology with DDR4, it's not possible to boot
-when no DIMMs are installed, even though memory-down is available. This
-happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
-available. Relax the length check when no DIMMs are present to overcome
-this problem.
-
-
-### Add FSP 2.3 support
-FSP 2.3 specification introduces following changes:
-
-1. FSP_INFO_HEADER changes
-   Updated SpecVersion from 0x22 to 0x23
-   Updated HeaderRevision from 5 to 6
-   Added ExtendedImageRevision
-   FSP_INFO_HEADER length changed to 0x50
-
-2. Added FSP_NON_VOLATILE_STORAGE_HOB2
-
-Following changes are implemented in the patch to support FSP 2.3:
-
-- Add Kconfig option
-- Update FSP build binary version info based on ExtendedImageRevision
-  field in header
-- New NV HOB related changes will be pushed as part of another patch
-
-
-### Join hash calculation for verification and measurement
-This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
-is enabled from the lookup step into the code where a file is actually
-loaded or mapped from flash. This has the advantage that CBFS routines
-which just look up a file to inspect its metadata (e.g. cbfs_get_size())
-do not cause the file to be measured twice. It also removes the existing
-inefficiency that files are loaded twice when measurement is enabled
-(once to measure and then again when they are used). When CBFS
-verification is enabled and uses the same hash algorithm as the TPM, we
-are even able to only hash the file a single time and use the result for
-both purposes.
-
-
-### Skip FSP Notify APIs
-Alder Lake SoC deselects Kconfigs as below:
-- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
-- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
-to skip FSP notify APIs (Ready to boot and End of Firmware) and make
-use of native coreboot driver to perform SoC recommended operations
-prior booting to payload/OS.
-
-Additionally, created a helper function `heci_finalize()` to keep HECI
-related operations separated for easy guarding again config.
-
-TODO: coreboot native implementation to skip FSP notify phase API (post
-pci enumeration) is still WIP.
-
-
-### Add support for PCIe Resizable BARs
-Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
-indicates support for "Resizable BARs" via a PCIe extended capability.
-
-When support this capability is indicated by the device, the size of
-each BAR is determined in a different way than the normal "moving
-bits" method. Instead, a pair of capability and control registers is
-allocated in config space for each BAR, which can be used to both
-indicate the different sizes the device is capable of supporting for
-the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
-to also inform the device of the size that the allocator actually
-reserved for the MMIO range.
-
-This patch adds a Kconfig for a mainboard to select if it knows that it
-will have a device that requires this support during PCI enumeration.
-If so, there is a corresponding Kconfig to indicate the maximum number
-of bits of address space to hand out to devices this way (again, limited
-by what devices can support and each individual system may want to
-support, but just like above, this number can range from 20 to 63) If
-the device can support more bits than this Kconfig, the resource request
-is truncated to the number indicated by this Kconfig.
+### Add significant changes here

Documentation/releases/coreboot-4.17-relnotes.md

@@ -1,19 +0,0 @@
-Upcoming release - coreboot 4.17
-================================
-
-The 4.17 release is planned for May, 2022.
-
-We are continuing the quarterly release cadence in order to enable others to
-release quarterly on a fresher version of coreboot.
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-
-Significant changes
--------------------
-
-### Add significant changes here

Documentation/releases/index.md

@@ -16,7 +16,6 @@ Release notes for previous releases
 * [4.13 - November 2020](coreboot-4.13-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)
-* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -24,13 +23,8 @@ names etc.
 
 * [checklist](checklist.md)
 
-For release related communications consider using a template so everything
-important is taken care of.
-
-* [templates](templates.md)
-
 Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.17 - May 2022](coreboot-4.17-relnotes.md)
+* [4.16 - May 2022](coreboot-4.16-relnotes.md)

Documentation/releases/templates.md

@@ -1,83 +0,0 @@
-# Communication templates related to release management
-
-## Deprecation notices
-
-Deprecation notices are part of release notes to act as a warning: at some
-point in the future some part of coreboot gets removed. That point must be
-at least 6 months after the release of the notice and it must be right after
-some release: That is, the specified release must still contain the part in
-question while one git commit later it might be removed.
-
-The usual reason is progress: Infrastructure module X has been replaced by
-infrastructure module X+1. Removing X helps keep the sources manageable
-and likely opens opportunities to improve the codebase even more.
-Sometimes everything using some module has been converted to its successor
-already and it's natural for such modules to be removed. Even then it might
-be useful to add an entry to the release notes to make everybody aware of
-such a change, for maintainers of incomplete boards that they might keep in
-their local trees and also to give credit to the developers of that change.
-
-However this template isn't about such cases. Sometimes the tree contains
-mainboards that rely on X and can't be easily migrated to X+1, often because
-no active developer has access to these mainboards, and that is where this
-type of deprecation notice comes in:
-
-A deprecation notice shall outline what is being removed, when it is planned
-for removal (always directly _after_ a future release so it remains clear when
-something is part of coreboot and when it isn't anymore) and which devices
-would be affected at the time of writing. Since past deprecation notices have
-been read as "we plan to remove mainboards A, B, and C", sparking outrage
-with the devoted users of A, B, or C, some care is necessary to make clear
-which parts are slated for removal and which parts are merely consequences
-if no action is taken. Or put differently: It should be obvious that besides
-the deprecation plan, there is a call to action to save a couple of devices
-from becoming officially unsupported.
-
-As such, consider the following template when announcing a deprecation:
-
-### The Thing to remove
-
-A short description of the Thing slated for removal.
-
-A short rationale why it's being removed (e.g. new and better Thing exists
-in parallel; new Thing already demonstrated to work in this many releases;
-removing Thing enables this or that improvement)
-
-Timeline: Announced here, Thing will be removed right after the release X
-months out (where X >= 6)
-
-#### Call to action
-
-Removing Thing requires work on a number of (boards, chipsets, …) that didn't
-make the switch yet. The work approximately looks like this: (e.g. pointers to
-commits where a board has been successfully migrated from Thing to new Thing).
-
-Working on migrating away from Thing involves (hardware components, coreboot
-systems, …) 1, 2, and 3. It's difficult to do on the remaining devices because
-...
-
-Parts of the tree that need work to become independent of Thing.
- - chipset A
-   - board A1
-   - board A2
- - chipset B
-   - board B1
-
-We prefer to move them along, but if we don't see any maintenance in our tree
-we'll have to assume that there's no more interest in these platforms. As a
-consequence these devices either have to work without Thing by the removal
-date or they will be removed together with Thing. (side note: these removals
-aren't the law, so if there's work in progress to move boards off X and a
-roadmap that makes it probable to succeed, just not within the announced
-deprecation timeline, we can still decide to postpone the actual removal by
-one release. This needn't be put in the release notes themselves though or
-it might encourage people to look for simple escape hatches.)
-
-(If there are developers offering to write patches: )
-There are developers interested in helping move these forward but they can't
-test any changes for lack of equipment. If you have an affected device and
-can run tests on it, please reach out to developers α, β, and γ.
-
-(Otherwise maybe something more generic like this: )
-If you want to take this on, the coreboot developer community will try to
-help you: Reach out through one of our [forums](../community/forums.md).

Documentation/security/vboot/list_vboot.md

@@ -1,7 +1,6 @@
 # vboot-enabled devices
 
 ## AMD
-- Chausie
 - Majolica
 
 ## Clevo
@@ -30,37 +29,9 @@
 - Panther (ASUS Chromebox CN60)
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
-- Agah
-- Anahera
-- Anahera4ES
-- Brask
-- Brya 0
-- Brya4ES
-- Felwinter
-- Gimble
-- Gimble4ES
-- Kano
-- Nivviks
-- Nereid
-- Primus
-- Primus4ES
-- Redrix
-- Redrix4ES
-- Taeko
-- Taeko4ES
-- Taniks
-- Vell
-- Volmar
-- Banshee
-- Crota
-- Moli
-- Kinox
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
-- Dojo
 - Tomato
-- Kingler
-- Krabby
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -99,31 +70,31 @@
 - Nipperkin
 - Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
-- Ambassador
-- Dooly
 - Dratini (HP Pro c640 Chromebook)
 - Duffy Legacy (32MB)
 - Duffy (ASUS Chromebox 4)
 - Faffy (ASUS Fanless Chromebox)
-- Genesis
 - Hatch
-- Helios (ASUS Chromebook Flip C436FA)
-- Helios_Diskswap
 - Jinlon (HP Elite c1030 Chromebook)
 - Kaisa Legacy (32MB)
 - Kaisa (Acer Chromebox CXI4)
-- Kindred (Acer Chromebook 712)
 - Kohaku (Samsung Galaxy Chromebook)
-- Moonbuggy
+- Kindred (Acer Chromebook 712)
+- Helios (ASUS Chromebook Flip C436FA)
 - Mushu
+- Palkia
 - Nightfury (Samsung Galaxy Chromebook 2)
 - Noibat (HP Chromebox G3)
-- Palkia
 - Puff
-- Scout
+- Helios_Diskswap
+- Stryke
 - Wyvern (CTL Chromebox CBx2)
+- Dooly
+- Ambassador
+- Genesis
+- Scout
+- Moonbuggy
 - Herobrine
-- Herobrine_Rev0
 - Senor
 - Piglin
 - Hoglin
@@ -194,6 +165,7 @@
 - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
+- Nasher
 - Coral
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
@@ -243,8 +215,6 @@
 - Alderlake-P RVP with Microchip EC
 - Alderlake-M RVP
 - Alderlake-M RVP with Chrome EC
-- Alderlake-N RVP
-- Alderlake-N RVP with Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11

Documentation/soc/intel/fsp/index.md

@@ -2,18 +2,6 @@
 
 This section contains documentation about Intel-FSP in public domain.
 
-## Integration Guidelines
-
-Some guiding principles when working on the glue to integrate FSP into
-coreboot, e.g. on how to configure a board in devicetree when that affects
-the way FSP works:
-
-* It should be possible to replace FSP based boot with a native coreboot
-  implementation for a given chipset without touching the mainboard code.
-* The devicetree configures coreboot and part of what coreboot does with the
-  information is setting some FSP UPDs. The devicetree isn't supposed to
-  directly configure FSP.
-
 ## Bugs
 As Intel doesn't even list known bugs, they are collected here until
 those are fixed. If possible a workaround is described here as well.

Documentation/superio/nuvoton/nct5539d.md

@@ -1,9 +1,9 @@
-# NCT5539D Super I/O
+# NCT5539D SuperIO
 
-The Super I/O has the ID `0xd121` and the source can be found in
+The SuperIO has the ID `0xd121` and the source can be found in
 `src/superio/nuvoton/nct5539d/`.
 
 ## For developers
 
-The Super I/O generates ACPI using the
+The SuperIO generates ACPI using the
 [SSDT generator for generic SuperIOs](../common/ssdt.md).

Documentation/tutorial/part2.md

@@ -12,24 +12,37 @@ select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your
 username for the account will be the username of the account you used to
 sign-in with. (ex. your Google username).
 
-## Step 2a: Set up SSH keys
+## Step 2a: Set up RSA Private/Public Key
 
 If you prefer to use an HTTP password instead, skip to Step 2b.
 
-If you do not have an SSH key set up on your account already (as is the case
+For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
+<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh>
+and follow the instructions there. Then, skip to Step 3.
+
+Additionally, that section of the Web site provides explanation on starting
+an ssh-agent, which may be particularly helpful for those who anticipate
+frequently uploading changes.
+
+If you instead prefer to have review.coreboot.org specific instructions,
+follow the steps below. Note that this particular section may have the
+most up-to-date instructions.
+
+If you do not have an RSA key set up on your account already (as is the case
 with a newly created account), follow the instructions below; otherwise,
 doing so could overwrite an existing key.
 
-In a terminal, run `ssh-keygen -t ed25519` and confirm the default path
-`.ssh/id_ed25519`.
+In the upper right corner, select your name and click on **Settings**.
+Select **SSH Public Keys** on the left-hand side.
+
+In a terminal, run `ssh-keygen` and confirm the default path `.ssh/id_rsa`.
 
 Make a passphrase -- remember this phrase. It will be needed whenever you use
-this public key. **Note:** You might want to use a short password, or
+this RSA Public Key. **Note:** You might want to use a short password, or
 forego the password altogether as you will be using it very often.
 
-Copy the content of `.ssh/id_ed25519.pub` (notice the ".pub" suffix
-as you need to send the public key) into the textbox "New SSH Key" at
-https://review.coreboot.org/settings/#SSHKeys and save it.
+Open `id_rsa.pub`, copy all contents and paste into the textbox under
+"Add SSH Public Key" in the https://review.coreboot.org webpage.
 
 ## Step 2b: Set up an HTTP Password
 
@@ -160,9 +173,7 @@ When you are done with your commit, run `git push` to push your commit to
 coreboot.org. **Note:** To submit as a private patch, use
 `git push origin HEAD:refs/for/master%private`. Submitting as a private patch
 means that your commit will be on review.coreboot.org, but is only visible to
-yourself and those you add as reviewers. This mode isn't perfect: Somebody who
-knows the commit ID can still fetch the change and everything it refers (e.g.
-parent commits).
+yourself and those you add as reviewers.
 
 This has been a quick primer on how to submit a change to Gerrit for review
 using git. You may wish to review the [Gerrit code review workflow

Documentation/util.md

@@ -12,8 +12,6 @@ settings. `Perl`
 * __apcb__ - AMD PSP Control Block tools
 	* _apcb_edit.py_ - This tool allows patching an existing APCB
 binary with specific SPDs and GPIO selection pins. `Python3`
-	* _apcb_v3_edit.py_ - This tool allows patching an existing APCB V3
-binary with specific SPDs. `Python3`
 * __archive__ - Concatenate files and create an archive `C`
 * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
 platforms `Go`

MAINTAINERS

@@ -141,9 +141,7 @@ AMD family 17h and 19h reference boards
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
-F:	src/mainboard/amd/chausie/
 F:	src/mainboard/amd/majolica/
 F:	src/mainboard/amd/mandolin/
 
@@ -221,18 +219,25 @@ F:	src/mainboard/clevo/
 
 FACEBOOK FBG1701 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/facebook/fbg1701/
 
 FACEBOOK MONOLITH MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/facebook/monolith/
 
 
 
+GETAC P470 MAINBOARD
+M:	Patrick Georgi <patrick@georgi.software>
+S:	Maintained
+F:	src/mainboard/getac/p470/
+
+
+
 GIGABYTE GA-D510UD MAINBOARD
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
@@ -396,7 +401,7 @@ F:	src/mainboard/pcengines/
 
 PORTWELL PQ-M107 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/portwell/m107/
 
@@ -446,13 +451,6 @@ F:	src/mainboard/siemens/mc_apl1/
 
 
 
-STAR LABS MAINBOARDS
-M:	Sean Rhodes <sean@starlabs.systems>
-S:	Maintained
-F:	src/mainboard/starlabs/
-
-
-
 SYSTEM76 MAINBOARDS
 M:	Jeremy Soller <jeremy@system76.com>
 M:	Tim Crawford <tcrawford@system76.com>
@@ -525,11 +523,6 @@ M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
 F:	src/ec/lenovo/
 
-STARLABS EC
-M:	Sean Rhodes <sean@starlabs.systems>
-S:	Maintained
-F:	src/ec/starlabs/
-
 SYSTEM76 EC
 M:	Jeremy Soller <jeremy@system76.com>
 M:	Tim Crawford <tcrawford@system76.com>
@@ -614,7 +607,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
@@ -624,7 +616,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/common/
 
@@ -633,21 +624,10 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
 
-AMD Sabrina
-M:	Marshall Dawson <marshalldawson3rd@gmail.com>
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-S:	Maintained
-F:	src/soc/amd/sabrina/
-F:	src/vendorcode/amd/fsp/sabrina/
-
 AMD Stoneyridge
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
@@ -739,6 +719,7 @@ F:	payloads/external/LinuxBoot/
 ################################################################################
 
 ABUILD
+M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	util/abuild/
@@ -747,6 +728,7 @@ BOARD STATUS
 F:	util/board_status/
 
 BUILD SYSTEM
+M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	Makefile
@@ -770,6 +752,7 @@ F:	.git*
 F:	/util/gitconfig
 
 LINT SCRIPTS
+M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	util/lint/
@@ -893,7 +876,7 @@ F:	*.ld
 
 ELTAN VENDORCODE
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/vendorcode/eltan/
 
@@ -907,7 +890,6 @@ TESTS
 M:	Jakub Czapiga <jacz@semihalf.com>
 S:	Maintained
 F:	tests/
-F:	payloads/libpayload/tests/
 
 MISSING: TIMERS / DELAYS
 
@@ -945,6 +927,7 @@ MISSING: SPI
 
 CODE OF CONDUCT
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
+M:	Patrick Georgi <patrick@coreboot.org>
 M:	Ronald Minnich <rminnich@coreboot.org>
 M:	Martin Roth <martin@coreboot.org>
 S:	Maintained

Makefile

@@ -20,6 +20,17 @@ VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib)
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
 COREBOOT_EXPORTS += top src srck obj objutil objk
 
+# reproducible builds
+LANG:=C
+LC_ALL:=C
+TZ:=UTC0
+ifneq ($(NOCOMPILE),1)
+SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
+endif
+# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
+# are reproducible
+export LANG LC_ALL TZ SOURCE_DATE_EPOCH
+
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
 KCONFIG_AUTOADS := $(obj)/cb-config.ads
@@ -52,7 +63,6 @@ ifneq ($(V),1)
 ifneq ($(Q),)
 .SILENT:
 MAKEFLAGS += -s
-quiet_errors := 2>/dev/null
 endif
 endif
 
@@ -165,17 +175,6 @@ $(error $(xcompile) deleted because it's invalid. \
 	Restarting the build should fix that, or explain the problem)
 endif
 
-# reproducible builds
-LANG:=C
-LC_ALL:=C
-TZ:=UTC0
-ifneq ($(NOCOMPILE),1)
-SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
-endif
-# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
-# are reproducible
-export LANG LC_ALL TZ SOURCE_DATE_EPOCH
-
 ifneq ($(CONFIG_MMX),y)
 CFLAGS_x86_32 += -mno-mmx
 endif

Makefile.inc

@@ -189,29 +189,29 @@ ramstage-generic-ccopts += -D__RAMSTAGE__
 ifeq ($(CONFIG_COVERAGE),y)
 ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
 endif
+
 ifneq ($(UPDATED_SUBMODULES),1)
 # try to fetch non-optional submodules if the source is under git
-forgetthis:=$(if $(GIT),$(shell git submodule update --init $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init))
 # Checkout Cmocka repository
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka))
 ifeq ($(CONFIG_USE_BLOBS),y)
 # These items are necessary because each has update=none in .gitmodules.  They are ignored
 # until expressly requested and enabled with --checkout
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors)))
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
 ifeq ($(CONFIG_FSP_USE_REPO),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
 endif
 ifeq ($(CONFIG_USE_AMD_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
 endif
 ifeq ($(CONFIG_USE_QC_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs))
 endif
 endif
 UPDATED_SUBMODULES:=1
 COREBOOT_EXPORTS += UPDATED_SUBMODULES
-
 endif
 
 postcar-c-deps:=$$(OPTION_TABLE_H)
@@ -263,24 +263,15 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
 # Redundant offset remarks are not useful in any way and are masking useful
 # ones that might indicate an issue so it is better to hide them.
 REDUNDANT_OFFSET_REMARK = 2158
-# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
-#	1) If _PRS is present, must have _CRS and _SRS
-#	2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
-#	3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
-#	4) If _SRS is present, probably should have a _DIS (Remark only)
-# A warning will be issued for each of these cases.
-# For existing ASL code, ignore this warnings
-IASL_MISSING_DEPENDENCY = 3141
+# Ignore _HID & _ADR coexisting in Intel Lynxpoint ASL code.
+# See cb:38802
+# "Multiple types (Device object requires either a _HID or _ADR, but not both)"
+MULTIPLE_TYPES_WARNING = 3073
 
 IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)
 
-ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
-	IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
-build_complete::
-	printf "*** WARNING: The ASL code for this platform is incomplete.  Please fix it. ***\n"
-	printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
-	printf "*** If _SRS is present, must have _PRS, _CRS, and _SRS ***\n"
-	printf "*** If _DIS is present, must have _SRS, _PRS, _CRS, and _SRS ***\n"
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
+IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING)
 endif
 
 IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
@@ -289,9 +280,6 @@ define asl_template
 $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
 $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw
 $(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-$(CONFIG_CBFS_PREFIX)/$(1).aml-align = 64
-endif
 cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml
 -include $(obj)/$(1).d
 $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
@@ -453,7 +441,6 @@ ADAFLAGS_common += -pipe -g -nostdinc
 ADAFLAGS_common += -Wstrict-aliasing -Wshadow
 ADAFLAGS_common += -fno-common -fomit-frame-pointer
 ADAFLAGS_common += -ffunction-sections -fdata-sections
-ADAFLAGS_common += -fno-pie
 # Ada warning options:
 #
 #  a   Activate most optional warnings.
@@ -601,8 +588,6 @@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
 
 APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
-APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
-
 CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
 
 FUTILITY?=$(objutil)/futility/futility
@@ -1229,10 +1214,6 @@ cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
 $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
 $(CONFIG_CBFS_PREFIX)/ramstage-type := stage
 $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-$(CONFIG_CBFS_PREFIX)/ramstage-align := 64
-endif
 
 cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
 $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)

configs/config.emulation_qemu_power9

@@ -1 +0,0 @@
-CONFIG_BOARD_EMULATION_QEMU_POWER9=y

configs/config.emulation_qemu_x86_i440fx_debug

@@ -8,4 +8,3 @@ CONFIG_DEBUG_PIRQ=y
 CONFIG_DEBUG_MALLOC=y
 CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
-CONFIG_CPU_QEMU_X86_PARALLEL_MP=y

configs/config.facebook_fbg1701.mboot_vboot

@@ -1,5 +1,6 @@
 CONFIG_VENDOR_FACEBOOK=y
 CONFIG_BOARD_FACEBOOK_FBG1701=y
+CONFIG_ONBOARD_SAMSUNG_MEM=y
 CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04"

configs/config.google_trogdor.build_test

@@ -1,8 +0,0 @@
-# Config to build test some optional Kconfigs on an Arm platform
-CONFIG_USE_BLOBS=y
-CONFIG_USE_QC_BLOBS=y
-CONFIG_VENDOR_GOOGLE=y
-CONFIG_BOARD_GOOGLE_TROGDOR=y
-CONFIG_CBFS_VERIFICATION=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_PAYLOAD_NONE=y

configs/config.google_volteer.build_test_purposes

@@ -30,4 +30,3 @@ CONFIG_DEBUG_MALLOC=y
 CONFIG_DEBUG_CONSOLE_INIT=y
 CONFIG_DEBUG_SPI_FLASH=y
 CONFIG_DEBUG_BOOT_STATE=y
-CONFIG_CBFS_VERIFICATION=y

configs/config.prodrive_hermes

@@ -1,13 +0,0 @@
-# Settings used by Prodrive to build coreboot for the Hermes
-CONFIG_VENDOR_PRODRIVE=y
-CONFIG_BOARD_PRODRIVE_HERMES=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Techonologies B.V."
-CONFIG_POST_IO=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-CONFIG_HERMES_USES_SPS_FIRMWARE=y
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_SMMSTORE=y
-CONFIG_SMMSTORE_V2=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
-CONFIG_POST_DEVICE_LPC=y
-CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"

payloads/Makefile.inc

@@ -28,7 +28,6 @@ payloads/external/tianocore \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
 payloads/external/Yabits \
-payloads/external/skiboot \
 
 force-payload:
 
@@ -49,16 +48,5 @@ distclean-payloads:
 print-repo-info-payloads:
 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
 
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-files_added:: warn_no_payload
-endif
-
-warn_no_payload:
-	printf "\n\t** WARNING **\n"
-	printf "coreboot has been built without a payload. Writing\n"
-	printf "a coreboot image without a payload to your board's\n"
-	printf "flash chip will result in a non-booting system. You\n"
-	printf "can use cbfstool to add a payload to the image.\n\n"
-
 .PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads

payloads/external/.gitignore

@@ -8,5 +8,3 @@ tint/tint/
 U-Boot/u-boot/
 Memtest86Plus/memtest86plus/
 iPXE/ipxe/
-skiboot/skiboot
-skiboot/build

payloads/external/Makefile.inc

@@ -136,29 +136,22 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
 
 # Tianocore
 
-$(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
+payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/tianocore all \
 		HOSTCC="$(HOSTCC)" \
 		CC="$(HOSTCC)" \
-		CONFIG_TIANOCORE_REPOSITORY=$(CONFIG_TIANOCORE_REPOSITORY) \
-		CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \
+		CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
+		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
+		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
+		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
-		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
-		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
-		CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \
+		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
 		CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
-		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-		CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
-		CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
-		CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
-		CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
-		CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
-		CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
+		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
 		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
-		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -168,7 +161,6 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 		OBJCOPY_arm=$(OBJCOPY_arm) \
 		OBJCOPY_arm64=$(OBJCOPY_arm64) \
 		MFLAGS= MAKEFLAGS=
-	mv payloads/external/tianocore/output/UEFIPAYLOAD.fd $@
 
 # FILO
 
@@ -205,9 +197,8 @@ payloads/external/GRUB2/grub2/build/default_payload.elf: grub2
 
 # U-Boot
 
-payloads/external/U-Boot/build/u-boot.bin u-boot: $(DOTCONFIG)
+payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/U-Boot \
-			STABLE_COMMIT_ID=$(CONFIG_UBOOT_STABLE_COMMIT_ID) \
 			CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \
 			CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE)
 
@@ -340,10 +331,3 @@ payloads/external/Yabits/uefi/build/uefi.elf yabits:
 
 payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf:
 	$(MAKE) -C payloads/external/BOOTBOOT all
-
-# skiboot
-
-payloads/external/skiboot/build/skiboot.elf:
-	$(MAKE) -C payloads/external/skiboot all \
-		CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
-		CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)

payloads/external/U-Boot/Kconfig

@@ -3,18 +3,13 @@ if PAYLOAD_UBOOT
 config PAYLOAD_SPECIFIC_OPTIONS
 	def_bool y
 	select PAYLOAD_IS_FLAT_BINARY
-	select WANT_LINEAR_FRAMEBUFFER
-
-config UBOOT_STABLE_COMMIT_ID
-	string
-	default "v2021.07"
 
 choice
 	prompt "U-Boot version"
 	default UBOOT_STABLE
 
 config UBOOT_STABLE
-	bool "v2021.07"
+	bool "v2019.4"
 	help
 	  Stable U-Boot version
 
@@ -37,9 +32,9 @@ config PAYLOAD_CONFIGFILE
 	  from the U-Boot config directory
 
 config PAYLOAD_FILE
-	default "payloads/external/U-Boot/build/u-boot.bin"
+	default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin"
 
 config PAYLOAD_OPTIONS
-	default "-l 0x1110000 -e 0x1110000"
+	default "-l 0x1110000 -e 0x1110015"
 
 endif

payloads/external/U-Boot/Makefile

@@ -1,15 +1,15 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+# 2019-4 tag
+STABLE_COMMIT_ID=3c99166441bf3ea325af2da83cfe65430b49c066
+
 TAG-$(CONFIG_UBOOT_MASTER)=origin/master
 TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
 
 project_name=U-Boot
 project_dir=u-boot
 project_git_repo=http://git.denx.de/u-boot.git
-project_build_dir=build
-project_config_file=$(project_build_dir)/.config
-
-make_args=-C $(project_dir) O=../build
+project_config_file=$(project_dir)/.config
 
 unexport KCONFIG_AUTOHEADER
 unexport KCONFIG_AUTOCONFIG
@@ -23,7 +23,7 @@ all: build
 
 $(project_dir):
 	echo "    Cloning $(project_name) from Git"
-	git clone $(project_git_repo) -b $(TAG-y) $(project_dir)
+	git clone $(project_git_repo) $(project_dir)
 
 fetch: $(project_dir)
 ifeq ($(CONFIG_UBOOT_MASTER),y)
@@ -31,11 +31,11 @@ ifeq ($(CONFIG_UBOOT_MASTER),y)
 	git fetch
 
 	#master doesn't get a file, so it's continuously updated
-	rm -f $(STABLE_COMMIT_ID)
+	rm -f $(project_dir)/$(STABLE_COMMIT_ID)
 else
 	cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ]; \
 	then echo "    Fetching new commits from the $(project_name) git repo"; git fetch; fi
-	touch $(STABLE_COMMIT_ID)
+	touch $(project_dir)/$(STABLE_COMMIT_ID)
 endif
 
 checkout: fetch
@@ -43,26 +43,26 @@ checkout: fetch
 	cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
 
 config: checkout
-	mkdir -p $(project_build_dir)
 	rm -f $(project_config_file)
 ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),)
 ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","")
 	cat $(CONFIG_PAYLOAD_CONFIGFILE)" > tag-$(project_config_file)
-	$(MAKE) $(make_args) olddefconfig
 else
 	echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist"
 	false
 endif
 else
-	$(MAKE) $(make_args) coreboot_defconfig
+	cat $(project_dir)/configs/coreboot_defconfig >> $(project_config_file)
 endif
 
+	$(MAKE) -C $(project_dir) olddefconfig
+
 build: config
 	echo "    MAKE       $(project_name) $(TAG-y)"
-	$(MAKE) $(make_args)
+	$(MAKE) -C $(project_dir)
 
 clean:
-	test -d $(project_dir) && $(MAKE) $(make_args) clean || exit 0
+	test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0
 
 distclean:
 	rm -rf $(project_dir)

payloads/external/skiboot/Kconfig

@@ -1,21 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-if PAYLOAD_SKIBOOT
-
-config PAYLOAD_FILE
-	default "payloads/external/skiboot/build/skiboot.elf"
-
-config SKIBOOT_GIT_REPO
-	string "Git repository of skiboot payload"
-	default "https://github.com/open-power/skiboot"
-	help
-	  Git repository which will be used to clone skiboot.
-
-config SKIBOOT_REVISION
-	string "Revision of skiboot payload"
-	default "d93ddbd39b4eeac0bc11dacbdadea76df2996c13" if BOARD_EMULATION_QEMU_POWER9
-	help
-	  Revision, that skiboot repository will be checked out to, before building
-	  an image.
-
-endif # PAYLOAD_SKIBOOT

payloads/external/skiboot/Kconfig.name

@@ -1,8 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config PAYLOAD_SKIBOOT
-	bool "skiboot"
-	depends on ARCH_PPC64
-	help
-	  Select this option if you want to build a coreboot image
-	  with a skiboot payload.

payloads/external/skiboot/Makefile

@@ -1,36 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-build_dir=$(CURDIR)/build
-skiboot_dir=$(CURDIR)/skiboot
-skiboot_git_repo=$(CONFIG_SKIBOOT_GIT_REPO)
-skiboot_revision=$(CONFIG_SKIBOOT_REVISION)
-skiboot_elf=$(build_dir)/skiboot.elf
-skiboot_cross=$(or $(CROSS),powerpc64-linux-gnu-)
-
-unexport $(COREBOOT_EXPORTS)
-
-.PHONY: all clean distclean
-
-all: $(skiboot_elf)
-
-$(skiboot_elf): | $(skiboot_dir) $(build_dir)
-	+$(MAKE) -C $(skiboot_dir) CROSS="$(skiboot_cross)"
-	cp $(skiboot_dir)/skiboot.elf $@
-	# skiboot is always built with debug information due to unconditional -ggdb
-	$(skiboot_cross)strip $@
-
-$(skiboot_dir):
-	git clone $(skiboot_git_repo) $(skiboot_dir)
-	git -C $(skiboot_dir) checkout $(skiboot_revision)
-
-$(build_dir):
-	mkdir -p $(build_dir)
-
-distclean: clean
-	rm -rf $(skiboot_dir)
-
-clean:
-	# Redefine RM because it's used like `$(RM) non-existent-file`
-	# Also ignore useless messages about removing test files
-	[ ! -d $(skiboot_dir) ] || $(MAKE) -C $(skiboot_dir) RM="rm -rf" clean > /dev/null
-	rm -rf $(build_dir)

payloads/external/tianocore/Kconfig

@@ -2,7 +2,7 @@ if PAYLOAD_TIANOCORE
 
 config PAYLOAD_FILE
 	string "Tianocore binary"
-	default "$(obj)/UEFIPAYLOAD.fd"
+	default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd"
 	help
 	  The result of a UefiPayloadPkg build
 
@@ -35,30 +35,13 @@ config TIANOCORE_COREBOOTPAYLOAD
 	  Select this option to build using MrChromebox's older (now deprecated)
 	  CorebootPayloadPkg-based Tianocore branch
 
-config TIANOCORE_CUSTOM
-	bool "Custom"
-	help
-	  Specify your own edk2 repository and branch to use.
-
 endchoice
 
-config TIANOCORE_REPOSITORY
-	string "URL to git repository for edk2"
-	default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM
-	default "https://github.com/mrchromebox/edk2" if TIANOCORE_UEFIPAYLOAD || TIANOCORE_COREBOOTPAYLOAD
-	help
-	  coreboot supports an array of build options which can be found below. These options
-	  will only have an effect if the relevant options exist in the target repository.
-
-config TIANOCORE_TAG_OR_REV
+config TIANOCORE_REVISION_ID
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD
-	default "origin/master" if TIANOCORE_UPSTREAM
-	default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD
 	help
-	  The commit's SHA-1 or branch name of the revision to use. This must exist in
-	  TIANOCORE_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
-	  "origin/uefipayload_202202"
+	   The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master"
+	   for master branch of Tianocore release on github.
 
 choice
 	prompt "Tianocore build"
@@ -81,33 +64,32 @@ endchoice
 
 if TIANOCORE_UEFIPAYLOAD
 
-config TIANOCORE_ABOVE_4G_MEMORY
-	bool "Enable above 4G memory"
-	default n
+config TIANOCORE_CBMEM_LOGGING
+	bool "Enable Tianocore logging to CBMEM"
 	help
-	  Select this option to enable Above 4G Decode. This will allow the
-	  payload to use all of the memory, rather than an maximum of 4G.
+	  Select this option if you want to enable Tianocore logging to CBMEM.
+	  You may want to increase the default cbmem buffer size when selecting
+	  this option, especially if using a debug (vs release) build.
+	  Selecting this option will increase the payload size in CBFS by ~220KB.
 
-	  Disabling memory above 4G is useful for bootloaders that are not
-	  fully 64-bit aware such as Qubes R4.0.4 bootloader.
-
-
-config TIANOCORE_BOOTSPLASH_FILE
-	string "Tianocore Bootsplash path and filename"
-	default "bootsplash.bmp"
+config TIANOCORE_BOOTSPLASH_IMAGE
+	bool "Use a custom bootsplash image"
 	help
 	  Select this option if you have a bootsplash image that you would
 	  like to be used. If this option is not selected, the default
 	  coreboot logo (European Brown Hare) will used.
 
+config TIANOCORE_BOOTSPLASH_FILE
+	string "Tianocore Bootsplash path and filename"
+	depends on TIANOCORE_BOOTSPLASH_IMAGE
+	default "bootsplash.bmp"
+	help
 	  The path and filename of the file to use as graphical bootsplash
-	  image. The file must be an uncompressed BMP, in BMP 3 format.
-
-	  Linux can create these with the below command:
-	      `convert splosh.bmp BMP3:splash.bmp`
+	  image. The file must be an uncompressed BMP.
 
 	  This image will also be used as the BGRT boot image, which may
-	  persist through your OS boot process.
+	  persist through your OS boot process, and will be displayed
+	  vertically centered 38.2% from the top of the display.
 
 	  See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and
 	  Microsoft's documentation on BGRT positioning:
@@ -119,61 +101,16 @@ config TIANOCORE_BOOTSPLASH_FILE
 	  If an absolute path is not given, the path will assumed to be
 	  relative to the coreboot root directory.
 
-config TIANOCORE_BOOT_MANAGER_ESCAPE
-	bool "Use Escape key for Boot Manager"
+config TIANOCORE_ABOVE_4G_MEMORY
+	bool "Enable above 4G memory"
 	default n
 	help
-	  Use Escape as the hot-key to access the Boot Manager. This replaces
-	  the default key of F2.
+	  Select this option to enable Above 4G Decode. This will allow the
+	  payload to use all of the memory, rather than an maximum of 4G.
 
-config TIANOCORE_BOOT_TIMEOUT
-	int
-	default 2
-	help
-	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
-	  For boards with an internal display, the default value of 2s is generally sufficient.
-	  For boards with an external display, a value of 5s is generally sufficient.
-
-config TIANOCORE_CBMEM_LOGGING
-	bool "Enable Tianocore logging to CBMEM"
-	help
-	  Select this option if you want to enable Tianocore logging to CBMEM.
-	  You may want to increase the default cbmem buffer size when selecting
-	  this option, especially if using a debug (vs release) build.
-	  Selecting this option will increase the payload size in CBFS by 0x10000.
-
-config TIANOCORE_FOLLOW_BGRT_SPEC
-	bool "Center logo 38.2% from the top of screen"
-	default n
-	help
-	  Follow the BGRT Specification implemented by Microsoft and
-	  the Boot Logo 38.2% will be vertically centered 38.2% from
-	  the top of the display.
-
-config TIANOCORE_HAVE_EFI_SHELL
-	bool "Include EFI Shell"
-	default y
-	help
-	  Include the EFI shell Binary
-
-config TIANOCORE_PRIORITIZE_INTERNAL
-	bool "Prioritize internal boot devices"
-	default y
-	help
-	  Prioritize internal boot devices over external devices
-
-config TIANOCORE_PS2_SUPPORT
-	bool "Support PS/2 Keyboards"
-	default y
-	help
-	  Include support for PS/2 keyboards
-
-config TIANOCORE_SD_MMC_TIMEOUT
-	int "Timeout in μs for initializing SD Card reader"
-	default 1000
-	help
-	  The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
-	  Most only require 1000μs, but certain readers can take 1000000μs.
+	  Disabling this option, which will reserve memory above 4G, is
+	  useful for bootloaders that are not fully 64-bit aware such as
+	  Qubes R4.0.4 bootloader.
 
 endif
 
@@ -186,4 +123,12 @@ config TIANOCORE_USE_8254_TIMER
 
 endif
 
+config TIANOCORE_BOOT_TIMEOUT
+	int
+	default 2
+	help
+	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
+	  For boards with an internal display, the default value of 2s is generally sufficient.
+	  For boards without an internal display, a value of 5s is generally sufficient.
+
 endif

payloads/external/tianocore/Makefile

@@ -3,112 +3,84 @@
 # force the shell to bash - the edksetup.sh script doesn't work with dash
 export SHELL := env bash
 
-project_name = Tianocore
-project_dir = $(CURDIR)/$(word 3,$(subst /, ,$(CONFIG_TIANOCORE_REPOSITORY)))
+project_name=Tianocore
+project_dir=$(CURDIR)/tianocore
+project_git_repo=https://github.com/mrchromebox/edk2
+project_git_branch=uefipayload_202107
+upstream_git_repo=https://github.com/tianocore/edk2
+
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
 
-BUILD_STR = -a IA32 -a X64 -t COREBOOT
 ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
-BUILD_STR += -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+project_git_branch=coreboot_fb
+bootloader=CorebootPayloadPkg
 else
-BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
-endif
-BUILD_STR += -D BOOTLOADER=COREBOOT -q
-
-#
-# EDK II has the following build options relevant to coreboot:
-#
-#
-# OPTION			= DEFAULT_VALUE
-#
-# ABOVE_4G_MEMORY		= TRUE
-ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
-BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
-endif
-# BOOTSPLASH_IMAGE		= FALSE
-ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),)
-BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
-endif
-# BOOT_MANAGER_ESCAPE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y)
-BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE
-endif
-# BUILD_TARGETS			= DEBUG
-ifeq ($(CONFIG_TIANOCORE_RELEASE),y)
-BUILD_STR += -b RELEASE
-endif
-# FOLLOW_BGRT_SPEC		= FALSE
-ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
-BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
-endif
-# PRIORITIZE_INTERNAL		= FALSE
-ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
-BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
-endif
-# PS2_KEYBOARD_ENABLE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
-BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
-endif
-# PLATFORM_BOOT_TIMEOUT		= 3
-ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
-BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
-endif
-# SIO_BUS_ENABLE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
-BUILD_STR += -D SIO_BUS_ENABLE=TRUE
-endif
-# SHELL_TYPE			= BUILD_SHELL
-ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y)
-BUILD_STR += -D SHELL_TYPE=NONE
-endif
-# USE_CBMEM_FOR_CONSOLE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
-BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
-endif
-# SD_MMC_TIMEOUT		= 1000000
-ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
-BUILD_STR += -D SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT)
-endif
-#
-# The below are legacy options only available in CorebootPayloadPkg:
-#
-# PCIE_BASE			= 0
-ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),)
-BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
-endif
-# USE_HPET_TIMER		= FALSE
-ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y)
-BUILD_STR += -D USE_HPET_TIMER=TRUE
+bootloader=UefiPayloadPkg
 endif
 
-bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
+ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y)
+TAG=upstream/master
+else
+TAG=origin/$(project_git_branch)
+endif
+
+ifneq ($(CONFIG_TIANOCORE_REVISION_ID),)
+TAG=$(CONFIG_TIANOCORE_REVISION_ID)
+endif
 
 export EDK_TOOLS_PATH=$(project_dir)/BaseTools
 
+ifeq ($(CONFIG_TIANOCORE_DEBUG),y)
+BUILD_TYPE=DEBUG
+else
+BUILD_TYPE=RELEASE
+endif
+
+ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
+CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE
+endif
+
+ifeq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
+4G=-D ABOVE_4G_MEMORY=TRUE
+else
+4G=-D ABOVE_4G_MEMORY=FALSE
+endif
+
+TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
+
+ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
+TIMER=-DUSE_HPET_TIMER
+endif
+
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE
+else
+BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G)
+endif
+
 all: clean build
 
 $(project_dir):
-	echo "    Cloning $(project_name) from $(CONFIG_TIANOCORE_REPOSITORY)"
-	git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
-		cd $(project_dir);
+	echo "    Cloning $(project_name) from Git"
+	git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \
+		cd $(project_dir); \
+		git remote add upstream $(upstream_git_repo)
 
 update: $(project_dir)
-	if [ ! -d "$(project_dir)" ]; then \
-		git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
-	fi
 	cd  $(project_dir); \
-		echo "    Fetching new commits from $(CONFIG_TIANOCORE_REPOSITORY)"; \
-		git fetch origin 2>/dev/null; \
-		if ! git rev-parse --verify -q $(CONFIG_TIANOCORE_TAG_OR_REV) >/dev/null; then \
-			echo "    $(CONFIG_TIANOCORE_TAG_OR_REV) is not a valid git reference"; \
+		echo "    Fetching new commits from the $(project_name) repo"; \
+		git fetch --multiple origin upstream 2>/dev/null; \
+		if ! git rev-parse --verify -q $(TAG) >/dev/null; then \
+			echo "    $(TAG) is not a valid git reference"; \
 			exit 1; \
 		fi; \
 		if git status --ignore-submodules=dirty | grep -qv clean; then \
-			echo "    Checking out $(project_name) revision $(CONFIG_TIANOCORE_TAG_OR_REV)"; \
-			git checkout --detach $(CONFIG_TIANOCORE_TAG_OR_REV) -f; \
+			echo "    Checking out $(project_name) revision $(TAG)"; \
+			git checkout --detach $(TAG); \
 		else \
 			echo "    Working directory not clean; will not overwrite"; \
 		fi; \
-		git submodule update --init --checkout
+		git submodule update --init
 
 checktools:
 	echo "Checking uuid-dev..."
@@ -122,15 +94,15 @@ checktools:
 		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
 
 build: update checktools
-	unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
-	echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)"
+	unset CC; $(MAKE) -C $(project_dir)/BaseTools
+	echo " build $(project_name) $(TAG)"
 	if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
 		echo "    Copying custom bootsplash image"; \
 		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
-			/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
-			*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+			/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+				$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+			*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+				$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
 		esac \
 	fi; \
 	cd $(project_dir); \
@@ -142,14 +114,13 @@ build: update checktools
 			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
 		fi; \
 		build $(BUILD_STR); \
-		mkdir -p $(project_dir)/../output
-		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/../output/UEFIPAYLOAD.fd; \
+		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
 		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true
 
 clean:
 	test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
 
 distclean:
-	rm -rf */
+	rm -rf $(project_dir)
 
 .PHONY: all update checktools config build clean distclean

payloads/libpayload/Kconfig

@@ -208,7 +208,11 @@ config PDCURSES
 
 endchoice
 
-source "libcbfs/Kconfig"
+config CBFS
+	bool "CBFS support"
+	default y
+	help
+	  CBFS is the archive format of coreboot
 
 config LZMA
 	bool "LZMA decoder"
@@ -223,9 +227,6 @@ config LZ4
 	help
 	  Decoder implementation for the LZ4 compression algorithm.
 	  Adds standalone functions (CBFS support coming soon).
-
-source "vboot/Kconfig"
-
 endmenu
 
 menu "Console Options"

payloads/libpayload/Makefile

@@ -29,23 +29,16 @@
 ## SUCH DAMAGE.
 ##
 
-ifneq ($(words $(CURDIR)),1)
-	$(error ERROR: Path to the main directory cannot contain spaces)
-endif
-
 ifeq ($(INNER_SCANBUILD),y)
 CC_real:=$(CC)
 endif
 
 export top := $(CURDIR)
-export coreboottop ?= $(abspath $(top)/../../)
 export src := src
 export srck := $(abspath $(top)/../../util/kconfig)
 export obj ?= build
 export objutil ?= $(obj)/util
 export objk := $(objutil)/lp_kconfig
-export absobj := $(abspath $(obj))
-VBOOT_SOURCE ?= $(coreboottop)/3rdparty/vboot
 
 export KCONFIG_AUTOHEADER := $(obj)/config.h
 export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
@@ -296,11 +289,9 @@ includemakefiles= \
 		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(foreach class,$(classes), \
 		$(eval $(class)-srcs+= \
-			$$(subst $(absobj)/,$(obj)/, \
 			$$(subst $(top)/,, \
-			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
-	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
-
+			$$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \
+	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
 
 # For each path in $(subdirs) call includemakefiles
 # Repeat until subdirs is empty
@@ -319,15 +310,8 @@ else
 include $(TOPLEVEL)/tests/Makefile.inc
 endif
 
-# Converts one or more source file paths to the corresponding build/ paths.
-# $1 lib name
-# $2 file path (list)
-src-to-obj=\
-	$(addsuffix .$(1).o,\
-	$(basename \
-	$(addprefix $(obj)/,\
-	$(subst $(coreboottop)/,coreboot/,$(2)))))
-$(foreach class,$(classes),$(eval $(class)-objs+=$(call src-to-obj,$(class),$($(class)-srcs))))
+src-to-obj=$(addsuffix .$(1).o, $(basename $(addprefix $(obj)/, $($(1)-srcs))))
+$(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class))))
 
 allsrcs:=$(foreach var, $(addsuffix -srcs,$(classes)), $($(var)))
 allobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var)))
@@ -341,7 +325,7 @@ define create_cc_template
 # $4 additional dependencies
 ifn$(EMPTY)def $(1)-objs_$(2)_template
 de$(EMPTY)fine $(1)-objs_$(2)_template
-$$(call src-to-obj,$(1), $$(1).$(2)): $$(1).$(2) $(obj)/libpayload-config.h $(4)
+$(obj)/$$(1).$(1).o: $$(1).$(2) $(obj)/libpayload-config.h $(4)
 	@printf "    CC         $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$(CC) $(3) -MMD $$$$(CFLAGS) $(EXTRA_CFLAGS) -c -o $$$$@ $$$$<
 en$(EMPTY)def
@@ -356,7 +340,7 @@ $(foreach class,$(classes), \
 foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(basename $(file)))))
 $(eval $(foreach class,$(classes),$(call foreach-src,$(class))))
 
-DEPENDENCIES = $($(filter %.o,%(allobjs)):.o=.d)
+DEPENDENCIES = $(allobjs:.o=.d)
 -include $(DEPENDENCIES)
 
 printall:

payloads/libpayload/Makefile.inc

@@ -46,8 +46,6 @@ classes-$(CONFIG_LP_CBFS) += libcbfs
 classes-$(CONFIG_LP_LZMA) += liblzma
 classes-$(CONFIG_LP_LZ4) += liblz4
 classes-$(CONFIG_LP_REMOTEGDB) += libgdb
-classes-$(CONFIG_LP_VBOOT_LIB) += vboot_fw
-classes-$(CONFIG_LP_VBOOT_LIB) += tlcl
 libraries := $(classes-y)
 classes-y += head.o
 
@@ -57,12 +55,9 @@ subdirs-$(CONFIG_LP_CURSES) += curses
 subdirs-$(CONFIG_LP_CBFS) += libcbfs
 subdirs-$(CONFIG_LP_LZMA) += liblzma
 subdirs-$(CONFIG_LP_LZ4) += liblz4
-subdirs-$(CONFIG_LP_VBOOT_LIB) += vboot
 
 INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj)
 INCLUDES += -include include/kconfig.h -include include/compiler.h
-INCLUDES += -I$(coreboottop)/src/commonlib/bsd/include
-INCLUDES += -I$(VBOOT_SOURCE)/firmware/include
 
 CFLAGS += $(INCLUDES) -Os -pipe -nostdinc -ggdb3
 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
@@ -95,11 +90,11 @@ includes-handler= \
 
 $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs))
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
-	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
+	$(AR) rc $@ $^
 
 $(obj)/%.a: $$(%-objs)
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
-	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
+	$(AR) rc $@ $^
 
 $(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o
 	printf "    CP         $(subst $(CURDIR)/,,$(@))\n"
@@ -120,24 +115,10 @@ install: real-target
 		install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \
 		install -m 644 $$file $(DESTDIR)/libpayload/$$file; \
 	done
-	for file in `find $(coreboottop)/src/commonlib/bsd/include -name *.h -type f`; do \
-		dest_file=$$(realpath --relative-to=$(coreboottop)/src/commonlib/bsd/ $$file); \
-		install -m 755 -d "$(DESTDIR)/libpayload/`dirname $$dest_file`"; \
-		install -m 644 "$$file" "$(DESTDIR)/libpayload/$$dest_file"; \
-	done
 	install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include
 	$(foreach item,$(includes), \
 		install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \
 		install -m 644 $(call extract_nth,1,$(item)) $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); )
-	printf "    INSTALL    $(DESTDIR)/libpayload/vboot\n"
-	install -m 755 -d $(DESTDIR)/libpayload/vboot
-	for file in `find $(VBOOT_SOURCE)/firmware/include \
-			  $(VBOOT_SOURCE)/firmware/2lib/include \
-			  -iname '*.h' -type f \
-			  | sed 's,$(VBOOT_SOURCE)/firmware/,,'`; do \
-		install -m 755 -d $(DESTDIR)/libpayload/vboot/$$(dirname $$file); \
-		install -m 644 $(VBOOT_SOURCE)/firmware/$$file $(DESTDIR)/libpayload/vboot/$$file ; \
-	done
 	printf "    INSTALL    $(DESTDIR)/libpayload/bin\n"
 	install -m 755 -d $(DESTDIR)/libpayload/bin
 	install -m 755 bin/lpgcc $(DESTDIR)/libpayload/bin

payloads/libpayload/arch/mock/Makefile.inc

@@ -5,5 +5,3 @@ head.o-y += head.c
 libc-y += virtual.c
 
 libcbfs-$(CONFIG_LP_CBFS) += mock_media.c
-
-CFLAGS += -Wno-address-of-packed-member

payloads/libpayload/arch/x86/Makefile.inc

@@ -42,7 +42,6 @@ libc-$(CONFIG_LP_GPL) += string.c
 libgdb-y += gdb.c
 
 libcbfs-$(CONFIG_LP_CBFS) += rom_media.c
-libcbfs-$(CONFIG_LP_CBFS) += boot_media.c
 
 # Multiboot support is configurable
 libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c

payloads/libpayload/arch/x86/boot_media.c

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-
-#include <arch/virtual.h>
-#include <boot_device.h>
-#include <commonlib/bsd/cb_err.h>
-#include <stddef.h>
-#include <string.h>
-#include <sysinfo.h>
-
-__attribute__((weak)) ssize_t boot_device_read(void *buf, size_t offset, size_t size)
-{
-	/* Memory-mapping usually only works for the top 16MB. */
-	if (!lib_sysinfo.boot_media_size || lib_sysinfo.boot_media_size - offset > 16 * MiB)
-		return CB_ERR_ARG;
-	const void *const ptr = phys_to_virt(0 - lib_sysinfo.boot_media_size + offset);
-	memcpy(buf, ptr, size);
-	return size;
-}

payloads/libpayload/arch/x86/coreboot.c

@@ -47,12 +47,20 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info)
 	info->x86_rom_var_mtrr_index = rom_mtrr->index;
 }
 
+static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info)
+{
+	info->mrc_cache = get_cbmem_addr(ptr);
+}
+
 int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
 {
 	switch(rec->tag) {
 	case CB_TAG_X86_ROM_MTRR:
 		cb_parse_x86_rom_var_mtrr(rec, info);
 		break;
+	case CB_TAG_MRC_CACHE:
+		cb_parse_mrc_cache(rec, info);
+		break;
 	default:
 		return 0;
 	}

payloads/libpayload/bin/lp.functions

@@ -63,9 +63,3 @@ if [ -d $BASE/../include ]; then
 else
 	_INCDIR=$LIBPAYLOAD_PREFIX/include
 fi
-
-if [ -d $BASE/../vboot ]; then
-	_VBOOTINCDIR=$BASE/../vboot/include
-else
-	_VBOOTINCDIR=$LIBPAYLOAD_PREFIX/../vboot/include
-fi

payloads/libpayload/bin/lpgcc

@@ -167,11 +167,6 @@ if [ $_LIBDIR = $_OBJ ]; then
     if [ "$CONFIG_LP_TINYCURSES" = y ]; then
 	_CFLAGS="$_CFLAGS -I$BASE/../curses"
     fi
-
-    _CFLAGS="$_CFLAGS -I$BASE/../../../src/commonlib/bsd/include"
-    _CFLAGS="$_CFLAGS -I$BASE/../../../3rdparty/vboot/firmware/include"
-else
-    _CFLAGS="$_CFLAGS -I$_VBOOTINCDIR"
 fi
 
 # Check for the -fno-stack-protector silliness
@@ -182,7 +177,7 @@ trygccoption -fno-stack-protector
 _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
 _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
 
-_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections"
+_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static"
 
 if [ $DOLINK -eq 0 ]; then
     if [ $DEBUGME -eq 1 ]; then

payloads/libpayload/include/assert.h

@@ -29,17 +29,6 @@
 #include <stdlib.h>
 #include <stdio.h>
 
-#ifdef __TEST__
-
-/* CMocka function redefinition */
-void mock_assert(const int result, const char *const expression, const char *const file,
-		 const int line);
-
-#define MOCK_ASSERT(result, expression) mock_assert((result), (expression), __FILE__, __LINE__)
-#define assert(statement) MOCK_ASSERT(!!(statement), #statement)
-
-#else
-
 // assert's existence depends on NDEBUG state on _last_ inclusion of assert.h,
 // so don't guard this against double-includes.
 #ifdef NDEBUG
@@ -54,5 +43,3 @@ void mock_assert(const int result, const char *const expression, const char *con
 		abort();					\
 	}
 #endif
-
-#endif /* __TEST__ */

payloads/libpayload/include/boot_device.h

@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-
-#ifndef _BOOT_DEVICE_H
-#define _BOOT_DEVICE_H
-
-#include <stddef.h>
-
-/**
- * This is a boot device access function, which is used by libpayload to read data from
- * the flash memory (or other boot device). It has to be implemented by payloads that want
- * to use FMAP or libcbfs.
- *
- * @param buf The output buffer to which the data should be written to.
- * @param offset Absolute offset in bytes of the requested boot device memory area. Not aligned.
- * @param size Size in bytes of the requested boot device memory area. Not aligned.
- *
- * @returns Number of bytes returned to the buffer, or negative value on error. Typically should
- *          be equal to the `size`, and not aligned forcefully.
- */
-ssize_t boot_device_read(void *buf, size_t offset, size_t size);
-
-#endif /* _BOOT_DEVICE_H */

payloads/libpayload/include/cbfs.h

@@ -1,146 +1,82 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
 
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
-#include <commonlib/bsd/cb_err.h>
-#include <commonlib/bsd/cbfs_mdata.h>
-#include <endian.h>
-#include <stdbool.h>
+#include <cbfs_core.h>
 
+/* legacy APIs */
+const struct cbfs_header *get_cbfs_header(void);
+struct cbfs_file *cbfs_find(const char *name);
+void *cbfs_find_file(const char *name, int type);
 
-/**********************************************************************************************
- *                                  CBFS FILE ACCESS APIs                                     *
- **********************************************************************************************/
+int cbfs_execute_stage(struct cbfs_media *media, const char *name);
+void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
+			  uint16_t device);
+void *cbfs_load_payload(struct cbfs_media *media, const char *name);
+void *cbfs_load_stage(struct cbfs_media *media, const char *name);
 
-/* For documentation look in src/include/cbfs.h file in the main coreboot source tree. */
+/* Simple buffer for streaming media. */
+struct cbfs_simple_buffer {
+	char *buffer;
+	size_t allocated;
+	size_t size;
+	size_t last_allocate;
+};
 
-static inline size_t cbfs_load(const char *name, void *buf, size_t size);
-static inline size_t cbfs_ro_load(const char *name, void *buf, size_t size);
-static inline size_t cbfs_unverified_area_load(const char *area, const char *name, void *buf,
-					       size_t size);
+void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
+			     struct cbfs_media *media,
+			     size_t offset, size_t count);
 
-static inline void *cbfs_map(const char *name, size_t *size_out);
-static inline void *cbfs_ro_map(const char *name, size_t *size_out);
-static inline void *cbfs_unverified_area_map(const char *area, const char *name,
-					     size_t *size_out);
+void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer,
+			       const void *address);
 
-void cbfs_unmap(void *mapping);
+// Utility functions
+int run_address(void *f);
 
-static inline size_t cbfs_get_size(const char *name);
-static inline size_t cbfs_ro_get_size(const char *name);
-
-static inline enum cbfs_type cbfs_get_type(const char *name);
-static inline enum cbfs_type cbfs_ro_get_type(const char *name);
-
-static inline bool cbfs_file_exists(const char *name);
-static inline bool cbfs_ro_file_exists(const char *name);
-
-/**********************************************************************************************
- *                         INTERNAL HELPERS FOR INLINES, DO NOT USE.                          *
- **********************************************************************************************/
-ssize_t _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mdata);
-
-void *_cbfs_load(const char *name, void *buf, size_t *size_inout, bool force_ro);
-
-void *_cbfs_unverified_area_load(const char *area, const char *name, void *buf,
-				 size_t *size_inout);
-
-/**********************************************************************************************
- *                                  INLINE IMPLEMENTATIONS                                    *
- **********************************************************************************************/
-
-static inline void *cbfs_map(const char *name, size_t *size_out)
-{
-	return _cbfs_load(name, NULL, size_out, false);
-}
-
-static inline void *cbfs_ro_map(const char *name, size_t *size_out)
-{
-	return _cbfs_load(name, NULL, size_out, true);
-}
-
-static inline void *cbfs_unverified_area_map(const char *area, const char *name,
-					     size_t *size_out)
-{
-	return _cbfs_unverified_area_load(area, name, NULL, size_out);
-}
-
-static inline size_t cbfs_load(const char *name, void *buf, size_t size)
-{
-	if (_cbfs_load(name, buf, &size, false))
-		return size;
-	else
-		return 0;
-}
-
-static inline size_t cbfs_ro_load(const char *name, void *buf, size_t size)
-{
-	if (_cbfs_load(name, buf, &size, true))
-		return size;
-	else
-		return 0;
-}
-
-static inline size_t cbfs_unverified_area_load(const char *area, const char *name, void *buf,
-					       size_t size)
-{
-	if (_cbfs_unverified_area_load(area, name, buf, &size))
-		return size;
-	else
-		return 0;
-}
-
-static inline size_t cbfs_get_size(const char *name)
-{
-	union cbfs_mdata mdata;
-	if (_cbfs_boot_lookup(name, false, &mdata) < 0)
-		return 0;
-	else
-		return be32toh(mdata.h.len);
-}
-
-static inline size_t cbfs_ro_get_size(const char *name)
-{
-	union cbfs_mdata mdata;
-	if (_cbfs_boot_lookup(name, true, &mdata) < 0)
-		return 0;
-	else
-		return be32toh(mdata.h.len);
-}
-
-static inline enum cbfs_type cbfs_get_type(const char *name)
-{
-	union cbfs_mdata mdata;
-	if (_cbfs_boot_lookup(name, false, &mdata) < 0)
-		return CBFS_TYPE_NULL;
-	else
-		return be32toh(mdata.h.type);
-}
-
-static inline enum cbfs_type cbfs_ro_get_type(const char *name)
-{
-	union cbfs_mdata mdata;
-	if (_cbfs_boot_lookup(name, true, &mdata) < 0)
-		return CBFS_TYPE_NULL;
-	else
-		return be32toh(mdata.h.type);
-}
-
-static inline bool cbfs_file_exists(const char *name)
-{
-	union cbfs_mdata mdata;
-	return _cbfs_boot_lookup(name, false, &mdata) >= 0;
-}
-
-static inline bool cbfs_ro_file_exists(const char *name)
-{
-	union cbfs_mdata mdata;
-	return _cbfs_boot_lookup(name, true, &mdata) >= 0;
-}
-
-
-/* Legacy API. Designated for removal in the future. */
-#include <cbfs_legacy.h>
+/* Defined in individual arch / board implementation. */
+int init_default_cbfs_media(struct cbfs_media *media);
 
 #endif

payloads/libpayload/include/cbfs_core.h

@@ -45,14 +45,139 @@
 #ifndef _CBFS_CORE_H_
 #define _CBFS_CORE_H_
 
-#include <commonlib/bsd/cbfs_serialized.h>
 #include <endian.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <stdlib.h>
 
+/** These are standard values for the known compression
+    alogrithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+#define CBFS_COMPRESS_LZ4   2
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_SELF       0x20
+#define CBFS_TYPE_FIT        0x21
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_STRUCT     0x70
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
+
 #define CBFS_HEADER_INVALID_ADDRESS	((void*)(0xffffffff))
 
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+	uint32_t magic;
+	uint32_t version;
+	uint32_t romsize;
+	uint32_t bootblocksize;
+	uint32_t align; /* fixed to 64 bytes */
+	uint32_t offset;
+	uint32_t architecture;
+	uint32_t pad[1];
+} __packed;
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
+#define CBFS_ARCHITECTURE_ARM64    0x00000011
+
+/** This is a component header - every entry in the CBFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+	char magic[8];
+	uint32_t len;
+	uint32_t type;
+	uint32_t attributes_offset;
+	uint32_t offset;
+	char filename[];
+} __packed;
+
+/* Depending on how the header was initialized, it may be backed with 0x00 or
+ * 0xff. Support both. */
+#define CBFS_FILE_ATTR_TAG_UNUSED 0
+#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
+#define CBFS_FILE_ATTR_TAG_HASH 0x68736148
+#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */
+
+/* The common fields of extended cbfs file attributes.
+   Attributes are expected to start with tag/len, then append their
+   specific fields. */
+struct cbfs_file_attribute {
+	uint32_t tag;
+	/* len covers the whole structure, incl. tag and len */
+	uint32_t len;
+	uint8_t data[0];
+} __packed;
+
+struct cbfs_file_attr_compression {
+	uint32_t tag;
+	uint32_t len;
+	/* whole file compression format. 0 if no compression. */
+	uint32_t compression;
+	uint32_t decompressed_size;
+} __packed;
+
+struct cbfs_file_attr_hash {
+	uint32_t tag;
+	uint32_t len;
+	uint32_t hash_type;
+	/* hash_data is len - sizeof(struct) bytes */
+	uint8_t  hash_data[];
+} __packed;
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
 struct cbfs_stage {
 	uint32_t compression;  /** Compression type */
 	uint64_t entry;  /** entry point */
@@ -61,6 +186,33 @@ struct cbfs_stage {
 	uint32_t memlen;	   /** total length of object in memory */
 } __packed;
 
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+	uint32_t type;
+	uint32_t compression;
+	uint32_t offset;
+	uint64_t load_addr;
+	uint32_t len;
+	uint32_t mem_len;
+} __packed;
+
+struct cbfs_payload {
+	struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct cbfs_optionrom {
+	uint32_t compression;
+	uint32_t len;
+} __packed;
+
 #define CBFS_MEDIA_INVALID_MAP_ADDRESS	((void*)(0xffffffff))
 #define CBFS_DEFAULT_MEDIA		((void*)(0x0))
 

payloads/libpayload/include/cbfs_glue.h

@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-
-#ifndef _CBFS_CBFS_GLUE_H
-#define _CBFS_CBFS_GLUE_H
-
-#include <libpayload-config.h>
-#include <boot_device.h>
-#include <stdio.h>
-
-#define CBFS_ENABLE_HASHING CONFIG(LP_CBFS_VERIFICATION)
-
-#define ERROR(...) printf("CBFS ERROR: " __VA_ARGS__)
-#define LOG(...) printf("CBFS: " __VA_ARGS__)
-#define DEBUG(...)                                                                             \
-	do {                                                                                   \
-		if (CONFIG(LP_DEBUG_CBFS))                                                     \
-			printf("CBFS DEBUG: " __VA_ARGS__);                                    \
-	} while (0)
-
-struct cbfs_dev {
-	size_t offset;
-	size_t size;
-};
-
-struct cbfs_boot_device {
-	struct cbfs_dev dev;
-	void *mcache;
-	size_t mcache_size;
-};
-
-typedef const struct cbfs_dev *cbfs_dev_t;
-
-static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size)
-{
-	if (offset + size < offset || offset + size > dev->size)
-		return CB_ERR_ARG;
-
-	return boot_device_read(buffer, dev->offset + offset, size);
-}
-
-static inline size_t cbfs_dev_size(cbfs_dev_t dev)
-{
-	return dev->size;
-}
-
-#endif /* _CBFS_CBFS_GLUE_H */

payloads/libpayload/include/cbfs_legacy.h

@@ -1,82 +0,0 @@
-/*
- *
- * Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
- * Copyright (C) 2013 Google, Inc.
- *
- * This file is dual-licensed. You can choose between:
- *   - The GNU GPL, version 2, as published by the Free Software Foundation
- *   - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_LEGACY_H_
-#define _CBFS_LEGACY_H_
-
-#include <cbfs_core.h>
-
-/* legacy APIs */
-const struct cbfs_header *get_cbfs_header(void);
-struct cbfs_file *cbfs_find(const char *name);
-void *cbfs_find_file(const char *name, int type);
-
-int cbfs_execute_stage(struct cbfs_media *media, const char *name);
-void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device);
-void *cbfs_load_payload(struct cbfs_media *media, const char *name);
-void *cbfs_load_stage(struct cbfs_media *media, const char *name);
-
-/* Simple buffer for streaming media. */
-struct cbfs_simple_buffer {
-	char *buffer;
-	size_t allocated;
-	size_t size;
-	size_t last_allocate;
-};
-
-void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
-			     struct cbfs_media *media,
-			     size_t offset, size_t count);
-
-void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer,
-			       const void *address);
-
-// Utility functions
-int run_address(void *f);
-
-/* Defined in individual arch / board implementation. */
-int init_default_cbfs_media(struct cbfs_media *media);
-
-#endif

payloads/libpayload/include/coreboot_tables.h

@@ -321,16 +321,6 @@ struct cb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
-
-struct cb_cbmem_entry {
-	uint32_t tag;
-	uint32_t size;
-
-	uint64_t address;
-	uint32_t entry_size;
-	uint32_t id;
-};
-
 struct cb_tsc_info {
 	uint32_t tag;
 	uint32_t size;
@@ -453,4 +443,6 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
+/* Helper functions */
+uintptr_t get_cbmem_addr(const void *cbmem_tab_entry);
 #endif

payloads/libpayload/include/fmap.h

@@ -1,12 +0,0 @@
-/* SPDX_License-Identifier: BSD-3-Clause */
-
-#ifndef _FMAP_H
-#define _FMAP_H
-
-#include <commonlib/bsd/cb_err.h>
-#include <stddef.h>
-
-/* Looks for area with |name| in FlashMap. Requires lib_sysinfo.fmap_cache. */
-cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size);
-
-#endif /* _FMAP_H */

payloads/libpayload/include/fmap_serialized.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ *    * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE		"__FMAP__"
+#define FMAP_VER_MAJOR		1	/* this header's FMAP minor version */
+#define FMAP_VER_MINOR		1	/* this header's FMAP minor version */
+#define FMAP_STRLEN		32	/* maximum length for strings, */
+					/* including null-terminator */
+
+enum fmap_flags {
+	FMAP_AREA_STATIC	= 1 << 0,
+	FMAP_AREA_COMPRESSED	= 1 << 1,
+	FMAP_AREA_RO		= 1 << 2,
+	FMAP_AREA_PRESERVE	= 1 << 3,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+	uint32_t offset;                /* offset relative to base */
+	uint32_t size;                  /* size in bytes */
+	uint8_t  name[FMAP_STRLEN];     /* descriptive name */
+	uint16_t flags;                 /* flags for this area */
+}  __packed;
+
+struct fmap {
+	uint8_t  signature[8];		/* "__FMAP__" (0x5F5F464D41505F5F) */
+	uint8_t  ver_major;		/* major version */
+	uint8_t  ver_minor;		/* minor version */
+	uint64_t base;			/* address of the firmware binary */
+	uint32_t size;			/* size of firmware binary in bytes */
+	uint8_t  name[FMAP_STRLEN];	/* name of this firmware binary */
+	uint16_t nareas;		/* number of areas described by
+					   fmap_areas[] below */
+	struct fmap_area areas[];
+} __packed;
+
+#endif	/* FLASHMAP_SERIALIZED_H__ */

payloads/libpayload/include/libpayload.h

@@ -45,11 +45,10 @@
 #include <stdbool.h>
 #include <libpayload-config.h>
 #include <cbgfx.h>
-#include <commonlib/bsd/fmap_serialized.h>
 #include <ctype.h>
 #include <die.h>
 #include <endian.h>
-#include <fmap.h>
+#include <fmap_serialized.h>
 #include <ipchksum.h>
 #include <kconfig.h>
 #include <stddef.h>
@@ -458,8 +457,6 @@ static inline int clz(u32 x)
 static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; }
 /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */
 static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); }
-/* Find Last Set: __fls(1) == 0, __fls(5) == 2, __fls(1 << 31) == 31 */
-static inline int __fls(u32 x) { return log2(x); }
 
 static inline int popcnt64(u64 x) { return __builtin_popcountll(x); }
 static inline int clz64(u64 x)
@@ -469,7 +466,6 @@ static inline int clz64(u64 x)
 
 static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; }
 static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); }
-static inline int __fls64(u64 x) { return log2_64(x); }
 /** @} */
 
 /**

payloads/libpayload/include/sysinfo.h

@@ -150,12 +150,6 @@ struct sysinfo_t {
 #endif
 	/* USB Type-C Port Configuration Info */
 	uintptr_t type_c_info;
-
-	/* CBFS RW/RO Metadata Cache */
-	uintptr_t cbfs_ro_mcache_offset;
-	uint32_t cbfs_ro_mcache_size;
-	uintptr_t cbfs_rw_mcache_offset;
-	uint32_t cbfs_rw_mcache_size;
 };
 
 extern struct sysinfo_t lib_sysinfo;

payloads/libpayload/libc/coreboot.c

@@ -29,7 +29,6 @@
 
 #include <libpayload-config.h>
 #include <libpayload.h>
-#include <commonlib/bsd/cbmem_id.h>
 #include <coreboot_tables.h>
 #include <stdint.h>
 
@@ -42,6 +41,12 @@
 /* === Parsing code === */
 /* This is the generic parsing code. */
 
+uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry)
+{
+	const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry;
+	return cbmem->cbmem_tab;
+}
+
 static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 {
 	struct cb_memory *mem = ptr;
@@ -78,6 +83,11 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
 	info->cb_serial = virt_to_phys(ptr);
 }
 
+static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->vboot_workbuf = get_cbmem_addr(ptr);
+}
+
 static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct lb_range *vbnv = (struct lb_range *)ptr;
@@ -118,6 +128,26 @@ static void cb_parse_mac_addresses(unsigned char *ptr,
 		info->macs[i] = macs->mac_addrs[i];
 }
 
+static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->tstamp_table = get_cbmem_addr(ptr);
+}
+
+static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->cbmem_cons = get_cbmem_addr(ptr);
+}
+
+static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->acpi_gnvs = get_cbmem_addr(ptr);
+}
+
+static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->acpi_cnvs = get_cbmem_addr(ptr);
+}
+
 static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_board_config *const config = (struct cb_board_config *)ptr;
@@ -158,6 +188,11 @@ static void cb_parse_string(const void *const ptr, uintptr_t *const info)
 	*info = virt_to_phys(str->string);
 }
 
+static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info)
+{
+	info->wifi_calibration = get_cbmem_addr(ptr);
+}
+
 static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info)
 {
 	struct lb_range *ramoops = (struct lb_range *)ptr;
@@ -201,6 +236,21 @@ static void cb_parse_boot_media_params(unsigned char *ptr,
 	info->boot_media_size = bmp->boot_media_size;
 }
 
+static void cb_parse_vpd(void *ptr, struct sysinfo_t *info)
+{
+	info->chromeos_vpd = get_cbmem_addr(ptr);
+}
+
+static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info)
+{
+	info->fmap_cache = get_cbmem_addr(ptr);
+}
+
+static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info)
+{
+	info->type_c_info = get_cbmem_addr(ptr);
+}
+
 #if CONFIG(LP_TIMER_RDTSC)
 static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
 {
@@ -214,57 +264,6 @@ static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
-{
-	const struct cb_cbmem_entry *cbmem_entry = ptr;
-
-	if (cbmem_entry->size != sizeof(*cbmem_entry))
-		return;
-
-	switch (cbmem_entry->id) {
-	case CBMEM_ID_ACPI_CNVS:
-		info->acpi_cnvs = cbmem_entry->address;
-		break;
-	case CBMEM_ID_ACPI_GNVS:
-		info->acpi_gnvs = cbmem_entry->address;
-		break;
-	case CBMEM_ID_CBFS_RO_MCACHE:
-		info->cbfs_ro_mcache_offset = cbmem_entry->address;
-		info->cbfs_ro_mcache_size = cbmem_entry->entry_size;
-		break;
-	case CBMEM_ID_CBFS_RW_MCACHE:
-		info->cbfs_rw_mcache_offset = cbmem_entry->address;
-		info->cbfs_rw_mcache_size = cbmem_entry->entry_size;
-		break;
-	case CBMEM_ID_CONSOLE:
-		info->cbmem_cons = cbmem_entry->address;
-		break;
-	case CBMEM_ID_MRCDATA:
-		info->mrc_cache = cbmem_entry->address;
-		break;
-	case CBMEM_ID_VBOOT_WORKBUF:
-		info->vboot_workbuf = cbmem_entry->address;
-		break;
-	case CBMEM_ID_TIMESTAMP:
-		info->tstamp_table = cbmem_entry->address;
-		break;
-	case CBMEM_ID_VPD:
-		info->chromeos_vpd = cbmem_entry->address;
-		break;
-	case CBMEM_ID_FMAP:
-		info->fmap_cache = cbmem_entry->address;
-		break;
-	case CBMEM_ID_WIFI_CALIBRATION:
-		info->wifi_calibration = cbmem_entry->address;
-		break;
-	case CBMEM_ID_TYPE_C_INFO:
-		info->type_c_info = cbmem_entry->address;
-		break;
-	default:
-		break;
-	}
-}
-
 int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
 	struct cb_header *header;
@@ -373,15 +372,33 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_VBNV:
 			cb_parse_vbnv(ptr, info);
 			break;
+		case CB_TAG_VBOOT_WORKBUF:
+			cb_parse_vboot_workbuf(ptr, info);
+			break;
 		case CB_TAG_MAC_ADDRS:
 			cb_parse_mac_addresses(ptr, info);
 			break;
 		case CB_TAG_SERIALNO:
 			cb_parse_string(ptr, &info->serialno);
 			break;
+		case CB_TAG_TIMESTAMPS:
+			cb_parse_tstamp(ptr, info);
+			break;
+		case CB_TAG_CBMEM_CONSOLE:
+			cb_parse_cbmem_cons(ptr, info);
+			break;
+		case CB_TAG_ACPI_GNVS:
+			cb_parse_acpi_gnvs(ptr, info);
+			break;
+		case CB_TAG_ACPI_CNVS:
+			cb_parse_acpi_cnvs(ptr, info);
+			break;
 		case CB_TAG_BOARD_CONFIG:
 			cb_parse_board_config(ptr, info);
 			break;
+		case CB_TAG_WIFI_CALIBRATION:
+			cb_parse_wifi_calibration(ptr, info);
+			break;
 		case CB_TAG_RAM_OOPS:
 			cb_parse_ramoops(ptr, info);
 			break;
@@ -397,14 +414,20 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_BOOT_MEDIA_PARAMS:
 			cb_parse_boot_media_params(ptr, info);
 			break;
-		case CB_TAG_CBMEM_ENTRY:
-			cb_parse_cbmem_entry(ptr, info);
-			break;
 #if CONFIG(LP_TIMER_RDTSC)
 		case CB_TAG_TSC_INFO:
 			cb_parse_tsc_info(ptr, info);
 			break;
 #endif
+		case CB_TAG_VPD:
+			cb_parse_vpd(ptr, info);
+			break;
+		case CB_TAG_FMAP:
+			cb_parse_fmap_cache(ptr, info);
+			break;
+		case CB_TAG_TYPE_C_INFO:
+			cb_parse_type_c_info(ptr, info);
+			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;

payloads/libpayload/libc/fmap.c

@@ -28,60 +28,10 @@
 
 #include <libpayload-config.h>
 #include <libpayload.h>
-#include <commonlib/bsd/fmap_serialized.h>
 #include <coreboot_tables.h>
 #include <cbfs.h>
-#include <boot_device.h>
+#include <fmap_serialized.h>
 #include <stdint.h>
-#include <arch/virtual.h>
-
-/* Private fmap cache. */
-static struct fmap *_fmap_cache;
-
-static cb_err_t fmap_find_area(struct fmap *fmap, const char *name, size_t *offset,
-			       size_t *size)
-{
-	for (size_t i = 0; i < le32toh(fmap->nareas); ++i) {
-		if (strncmp((const char *)fmap->areas[i].name, name, FMAP_STRLEN) != 0)
-			continue;
-		if (offset)
-			*offset = le32toh(fmap->areas[i].offset);
-		if (size)
-			*size = le32toh(fmap->areas[i].size);
-		return CB_SUCCESS;
-	}
-
-	return CB_ERR;
-}
-
-static bool fmap_is_signature_valid(struct fmap *fmap)
-{
-	return memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature)) == 0;
-}
-
-static bool fmap_setup_cache(void)
-{
-	/* Use FMAP cache if available */
-	if (lib_sysinfo.fmap_cache
-	    && fmap_is_signature_valid((struct fmap *)phys_to_virt(lib_sysinfo.fmap_cache))) {
-		_fmap_cache = (struct fmap *)phys_to_virt(lib_sysinfo.fmap_cache);
-		return true;
-	}
-
-	return false;
-}
-
-cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
-{
-	if (!_fmap_cache && !fmap_setup_cache())
-		return CB_ERR;
-
-	return fmap_find_area(_fmap_cache, name, offset, size);
-}
-
-/***********************************************************************************************
- *                                         LEGACY CODE                                         *
- **********************************************************************************************/
 
 int fmap_region_by_name(const uint32_t fmap_offset, const char * const name,
 			uint32_t * const offset, uint32_t * const size)

payloads/libpayload/libcbfs/Kconfig

@@ -1,31 +0,0 @@
-## SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
-
-config CBFS
-	bool "CBFS support"
-	default y
-	help
-	  CBFS is the archive format of coreboot
-
-if CBFS
-
-config DEBUG_CBFS
-	bool "Output verbose CBFS debug messages"
-	default n
-	help
-	  This option enables additional CBFS related debug messages.
-
-config ENABLE_CBFS_FALLBACK
-	bool "Fallback to RO (COREBOOT) region"
-	default n
-	help
-	  When this option is enabled, the CBFS code will look for a file in the
-	  RO (COREBOOT) region, if it isn't available in the active RW region.
-	  This option makes sense only if CONFIG_VBOOT was enabled in the coreboot.
-
-config CBFS_VERIFICATION
-	bool "Enable CBFS verification"
-	depends on VBOOT_LIB
-	help
-	  This option enables hash verification of CBFS files in RO (COREBOOT) and RW regions.
-
-endif

payloads/libpayload/libcbfs/Makefile.inc

@@ -28,9 +28,3 @@
 
 libcbfs-$(CONFIG_LP_CBFS) += cbfs.c
 libcbfs-$(CONFIG_LP_CBFS) += ram_media.c
-libcbfs-$(CONFIG_LP_CBFS) += cbfs_legacy.c
-
-ifeq ($(CONFIG_LP_CBFS),y)
-libcbfs-srcs += $(coreboottop)/src/commonlib/bsd/cbfs_private.c
-libcbfs-srcs += $(coreboottop)/src/commonlib/bsd/cbfs_mcache.c
-endif

payloads/libpayload/libcbfs/cbfs.c

@@ -1,225 +1,243 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ *
+ * Copyright (C) 2011 secunet Security Networks AG
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#define LIBPAYLOAD
+
+#ifdef LIBPAYLOAD
+# include <libpayload-config.h>
+# if CONFIG(LP_LZMA)
+#  include <lzma.h>
+#  define CBFS_CORE_WITH_LZMA
+# endif
+# if CONFIG(LP_LZ4)
+#  include <lz4.h>
+#  define CBFS_CORE_WITH_LZ4
+# endif
+# define CBFS_MINI_BUILD
+#elif defined(__SMM__)
+# define CBFS_MINI_BUILD
+#else
+# define CBFS_CORE_WITH_LZMA
+# define CBFS_CORE_WITH_LZ4
+# include <lib.h>
+#endif
 
-#include <libpayload-config.h>
-#include <arch/virtual.h>
-#include <assert.h>
 #include <cbfs.h>
-#include <cbfs_glue.h>
-#include <commonlib/bsd/cbfs_private.h>
-#include <commonlib/bsd/fmap_serialized.h>
-#include <libpayload.h>
-#include <lz4.h>
-#include <lzma.h>
 #include <string.h>
-#include <sysinfo.h>
 
+#ifdef LIBPAYLOAD
+# include <stdio.h>
+# define DEBUG(x...)
+# define LOG(x...)
+# define ERROR(x...) printf(x)
+#else
+# include <console/console.h>
+# define ERROR(x...) printk(BIOS_ERR, "CBFS: " x)
+# define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
+# if CONFIG_LP_DEBUG_CBFS
+#  define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
+# else
+#  define DEBUG(x...)
+# endif
+#endif
 
-static const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro)
+#include "cbfs_core.c"
+
+#ifndef __SMM__
+static inline int tohex4(unsigned int c)
 {
-	static struct cbfs_boot_device ro;
-	static struct cbfs_boot_device rw;
-
-	if (!force_ro) {
-		if (!rw.dev.size) {
-			rw.dev.offset = lib_sysinfo.cbfs_offset;
-			rw.dev.size = lib_sysinfo.cbfs_size;
-			rw.mcache = phys_to_virt(lib_sysinfo.cbfs_rw_mcache_offset);
-			rw.mcache_size = lib_sysinfo.cbfs_rw_mcache_size;
-		}
-		return &rw;
-	}
-
-	if (ro.dev.size)
-		return &ro;
-
-	if (fmap_locate_area("COREBOOT", &ro.dev.offset, &ro.dev.size))
-		return NULL;
-
-	ro.mcache = phys_to_virt(lib_sysinfo.cbfs_ro_mcache_offset);
-	ro.mcache_size = lib_sysinfo.cbfs_ro_mcache_size;
-
-	return &ro;
+	return (c <= 9) ? (c + '0') : (c - 10 + 'a');
 }
 
-ssize_t _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mdata)
+static void tohex16(unsigned int val, char* dest)
 {
-	const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro);
-	if (!cbd)
-		return CB_ERR;
-
-	size_t data_offset;
-	cb_err_t err = CB_CBFS_CACHE_FULL;
-	if (cbd->mcache_size)
-		err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size, name, mdata,
-					 &data_offset);
-
-	if (err == CB_CBFS_CACHE_FULL)
-		err = cbfs_lookup(&cbd->dev, name, mdata, &data_offset, NULL);
-
-	/* Fallback to RO if possible. */
-	if (CONFIG(LP_ENABLE_CBFS_FALLBACK) && !force_ro && err == CB_CBFS_NOT_FOUND) {
-		LOG("Fall back to RO region for '%s'\n", name);
-		return _cbfs_boot_lookup(name, true, mdata);
-	}
-
-	if (err) {
-		if (err == CB_CBFS_NOT_FOUND)
-			LOG("'%s' not found.\n", name);
-		else
-			ERROR("Error %d when looking up '%s'\n", err, name);
-		return err;
-	}
-
-	return cbd->dev.offset + data_offset;
+	dest[0] = tohex4(val>>12);
+	dest[1] = tohex4((val>>8) & 0xf);
+	dest[2] = tohex4((val>>4) & 0xf);
+	dest[3] = tohex4(val & 0xf);
 }
 
-void cbfs_unmap(void *mapping)
+void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
+			  uint16_t device)
 {
-	free(mapping);
+	char name[17] = "pciXXXX,XXXX.rom";
+
+	tohex16(vendor, name+3);
+	tohex16(device, name+8);
+
+	return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
 }
 
-static bool cbfs_file_hash_mismatch(const void *buffer, size_t size,
-				    const union cbfs_mdata *mdata, bool skip_verification)
+void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 {
-	if (!CONFIG(LP_CBFS_VERIFICATION) || skip_verification)
-		return false;
+	struct cbfs_stage *stage = (struct cbfs_stage *)
+		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL);
+	/* this is a mess. There is no ntohll. */
+	/* for now, assume compatible byte order until we solve this. */
+	uintptr_t entry;
+	uint32_t final_size;
 
-	const struct vb2_hash *hash = cbfs_file_hash(mdata);
-	if (!hash) {
-		ERROR("'%s' does not have a file hash!\n", mdata->h.filename);
-		return true;
-	}
-	if (vb2_hash_verify(buffer, size, hash) != VB2_SUCCESS) {
-		ERROR("'%s' file hash mismatch!\n", mdata->h.filename);
-		return true;
-	}
+	if (stage == NULL)
+		return (void *) -1;
 
-	return false;
-}
+	LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n",
+			name,
+			(void*)(uintptr_t) stage->load, stage->memlen,
+			stage->entry);
 
-static size_t cbfs_load_and_decompress(size_t offset, size_t in_size, void *buffer,
-				       size_t buffer_size, uint32_t compression,
-				       const union cbfs_mdata *mdata, bool skip_verification)
-{
-	void *load = buffer;
-	size_t out_size = 0;
-
-	DEBUG("Decompressing %zu bytes from '%s' to %p with algo %d\n", in_size,
-	      mdata->h.filename, buffer, compression);
-
-	if (compression != CBFS_COMPRESS_NONE) {
-		load = malloc(in_size);
-		if (!load) {
-			ERROR("'%s' buffer allocation failed\n", mdata->h.filename);
-			return 0;
-		}
-	}
-
-	if (boot_device_read(load, offset, in_size) != in_size) {
-		ERROR("'%s' failed to read contents of file\n", mdata->h.filename);
+	final_size = cbfs_decompress(stage->compression,
+				     ((unsigned char *) stage) +
+				     sizeof(struct cbfs_stage),
+				     stage->len,
+				     (void *) (uintptr_t) stage->load,
+				     stage->memlen);
+	if (!final_size) {
+		entry = -1;
 		goto out;
 	}
 
-	if (cbfs_file_hash_mismatch(buffer, in_size, mdata, skip_verification))
-		goto out;
+	memset((void *)((uintptr_t)stage->load + final_size), 0,
+	       stage->memlen - final_size);
+
+	DEBUG("stage loaded.\n");
+
+	entry = stage->entry;
+	// entry = ntohll(stage->entry);
 
-	switch (compression) {
-	case CBFS_COMPRESS_NONE:
-		out_size = in_size;
-		break;
-	case CBFS_COMPRESS_LZ4:
-		if (!CONFIG(LP_LZ4))
-			goto out;
-		out_size = ulz4fn(load, in_size, buffer, buffer_size);
-		break;
-	case CBFS_COMPRESS_LZMA:
-		if (!CONFIG(LP_LZMA))
-			goto out;
-		out_size = ulzman(load, in_size, buffer, buffer_size);
-		break;
-	default:
-		ERROR("'%s' decompression algo %d not supported\n", mdata->h.filename,
-		      compression);
-	}
 out:
-	if (load != buffer)
-		free(load);
-	return out_size;
+	free(stage);
+	return (void *) entry;
 }
 
-static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t *size_inout,
-		     bool skip_verification)
+int cbfs_execute_stage(struct cbfs_media *media, const char *name)
 {
-	bool malloced = false;
-	size_t out_size;
-	uint32_t compression = CBFS_COMPRESS_NONE;
-	const struct cbfs_file_attr_compression *cattr =
-		cbfs_find_attr(mdata, CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*cattr));
-	if (cattr) {
-		compression = be32toh(cattr->compression);
-		out_size = be32toh(cattr->decompressed_size);
-	} else {
-		out_size = be32toh(mdata->h.len);
+	struct cbfs_stage *stage = (struct cbfs_stage *)
+		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL);
+
+	if (stage == NULL)
+		return 1;
+
+	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
+		LOG("Unable to run %s:  Compressed file"
+		       "Not supported for in-place execution\n", name);
+		free(stage);
+		return 1;
 	}
 
-	if (buf) {
-		if (!size_inout || *size_inout < out_size) {
-			ERROR("'%s' buffer too small\n", mdata->h.filename);
-			return NULL;
-		}
-	} else {
-		buf = malloc(out_size);
-		if (!buf) {
-			ERROR("'%s' allocation failure\n", mdata->h.filename);
-			return NULL;
-		}
-		malloced = true;
-	}
-
-	if (cbfs_load_and_decompress(offset, be32toh(mdata->h.len), buf, out_size, compression,
-				     mdata, skip_verification)
-	    != out_size) {
-		if (malloced)
-			free(buf);
-		return NULL;
-	}
-	if (size_inout)
-		*size_inout = out_size;
-
-	return buf;
+	LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry));
+	int result = run_address((void *)(uintptr_t)ntohll(stage->entry));
+	free(stage);
+	return result;
 }
 
-void *_cbfs_load(const char *name, void *buf, size_t *size_inout, bool force_ro)
+void *cbfs_load_payload(struct cbfs_media *media, const char *name)
 {
-	ssize_t offset;
-	union cbfs_mdata mdata;
-
-	DEBUG("%s(name='%s', buf=%p, force_ro=%s)\n", __func__, name, buf,
-	      force_ro ? "true" : "false");
-
-	offset = _cbfs_boot_lookup(name, force_ro, &mdata);
-	if (offset < 0)
-		return NULL;
-
-	return do_load(&mdata, offset, buf, size_inout, false);
+	return (struct cbfs_payload *)cbfs_get_file_content(
+		media, name, CBFS_TYPE_SELF, NULL);
 }
 
-void *_cbfs_unverified_area_load(const char *area, const char *name, void *buf,
-				 size_t *size_inout)
-{
-	struct cbfs_dev dev;
-	union cbfs_mdata mdata;
-	size_t data_offset;
+struct cbfs_file *cbfs_find(const char *name) {
+	struct cbfs_handle *handle = cbfs_get_handle(CBFS_DEFAULT_MEDIA, name);
+	struct cbfs_media *m = &handle->media;
+	void *ret;
 
-	DEBUG("%s(area='%s', name='%s', buf=%p)\n", __func__, area, name, buf);
-
-	if (fmap_locate_area(area, &dev.offset, &dev.size) != CB_SUCCESS)
+	if (!handle)
 		return NULL;
 
-	if (cbfs_lookup(&dev, name, &mdata, &data_offset, NULL)) {
-		ERROR("'%s' not found in '%s'\n", name, area);
+	ret = m->map(m, handle->media_offset,
+		     handle->content_offset + handle->content_size);
+	if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
+		free(handle);
 		return NULL;
 	}
 
-	return do_load(&mdata, dev.offset + data_offset, buf, size_inout, true);
+	free(handle);
+	return ret;
 }
+
+void *cbfs_find_file(const char *name, int type) {
+	return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL);
+}
+
+const struct cbfs_header *get_cbfs_header(void) {
+	return cbfs_get_header(CBFS_DEFAULT_MEDIA);
+}
+
+/* Simple buffer */
+
+void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
+			     struct cbfs_media *media,
+			     size_t offset, size_t count) {
+	void *address = buffer->buffer + buffer->allocated;
+	DEBUG("simple_buffer_map(offset=%zu, count=%zu): "
+	      "allocated=%zu, size=%zu, last_allocate=%zu\n",
+	    offset, count, buffer->allocated, buffer->size,
+	    buffer->last_allocate);
+	if (buffer->allocated + count >= buffer->size)
+		return CBFS_MEDIA_INVALID_MAP_ADDRESS;
+	if (media->read(media, address, offset, count) != count) {
+		ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n",
+		      count, offset);
+		return CBFS_MEDIA_INVALID_MAP_ADDRESS;
+	}
+	buffer->allocated += count;
+	buffer->last_allocate = count;
+	return address;
+}
+
+void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer,
+			       const void *address) {
+	// TODO Add simple buffer management so we can free more than last
+	// allocated one.
+	DEBUG("simple_buffer_unmap(address=%p): "
+	      "allocated=%zu, size=%zu, last_allocate=%zu\n",
+	    address, buffer->allocated, buffer->size,
+	    buffer->last_allocate);
+	if ((buffer->buffer + buffer->allocated - buffer->last_allocate) ==
+	    address) {
+		buffer->allocated -= buffer->last_allocate;
+		buffer->last_allocate = 0;
+	}
+	return NULL;
+}
+
+/**
+ * run_address is passed the address of a function taking no parameters and
+ * jumps to it, returning the result.
+ * @param f the address to call as a function.
+ * @return value returned by the function.
+ */
+
+int run_address(void *f)
+{
+	int (*v) (void);
+	v = f;
+	return v();
+}
+
+#endif

payloads/libpayload/libcbfs/cbfs_legacy.c

@@ -1,243 +0,0 @@
-/*
- *
- * Copyright (C) 2011 secunet Security Networks AG
- * Copyright (C) 2013 Google, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#define LIBPAYLOAD
-
-#ifdef LIBPAYLOAD
-# include <libpayload-config.h>
-# if CONFIG(LP_LZMA)
-#  include <lzma.h>
-#  define CBFS_CORE_WITH_LZMA
-# endif
-# if CONFIG(LP_LZ4)
-#  include <lz4.h>
-#  define CBFS_CORE_WITH_LZ4
-# endif
-# define CBFS_MINI_BUILD
-#elif defined(__SMM__)
-# define CBFS_MINI_BUILD
-#else
-# define CBFS_CORE_WITH_LZMA
-# define CBFS_CORE_WITH_LZ4
-# include <lib.h>
-#endif
-
-#include <cbfs.h>
-#include <string.h>
-
-#ifdef LIBPAYLOAD
-# include <stdio.h>
-# define DEBUG(x...)
-# define LOG(x...)
-# define ERROR(x...) printf(x)
-#else
-# include <console/console.h>
-# define ERROR(x...) printk(BIOS_ERR, "CBFS: " x)
-# define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
-# if CONFIG_LP_DEBUG_CBFS
-#  define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
-# else
-#  define DEBUG(x...)
-# endif
-#endif
-
-#include "cbfs_core.c"
-
-#ifndef __SMM__
-static inline int tohex4(unsigned int c)
-{
-	return (c <= 9) ? (c + '0') : (c - 10 + 'a');
-}
-
-static void tohex16(unsigned int val, char* dest)
-{
-	dest[0] = tohex4(val>>12);
-	dest[1] = tohex4((val>>8) & 0xf);
-	dest[2] = tohex4((val>>4) & 0xf);
-	dest[3] = tohex4(val & 0xf);
-}
-
-void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
-			  uint16_t device)
-{
-	char name[17] = "pciXXXX,XXXX.rom";
-
-	tohex16(vendor, name+3);
-	tohex16(device, name+8);
-
-	return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL);
-}
-
-void * cbfs_load_stage(struct cbfs_media *media, const char *name)
-{
-	struct cbfs_stage *stage = (struct cbfs_stage *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL);
-	/* this is a mess. There is no ntohll. */
-	/* for now, assume compatible byte order until we solve this. */
-	uintptr_t entry;
-	uint32_t final_size;
-
-	if (stage == NULL)
-		return (void *) -1;
-
-	LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n",
-			name,
-			(void*)(uintptr_t) stage->load, stage->memlen,
-			stage->entry);
-
-	final_size = cbfs_decompress(stage->compression,
-				     ((unsigned char *) stage) +
-				     sizeof(struct cbfs_stage),
-				     stage->len,
-				     (void *) (uintptr_t) stage->load,
-				     stage->memlen);
-	if (!final_size) {
-		entry = -1;
-		goto out;
-	}
-
-	memset((void *)((uintptr_t)stage->load + final_size), 0,
-	       stage->memlen - final_size);
-
-	DEBUG("stage loaded.\n");
-
-	entry = stage->entry;
-	// entry = ntohll(stage->entry);
-
-out:
-	free(stage);
-	return (void *) entry;
-}
-
-int cbfs_execute_stage(struct cbfs_media *media, const char *name)
-{
-	struct cbfs_stage *stage = (struct cbfs_stage *)
-		cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL);
-
-	if (stage == NULL)
-		return 1;
-
-	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
-		LOG("Unable to run %s:  Compressed file"
-		       "Not supported for in-place execution\n", name);
-		free(stage);
-		return 1;
-	}
-
-	LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry));
-	int result = run_address((void *)(uintptr_t)ntohll(stage->entry));
-	free(stage);
-	return result;
-}
-
-void *cbfs_load_payload(struct cbfs_media *media, const char *name)
-{
-	return (struct cbfs_payload *)cbfs_get_file_content(
-		media, name, CBFS_TYPE_SELF, NULL);
-}
-
-struct cbfs_file *cbfs_find(const char *name) {
-	struct cbfs_handle *handle = cbfs_get_handle(CBFS_DEFAULT_MEDIA, name);
-	struct cbfs_media *m = &handle->media;
-	void *ret;
-
-	if (!handle)
-		return NULL;
-
-	ret = m->map(m, handle->media_offset,
-		     handle->content_offset + handle->content_size);
-	if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) {
-		free(handle);
-		return NULL;
-	}
-
-	free(handle);
-	return ret;
-}
-
-void *cbfs_find_file(const char *name, int type) {
-	return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL);
-}
-
-const struct cbfs_header *get_cbfs_header(void) {
-	return cbfs_get_header(CBFS_DEFAULT_MEDIA);
-}
-
-/* Simple buffer */
-
-void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
-			     struct cbfs_media *media,
-			     size_t offset, size_t count) {
-	void *address = buffer->buffer + buffer->allocated;
-	DEBUG("simple_buffer_map(offset=%zu, count=%zu): "
-	      "allocated=%zu, size=%zu, last_allocate=%zu\n",
-	    offset, count, buffer->allocated, buffer->size,
-	    buffer->last_allocate);
-	if (buffer->allocated + count >= buffer->size)
-		return CBFS_MEDIA_INVALID_MAP_ADDRESS;
-	if (media->read(media, address, offset, count) != count) {
-		ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n",
-		      count, offset);
-		return CBFS_MEDIA_INVALID_MAP_ADDRESS;
-	}
-	buffer->allocated += count;
-	buffer->last_allocate = count;
-	return address;
-}
-
-void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer,
-			       const void *address) {
-	// TODO Add simple buffer management so we can free more than last
-	// allocated one.
-	DEBUG("simple_buffer_unmap(address=%p): "
-	      "allocated=%zu, size=%zu, last_allocate=%zu\n",
-	    address, buffer->allocated, buffer->size,
-	    buffer->last_allocate);
-	if ((buffer->buffer + buffer->allocated - buffer->last_allocate) ==
-	    address) {
-		buffer->allocated -= buffer->last_allocate;
-		buffer->last_allocate = 0;
-	}
-	return NULL;
-}
-
-/**
- * run_address is passed the address of a function taking no parameters and
- * jumps to it, returning the result.
- * @param f the address to call as a function.
- * @return value returned by the function.
- */
-
-int run_address(void *f)
-{
-	int (*v) (void);
-	v = f;
-	return v();
-}
-
-#endif

payloads/libpayload/tests/Makefile.inc

@@ -11,6 +11,8 @@ testobj := $(obj)/tests
 endif
 coverage-dir := $(testobj)/coverage_reports
 
+coreboottop := ../../
+
 cmockasrc := $(coreboottop)/3rdparty/cmocka
 cmockaobj := $(objutil)/cmocka
 CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so
@@ -32,19 +34,16 @@ TEST_CONFIG_ := CONFIG_LP_
 # Default includes
 TEST_CFLAGS := -include include/kconfig.h -include include/compiler.h
 TEST_CFLAGS += -Iinclude -Iinclude/mock
-TEST_CFLAGS += -I$(coreboottop)/src/commonlib/bsd/include
 TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER))
-TEST_CFLAGS += -I$(VBOOT_SOURCE)/firmware/include
 
 # Test specific includes
-TEST_CFLAGS += -I$(testsrc)/include
+TEST_CFLAGS += -I$(testsrc)/include -I$(testsrc)/include/mocks
 TEST_CFLAGS += -I$(cmockasrc)/include
 
 # Minimal subset of warnings and errors. Tests can be less strict than actual build.
 TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla
 TEST_CFLAGS += -Wwrite-strings -Wno-trigraphs -Wimplicit-fallthrough
 TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror
-TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type
 
 TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin
 
@@ -141,10 +140,10 @@ $($(1)-objs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file)
 	objcopy_wrap_flags=''; \
 	for sym in $$($(1)-mocks); do \
 		sym_line="$$$$($(HOSTOBJDUMP) -t $$@.orig \
-			| grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s+$$$$sym$$$$")"; \
+			| grep -E \"[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$\")"; \
 		if [ ! -z "$$$$sym_line" ] ; then \
-			addr="$$$$(echo "$$$$sym_line" | awk '{ print $$$$1 }')"; \
-			section="$$$$(echo "$$$$sym_line" | awk '{ print $$$$(NF - 2) }')"; \
+			addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \
+			section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \
 			objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \
 		fi \
 	done ; \

payloads/libpayload/tests/include/mocks/cbfs_util.h

@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef MOCKS_CBFS_UTIL_H
-#define MOCKS_CBFS_UTIL_H
-
-#include <cbfs.h>
-#include <stddef.h>
-#include <tests/test.h>
-
-#define BE32(be32) EMPTY_WRAP(\
-	((be32) >> 24) & 0xff, ((be32) >> 16) & 0xff, \
-	((be32) >> 8) & 0xff, ((be32) >> 0) & 0xff)
-
-#define BE64(be64) EMPTY_WRAP( \
-	BE32(((be64) >> 32) & 0xFFFFFFFF), \
-	BE32(((be64) >> 0) & 0xFFFFFFFF))
-
-#define LE32(val32) EMPTY_WRAP(\
-	((val32) >> 0) & 0xff, ((val32) >> 8) & 0xff, \
-	((val32) >> 16) & 0xff, ((val32) >> 24) & 0xff)
-
-#define LE64(val64) EMPTY_WRAP( \
-	BE32(((val64) >> 0) & 0xFFFFFFFF), \
-	BE32(((val64) >> 32) & 0xFFFFFFFF))
-
-#define FILENAME_SIZE 16
-
-struct cbfs_test_file {
-	struct cbfs_file header;
-	u8 filename[FILENAME_SIZE];
-	u8 attrs_and_data[200];
-};
-
-#define TEST_MCACHE_SIZE (2 * MiB)
-
-#define HEADER_INITIALIZER(ftype, attr_len, file_len) { \
-	.magic = CBFS_FILE_MAGIC, \
-	.len = htobe32(file_len), \
-	.type = htobe32(ftype), \
-	.attributes_offset = \
-		htobe32(attr_len ? sizeof(struct cbfs_file) + FILENAME_SIZE : 0), \
-	.offset = htobe32(sizeof(struct cbfs_file) + FILENAME_SIZE + attr_len), \
-}
-
-#define HASH_ATTR_SIZE (offsetof(struct cbfs_file_attr_hash, hash.raw) + VB2_SHA256_DIGEST_SIZE)
-
-/* This macro basically does nothing but suppresses linter messages */
-#define EMPTY_WRAP(...) __VA_ARGS__
-
-#define TEST_DATA_1_FILENAME "test/data/1"
-#define TEST_DATA_1_SIZE sizeof((u8[]){TEST_DATA_1})
-#define TEST_DATA_1 EMPTY_WRAP( \
-	'!', '"', '#', '$', '%', '&', '\'', '(', ')', '*', '+', ',', '-', '.', '/', \
-	'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', \
-	'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', \
-	'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', \
-	'[', '\\', ']', '^', '_', '`', \
-	'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', \
-	'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z')
-
-#define TEST_DATA_2_FILENAME "test/data/2"
-#define TEST_DATA_2_SIZE sizeof((u8[]){TEST_DATA_2})
-#define TEST_DATA_2 EMPTY_WRAP( \
-	0x9d, 0xa9, 0x91, 0xac, 0x5d, 0xb2, 0x70, 0x76, 0x37, 0x94, 0x94, 0xa8, 0x8b, 0x78, \
-	0xb9, 0xaa, 0x1a, 0x8e, 0x9a, 0x16, 0xbe, 0xdc, 0x29, 0x42, 0x46, 0x58, 0xd4, 0x37, \
-	0x94, 0xca, 0x05, 0xdb, 0x54, 0xfa, 0xd8, 0x6e, 0x54, 0xd8, 0x30, 0x46, 0x5d, 0x62, \
-	0xc2, 0xce, 0xd8, 0x74, 0x60, 0xaf, 0x83, 0x8f, 0xfa, 0x97, 0xdd, 0x6e, 0xcb, 0x60, \
-	0xfa, 0xed, 0x8b, 0x55, 0x9e, 0xc1, 0xc2, 0x18, 0x4f, 0xe2, 0x28, 0x7e, 0xd7, 0x2f, \
-	0xa2, 0x86, 0xfb, 0x4d, 0x3e, 0x00, 0x5a, 0xf7, 0xc2, 0xad, 0x0e, 0xa7, 0xa2, 0xf7, \
-	0x38, 0x66, 0xe6, 0x5c, 0x76, 0x98, 0x89, 0x63, 0xeb, 0xc5, 0xf5, 0xb7, 0xa7, 0x58, \
-	0xe0, 0xf0, 0x2e, 0x2f, 0xb0, 0x95, 0xb7, 0x43, 0x28, 0x19, 0x2d, 0xef, 0x1a, 0xb3, \
-	0x42, 0x31, 0x55, 0x0f, 0xbc, 0xcd, 0x01, 0xe5, 0x39, 0x18, 0x88, 0x83, 0xb2, 0xc5, \
-	0x4b, 0x3b, 0x38, 0xe7)
-
-#define TEST_DATA_INT_1_FILENAME "test-int-1"
-#define TEST_DATA_INT_1_SIZE 8
-#define TEST_DATA_INT_1 0xFEDCBA9876543210ULL
-
-#define TEST_DATA_INT_2_FILENAME "test-int-2"
-#define TEST_DATA_INT_2_SIZE 8
-#define TEST_DATA_INT_2 0x10FE32DC54A97698ULL
-
-#define TEST_DATA_INT_3_FILENAME "test-int-3"
-#define TEST_DATA_INT_3_SIZE 8
-#define TEST_DATA_INT_3 0xFA57F003B0036667ULL
-
-#define TEST_SHA256                                                                            \
-	EMPTY_WRAP(0xef, 0xc7, 0xb1, 0x0a, 0xbf, 0x54, 0x2f, 0xaa, 0x12, 0xa6, 0xeb, 0xf,      \
-		   0xff, 0xf4, 0x19, 0xc1, 0x63, 0xf4, 0x60, 0x50, 0xc5, 0xb0, 0xbe, 0x37,     \
-		   0x32, 0x11, 0x19, 0x63, 0x61, 0xe0, 0x53, 0xe0)
-
-#define INVALID_SHA256                                                                         \
-	EMPTY_WRAP('T', 'h', 'i', 's', ' ', 'i', 's', ' ', 'n', 'o', 't', ' ', 'a', ' ', 'v',  \
-		   'a', 'l', 'i', 'd', ' ', 'S', 'H', 'A', '2', '5', '6', '!', '!', '!', '!',  \
-		   '!', '!')
-
-extern const u8 test_data_1[TEST_DATA_1_SIZE];
-extern const u8 test_data_2[TEST_DATA_2_SIZE];
-extern const u8 test_data_int_1[TEST_DATA_INT_1_SIZE];
-extern const u8 test_data_int_2[TEST_DATA_INT_2_SIZE];
-extern const u8 test_data_int_3[TEST_DATA_INT_3_SIZE];
-
-extern const u8 good_hash[VB2_SHA256_DIGEST_SIZE];
-extern const u8 bad_hash[VB2_SHA256_DIGEST_SIZE];
-
-extern const struct cbfs_test_file file_no_hash;
-extern const struct cbfs_test_file file_valid_hash;
-extern const struct cbfs_test_file file_broken_hash;
-extern const struct cbfs_test_file test_file_1;
-extern const struct cbfs_test_file test_file_2;
-extern const struct cbfs_test_file test_file_int_1;
-extern const struct cbfs_test_file test_file_int_2;
-extern const struct cbfs_test_file test_file_int_3;
-
-#endif /* MOCKS_CBFS_UTIL_H */

payloads/libpayload/tests/libc/Makefile.inc

@@ -1,3 +0,0 @@
-tests-y += fmap_locate_area-test
-
-fmap_locate_area-test-srcs += tests/libc/fmap_locate_area-test.c

payloads/libpayload/tests/libc/fmap_locate_area-test.c

@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "../libc/fmap.c"
-
-#include <libpayload.h>
-#include <tests/test.h>
-
-
-/* Mocks */
-struct sysinfo_t lib_sysinfo;
-unsigned long virtual_offset = 0;
-
-static void reset_fmap_cache(void)
-{
-	_fmap_cache = NULL;
-}
-
-static int setup_fmap_test(void **state)
-{
-	reset_fmap_cache();
-	lib_sysinfo.fmap_cache = 0;
-	return 0;
-}
-
-static void test_fmap_locate_area_no_fmap_available(void **state)
-{
-	size_t offset = 0;
-	size_t size = 0;
-
-	assert_int_equal(-1, fmap_locate_area("COREBOOT", &offset, &size));
-}
-
-static void test_fmap_locate_area_incorrect_signature(void **state)
-{
-	size_t offset = 0;
-	size_t size = 0;
-	struct fmap mock_fmap = {
-		.signature = "NOT_MAP",
-	};
-	lib_sysinfo.fmap_cache = (uintptr_t)&mock_fmap;
-
-	assert_int_equal(-1, fmap_locate_area("COREBOOT", &offset, &size));
-}
-
-static void test_fmap_locate_area_success(void **state)
-{
-	size_t offset = 0;
-	size_t size = 0;
-	struct fmap mock_fmap = {
-		.signature = FMAP_SIGNATURE,
-		.ver_major = 1,
-		.ver_minor = 1,
-		.base = 0xAABB,
-		.size = 0x10000,
-		.nareas = 3,
-	};
-	struct fmap_area area_1 = {
-		.size = 0x1100,
-		.offset = 0x11,
-		.name = {'F', 'I', 'R', 'S', 'T', '_', 'A', 'R', 'E', 'A', 0},
-		.flags = 0,
-	};
-	struct fmap_area area_2 = {
-		.size = 0x2200,
-		.offset = 0x1111,
-		.name = {'S', 'E', 'C', 'O', 'N', 'D', '_', 'A', 'R', 'E', 'A', 0},
-		.flags = 0,
-	};
-	struct fmap_area area_3 = {
-		.size = 0x100,
-		.offset = 0x3311,
-		.name = {'T', 'H', 'I', 'R', 'D', '_', 'A', 'R', 'E', 'A', 0},
-		.flags = 0,
-	};
-	u8 fmap_buffer[sizeof(struct fmap) + 3 * sizeof(struct fmap_area)];
-	memcpy(fmap_buffer, &mock_fmap, sizeof(mock_fmap));
-	memcpy(&fmap_buffer[sizeof(mock_fmap)], &area_1, sizeof(area_1));
-	memcpy(&fmap_buffer[sizeof(mock_fmap) + sizeof(area_1)], &area_2, sizeof(area_2));
-	memcpy(&fmap_buffer[sizeof(mock_fmap) + sizeof(area_1) + sizeof(area_2)], &area_3,
-	       sizeof(area_3));
-
-	/* Cache only */
-	reset_fmap_cache();
-	lib_sysinfo.fmap_cache = (uintptr_t)fmap_buffer;
-
-	assert_int_equal(0, fmap_locate_area("FIRST_AREA", &offset, &size));
-	assert_int_equal(area_1.offset, offset);
-	assert_int_equal(area_1.size, size);
-
-	assert_int_equal(0, fmap_locate_area("THIRD_AREA", &offset, &size));
-	assert_int_equal(area_3.offset, offset);
-	assert_int_equal(area_3.size, size);
-
-	assert_int_equal(0, fmap_locate_area("SECOND_AREA", &offset, &size));
-	assert_int_equal(area_2.offset, offset);
-	assert_int_equal(area_2.size, size);
-
-	reset_fmap_cache();
-}
-
-#define FMAP_LOCATE_AREA_TEST(fn) cmocka_unit_test_setup(fn, setup_fmap_test)
-
-int main(void)
-{
-	const struct CMUnitTest tests[] = {
-		FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_no_fmap_available),
-		FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_incorrect_signature),
-		FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_success),
-	};
-
-	return lp_run_group_tests(tests, NULL, NULL);
-}

payloads/libpayload/tests/libcbfs/Makefile.inc

@@ -1,33 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-tests-y += cbfs-lookup-no-fallback-test
-tests-y += cbfs-lookup-has-fallback-test
-tests-y += cbfs-verification-no-sha512-test
-tests-y += cbfs-verification-has-sha512-test
-tests-y += cbfs-no-verification-no-sha512-test
-tests-y += cbfs-no-verification-has-sha512-test
-
-
-cbfs-lookup-no-fallback-test-srcs += tests/libcbfs/cbfs-lookup-test.c
-cbfs-lookup-no-fallback-test-srcs += tests/mocks/cbfs_file_mock.c
-cbfs-lookup-no-fallback-test-config += CONFIG_LP_ENABLE_CBFS_FALLBACK=0
-cbfs-lookup-no-fallback-test-config += CONFIG_LP_LZ4=1
-cbfs-lookup-no-fallback-test-config += CONFIG_LP_LZMA=1
-
-$(call copy-test,cbfs-lookup-no-fallback-test,cbfs-lookup-has-fallback-test)
-cbfs-lookup-has-fallback-test-config += CONFIG_LP_ENABLE_CBFS_FALLBACK=1
-
-cbfs-verification-no-sha512-test-srcs += tests/libcbfs/cbfs-verification-test.c
-cbfs-verification-no-sha512-test-srcs += tests/mocks/cbfs_file_mock.c
-cbfs-verification-no-sha512-test-config += CONFIG_LP_CBFS_VERIFICATION=1
-cbfs-verification-no-sha512-test-config += VB2_SUPPORT_SHA512=0
-
-$(call copy-test,cbfs-verification-no-sha512-test,cbfs-verification-has-sha512-test)
-cbfs-verification-has-sha512-test-config += VB2_SUPPORT_SHA512=1
-
-$(call copy-test,cbfs-verification-no-sha512-test,cbfs-no-verification-no-sha512-test)
-cbfs-verification-has-sha512-test-config += CONFIG_LP_CBFS_VERIFICATION=0
-
-$(call copy-test,cbfs-verification-no-sha512-test,cbfs-no-verification-has-sha512-test)
-cbfs-verification-has-sha512-test-config += CONFIG_LP_CBFS_VERIFICATION=0
-cbfs-verification-has-sha512-test-config += VB2_SUPPORT_SHA512=1

payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c

@@ -1,729 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0.-only */
-
-#include <libpayload-config.h>
-#include <cbfs.h>
-#include <cbfs_glue.h>
-#include <commonlib/bsd/cb_err.h>
-#include <commonlib/bsd/cbfs_mdata.h>
-#include <endian.h>
-#include <mocks/cbfs_util.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sysinfo.h>
-#include <tests/test.h>
-
-#include "../libcbfs/cbfs.c"
-
-/* Mocks */
-
-unsigned long virtual_offset = 0;
-struct sysinfo_t lib_sysinfo;
-
-unsigned long ulzman(const unsigned char *src, unsigned long srcn, unsigned char *dst,
-		     unsigned long dstn)
-{
-	assert_true(dstn != 0);
-	check_expected(srcn);
-	check_expected(dstn);
-	memcpy(dst, src, dstn);
-	return dstn;
-}
-
-size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
-{
-	assert_non_null(dstn);
-	check_expected(srcn);
-	check_expected(dstn);
-	memcpy(dst, src, dstn);
-	return dstn;
-}
-
-static size_t test_fmap_offset = 0;
-static size_t test_fmap_size = 0;
-static cb_err_t test_fmap_result = CB_SUCCESS;
-
-static void set_fmap_locate_area_results(size_t offset, size_t size, size_t result)
-{
-	test_fmap_offset = offset;
-	test_fmap_size = size;
-	test_fmap_result = result;
-}
-
-cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
-{
-	*offset = test_fmap_offset;
-	*size = test_fmap_size;
-	return test_fmap_result;
-}
-
-cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
-			    union cbfs_mdata *mdata_out, size_t *data_offset_out)
-{
-	assert_non_null(mcache);
-	assert_true(mcache_size > 0 && mcache_size % CBFS_MCACHE_ALIGNMENT == 0);
-	assert_non_null(mdata_out);
-	assert_non_null(data_offset_out);
-
-	check_expected(name);
-
-	cb_err_t ret = mock_type(cb_err_t);
-	if (ret != CB_SUCCESS)
-		return ret;
-
-	memcpy(mdata_out, mock_ptr_type(const union cbfs_mdata *), sizeof(union cbfs_mdata));
-	*data_offset_out = mock_type(size_t);
-	return CB_SUCCESS;
-}
-
-static void expect_cbfs_mcache_lookup(const char *name, cb_err_t err,
-				      const union cbfs_mdata *mdata, size_t data_offset_out)
-{
-	expect_string(cbfs_mcache_lookup, name, name);
-	will_return(cbfs_mcache_lookup, err);
-
-	if (err == CB_SUCCESS) {
-		will_return(cbfs_mcache_lookup, mdata);
-		will_return(cbfs_mcache_lookup, data_offset_out);
-	}
-}
-
-cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
-		     size_t *data_offset_out, struct vb2_hash *metadata_hash)
-{
-	assert_non_null(dev);
-	check_expected(name);
-
-	cb_err_t ret = mock_type(cb_err_t);
-	if (ret != CB_SUCCESS)
-		return ret;
-
-	memcpy(mdata_out, mock_ptr_type(const union cbfS_mdata *), sizeof(union cbfs_mdata));
-	*data_offset_out = mock_type(size_t);
-	return CB_SUCCESS;
-}
-
-static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata,
-			       size_t data_offset_out)
-{
-	expect_string(cbfs_lookup, name, name);
-	will_return(cbfs_lookup, err);
-
-	if (err == CB_SUCCESS) {
-		will_return(cbfs_lookup, mdata);
-		will_return(cbfs_lookup, data_offset_out);
-	}
-}
-
-const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check)
-{
-	return mock_ptr_type(void *);
-}
-
-static bool force_single_boot_device_size_failure = false;
-
-ssize_t boot_device_read(void *buf, size_t offset, size_t size)
-{
-	memcpy(buf, (void *)offset, size);
-	if (force_single_boot_device_size_failure) {
-		force_single_boot_device_size_failure = false;
-		return CB_ERR;
-	}
-	return size;
-}
-
-/* Utils */
-
-static size_t get_cbfs_file_size(const void *file_ptr)
-{
-	const struct cbfs_file *f = file_ptr;
-	return be32toh(f->offset) + be32toh(f->len);
-}
-
-static void create_cbfs(const struct cbfs_test_file *files[], const size_t nfiles,
-			uint8_t *buffer, const size_t buffer_size)
-{
-	uint8_t *data_ptr = buffer;
-	size_t file_size = 0;
-	memset(buffer, 0, buffer_size);
-	for (size_t i = 0; i < nfiles; ++i) {
-		if (files[i] == NULL) {
-			file_size = CBFS_ALIGNMENT;
-			assert_true(&data_ptr[file_size] < &buffer[buffer_size]);
-		} else {
-			file_size = get_cbfs_file_size(files[i]);
-			assert_true(&data_ptr[file_size] < &buffer[buffer_size]);
-			memcpy(data_ptr, files[i], file_size);
-		}
-		data_ptr = &data_ptr[file_size];
-		data_ptr = &buffer[ALIGN_UP((uintptr_t)data_ptr - (uintptr_t)buffer,
-					    CBFS_ALIGNMENT)];
-	}
-}
-
-static size_t get_created_cbfs_file_start_offset(const struct cbfs_test_file *files[],
-						 const size_t nfile)
-{
-	size_t offset_out = 0;
-	size_t offset = 0;
-	for (size_t i = 0; i < nfile; ++i) {
-		offset = files[i] ? get_cbfs_file_size(files[i]) : CBFS_ALIGNMENT;
-		offset_out = ALIGN_UP(offset_out + offset, CBFS_ALIGNMENT);
-	}
-	return offset_out;
-}
-
-/* Setup */
-
-static uint8_t
-	aligned_cbfs_ro_buffer[(sizeof(struct cbfs_test_file) + CBFS_ALIGNMENT * 50)] __aligned(
-		CBFS_ALIGNMENT);
-static const size_t aligned_cbfs_ro_buffer_size = sizeof(aligned_cbfs_ro_buffer);
-static uint8_t
-	aligned_cbfs_rw_buffer[(sizeof(struct cbfs_test_file) + CBFS_ALIGNMENT * 50)] __aligned(
-		CBFS_ALIGNMENT);
-static const size_t aligned_cbfs_rw_buffer_size = sizeof(aligned_cbfs_rw_buffer);
-
-static uint8_t *unaligned_cbfs_ro_buffer = &aligned_cbfs_ro_buffer[5];
-static const size_t unaligned_cbfs_ro_buffer_size = aligned_cbfs_ro_buffer_size - 5;
-static uint8_t *unaligned_cbfs_rw_buffer = &aligned_cbfs_rw_buffer[5];
-static const size_t unaligned_cbfs_rw_buffer_size = aligned_cbfs_rw_buffer_size - 5;
-
-struct cbfs_test_state {
-	uint8_t *cbfs_ro_buf;
-	uint64_t cbfs_ro_size;
-	uint8_t *cbfs_rw_buf;
-	uint64_t cbfs_rw_size;
-
-	size_t mcache_ro_offset;
-	size_t mcache_ro_size;
-	size_t mcache_rw_offset;
-	size_t mcache_rw_size;
-
-	struct cbfs_test_setup {
-		bool unaligned;
-		bool init_ro;
-		bool init_rw;
-	} ex;
-};
-
-
-/* Because of how CMocka works, it should be called in the test function, or in the setup
-   function only if CBFS API capable of initializing RO CBFS boot device is called. */
-static void setup_cbfs_boot_device(struct cbfs_test_state *s)
-{
-	set_fmap_locate_area_results(0, 0, CB_SUCCESS);
-	lib_sysinfo.cbfs_ro_mcache_offset = 0;
-	lib_sysinfo.cbfs_ro_mcache_size = 0;
-	memset((void *)cbfs_get_boot_device(true), 0, sizeof(struct cbfs_boot_device));
-	if (s->ex.init_ro) {
-		set_fmap_locate_area_results((size_t)s->cbfs_ro_buf, s->cbfs_ro_size,
-					     CB_SUCCESS);
-		lib_sysinfo.cbfs_ro_mcache_offset = s->mcache_ro_offset;
-		lib_sysinfo.cbfs_ro_mcache_size = s->mcache_ro_size;
-	}
-
-	lib_sysinfo.cbfs_offset = 0;
-	lib_sysinfo.cbfs_size = 0;
-	lib_sysinfo.cbfs_rw_mcache_offset = 0;
-	lib_sysinfo.cbfs_rw_mcache_size = 0;
-	memset((void *)cbfs_get_boot_device(false), 0, sizeof(struct cbfs_boot_device));
-	if (s->ex.init_rw) {
-		lib_sysinfo.cbfs_offset = (uint64_t)s->cbfs_rw_buf;
-		lib_sysinfo.cbfs_size = s->cbfs_rw_size;
-		lib_sysinfo.cbfs_rw_mcache_offset = s->mcache_rw_offset;
-		lib_sysinfo.cbfs_rw_mcache_size = s->mcache_rw_size;
-	}
-}
-
-static int setup_cbfs_test(void **state)
-{
-	struct cbfs_test_state *s = calloc(1, sizeof(*s));
-
-	if (!s)
-		return 1;
-
-	if (*state)
-		memcpy(&s->ex, *state, sizeof(s->ex));
-
-	if (s->ex.init_ro) {
-		if (s->ex.unaligned) {
-			s->cbfs_ro_buf = unaligned_cbfs_ro_buffer;
-			s->cbfs_ro_size = unaligned_cbfs_ro_buffer_size;
-		} else {
-			s->cbfs_ro_buf = aligned_cbfs_ro_buffer;
-			s->cbfs_ro_size = aligned_cbfs_ro_buffer_size;
-		}
-	}
-
-	if (s->ex.init_rw) {
-		if (s->ex.unaligned) {
-			s->cbfs_rw_buf = unaligned_cbfs_rw_buffer;
-			s->cbfs_rw_size = unaligned_cbfs_rw_buffer_size;
-		} else {
-			s->cbfs_rw_buf = aligned_cbfs_rw_buffer;
-			s->cbfs_rw_size = aligned_cbfs_rw_buffer_size;
-		}
-	}
-
-	*state = s;
-
-	return 0;
-}
-
-static int teardown_cbfs_test(void **state)
-{
-	if (*state)
-		free(*state);
-
-	return 0;
-}
-
-/* Tests */
-
-static void test_cbfs_boot_device_init(void **state)
-{
-	const struct cbfs_boot_device *cbd = NULL;
-
-	/* No valid RO, should fail */
-	set_fmap_locate_area_results(0, 0, CB_ERR);
-	lib_sysinfo.cbfs_offset = 0;
-	lib_sysinfo.cbfs_size = 0;
-	lib_sysinfo.cbfs_rw_mcache_size = 0;
-	lib_sysinfo.cbfs_rw_mcache_offset = 0;
-	lib_sysinfo.cbfs_ro_mcache_offset = 0;
-	lib_sysinfo.cbfs_ro_mcache_size = 0;
-	assert_int_equal(NULL, cbfs_get_boot_device(true));
-	assert_null(cbfs_ro_map("file", NULL));
-
-	/* Valid RO */
-	set_fmap_locate_area_results(0x12345678, 0x90ABCDEF, CB_SUCCESS);
-	lib_sysinfo.cbfs_ro_mcache_offset = 0x600D41C3;
-	lib_sysinfo.cbfs_ro_mcache_size = 0xBADBEEFF;
-	cbd = cbfs_get_boot_device(true);
-	assert_non_null(cbd);
-	assert_int_equal(0x12345678, cbd->dev.offset);
-	assert_int_equal(0x90ABCDEF, cbd->dev.size);
-	assert_int_equal(0xBADBEEFF, cbd->mcache_size);
-	assert_int_equal(0x600D41C3, cbd->mcache);
-
-	lib_sysinfo.cbfs_offset = 0xAABBCCDD;
-	lib_sysinfo.cbfs_size = 0x1000;
-	lib_sysinfo.cbfs_rw_mcache_offset = 0x8F8F8F8F;
-	lib_sysinfo.cbfs_rw_mcache_size = 0x500;
-	cbd = cbfs_get_boot_device(false);
-	assert_non_null(cbd);
-	assert_int_equal(0xAABBCCDD, cbd->dev.offset);
-	assert_int_equal(0x1000, cbd->dev.size);
-	assert_int_equal(0x8F8F8F8F, cbd->mcache);
-	assert_int_equal(0x500, cbd->mcache_size);
-}
-
-/* This test checks cbfs_map() basic cases and covers only RW CBFS. */
-void test_cbfs_map(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	void *mapping = NULL;
-	size_t size_out = 0;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_int_1, &test_file_2, NULL, &test_file_int_3,
-		&test_file_int_2, NULL,		NULL, &test_file_1,
-	};
-	uint8_t *cbfs_buf = NULL;
-	size_t foffset = 0;
-
-	setup_cbfs_boot_device(s);
-	cbfs_buf = s->cbfs_rw_buf;
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 0);
-	expect_cbfs_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_map(TEST_DATA_INT_1_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_1_SIZE, size_out);
-	assert_memory_equal(test_data_int_1, mapping, TEST_DATA_INT_1_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 1);
-	expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_2.header.offset));
-	will_return(cbfs_find_attr, &test_file_2.attrs_and_data);
-	expect_value(ulzman, srcn, TEST_DATA_2_SIZE);
-	expect_value(ulzman, dstn, TEST_DATA_2_SIZE);
-	mapping = cbfs_map(TEST_DATA_2_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_2_SIZE, size_out);
-	assert_memory_equal(test_data_2, mapping, TEST_DATA_2_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 3);
-	expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_3.header.offset));
-	will_return(cbfs_find_attr, &test_file_int_3.attrs_and_data);
-	expect_value(ulz4fn, srcn, TEST_DATA_INT_3_SIZE);
-	expect_value(ulz4fn, dstn, TEST_DATA_INT_3_SIZE);
-	mapping = cbfs_map(TEST_DATA_INT_3_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_3_SIZE, size_out);
-	assert_memory_equal(test_data_int_3, mapping, TEST_DATA_INT_3_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 4);
-	expect_cbfs_lookup(TEST_DATA_INT_2_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_2.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_map(TEST_DATA_INT_2_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_2_SIZE, size_out);
-	assert_memory_equal(test_data_int_2, mapping, TEST_DATA_INT_2_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 7);
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_map(TEST_DATA_1_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_1_SIZE, size_out);
-	assert_memory_equal(test_data_1, mapping, TEST_DATA_1_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	expect_cbfs_lookup("invalid_file", CB_CBFS_NOT_FOUND, 0, 0);
-	if (s->ex.init_rw && CONFIG(LP_ENABLE_CBFS_FALLBACK))
-		expect_cbfs_lookup("invalid_file", CB_CBFS_NOT_FOUND, 0, 0);
-	mapping = cbfs_map("invalid_file", &size_out);
-	assert_null(mapping);
-}
-
-static void test_cbfs_invalid_compression_algo(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	void *mapping = NULL;
-	size_t size_out = 0;
-	uint8_t *cbfs_buf = NULL;
-	struct cbfs_test_file *f;
-	struct cbfs_file_attr_compression *comp;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_2,
-	};
-
-	setup_cbfs_boot_device(s);
-	cbfs_buf = s->cbfs_rw_buf;
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size);
-
-	f = (struct cbfs_test_file *)cbfs_buf;
-	comp = (struct cbfs_file_attr_compression *)&f->attrs_and_data[0];
-	comp->compression = 0xFFFFFFF0;
-
-	size_out = 0;
-	expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS, (const union cbfs_mdata *)cbfs_buf,
-			   be32toh(test_file_1.header.offset));
-	will_return(cbfs_find_attr, comp);
-	mapping = cbfs_map(TEST_DATA_2_FILENAME, &size_out);
-	assert_null(mapping);
-}
-
-static void test_cbfs_io_error(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	setup_cbfs_boot_device(s);
-
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_CBFS_IO, 0, 0);
-	assert_null(cbfs_map(TEST_DATA_1_FILENAME, NULL));
-}
-
-static void test_cbfs_successful_fallback_to_ro(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	void *mapping = NULL;
-	size_t size_out = 0;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_1,	  &test_file_2,	    &test_file_int_1,
-		&test_file_int_1, &test_file_int_2, &test_file_int_3,
-	};
-	uint8_t *cbfs_buf = NULL;
-	size_t foffset = 0;
-
-	if (!CONFIG(LP_ENABLE_CBFS_FALLBACK)) {
-		print_message("Skipping test, because LP_ENABLE_CBFS_FALLBACK == 0\n");
-		skip();
-	}
-
-	setup_cbfs_boot_device(s);
-	cbfs_buf = s->cbfs_ro_buf;
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_ro_buf, s->cbfs_ro_size);
-	if (s->ex.init_rw)
-		create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files) - 2, s->cbfs_rw_buf,
-			    s->cbfs_rw_size);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 1);
-	expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_CBFS_NOT_FOUND, 0, 0);
-	expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_2.header.offset));
-	will_return(cbfs_find_attr, &test_file_2.attrs_and_data);
-	expect_value(ulzman, srcn, TEST_DATA_2_SIZE);
-	expect_value(ulzman, dstn, TEST_DATA_2_SIZE);
-	mapping = cbfs_map(TEST_DATA_2_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_2_SIZE, size_out);
-	assert_memory_equal(test_data_2, mapping, TEST_DATA_2_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 5);
-	expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_CBFS_NOT_FOUND, 0, 0);
-	expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_3.header.offset));
-	will_return(cbfs_find_attr, &test_file_int_3.attrs_and_data);
-	expect_value(ulz4fn, srcn, TEST_DATA_INT_3_SIZE);
-	expect_value(ulz4fn, dstn, TEST_DATA_INT_3_SIZE);
-	mapping = cbfs_map(TEST_DATA_INT_3_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_3_SIZE, size_out);
-	assert_memory_equal(test_data_int_3, mapping, TEST_DATA_INT_3_SIZE);
-	cbfs_unmap(mapping);
-}
-
-static void test_cbfs_load(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	size_t size_out = 0;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_int_1, &test_file_2, NULL, &test_file_int_3,
-		&test_file_int_2, NULL,		NULL, &test_file_1,
-	};
-	uint8_t *cbfs_buf = NULL;
-	uint8_t load_buf[1 * KiB];
-	size_t foffset = 0;
-
-	setup_cbfs_boot_device(s);
-	cbfs_buf = s->cbfs_rw_buf;
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size);
-
-	/* Successful load */
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 0);
-	expect_cbfs_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	size_out = cbfs_load(TEST_DATA_INT_1_FILENAME, load_buf, sizeof(load_buf));
-	assert_int_equal(TEST_DATA_INT_1_SIZE, size_out);
-	assert_memory_equal(test_data_int_1, load_buf, TEST_DATA_INT_1_SIZE);
-
-	/* Buffer too small */
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 7);
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	size_out = cbfs_load(TEST_DATA_1_FILENAME, load_buf, TEST_DATA_1_SIZE / 2);
-	assert_int_equal(0, size_out);
-}
-
-static void test_cbfs_map_with_mcache(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	void *mapping = NULL;
-	size_t size_out = 0;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_int_2, &test_file_1,	    NULL,
-		&test_file_int_3, &test_file_int_1, &test_file_2,
-	};
-	uint8_t *cbfs_buf = NULL;
-	size_t foffset = 0;
-
-	/* Will not be accessed, just needs to be valid. */
-	s->mcache_ro_offset = ALIGN_UP(0x1000, CBFS_MCACHE_ALIGNMENT);
-	s->mcache_ro_size = ALIGN_UP(0x500, CBFS_MCACHE_ALIGNMENT);
-	s->mcache_rw_offset = ALIGN_UP(0x3000, CBFS_MCACHE_ALIGNMENT);
-	s->mcache_rw_size = ALIGN_UP(0x600, CBFS_MCACHE_ALIGNMENT);
-	setup_cbfs_boot_device(s);
-	cbfs_buf = s->cbfs_rw_buf;
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 4);
-	expect_cbfs_mcache_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS,
-				  (const union cbfs_mdata *)&cbfs_buf[foffset],
-				  foffset + be32toh(test_file_int_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_map(TEST_DATA_INT_1_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_1_SIZE, size_out);
-	assert_memory_equal(test_data_int_1, mapping, TEST_DATA_INT_1_SIZE);
-	cbfs_unmap(mapping);
-}
-
-static void test_cbfs_boot_device_read_failure(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	void *mapping = NULL;
-	size_t size_out = 0;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_int_3, &test_file_1,	    NULL,
-		&test_file_int_3, &test_file_int_1, &test_file_2,
-	};
-	uint8_t *cbfs_buf = NULL;
-	size_t foffset = 0;
-
-	setup_cbfs_boot_device(s);
-	cbfs_buf = s->cbfs_rw_buf;
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 1);
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	force_single_boot_device_size_failure = true;
-	mapping = cbfs_map(TEST_DATA_1_FILENAME, &size_out);
-	assert_null(mapping);
-}
-
-/* This test uses RW CBFS only */
-static void test_cbfs_unverified_area_map(void **state)
-{
-	struct cbfs_test_state *s = *state;
-	void *mapping = NULL;
-	size_t size_out = 0;
-	const struct cbfs_test_file *cbfs_files[] = {
-		&test_file_int_1, &test_file_2, NULL, &test_file_int_3,
-		&test_file_int_2, NULL,		NULL, &test_file_1,
-	};
-	uint8_t *cbfs_buf = NULL;
-	size_t foffset = 0;
-
-	cbfs_buf = s->cbfs_rw_buf;
-	set_fmap_locate_area_results((size_t)cbfs_buf, s->cbfs_rw_size, CB_SUCCESS);
-	create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 0);
-	expect_cbfs_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_INT_1_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_1_SIZE, size_out);
-	assert_memory_equal(test_data_int_1, mapping, TEST_DATA_INT_1_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 1);
-	expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_2.header.offset));
-	will_return(cbfs_find_attr, &test_file_2.attrs_and_data);
-	expect_value(ulzman, srcn, TEST_DATA_2_SIZE);
-	expect_value(ulzman, dstn, TEST_DATA_2_SIZE);
-	mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_2_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_2_SIZE, size_out);
-	assert_memory_equal(test_data_2, mapping, TEST_DATA_2_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 3);
-	expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_3.header.offset));
-	will_return(cbfs_find_attr, &test_file_int_3.attrs_and_data);
-	expect_value(ulz4fn, srcn, TEST_DATA_INT_3_SIZE);
-	expect_value(ulz4fn, dstn, TEST_DATA_INT_3_SIZE);
-	mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_INT_3_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_3_SIZE, size_out);
-	assert_memory_equal(test_data_int_3, mapping, TEST_DATA_INT_3_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 4);
-	expect_cbfs_lookup(TEST_DATA_INT_2_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_int_2.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_INT_2_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_INT_2_SIZE, size_out);
-	assert_memory_equal(test_data_int_2, mapping, TEST_DATA_INT_2_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	foffset = get_created_cbfs_file_start_offset(cbfs_files, 7);
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&cbfs_buf[foffset],
-			   foffset + be32toh(test_file_1.header.offset));
-	will_return(cbfs_find_attr, NULL);
-	mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_1_FILENAME, &size_out);
-	assert_non_null(mapping);
-	assert_int_equal(TEST_DATA_1_SIZE, size_out);
-	assert_memory_equal(test_data_1, mapping, TEST_DATA_1_SIZE);
-	cbfs_unmap(mapping);
-
-	size_out = 0;
-	expect_cbfs_lookup("invalid_file", CB_CBFS_NOT_FOUND, 0, 0);
-	mapping = cbfs_unverified_area_map("TEST_AREA", "invalid_file", &size_out);
-	assert_null(mapping);
-}
-
-#define TEST_CBFS_NAME_ALIGN_RO_RW(fn, test_name, enable_unaligned, enable_init_ro,            \
-				   enable_init_rw)                                             \
-	((struct CMUnitTest){                                                                  \
-		.name = (test_name),                                                           \
-		.test_func = (fn),                                                             \
-		.setup_func = setup_cbfs_test,                                                 \
-		.teardown_func = teardown_cbfs_test,                                           \
-		.initial_state =                                                               \
-			&(struct cbfs_test_setup){                                             \
-				.unaligned = enable_unaligned,                                 \
-				.init_ro = enable_init_ro,                                     \
-				.init_rw = enable_init_rw,                                     \
-			},                                                                     \
-	})
-
-#define TEST_CBFS_LOOKUP(fn)                                                                   \
-	EMPTY_WRAP(TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW, aligned", false, false, true),    \
-		   TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW, unaligned", true, false, true))
-
-#define TEST_CBFS_RO_FALLBACK(fn)                                                              \
-	EMPTY_WRAP(TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW+RO, aligned", false, true, true),  \
-		   TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW+RO, unaligned", true, true, true), \
-		   TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RO, aligned", false, true, false),    \
-		   TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RO, unaligned", true, true, false))
-
-
-int main(void)
-{
-	const struct CMUnitTest tests[] = {
-		cmocka_unit_test(test_cbfs_boot_device_init),
-		TEST_CBFS_LOOKUP(test_cbfs_map),
-		TEST_CBFS_LOOKUP(test_cbfs_invalid_compression_algo),
-		TEST_CBFS_LOOKUP(test_cbfs_io_error),
-		TEST_CBFS_RO_FALLBACK(test_cbfs_successful_fallback_to_ro),
-		TEST_CBFS_LOOKUP(test_cbfs_load),
-		TEST_CBFS_LOOKUP(test_cbfs_map_with_mcache),
-		TEST_CBFS_LOOKUP(test_cbfs_boot_device_read_failure),
-		TEST_CBFS_LOOKUP(test_cbfs_unverified_area_map),
-	};
-
-	return lp_run_group_tests(tests, NULL, NULL);
-}

payloads/libpayload/tests/libcbfs/cbfs-verification-test.c

@@ -1,247 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cbfs.h>
-#include <cbfs_glue.h>
-#include <string.h>
-#include <mocks/cbfs_util.h>
-#include <tests/test.h>
-
-#include "../libcbfs/cbfs.c"
-
-/* Mocks */
-
-unsigned long virtual_offset = 0;
-struct sysinfo_t lib_sysinfo;
-
-size_t vb2_digest_size(enum vb2_hash_algorithm hash_alg)
-{
-	if (hash_alg != VB2_HASH_SHA256) {
-		fail_msg("Unsupported hash algorithm: %d\n", hash_alg);
-		return 0;
-	}
-
-	return VB2_SHA256_DIGEST_SIZE;
-}
-
-vb2_error_t vb2_hash_verify(const void *buf, uint32_t size, const struct vb2_hash *hash)
-{
-	check_expected_ptr(buf);
-	check_expected(size);
-
-	assert_int_equal(hash->algo, VB2_HASH_SHA256);
-
-	if (!memcmp(hash->sha256, good_hash, sizeof(good_hash)))
-		return VB2_SUCCESS;
-
-	if (!memcmp(hash->sha256, bad_hash, sizeof(bad_hash)))
-		return VB2_ERROR_SHA_MISMATCH;
-
-	fail_msg("%s called with bad hash", __func__);
-	return VB2_ERROR_SHA_MISMATCH;
-}
-
-unsigned long ulzman(const unsigned char *src, unsigned long srcn, unsigned char *dst,
-		     unsigned long dstn)
-{
-	fail_msg("Unexpected call to %s", __func__);
-	return 0;
-}
-
-size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
-{
-	fail_msg("Unexpected call to %s", __func__);
-	return 0;
-}
-
-cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
-			    union cbfs_mdata *mdata_out, size_t *data_offset_out)
-{
-	return CB_CBFS_CACHE_FULL;
-}
-
-cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
-		     size_t *data_offset_out, struct vb2_hash *metadata_hash)
-{
-	assert_non_null(dev);
-	check_expected(name);
-
-	cb_err_t ret = mock_type(cb_err_t);
-	if (ret != CB_SUCCESS)
-		return ret;
-
-	memcpy(mdata_out, mock_ptr_type(const union cbfs_mdata *), sizeof(union cbfs_mdata));
-	*data_offset_out = mock_type(size_t);
-	return CB_SUCCESS;
-}
-
-static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata,
-			       size_t data_offset_out)
-{
-	expect_string(cbfs_lookup, name, name);
-	will_return(cbfs_lookup, err);
-
-	if (err == CB_SUCCESS) {
-		will_return(cbfs_lookup, mdata);
-		will_return(cbfs_lookup, data_offset_out);
-	}
-}
-
-const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check)
-{
-	return mock_ptr_type(void *);
-}
-
-cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
-{
-	*offset = 0;
-	*size = 0;
-	return CB_SUCCESS;
-}
-
-ssize_t boot_device_read(void *buf, size_t offset, size_t size)
-{
-	/* Offset should be based on an address from lib_sysinfo.cbfs_offset */
-	memcpy(buf, (void *)offset, size);
-
-	return size;
-}
-
-const struct vb2_hash *cbfs_file_hash(const union cbfs_mdata *mdata)
-{
-	return mock_ptr_type(const struct vb2_hash *);
-}
-
-/* Utils */
-
-static void clear_cbfs_boot_devices(void)
-{
-	lib_sysinfo.cbfs_ro_mcache_offset = 0;
-	lib_sysinfo.cbfs_ro_mcache_size = 0;
-	lib_sysinfo.cbfs_offset = 0;
-	lib_sysinfo.cbfs_size = 0;
-	lib_sysinfo.cbfs_rw_mcache_offset = 0;
-	lib_sysinfo.cbfs_rw_mcache_size = 0;
-	memset((void *)cbfs_get_boot_device(true), 0, sizeof(struct cbfs_boot_device));
-	memset((void *)cbfs_get_boot_device(false), 0, sizeof(struct cbfs_boot_device));
-}
-
-void set_cbfs(uint64_t offset, size_t size)
-{
-	clear_cbfs_boot_devices();
-	lib_sysinfo.cbfs_offset = offset;
-	lib_sysinfo.cbfs_size = size;
-}
-
-/* Tests */
-
-static int setup_test_cbfs(void **state)
-{
-	clear_cbfs_boot_devices();
-	return 0;
-}
-
-static void test_cbfs_map_no_hash(void **state)
-{
-	void *mapping = NULL;
-	size_t size = 0;
-
-	set_cbfs((uint64_t)&file_no_hash, sizeof(file_no_hash));
-
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&file_no_hash,
-			   be32toh(file_no_hash.header.offset));
-	will_return(cbfs_find_attr, NULL);
-
-	if (CONFIG(LP_CBFS_VERIFICATION)) {
-		/* File with no hash. No hash causes hash mismatch by default,
-		   so mapping will not be completed successfully. */
-		will_return(cbfs_file_hash, NULL);
-		mapping = cbfs_map(TEST_DATA_1_FILENAME, NULL);
-		assert_null(mapping);
-	} else {
-		mapping = cbfs_map(TEST_DATA_1_FILENAME, &size);
-		assert_non_null(mapping);
-		assert_int_equal(TEST_DATA_1_SIZE, size);
-		assert_memory_equal(test_data_1, mapping, size);
-		cbfs_unmap(mapping);
-	}
-}
-
-static void test_cbfs_map_valid_hash(void **state)
-{
-	void *mapping = NULL;
-	size_t size = 0;
-	struct vb2_hash hash = {
-		.algo = VB2_HASH_SHA256,
-	};
-	memcpy(&hash.sha256, good_hash, VB2_SHA256_DIGEST_SIZE);
-
-	set_cbfs((uint64_t)&file_valid_hash, sizeof(file_valid_hash));
-
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&file_valid_hash,
-			   be32toh(file_valid_hash.header.offset));
-	will_return(cbfs_find_attr, NULL);
-
-
-	if (CONFIG(LP_CBFS_VERIFICATION)) {
-		will_return(cbfs_file_hash, &hash);
-		expect_memory(vb2_hash_verify, buf,
-			      &file_valid_hash.attrs_and_data[HASH_ATTR_SIZE], HASH_ATTR_SIZE);
-		expect_value(vb2_hash_verify, size, TEST_DATA_1_SIZE);
-		mapping = cbfs_map(TEST_DATA_1_FILENAME, &size);
-		assert_non_null(mapping);
-		assert_int_equal(TEST_DATA_1_SIZE, size);
-		assert_memory_equal(mapping, &file_valid_hash.attrs_and_data[HASH_ATTR_SIZE],
-				    size);
-	} else {
-		mapping = cbfs_map(TEST_DATA_1_FILENAME, &size);
-		assert_non_null(mapping);
-		assert_int_equal(TEST_DATA_1_SIZE, size);
-		assert_memory_equal(test_data_1, mapping, size);
-		cbfs_unmap(mapping);
-	}
-}
-
-static void test_cbfs_map_invalid_hash(void **state)
-{
-	void *mapping = NULL;
-	size_t size = 0;
-	struct vb2_hash hash = {
-		.algo = VB2_HASH_SHA256,
-	};
-	memcpy(&hash.sha256, bad_hash, VB2_SHA256_DIGEST_SIZE);
-
-	set_cbfs((uint64_t)&file_broken_hash, sizeof(file_broken_hash));
-
-	expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS,
-			   (const union cbfs_mdata *)&file_broken_hash,
-			   be32toh(file_broken_hash.header.offset));
-	will_return(cbfs_find_attr, NULL);
-
-	if (CONFIG(LP_CBFS_VERIFICATION)) {
-		will_return(cbfs_file_hash, &hash);
-		expect_memory(vb2_hash_verify, buf,
-			      &file_broken_hash.attrs_and_data[HASH_ATTR_SIZE], HASH_ATTR_SIZE);
-		expect_value(vb2_hash_verify, size, TEST_DATA_1_SIZE);
-		mapping = cbfs_map(TEST_DATA_1_FILENAME, NULL);
-		assert_null(mapping);
-	} else {
-		mapping = cbfs_map(TEST_DATA_1_FILENAME, &size);
-		assert_non_null(mapping);
-		assert_int_equal(TEST_DATA_1_SIZE, size);
-		assert_memory_equal(test_data_1, mapping, size);
-		cbfs_unmap(mapping);
-	}
-}
-
-int main(void)
-{
-	const struct CMUnitTest tests[] = {
-		cmocka_unit_test_setup(test_cbfs_map_no_hash, setup_test_cbfs),
-		cmocka_unit_test_setup(test_cbfs_map_valid_hash, setup_test_cbfs),
-		cmocka_unit_test_setup(test_cbfs_map_invalid_hash, setup_test_cbfs),
-	};
-
-	return lp_run_group_tests(tests, NULL, NULL);
-}

payloads/libpayload/tests/mocks/cbfs_file_mock.c

@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mocks/cbfs_util.h>
-
-
-const u8 test_data_1[TEST_DATA_1_SIZE] = { TEST_DATA_1 };
-const u8 test_data_2[TEST_DATA_2_SIZE] = { TEST_DATA_2 };
-const u8 test_data_int_1[TEST_DATA_INT_1_SIZE] = { LE64(TEST_DATA_INT_1) };
-const u8 test_data_int_2[TEST_DATA_INT_2_SIZE] = { LE64(TEST_DATA_INT_2) };
-const u8 test_data_int_3[TEST_DATA_INT_3_SIZE] = { LE64(TEST_DATA_INT_3) };
-
-const u8 good_hash[VB2_SHA256_DIGEST_SIZE] = { TEST_SHA256 };
-const u8 bad_hash[VB2_SHA256_DIGEST_SIZE] = { INVALID_SHA256 };
-
-const struct cbfs_test_file file_no_hash = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_1_SIZE),
-	.filename = TEST_DATA_1_FILENAME,
-	.attrs_and_data = {
-		TEST_DATA_1,
-	},
-};
-
-const struct cbfs_test_file file_valid_hash = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, HASH_ATTR_SIZE, TEST_DATA_1_SIZE),
-	.filename = TEST_DATA_1_FILENAME,
-	.attrs_and_data = {
-		BE32(CBFS_FILE_ATTR_TAG_HASH),
-		BE32(HASH_ATTR_SIZE),
-		BE32(VB2_HASH_SHA256),
-		TEST_SHA256,
-		TEST_DATA_1,
-	},
-};
-
-const struct cbfs_test_file file_broken_hash = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, HASH_ATTR_SIZE, TEST_DATA_1_SIZE),
-	.filename = TEST_DATA_1_FILENAME,
-	.attrs_and_data = {
-		BE32(CBFS_FILE_ATTR_TAG_HASH),
-		BE32(HASH_ATTR_SIZE),
-		BE32(VB2_HASH_SHA256),
-		INVALID_SHA256,
-		TEST_DATA_1,
-	},
-};
-
-const struct cbfs_test_file test_file_1 = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_1_SIZE),
-	.filename = TEST_DATA_1_FILENAME,
-	.attrs_and_data = {
-		TEST_DATA_1,
-	},
-};
-
-const struct cbfs_test_file test_file_2 = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, sizeof(struct cbfs_file_attr_compression),
-				     TEST_DATA_2_SIZE),
-	.filename = TEST_DATA_2_FILENAME,
-	.attrs_and_data = {
-		BE32(CBFS_FILE_ATTR_TAG_COMPRESSION),
-		BE32(sizeof(struct cbfs_file_attr_compression)),
-		BE32(CBFS_COMPRESS_LZMA),
-		BE32(TEST_DATA_2_SIZE),
-		TEST_DATA_2,
-	},
-};
-
-const struct cbfs_test_file test_file_int_1 = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_INT_1_SIZE),
-	.filename = TEST_DATA_INT_1_FILENAME,
-	.attrs_and_data = {
-		LE64(TEST_DATA_INT_1),
-	},
-};
-
-const struct cbfs_test_file test_file_int_2 = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_INT_2_SIZE),
-	.filename = TEST_DATA_INT_2_FILENAME,
-	.attrs_and_data = {
-		LE64(TEST_DATA_INT_2),
-	},
-};
-
-const struct cbfs_test_file test_file_int_3 = {
-	.header = HEADER_INITIALIZER(CBFS_TYPE_RAW, sizeof(struct cbfs_file_attr_compression),
-				     TEST_DATA_INT_3_SIZE),
-	.filename = TEST_DATA_INT_3_FILENAME,
-	.attrs_and_data = {
-		BE32(CBFS_FILE_ATTR_TAG_COMPRESSION),
-		BE32(sizeof(struct cbfs_file_attr_compression)),
-		BE32(CBFS_COMPRESS_LZ4),
-		BE32(TEST_DATA_INT_3_SIZE),
-		LE64(TEST_DATA_INT_3),
-	},
-};

payloads/libpayload/tests/mocks/die.c

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <tests/test.h>
-#include <stdbool.h>
-
-void die_work(const char *file, const char *func, int line, const char *fmt, ...)
-{
-	/* Failing asserts are jumping to the user code (test) if expect_assert_failed() was
-	   previously called. Otherwise it jumps to the cmocka code and fails the test. */
-	mock_assert(false, "Mock assetion called", file, line);
-
-	/* Should never be reached */
-	print_error("%s() called...\n", __func__);
-	while (1)
-		;
-}

payloads/libpayload/vboot/Kconfig

@@ -1,27 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-config VBOOT_LIB
-	bool "Compile verified boot (vboot) library"
-	default y if CHROMEOS
-	default n
-	help
-	  This option enables compiling and building vboot libraries vboot_fw and tlcl.
-
-if VBOOT_LIB
-
-config VBOOT_TPM2_MODE
-	bool "TPM2 Mode"
-	default y
-	help
-	  This option enables TPM 2.0 support in vboot. Disabling it allows using TPM 1.2.
-
-config VBOOT_X86_SHA_EXT
-	bool "x86 SHA Extension"
-	default y if CHROMEOS
-	default n
-	depends on ARCH_X86
-	help
-	  This option enables SHA256 implementation using x86 SHA processor extension
-	  instructions: sha256msg1, sha256msg2, sha256rnds2.
-
-endif

payloads/libpayload/vboot/Makefile.inc

@@ -1,46 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-VBOOT_BUILD_DIR ?= $(abspath $(obj)/external/vboot)
-VBOOT_FW_LIB = $(VBOOT_BUILD_DIR)/vboot_fw.a
-TLCL_LIB = $(VBOOT_BUILD_DIR)/tlcl.a
-
-vboot_fw-objs += $(VBOOT_FW_LIB)
-tlcl-objs += $(TLCL_LIB)
-
-kconfig-to-binary=$(if $(strip $(1)),1,0)
-vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\
-		       $(patsubst include/%.h,$(top)/include/%.h,\
-		       $(filter-out -I$(obj),$(1))))
-
-ifeq ($(CONFIG_LP_ARCH_MOCK),)
-VBOOT_CFLAGS += $(call vboot-fixup-includes,$(CFLAGS))
-VBOOT_CFLAGS += -I$(abspath $(obj))
-endif
-
-# Enable vboot debug by default
-VBOOT_CFLAGS += -DVBOOT_DEBUG
-
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
-
-ifeq ($(CONFIG_LP_ARCH_MOCK)$(VBOOT_FIRMWARE_ARCH-y),)
-$(error vboot requires architecture to be set in the configuration)
-endif
-
-$(VBOOT_FW_LIB): $(obj)/libpayload-config.h
-	@printf "    MAKE       $(subst $(obj)/,,$(@))\n"
-	+$(Q) FIRMWARE_ARCH="$(VBOOT_FIRMWARE_ARCH-y)" \
-		CC="$(CC)" \
-		CFLAGS="$(VBOOT_CFLAGS)" \
-		$(MAKE) -C "$(VBOOT_SOURCE)" \
-		TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \
-		X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \
-		UNROLL_LOOPS=1 \
-		BUILD="$(VBOOT_BUILD_DIR)" \
-		V=$(V) \
-		$(VBOOT_BUILD_DIR)/vboot_fw.a tlcl
-
-$(TLCL_LIB): $(VBOOT_FW_LIB)
-
-.PHONY: $(VBOOT_FW_LIB) $(TLCL_LIB)

spd/lp4x/memory_parts.json

@@ -339,18 +339,6 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 4267
             }
-        },
-	{
-            "name": "MT53E2G32D4NQ-046 WT:C",
-            "attribs": {
-                "densityPerChannelGb": 16,
-                "banks": 8,
-                "channelsPerDie": 2,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 2,
-                "speedMbps": 4267
-            }
         }
     ]
 }

spd/lp4x/set-0/parts_spd_manifest.generated.txt

@@ -29,4 +29,3 @@ H54G46CYRBX267,spd-1.hex
 H54G56CYRBX247,spd-3.hex
 K4U6E3S4AB-MGCL,spd-1.hex
 K4UBE3D4AB-MGCL,spd-3.hex
-MT53E2G32D4NQ-046 WT:C,spd-7.hex

spd/lp4x/set-1/parts_spd_manifest.generated.txt

@@ -29,4 +29,3 @@ H54G46CYRBX267,spd-1.hex
 H54G56CYRBX247,spd-3.hex
 K4U6E3S4AB-MGCL,spd-1.hex
 K4UBE3D4AB-MGCL,spd-3.hex
-MT53E2G32D4NQ-046 WT:C,spd-10.hex

spd/lp5/memory_parts.json

@@ -29,26 +29,6 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 6400
             }
-        },
-        {
-            "name": "K3LKBKB0BM-MGCP",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 6400
-            }
-        },
-        {
-            "name": "H9JCNNNBK3MLYR-N6E",
-            "attribs": {
-                "densityPerDieGb": 8,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 6400
-            }
         }
     ]
 }

spd/lp5/platforms_manifest.generated.txt

@@ -2,4 +2,3 @@
 # util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
 
 ADL,set-0
-SBR,set-1

spd/lp5/set-0/parts_spd_manifest.generated.txt

@@ -4,5 +4,3 @@
 MT62F512M32D2DR-031 WT:B,spd-1.hex
 MT62F1G32D4DR-031 WT:B,spd-2.hex
 H9JCNNNCP3MLYR-N6E,spd-2.hex
-K3LKBKB0BM-MGCP,spd-3.hex
-H9JCNNNBK3MLYR-N6E,spd-1.hex