Add board.fmd and update amdfw

Change-Id: I455a6610810e00dcf44bcf9e88117bd85cd04ed6

.checkpatch.conf

@@ -22,7 +22,6 @@
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore ASSIGN_IN_IF
 --ignore UNNECESSARY_ELSE
---ignore GERRIT_CHANGE_ID
 
 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file

.gitmodules

@@ -1,63 +1,62 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = https://review.coreboot.org/blobs.git
+	url = ../blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = https://review.coreboot.org/nvidia-cbootimage.git
+	url = ../nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = https://review.coreboot.org/vboot.git
+	url = ../vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = https://review.coreboot.org/arm-trusted-firmware.git
+	url = ../arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = https://review.coreboot.org/chrome-ec.git
+	url = ../chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = https://review.coreboot.org/libhwbase.git
+	url = ../libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = https://review.coreboot.org/libgfxinit.git
+	url = ../libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = https://review.coreboot.org/fsp.git
+	url = ../fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = https://review.coreboot.org/opensbi.git
+	url = ../opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = https://review.coreboot.org/intel-microcode.git
+	url = ../intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = https://review.coreboot.org/ffs.git
+	url = ../ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = https://review.coreboot.org/amd_blobs
+	url = ../amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = https://review.coreboot.org/cmocka.git
+	url = ../cmocka.git
 	update = none
-	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = https://review.coreboot.org/qc_blobs.git
+	url = ../qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = https://review.coreboot.org/9esec-security-tooling.git
+	url = ../9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = https://review.coreboot.org/STM
+	url = ../STM
 	branch = stmpe

.mailmap

@@ -1,425 +0,0 @@
-# Map author and committer names and email addresses to canonical real names and
-# email addresses. https://git-scm.com/docs/gitmailmap
-#
-# Note that this is only needed in the case where someone has contributed
-# with multiple different email addresses or Names.
-#
-# Forms: Proper Name <commit@email.xx>
-#        Proper Name <proper@email.xx> <commit@email.xx>
-#        Proper Name <proper@email.xx> Commit Name <commit@email.xx>
-
-
-Aamir Bohra <aamirbohra@gmail.com> <aamir.bohra@intel.com>
-Aaron Durbin <adurbin@chromium.org>
-Aaron Durbin <adurbin@chromium.org> <adurbin@adurbin.bld.corp.google.com>
-Aaron Durbin <adurbin@chromium.org> <adurbin@google.com>
-Abhay Kumar <abhay.kumar@intel.com>
-Abhinav Hardikar <realdevmaster64@gmail.com> devmaster64 <devmaster64@gmail.com>
-Alex Levin <levinale@google.com> <levinale@chromium.org>
-Alex Miao <alex.miao@mediatek.corp-partner.google.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> <alexandrux.gagniuc@intel.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> mrnuke <mrnuke@nukelap.gtech>
-Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
-Amol N Sukerkar <amol.n.sukerkar@intel.com>
-Andrea Barberio <barberio@fb.com> <insomniac@slackware.it>
-Andrey Petrov <anpetrov@fb.com> <andrey.petrov@intel.com>
-Andrey Pronin <apronin@chromium.org> <apronin@google.com>
-Andriy Gapon <avg@FreeBSD.org> <avg@icyb.net.ua>
-Anil Kumar <anil.kumar.k@intel.com> <anil.kumar.k@intel.corp-partner.google.com>
-Anish K. Patel <anishp@win-ent.com>
-Anton Kochkov <anton.kochkov@gmail.com> <a.kochkov@securitycode.ru>
-Antonello Dettori <dev@dettori.io> <dettori.an@gmail.com>
-Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
-Arne Georg Gleditsch <arne.gleditsch@numascale.com> <arne.gleditsch@numscale.com>
-Asami Doi <d0iasm.pub@gmail.com> <doiasami1219@gmail.com>
-Ashwin Kumar <ashk@codeaurora.org>
-Axel Holewa <mono@posteo.de> Mono <mono-for-coreboot@donderklumpen.de>
-Axel Holewa <mono@posteo.de> Mono <mono@posteo.de>
-Bao Zheng <fishbaozi@gmail.com>
-Bao Zheng <fishbaozi@gmail.com> <Zheng Bao zheng.bao@amd.com>
-Bao Zheng <fishbaozi@gmail.com> <zheng.bao@amd.com>
-Bayi Cheng <bayi.cheng@mediatek.com>
-Ben Zhang <benzh@google.com> <benzh@chromium.org>
-Bernhard M. Wiedermann <corebootbmw@lsmod.de>
-Bill Xie <persmule@hardenedlinux.org> <persmule@gmail.com>
-Bill Xie <persmule@hardenedlinux.org> Bill XIE <persmule@hardenedlinux.org>
-Bingxun Shi <bingxunshi@gmail.com>
-Bingxun Shi <bingxunshi@gmail.com> <bxshi@msik.com.cn>
-Brandon Breitenstein <brandon.breitenstein@intel.com> <brandon.breitenstein@intel.corp-partner.google.com>
-Bruce Griffith <bruce.griffith@se-eng.com> <Bruce.Griffith@se-eng.com>
-Bryant Ou <Bryant.Ou.Q@gmail.com>
-Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> <Carl-Daniel Hailfinger>
-Casper Chang<casper_chang@wistron.corp-partner.google.com> <casper.chang@bitland.corp-partner.google.com>
-Caveh Jalali <caveh@chromium.org> <caveh@google.com>
-Caveh Jalali <caveh@chromium.org> caveh jalali <caveh@chromium.org>
-Charles Marslett <charles@scarlettechnologies.com> <charles.marslett@silverbackltd.com>
-Chee Soon Lew <chee.soon.lew@intel.com>
-Cheng-Yi Chiang <cychiang@chromium.org> <cychiang@google.com>
-Chris Ching <chris@ching.codes> <chingcodes@chromium.org>
-Chris Ching <chris@ching.codes> <chingcodes@google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> <chriswang@ami.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris Wang <chris.wang@amd-corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> chris wang <chris.wang@amd.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris.Wang <chris.wang@amd.corp-partner.google.com>
-Chris Zhou <chris_zhou@compal.corp-partner.google.com>
-Christian Ruppert <idl0r@qasl.de> <idl0r@gentoo.org>
-Chun-Jie Chen <chun-jie.chen@mediatek.corp-partner.google.com>
-Clay Daniels Jr <clay.daniels.jr@gmail.com>
-Cole Nelson<colex.nelson@intel.com>
-Corey Osgood <corey.osgod@gmail.com> <corey_osgood@verizon.net>
-Corey Osgood <corey.osgod@gmail.com> <corey.osgood@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
-Da Lao <dalao@tutanota.com> dalao <dalao@tutanota.com>
-Daisuke Nojiri <dnojiri@chromium.org> dnojiri <dnojiri@chromium.org>
-Dan Elkouby <streetwalkermc@gmail.com> <streetwalrus@codewalr.us>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@chromium.org>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@google.com>
-Dave Parker <dparker@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <david.hendricks@gmail.com>
-David Hendricks <davidhendricks@gmail.com> <dhendricks@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@google.com>
-David Hendricks <davidhendricks@gmail.com> David W. Hendricks <dwh@lanl.gov>
-David Wu <david_wu@quantatw.com> <david_wu@quanta.corp-partner.google.com>
-David Wu <david_wu@quantatw.com> david <david_wu@quantatw.com>
-Dawei Chien <dawei.chien@mediatek.com>
-Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> <GNUtoo@no-log.org>
-Derek Huang <derek.huang@intel.com> <derek.huang@intel.corp-partner.google.com>
-Dmitry Ponamorev <dponamorev@gmail.com>
-Douglas Anderson <dianders@chromium.org>
-Duncan Laurie <dlaurie@chromium.org> <dlaurie@google.com>
-Ed Swierk <eswierk@aristanetworks.com> <eswierk@arastra.com>
-Edward O'Callaghan <quasisec@google.com> <edward.ocallaghan@koparo.com>
-Edward O'Callaghan <quasisec@google.com> <eocallaghan@alterapraxis.com>
-Edward O'Callaghan <quasisec@google.com> <funfunctor@folklore1984.net>
-Edward O'Callaghan <quasisec@google.com> <quasisec@chromium.org>
-Eric Biederman <ebiederm@xmission.com> <ebiederman@lnxi.com>
-Eric Biederman <ebiederm@xmission.com> Eric W. Biederman <ebiederm@xmission.com>
-Eugene Myers <edmyers@tycho.nsa.gov> <cedarhouse@comcast.net>
-Evgeny Zinoviev <me@ch1p.io> <me@ch1p.com>
-Felix Durairaj <felixx.durairaj@intel.com>
-Felix Held <felix-coreboot@felixheld.de> <felix-github@felixheld.de>
-Felix Held <felix-coreboot@felixheld.de> <felix.held@amd.corp-partner.google.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@9elements.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@secunet.com>
-Felix Singer <felixsinger@posteo.net> <migy@darmstadt.ccc.de>
-Francois Toguo Fotso <francois.toguo.fotso@intel.com> Francois Toguo <francois.toguo.fotso@intel.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Vibrans <efdesign98@gmail.com> efdesign98 <efdesign98@gmail.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@amd.com>
-Frank Vibrans <efdesign98@gmail.com> frank vibrans <frank.vibrans@scarletltd.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@se-eng.com>
-Frank Vibrans <efdesign98@gmail.com> Frank.Vibrans <frank.vibrans@amd.com>
-Furquan Shaikh <furquan@chromium.org> <furquan@google.com>
-G. Pangao <gtk_pangao@mediatek.com> <gtk_pangao@mediatek.corp-partner.google.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@chromium.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@google.com>
-Gaggery Tsai <gaggery.tsai@intel.com>
-Georg Wicherski <gwicherski@gmail.com> <gw@oxff.net>
-Gomathi Kumar <gomathi.kumar@intel.com>
-Greg V <greg@unrelenting.technology>
-Greg Watson <gwatson@lanl.gov> <jarrah@users.sourceforge.net>
-Hannah Williams <hannah.williams@dell.com> <hannah.williams@intel.com>
-Hao Chou <hao_chou@pegatron.corp-partner.google.com>
-Haridhar Kalvala <haridhar.kalvala@intel.com> haridhar <haridhar.kalvala@intel.com>
-Harsha Priya <harshapriya.n@intel.com>
-Harsha Priya <harshapriya.n@intel.com> <harhapriya.n@intel.com>
-Harshit Sharma <harshitsharmajs@gmail.com> harshit <harshitsharmajs@gmail.com>
-Henry C Chen <henryc.chen@mediatek.com> henryc.chen <henryc.chen@mediatek.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> <himanshusah@hcl.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
-Hsuan Ting Chen <roccochen@chromium.org> Hsuan-ting Chen <roccochen@google.com>
-Huang Lin <hl@rock-chips.com>
-Huayang Duan <huayang.duan@mediatek.com>
-Huki Huang <huki.huang@intel.com>
-Idwer Vollering <vidwer@gmail.com> <idwer_v@hotmail.com>
-Igor Bagnucki <bagnucki02@gmail.com> <igor.bagnucki@3mdeb.com>
-Indrek Kruusa <indrek.kruusa@artecdesign.ee>  <Indrek Kruusa>
-Ivy Jian <ivy_jian@compal.com> <ivy_jian@compal.corp-partner.google.com>
-Jacob Laska <jlaska91@gmail.com> <jlaska@xes-inc.com>
-Jakub Czapiga <jacz@semihalf.com>
-Jason Wang <Qingpei.Wang@amd.com> Jason WangQingpei.wang <Jason WangQingpei.wang@amd.com>
-JasonX Z Chen <jasonx.z.chen@intel.com>
-Jens Kühnel <coreboot@jens.kuehnel.org> Jens Kuehnel <coreboot@jens.kuehnel.org>
-Jens Rottmann <JRottmann@LiPPERTembedded.de> <JRottmann@LiPPERTEmbedded.de>
-Jeremy Compostella  <jeremy.compostella@intel.com> <jeremy.compostella@gmail.com>
-Jeremy Soller <jackpot51@gmail.com> <jeremy@system76.com>
-Jiaxin Yu <jiaxin.yu@mediatek.com>
-Jiazi Yang <Tomato_Yang@asus.com>
-Jim Lai <jim.lai@intel.com>
-Jingle Hsu <jingle_hsu@wiwynn.com>
-Jinkun Hong <jinkun.hong@rock-chips.com>
-Joe Moore <awokd@danwin1210.me>
-Joe Pillow <joseph.a.pillow@gmail.com>
-Johanna Schander <coreboot@mimoja.de>
-John Zhao <john.zhao@intel.com>
-Jonathan Kollasch <jakllsch@kollasch.net>
-Jordan Crouse <jordan@cosmicpenguin.net>  <Jordan Crouse>
-Jordan Crouse <jordan@cosmicpenguin.net> <jordan.crouse@amd.com>
-Josef Kellermann <Joseph.Kellermann@heitec.de> <seppk@arcor.de>
-Josef Kellermann <Joseph.Kellermann@heitec.de> Josef Kellermannseppk <Josef Kellermannseppk@arcor.de>
-Joseph Smith <joe@settoplinux.org> <joe@settoplinux.org Acked-by: Joseph Smith joe@settoplinux.org>
-Joseph Smith <joe@settoplinux.org> <joe@smittys.pointclark.net>
-Juergen Beisert <juergen@kreuzholzen.de> <juergen127@kreuzholzen.de>
-Julian Schroeder <julianmarcusschroeder@gmail.com> <julian.schroeder@amd.com>
-Julien Viard de Galbert <julien@vdg.name> <jviarddegalbert@online.net>
-Justin Wu <amersel@runbox.me>
-Kaiyen Chang <kaiyen.chang@intel.com> <kaiyen.chang@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane.chen@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> Kane Chenffd <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> kane_chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
-Karthikeyan Ramasubramanian <kramasub@google.com> <kramasub@chromium.org>
-Katie Roberts-Hoffman <katierh@chromium.org>  <katierh@google.com>
-Kerry She <kerry.she@amd.com> <Kerry.she@amd.com>
-Kerry Sheh <shekairui@gmail.com>
-Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quanta.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quantatw.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <Kevin.Chiu@quantatw.com>
-Kevin Paul Herbert <kph@platinasystems.com> <kevin@trippers.org>
-Kevin Paul Herbert <kph@platinasystems.com> <kph@meraki.net>
-Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
-Konstantin Aladyshev <aladyshev22@gmail.com> <aladyshev@nicevt.ru>
-Kyösti Mälkki <kyosti.malkki@gmail.com>
-Kyösti Mälkki <kyosti.malkki@gmail.com> <kyosti.malkki@3mdeb.com>
-Lean Sheng Tan <sheng.tan@9elements.com> <lean.sheng.tan@intel.com>
-Lee Leahy <lpleahyjr@gmail.com> <leroy.p.leahy@intel.com>
-Li Cheng Sooi <li.cheng.sooi@intel.com>
-Lijian Zhao <lijian.zhao@intel.com>
-Lin Huang <hl@rock-chips.com>
-Maciej Matuszczyk <maccraft123mc@gmail.com>
-Maggie Li <maggie.li@amd.com> <Maggie.li@amd.com>
-Manideep Kurumella <mkurumel@qualcomm.corp-partner.google.com> <mkurumel@codeaurora.org>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@scarletltd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@se-eng.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@yahoo.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcjones@sysproconsulting.com>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones(marc.jones <Marc Jones(marc.jones@amd.com)>
-Marcello Sylvester Bauer <sylv@sylv.io>
-Marcello Sylvester Bauer <sylv@sylv.io> <info@marcellobauer.com>
-Marcello Sylvester Bauer <sylv@sylv.io> <sylvblck@sylv.io>
-Marco Chen <marcochen@google.com> <marcochen@chromium.org>
-Mariusz Szafrański <mariuszx.szafranski@intel.com> Mariusz Szafranski <mariuszx.szafranski@intel.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@amd.corp-partner.google.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@scarletltd.com>
-Mart Raudsepp <leio@gentoo.org> <mart.raudsepp@artecdesign.ee>
-Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
-Martin Roth <gaumless@gmail.com> <martin.roth@se-eng.com>
-Martin Roth <gaumless@gmail.com> <martin@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinr@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinroth@chromium.org>
-Martin Roth <gaumless@gmail.com> <martinroth@google.com>
-Martin Roth <gaumless@gmail.com> Martin Roth <martin@se-eng.com>
-Marx Wang <marx.wang@intel.com>
-Mathias Krause <minipli@googlemail.com> <mathias.krause@secunet.com>
-Mathias Krause <minipli@googlemail.com> <Mathias.Krause@secunet.com>
-Mats Erik Andersson <mats.andersson@gisladisker.org> <mats.andersson@gisladisker.se>
-Matt DeVillier <matt.devillier@gmail.com> <matt.devillier@puri.sm>
-Matt Papageorge <matthewpapa07@gmail.com> <matt.papageorge@amd.corp-partner.google.com>
-Matt Ziegelbaum <ziegs@google.com> <ziegs@chromium.org>
-Maulik V Vaghela <maulik.v.vaghela@intel.com>
-Maulik V Vaghela <maulik.v.vaghela@intel.com> <maulik.v.vaghela@intel.corp-partner.google.com>
-Max Blau <tripleshiftone@gmail.com> Bluemax <1403092+BlueMax@users.noreply.github.com>
-Maxim Polyakov <max.senia.poliak@gmail.com> <m.poliakov@yahoo.com>
-Mengqi Zhang <Mengqi.Zhang@mediatek.com> mengqi.zhang <mengqi.zhang@mediatek.com>
-Michael Niewöhner <foss@mniewoehner.de> <michael.niewoehner@8com.de>
-Michael Xie <Michael.Xie@amd.com> <Michael Xie Michael.Xie@amd.com>
-Michele Guerini Rocco <rnhmjoj@inventati.org>
-Mike Banon <mikebdp2@gmail.com> <mike.banon@3mdeb.com>
-Mike Hsieh <Mike_Hsieh@wistron.com> <mike_hsieh@wistron.corp-partner.google.com>
-Mike Loptien <loptienm@gmail.com> <mike.loptien@se-eng.com>
-Mondrian Nuessle <nuessle@uni-hd.de>
-Mondrian Nuessle <nuessle@uni-hd.de> <nuessle@uni-mannheim.de>
-Motiejus Jakštys <desired.mta@gmail.com>
-Myles Watson <mylesgw@gmail.com>  <myles@pel.cs.byu.edu>
-Nancy Lin <nancy.lin@mediatek.com>
-Naresh Solanki <naresh.solanki@intel.com>
-Naresh Solanki <naresh.solanki@intel.com> <Naresh.Solanki@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Neil Chen <neilc@nvidia.com> <neilc%nvidia.com@gtempaccount.com>
-Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
-Nick Vaccaro <nvaccaro@google.com> <nvaccaro@chromium.org>
-Nicky Sielicki <nlsielicki@wisc.edu>
-Nico Huber <nico.h@gmx.de> <nico.huber@secunet.com>
-Nicolas Boichat <drinkcat@chromium.org> <drinkcat@google.com>
-Nicolas Reinecke <nr@das-labor.org>
-Nils Jacobs <njacobs8@adsltotaal.nl> <njacobs8@hetnet.nl>
-Nina Wu <nina-cm.wu@mediatek.com> <nina-cm.wu@mediatek.corp-partner.google.com>
-Oskar Enoksson <enok@lysator.liu.se>
-Oskar Enoksson <enok@lysator.liu.se> <oskeno@foi.se>
-Pablo Moyano <42.pablo.ms@gmail.com> p4block <p4block@users.noreply.github.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick.Georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi.software>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@chromium.org>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@google.com>
-Patrick Rudolph  <siro@das-labor.org> <patrick.rudolph@9elements.com>
-Paul Fagerburg <pfagerburg@chromium.org> <pfagerburg@google.com>
-Paul Kocialkowski <contact@paulk.fr>
-Paul Ma <magf@bitland.com.cn> <magf@bitland.corp-partner.google.com>
-Paul Ma <magf@bitland.com.cn> Magf - <magf@bitland.corp-partner.google.com>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@mailbox.org>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@users.sourceforge.net>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Philip Chen <philipchen@google.com>
-Philip Chen <philipchen@google.com> <philipchen@chromium.org>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <philipp.deppenwiese@9elements.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <zaolin@das-labor.org>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> <piotr.kleins@gmail.com>
-Piotr Szymaniak <szarpaj@grubelek.pl>
-Po Xu <jg_poxu@mediatek.com>
-Po Xu <jg_poxu@mediatek.com> <jg_poxu@mediatek.corp-partner.google.com>
-Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
-Preetham Chandrian <preetham.chandrian@intel.com>
-Puthikorn Voravootivat <puthik@chromium.org> <puthik@google.com>
-QingPei Wang <wangqingpei@gmail.com>
-Quan Tran <qeed.quan@gmail.com>
-Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
-Raul Rangel <rrangel@chromium.org>
-Ravi Kumar Bokka <rbokka@codeaurora.org>
-Ravindra <ravindra@intel.com>
-Ravindra <ravindra@intel.com> Ravindra N <ravindra@intel.corp-partner.google.com>
-Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
-Raymond Chung <raymondchung@ami.corp-partner.google.com>
-Raymond Danks <raymonddanks@gmail.com> <ray.danks@se-eng.com>
-Reka Norman <rekanorman@google.com> <rekanorman@chromium.org>
-Ren Kuo <ren.kuo@quantatw.com>
-Ren Kuo <ren.kuo@quantatw.com> <ren.kuo@quanta.corp-partner.google.com>
-Rex-BC Chen <rex-bc.chen@mediatek.com> <rex-bc.chen@mediatek.corp-partner.google.com>
-Ricardo Ribalda <ribalda@chromium.org> <ricardo.ribalda@gmail.com>
-Richard Spiegel <richard.spiegel@silverbackltd.com> <richard.spiegel@amd.corp-partner.google.com>
-Rishavnath Satapathy <rishavnath.satapathy@intel.com>
-Ritul Guru <ritul.bits@gmail.com>
-Rizwan Qureshi <rizwan.qureshi@intel.com> <rizwan.qureshi@intel.corp-partner.google.com>
-Robbie Zhang <robbie.zhang@intel.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com> = <robert.chen@quanta.corp-partner.google.com>
-Roger Pau Monne <roger.pau@citrix.com>
-Roman Kononov <kononov@dls.net> <kononov195-lbl@yahoo.com>
-Ron Minnich <rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> <Ron Minnich>
-Ron Minnich <rminnich@gmail.com> <Ronald G. Minnich rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <minnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@chromium.org>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@lanl.gov>
-Ron Minnich <rminnich@gmail.com> ronald g. minnich <ronald g. minnich>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <Ronald G. Minnich>
-Ronak Kanabar <ronak.kanabar@intel.com>
-Rudolf Marek <r.marek@assembler.cz> <r.marek@asssembler.cz>
-Ryan Chuang <ryan.chuang@mediatek.com> <ryan.chuang@mediatek.corp-partner.google.com>
-Santhosh Janardhana Hassan <sahassan@google.com>
-Scott Chao <scott_chao@wistron.corp-partner.google.com> <scott.chao@bitland.corp-partner.google.com>
-Scott Duplichan <scott@notabs.org> <sc...@notabs.org>
-Scott Tsai <AT>
-Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
-Selma Bensaid <selma.bensaid@intel.com>
-Seunghwan Kim <sh_.kim@samsung.com>
-Seunghwan Kim <sh_.kim@samsung.com> <sh_.kim@samsung.corp-partner.google.com>
-Seunghwan Kim <sh_.kim@samsung.com> sh.kim <sh_.kim@samsung.corp-partner.google.com>
-Shawn Chang <citypw@gmail.com>
-Shawn Nematbakhsh <shawnn@google.com> <shawnn@chromium.org>
-Shelley Chen <shchen@google.com> <shchen@chromium.org>
-Sheng-Liang Pan <Sheng-Liang.Pan@quantatw.com> <sheng-liang.pan@quanta.corp-partner.google.com>
-Shreesh Chhabbi <shreesh.chhabbi@intel.com> <shreesh.chhabbi@intel.corp-partner.google.com>
-Shunqian Zheng <zhengsq@rock-chips.com>
-Siyuan Wang <wangsiyuanbuaa@gmail.com>
-Sowmya <v.sowmya@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com> <sridhar.siricilla@intel.corp-partner.google.com>
-Srinidhi Kaushik <srinidhi.n.kaushik@intel.com>
-Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
-Stefan Ott <stefan@ott.net> <coreboot@desire.ch>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@chromium.org>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@google.com>
-Stefan Reinauer <stepan@coreboot.org> <Stefan Reinauerstepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stefan.reinauer@coreboot.org>
-Stefan Reinauer <stepan@coreboot.org> <stepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stepan@openbios.org>
-Stephan Guilloux <stephan.guilloux@free.fr> <mailto:stephan.guilloux@free.fr>
-Subrata Banik <subratabanik@google.com> <subi.banik@gmail.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Sudheer Kumar Amrabadi <samrab@codeaurora.org>
-Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
-Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
-Susendra Selvaraj <susendra.selvaraj@intel.com>
-Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
-T Michael Turney <mturney@codeaurora.org> mturney mturney <quic_mturney@quicinc.com>
-T Michael Turney <mturney@codeaurora.org> T Michael Turney <quic_mturney@quicinc.com>
-T.H. Lin <T.H_Lin@quantatw.com> <t.h_lin@quanta.corp-partner.google.com>
-T.H. Lin <T.H_Lin@quantatw.com> T.H.Lin <T.H_Lin@quantatw.com>
-Taniya Das <quic_tdas@quicinc.com> <tdas@codeaurora.org>
-Tao Xia <xiatao5@huaqin.corp-partner.google.com>
-Thejaswani Putta  <thejaswani.putta@intel.com> <thejaswani.putta@intel.corp-partner.google.com>
-Thejaswani Putta <thejaswani.putta@intel.com>
-Thejaswani Putta <thejaswani.putta@intel.com> Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
-Thomas Heijligen <thomas.heijligen@secunet.com> <src@posteo.de>
-Tim Chen <Tim-Chen@quantatw.com> <tim-chen@quanta.corp-partner.google.com>
-Tim Chu <Tim.Chu@quantatw.com>
-Tim Wawrzynczak <twawrzynczak@chromium.org> <twawrzynczak@google.com>
-Timothy Pearson <tpearson@raptorengineering.com> <tpearson@raptorengineeringinc.com>
-Tinghan Shen <tinghan.shen@mediatek.com>
-Tobias Diedrich <ranma+coreboot@tdiedrich.de> <ranma+openocd@tdiedrich.de>
-Tracy Wu <tracy.wu@intel.com> <tracy.wu@intel.corp-partner.google.com>
-Tristan Corrick <tristan@corrick.kiwi> <tristancorrick86@gmail.com>
-Tyler Wang <tyler.wang@quanta.corp-partner.google.com> <Tyler.Wang@quanta.corp-partner.google.com>
-Usha P <usha.p@intel.com> <usha.p@intel.corp-partner.google.com>
-V Sujith Kumar Reddy <vsujithk@codeaurora.org>
-Vadim Bendebury <vbendeb@chromium.org> <vbendeb@google.com>
-Vaibhav Shankar <vaibhav.shankar@intel.com>
-Van Chen <van_chen@compal.corp-partner.google.com>
-Varshit Pandya <varshit.b.pandya@intel.com>
-Varshit Pandya <varshit.b.pandya@intel.com> Varshit B Pandya <varshit.b.pandya@intel.com>
-Varun Joshi <varun.joshi@intel.com> <varun.joshi@intel.corp-partner.google.com>
-Vincent Lim <vincent.lim@amd.com>  <Vincent Lim vincent.lim@amd.com>
-Vladimir Serbinenko <phcoder@gmail.com>
-Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> <Wayne3_Wang@pegatron.corp-partner.google.com>
-William Wu <wulf@rock-chips.com>
-Wim Vervoorn <wvervoorn@eltan.com>
-Wisley Chen <wisley.chen@quantatw.com>
-Wisley Chen <wisley.chen@quantatw.com> <wisley.chen@quanta.corp-partner.google.com>
-Xi Chen <xixi.chen@mediatek.com> <xixi.chen@mediatek.corp-partner.google.com>
-Xiang Wang <merle@hardenedlinux.org> <wxjstz@126.com>
-Xingyu Wu <wuxy@bitland.corp-partner.google.com>
-Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
-Yang A Fang <yang.a.fang@intel.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu at amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu@amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai@kernel.org>
-Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
-Yongqiang Niu <yongqiang.niu@mediatek.com>
-Youness Alaoui <snifikino@gmail.com> <kakaroto@kakaroto.homelinux.net>
-Youness Alaoui <snifikino@gmail.com> <youness.alaoui@puri.sm>
-Yu-Hsuan Hsu <yuhsuan@google.com>
-Yu-Hsuan Hsu <yuhsuan@google.com> <yuhsuan@chromium.org>
-Yu-Ping Wu <yupingso@google.com> <yupingso@chromium.org>
-Yuanlidingm <yuanliding@huaqin.corp-partner.google.com>
-Yuchen Huang <yuchen.huang@mediatek.com> <yuchen.huang@mediatek.corp-partner.google.com>
-Yuji Sasaki <sasakiy@chromium.org> <sasakiy@google.com>
-Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
-Zhi Li <lizhi7@huaqin.corp-partner.google.com>
-Zhongze Hu <frankhu@chromium.org> <frankhu@google.com>
-Zhuo-Hao Lee <zhuo-hao.lee@intel.com>
-Zhuohao Lee <zhuohao@chromium.org> <zhuohao@google.com>

Documentation/arch/x86/index.md

@@ -26,7 +26,9 @@ In order to add support for x86_64 the following assumptions were made:
 * A stage can install new page tables in RAM
 
 ## Page tables
-A `pagetables` cbfs file is generated based on an assembly file.
+Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
+the page tables to a file which is then included into the CBFS as file called
+`pagetables`.
 
 To generate the static page tables it must know the physical address where to
 place the file.

Documentation/community/code_of_conduct.md

@@ -115,4 +115,4 @@ Our arbitration team consists of the following people
 This Code of Conduct is distributed under
 a [Creative Commons Attribution-ShareAlike
 license](http://creativecommons.org/licenses/by-sa/3.0/).  It is based
-on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofconduct.org/)
+on the [Citizen Code of Conduct](http://citizencodeofconduct.org/)

Documentation/community/conferences.md

@@ -14,7 +14,7 @@ their development kit with them and conduct development sessions.
 
 [Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_facebook/)  by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebook.mp4)) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03)
 
-[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/congress/2018/wiki/index.php/Main_Page)
+[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018)
 ([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27)
 
 [coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018

Documentation/community/index.md

@@ -3,4 +3,5 @@
 * [Code of Conduct](code_of_conduct.md)
 * [Language style](language_style.md)
 * [Community forums](forums.md)
+* [Project services](services.md)
 * [coreboot at conferences](conferences.md)

Documentation/contributing/coding_style.md

@@ -960,55 +960,17 @@ asm ("magic %reg1, #42nt"
 	: /* outputs */ : /* inputs */ : /* clobbers */);
 ```
 
-GCC extensions
---------------
-
-GCC is the only officially-supported compiler for coreboot, and a
-variety of its C language extensions are heavily used throughout the
-code base. There have been occasional attempts to add clang as a second
-compiler option, which is generally compatible to the same language
-extensions that have been long-established by GCC.
-
-Some GCC extensions (e.g. inline assembly) are basically required for
-proper firmware development. Others enable more safe or flexible
-coding patterns than can be expressed with standard C (e.g. statement
-expressions and `typeof()` to avoid double evaluation in macros like
-`MAX()`). Yet others just add some simple convenience and reduce
-boilerplate (e.g. `void *` arithmetic).
-
-Since some GCC extensions are necessary either way, there is no gain
-from avoiding other GCC extensions elsewhere. The use of all official
-GCC extensions is expressly allowed within coreboot. In cases where an
-extension can be replaced by a 100% equivalent C standard feature with
-no extra boilerplate or loss of readability, the C standard feature
-should be preferred (this usually only happens when GCC retains an
-older pre-standardization extension for backwards compatibility, e.g.
-the old pre-C99 syntax for designated initializers). But if there is
-any advantage offered by the GCC extension (e.g. using GCC zero-length
-arrays instead of C99 variable-length arrays because they don't inhibit
-`sizeof()`), there is no reason to deprive ourselves of that, and "this
-is not C standard compliant" should not be a reason to argue against
-its use in reviews.
-
-This rule only applies to explicit GCC extensions listed in the
-"Extensions to the C Language Family" section of the GCC manual. Code
-should never rely on incidental GCC translation behavior that is not
-explicitly documented as a feature and could change at any moment.
-
 References
 ----------
 
 The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
-<https://duckduckgo.com/?q=isbn+0-13-110362-8> or
+<http://cm.bell-labs.com/cm/cs/cbook/>
-<https://www.google.com/search?q=isbn+0-13-110362-8.
-
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.
 Addison-Wesley, Inc., 1999. ISBN 0-201-61586-X. URL:
-<https://duckduckgo.com/?q=ISBN+0-201-61586-X> or
+<http://cm.bell-labs.com/cm/cs/tpop/>
-<https://www.google.com/search?q=ISBN+0-201-61586-X>
 
 GNU manuals - where in compliance with K&R and this text - for cpp, gcc,
 gcc internals and indent, all available from

Documentation/contributing/gsoc.md

@@ -33,25 +33,6 @@ Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
     framework for initial hardware initialization and you can help us succeed.
 
 
-## Collection of official GSoC guides & documents
-
-  * [Timeline][GSoC Timeline]
-
-  * [Roles and Responsibilities][GSoC Roles and Responsibilities]
-
-  * [Contributor Guide][GSoC Contributor Guide]
-
-  * [Contributor Advice][GSoC Contributor Advice]
-
-  * [Mentor Guide][GSoC Mentor Guide]
-
-  * [FAQ][GSoC FAQ]
-
-  * [Rules][GSoC Rules]
-
-  * [Glossary][GSoC Glossary]
-
-
 ## Contributor requirements & commitments
 
 Google Summer of Code is a significant time commitment for you. Medium-sized
@@ -91,8 +72,8 @@ amount of spare time. If this is not the case, then you should not apply.
       process and common issues.
 
     * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [easy project list][Project ideas] or ask for simple tasks on
+      Check Easy projects or ask for simple tasks on the [mailing list] or on our
-      the [mailing list] or on our other [community forums] if you need ideas.
+      other [community forums] if you need ideas.
 
 
 ### During the program
@@ -260,16 +241,9 @@ questions.
 [mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
 [Getting started]: ../getting_started/index.md
 [Tutorial]: ../tutorial/index.md
-[Flashing firmware tutorial]: ../tutorial/flashing_firmware/index.md
+[Flashing firmware tutorial]: ../flash_tutorial/index.md
 [Coding style]: coding_style.md
 [Code of Conduct]: ../community/code_of_conduct.md
 [Language style]: ../community/language_style.md
-[Project ideas]: project_ideas.md
-[GSoC Timeline]: https://developers.google.com/open-source/gsoc/timeline
-[GSoC Roles and Responsibilities]: https://developers.google.com/open-source/gsoc/help/responsibilities
 [GSoC Contributor Guide]: https://google.github.io/gsocguides/student
-[GSoC Contributor Advice]: https://developers.google.com/open-source/gsoc/help/student-advice
 [GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor
-[GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
-[GSoC Rules]: https://summerofcode.withgoogle.com/rules
-[GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary

Documentation/contributing/index.md

@@ -1,7 +1,6 @@
 # Contributing
 
 * [Coding Style](coding_style.md)
-* [Gerrit Guidelines](gerrit_guidelines.md)
 * [Project Ideas](project_ideas.md)
 * [Documentation Ideas](documentation_ideas.md)
 * [Google Summer of Code](gsoc.md)

Documentation/contributing/project_ideas.md

@@ -20,24 +20,6 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Easy projects
-
-This is a collection of tasks which don't require deep knowledge on
-coreboot itself. If you are a beginner and want to get familiar with the
-the project and the code base, or if you just want to get your hands
-dirty with some easy tasks, then these are for you.
-
-  * Resolve static analysis issues reported by [scan-build] and
-    [Coverity scan]. More details on the page for
-    [Coverity scan integration].
-
-  * Resolve issues reported by the [linter][Linter issues]
-
-[scan-build]: https://coreboot.org/scan-build/
-[Coverity scan]: https://scan.coverity.com/projects/coreboot
-[Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt
-
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
 working on coreboot and related projects. Sadly, building it takes hours,

Documentation/getting_started/gpio.md

@@ -167,61 +167,32 @@ could cause catastrophic failures, up to and including your mainboard!
 As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
 supports four different types of GPIO reset as:
 
-```eval_rst
+| PAD   Reset Config                              | Platform Reset | GPP | GPD |
-+------------------------+----------------+-------------+-------------+
+|-------------------------------------------------|----------------|-----|-----|
-|                        |                |         PAD Reset ?       |
+| 00 - Power Good (GPP: RSMRST,  GPD: DSW_PWROK)  | Warm Reset     | N   | N   |
-+ PAD Reset Config       + Platform Reset +-------------+-------------+
+|                                                 | Cold Reset     | N   | N   |
-|                        |                |     GPP     |     GPD     |
+|                                                 | S3/S4/S5       | N   | N   |
-+========================+================+=============+=============+
+|                                                 | Global Reset   | N   | N   |
-| | 00 - Power Good      |  Warm Reset    |     N       |    N        |
+|                                                 | Deep Sx        | Y   | N   |
-| | (GPP: RSMRST,        +----------------+-------------+-------------+
+|                                                 | G3             | Y   | N   |
-| | GPD: DSW_PWROK)      |  Cold Reset    |     N       |    N        |
+| 01 - Deep                                       | Warm Reset     | Y   | Y   |
-|                        +----------------+-------------+-------------+
+|                                                 | Cold Reset     | Y   | Y   |
-|                        |  S3/S4/S5      |     N       |    N        |
+|                                                 | S3/S4/S5       | N   | N   |
-|                        +----------------+-------------+-------------+
+|                                                 | Global Reset   | Y   | Y   |
-|                        |  Global Reset  |     N       |    N        |
+|                                                 | Deep Sx        | Y   | Y   |
-|                        +----------------+-------------+-------------+
+|                                                 | G3             | Y   | Y   |
-|                        |  Deep Sx       |     Y       |    N        |
+| 10 - Host Reset/PLTRST                          | Warm Reset     | Y   | Y   |
-|                        +----------------+-------------+-------------+
+|                                                 | Cold Reset     | Y   | Y   |
-|                        |  G3            |     Y       |    Y        |
+|                                                 | S3/S4/S5       | Y   | Y   |
-+------------------------+----------------+-------------+-------------+
+|                                                 | Global Reset   | Y   | Y   |
-| 01 - Deep              |  Warm Reset    |     Y       |    Y        |
+|                                                 | Deep Sx        | Y   | Y   |
-|                        +----------------+-------------+-------------+
+|                                                 | G3             | Y   | Y   |
-|                        |  Cold Reset    |     Y       |    Y        |
+| 11 - Resume Reset (GPP: Reserved,  GPD: RSMRST) | Warm Reset     | -   | N   |
-|                        +----------------+-------------+-------------+
+|                                                 | Cold Reset     | -   | N   |
-|                        |  S3/S4/S5      |     N       |    N        |
+|                                                 | S3/S4/S5       | -   | N   |
-|                        +----------------+-------------+-------------+
+|                                                 | Global Reset   | -   | N   |
-|                        |  Global Reset  |     Y       |    Y        |
+|                                                 | Deep Sx        | -   | Y   |
-|                        +----------------+-------------+-------------+
+|                                                 | G3             | -   | Y   |
-|                        |  Deep Sx       |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| 10 - Host Reset/PLTRST |  Warm Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Cold Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| | 11 - Resume Reset    |  Warm Reset    |     n/a     |    N        |
-| | (GPP: Reserved,      +----------------+-------------+-------------+
-| | GPD: RSMRST)         |  Cold Reset    |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     n/a     |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     n/a     |    Y        |
-+------------------------+----------------+-------------+-------------+
-```
 
 Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
 specific register fields in the PAD configuration register.

Documentation/getting_started/index.md

@@ -4,5 +4,7 @@
 * [Build System](build_system.md)
 * [Submodules](submodules.md)
 * [Kconfig](kconfig.md)
+* [Gerrit Guidelines](gerrit_guidelines.md)
+* [Documentation License](license.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)

Documentation/getting_started/kconfig.md

@@ -786,7 +786,7 @@ select <symbol> \[if <expr>\]
     config TPM
         bool
         default n
-        select MEMORY_MAPPED_TPM if ARCH_X86
+        select LPC_TPM if ARCH_X86
         select I2C_TPM if ARCH_ARM
         select I2C_TPM if ARCH_ARM64
         help

Documentation/getting_started/writing_documentation.md

@@ -159,5 +159,5 @@ TOC tree.
 [guide]: http://www.sphinx-doc.org/en/stable/install.html
 [Sphinx]: http://www.sphinx-doc.org/en/master/
 [Markdown Guide]: https://www.markdownguide.org/
-[Gerrit Guidelines]: ../contributing/gerrit_guidelines.md
+[Gerrit Guidelines]: gerrit_guidelines.md
 [review.coreboot.org]: https://review.coreboot.org

Documentation/index.md

@@ -188,6 +188,6 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Project infrastructure & services](infrastructure/index.md)
+* [coreboot infrastructure](infrastructure/index.md)
-* [Release notes](releases/index.md)
+* [Release notes for past releases](releases/index.md)
-* [Documentation License](documentation_license.md)
+* [Flashing firmware tutorial](flash_tutorial/index.md)

Documentation/infrastructure/builders.md

@@ -8,8 +8,8 @@ Let a jenkins admin know that you’re interested in setting up a jenkins
 build system.
 
 For a permanent build system, this should generally be a dedicated
-machine workstation or server class machine that is not generally being
+machine that is not generally being used for other purposes.  The
-used for other purposes.  The coreboot builds are very intensive.
+coreboot builds are very intensive.
 
 It's also best to be aware that although we don't know of any security
 issues, the jenkins-node image is run with the privileged flag which
@@ -26,40 +26,34 @@ Currently active Jenkins admins:
 *   Patrick Georgi:
     *   Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de)
     *   IRC: pgeorgi
-*   Martin Roth:
+
-    *   Email: [gaumless@gmail.com](mailto:gaumless@gmail.com)
-    *   IRC: martinr
 
 ### Build Machine requirements
 
-For a builder, we need a very fast system with lots of threads and
+For a builder, we need a fast system with lots of threads and plenty of
-plenty of RAM.  The builder builds and stores the git repos and output
+RAM.  The builder builds and stores the git repos and output in tmpfs
-in tmpfs along with the ccache save area, so if there isn't enough
+along with the ccache save area, so if there isn't enough memory, the
-memory, the builds will slow down because of smaller ccache areas and
+builds will slow down because of smaller ccache areas and can run into
-can run into "out of storage space" errors.
+"out of storage space" errors.
 
 #### Current Build Machines
 
 To give an idea of what a suitable build machine might be, currently the
-coreboot project has 4 active jenkins build machines.
+coreboot project has 3 active jenkins build machines.
-
-These times are taken from the week of Feb 21 - Feb 28, 2022
 
 * Congenialbuilder - 128 threads, 256GiB RAM
-  *  Fastest Passing coreboot gerrit build: 6 min, 47 sec
+  *  Fastest Passing coreboot gerrit build: 4 min, 30 sec
-  *  Slowest Passing coreboot gerrit build: 14 min
+  *  Slowest Passing coreboot gerrit build: 9 min, 56 sec
 
-* Gleefulbuilder - 64 thread, 64GiB RAM
-  *  Fastest Passing coreboot gerrit build: 10 min
-  *  Slowest Passing coreboot gerrit build: 46 min
 
-* Fabulousbuilder - 64 threads, 64GiB RAM
+* Gleeful builder - 64 thread, 64GiB RAM
-  *  Fastest Passing coreboot gerrit build: 7 min, 56 sec
+  *  Fastest Passing coreboot gerrit build: 6 min, 6 sec
-  *  Slowest Passing coreboot gerrit build: 56 min (No ccache)
+  *  Slowest Passing coreboot gerrit build, 34 min
+
 
 * Ultron (9elements) - 48 threads, 128GiB RAM
-  *  Fastest Passing coreboot gerrit build: 12
+  *  Fastest Passing coreboot gerrit build: 6 min, 32 sec
-  *  Slowest Passing coreboot gerrit build: 58 min
+  *  Slowest Passing coreboot gerrit build: 44 min
 
 
 ### Jenkins Builds
@@ -67,13 +61,13 @@ These times are taken from the week of Feb 21 - Feb 28, 2022
 There are a number of builds handled by the coreboot jenkins builders,
 for a number of different projects - coreboot, flashrom, memtest86+,
 em100, etc.  Many of these have builders for their current master branch
-as well as Gerrit and [Coverity](coverity.md) builds.
+as well as gerrit and coverity builds.
 
 You can see all the builds here:
 [https://qa.coreboot.org/](https://qa.coreboot.org/)
 
 Most of the time on the builders is taken up by the coreboot master and
-coreboot gerrit builds.
+gerrit builds.
 
 * [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
 ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
@@ -133,23 +127,10 @@ the machine remotely (if you allow them).
 
 ### Install and set up docker
 
-Install docker by following [the
+Install docker by following the
-directions](https://docs.docker.com/engine/install/) on the docker site.
+[directions](https://docs.docker.com/engine/install/) on the docker
-These instructions keep changing, so just check the latest information.
+site.  These instructions keep changing, so just check the latest
-
+information.
-
-### Set up the system for the jenkins builder
-
-As a regular user - *Not root*, run:
-
-```
-sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
-sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR}
-wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar
-mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR}
-```
 
 
 #### Set up environment variables
@@ -162,8 +143,8 @@ using something other than the default.
 # Set the port used on your machine to connect to jenkins.
 export COREBOOT_JENKINS_PORT=49151
 
-# Set the revision of the container from [docker hub](https://hub.docker.com/repository/docker/coreboot/coreboot-sdk)
+# Set the revision of the container from docker hub
-export DOCKER_COMMIT=2021-09-23_b0d87f753c
+export DOCKER_COMMIT=65718760fa
 
 # Set the location of where the jenkins cache directory will be.
 export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache"
@@ -218,6 +199,18 @@ Variables:
   DOCKER_COMMIT=65718760fa
 ```
 
+### Set up the system for the jenkins builder
+
+As a regular user - *Not root*, run:
+
+```
+sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
+sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
+sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
+sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR}
+wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar
+mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR}
+```
 
 ### Install the coreboot jenkins builder
 
@@ -233,17 +226,17 @@ machine profile on qa.coreboot.org.
 
 They need to know:
 *   Your external IP address or domain name.  If you don’t have a static
-    IP, make sure you have a dynamic dns hostname configured.
+IP, make sure you have a dynamic dns hostname configured.
 *   The port on your machine and firewall that’s exposed for jenkins:
-    `$COREBOOT_JENKINS_PORT`
+`$COREBOOT_JENKINS_PORT`
 *   The core count of the machine.
 *   How much memory is available on the machine.  This helps determine
-    the amount of memory used for ccache.
+the amount of memory used for ccache.
 
 
 ### First build
 On the first build after a machine is reset, it will frequently take
-an hour to do the entire what-jenkins-does build while the ccache
+20-25 minutes to do the entire what-jenkins-does build while the ccache
 is getting filled up and the entire coreboot repo gets downloaded.  As
 the ccache gets populated, the build time will drop.
 
@@ -261,12 +254,12 @@ the ccache gets populated, the build time will drop.
 
 
 WARNING: This should not be used to make changes to the build system,
-but just to debug issues. Changes to the build system image are highly
+but just to debug issues. Changes to the build system are highly
 discouraged as it leads to situations where patches can pass the build
 testing on one builder and fail on another builder. Any changes that are
 made in the image will be lost on the next update, so if you
-accidentally change something, you can remove the containers and images,
+accidentally change something, you can remove the containers and images
-then update to get a fresh installation.
+and update to get a fresh installation.
 
 
 ### How to download containers/images for a fresh installation and remove old containers
@@ -383,7 +376,6 @@ to be marked as a coverity builder.
 
 Download the Linux-64 coverity build tool and decompress it into your
 cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable
-on the jenkins server.
 
 [https://scan.coverity.com/download](https://scan.coverity.com/download)
 

Documentation/infrastructure/coverity.md

@@ -1,103 +0,0 @@
-# Coverity Scan for open source firmware
-
-## What’s Coverity and Coverity Scan?
-
-Coverity is a static analysis tool. It hooks into the build process
-and in addition to the compiler creating object files, Coverity collects
-information about the code. That data is then processed in a separate pass
-to identify common programming errors, like out of bounds accesses in C.
-
-Coverity Scan is an online service for Open Source projects providing this
-analysis for free. The analysis pass is done on their servers and issues
-can be handled in their [web UI](https://scan.coverity.com/).
-
-The Scan service has some quotas based on code size to avoid overloading
-the system, but even at one build per week, that’s usually good enough
-because the identified issues still need to be triaged and fixed or they
-will simply be re-identified next week.
-
-### Triage?
-
-The Web UI looks a bit like an issue tracker, even if it’s not a very
-good one. It’s possible to mark identified issues as valid or invalid,
-and annotate them with metadata which CLs fix them. The latter isn’t
-strictly necessary because Coverity Scan simply marks issues it can’t
-find anymore as fixed, but at times it helped identify issues that made
-a comeback.
-
-### Alternatives
-
-There’s also clang’s scan-build, which is fully open-source, and
-finds different issues. As such, it’s less of an alternative and more
-of a complement.
-
-There’s a regular run of that for coreboot but not for the other projects
-hosted at coreboot.org.
-
-One downside is that it emits a bunch of HTML to report on issues,
-but there’s no interactivity (e.g. marking issues solved), no way
-to merge multiple builds (e.g. multiple board builds of a single tree)
-or a simple way to extract burndown charts and the like from that.
-
-#### Looking for a project?
-
-On the upside, it can emit the data in a machine readable format, so if
-anybody needs a project, a scan-build web-frontend like Coverity Scan would
-be feasible without having to go through scan-build’s guts, just by parsing
-text files - plus all the stateful and web parts to build on top.
-
-## Logging into Coverity Scan
-
-Coverity Scan needs an account. It supports its own accounts and GitHub
-OAuth.
-
-Access to the dashboards needs approval: Request and you shall receive.
-
-## coreboot & friends and Coverity Scan
-
-coreboot, flashrom, Chromium EC and other projects of that family have
-been made Coverity aware, that is, their build systems support building
-with a custom compiler configuration passed in “just right” to enable
-Coverity to add its hooks.
-
-The public coreboot CI system at
-[https://qa.coreboot.org/](https://qa.coreboot.org/) regularly does
-builds with Coverity and sends them off to Coverity Scan.
-
-Specifically, it covers:
-
-* Chromium EC: [Coverity Scan site][crECCoverity] ([build job][crECBuildJob])
-* coreboot: [Coverity Scan site][corebootCoverity] ([build job][corebootBuildJob]), [scan-build output][corebootScanBuild] ([build job][corebootScanBuildJob])
-* em100: [Coverity Scan site][em100Coverity] ([build job][em100BuildJob])
-* fcode-utils: [Coverity Scan site][fcodeUtilsCoverity] ([build job][fcodeUtilsBuildJob])
-* flashrom: [Coverity Scan site][flashromCoverity] ([build job][flashromBuildJob])
-* memtest86+: [Coverity Scan site][memtestCoverity] ([build job][memtestBuildJob])
-* vboot: [Coverity Scan site][vbootCoverity] ([build job][vbootBuildJob])
-
-[crECCoverity]: https://scan.coverity.com/projects/chromium-ec
-[corebootCoverity]: https://scan.coverity.com/projects/coreboot
-[em100Coverity]: https://scan.coverity.com/projects/em100
-[fcodeUtilsCoverity]: https://scan.coverity.com/projects/fcode-utils
-[flashromCoverity]: https://scan.coverity.com/projects/flashrom
-[memtestCoverity]: https://scan.coverity.com/projects/memtest86
-[vbootCoverity]: https://scan.coverity.com/projects/vboot
-
-[corebootScanBuild]: https://www.coreboot.org/scan-build/
-
-[crECBuildJob]: https://qa.coreboot.org/view/coverity/job/ChromeEC-Coverity/
-[corebootBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot-coverity/
-[corebootScanBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot_scanbuild/
-[em100BuildJob]: https://qa.coreboot.org/view/coverity/job/em100-coverity/
-[fcodeUtilsBuildJob]: https://qa.coreboot.org/view/coverity/job/fcode-utils-coverity/
-[flashromBuildJob]: https://qa.coreboot.org/view/coverity/job/flashrom-coverity/
-[memtestBuildJob]: https://qa.coreboot.org/view/coverity/job/memtest86plus-coverity/
-[vbootBuildJob]: https://qa.coreboot.org/view/coverity/job/vboot-coverity/
-
-Some projects (e.g. Chromium EC) build a different subset of boards on
-each run, ensuring that everything is analyzed eventually. The downside
-is that coverity issues pop up and disappear somewhat randomly as they
-are discovered and go unnoticed in a later build.
-
-More projects that are hosted on review.coreboot.org (potentially as a
-mirror, like vboot and EC) could be served through that pipeline. Reach
-out to {stepan,patrick,martin}@coreboot.org.

Documentation/infrastructure/index.md

@@ -1,12 +1,6 @@
-# Project infrastructure & services
+# coreboot infrastructure
-
-This section contains documentation about our infrastructure
-
-## Services
-
-* [Project services](services.md)
 
+This section contains documentation about coreboot infrastructure
 
 ## Jenkins builders and builds
 * [Setting up Jenkins build machines](builders.md)
-* [Coverity Scan integration](coverity.md)

Documentation/mainboard/acer/g43t-am3.md

@@ -124,7 +124,7 @@ $ sudo flashrom \
 
 ```eval_rst
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
+:doc:`../../flash_tutorial/index`.
 ```
 
 ### External flashing

Documentation/mainboard/asrock/h110m-dvs.md

@@ -58,7 +58,7 @@ The main SPI flash can be accessed using [flashrom]. By default, only
 the BIOS region of the flash is writable. If you wish to change any
 other region, such as the Management Engine or firmware descriptor, then
 an external programmer is required (unless you find a clever way around
-the flash protection). More information about this [here](../../tutorial/flashing_firmware/index.md).
+the flash protection). More information about this [here](../../flash_tutorial/index.md).
 
 ### External programming
 
@@ -131,4 +131,4 @@ facing towards the bottom of the board.
 [ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
 [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2064Mb,%20v1.4.pdf
 [flashrom]: https://flashrom.org/Flashrom
-[H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
+[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf

Documentation/mainboard/asrock/h77pro4-m.md

@@ -115,7 +115,7 @@ region is not readable even by the host.
 
 ```eval_rst
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
+:doc:`../../flash_tutorial/index`.
 ```
 
 ## Hardware monitoring and fan control

Documentation/mainboard/asrock/h81m-hds.md

@@ -130,4 +130,4 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 [ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
 [W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
 [flashrom]: https://flashrom.org/Flashrom
-[Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
+[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf

Documentation/mainboard/asus/f2a85-m.md

@@ -190,9 +190,9 @@ This version is usable for all the GPUs.
 - [Board manual]
 - Flash chip datasheet [W25Q64FV]
 
-[ASUS F2A85-M]: https://web.archive.org/web/20160320065008/http://www.asus.com/Motherboards/F2A85M/
+[ASUS F2A85-M]: https://www.asus.com/Motherboards/F2A85M/
-[Board manual]: https://web.archive.org/web/20211028063105/https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
 [flashrom]: https://flashrom.org/Flashrom
 [Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
 [TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
-[W25Q64FV]: https://web.archive.org/web/20220127184640/https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf

Documentation/mainboard/asus/p5q.md

@@ -130,5 +130,5 @@ You can also control the CPU fan with similar rules:
     echo 2000 >/sys/class/hwmon/hwmon2/pwm1_tolerance
 
 [ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
-[this guide]: ../../tutorial/flashing_firmware/int_flashrom.md
+[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
 [kernel docs]: https://www.kernel.org/doc/Documentation/hwmon/w83627ehf.rst

Documentation/mainboard/asus/p8h61-m_lx.md

@@ -106,6 +106,6 @@ region is not readable even by the host.
 - [Flash chip datasheet][W25Q32BV]
 
 [ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
-[W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
+[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
 [flashrom]: https://flashrom.org/Flashrom
 [Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip

Documentation/mainboard/emulation/qemu-riscv.md

@@ -1,8 +1,8 @@
-# QEMU RISC-V emulator
+# Qemu RISC-V emulator
 
-## Building coreboot and running it in QEMU
+## Building coreboot and running it in Qemu
 
 - Configure coreboot and run `make` as usual
 - Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
-  convert coreboot to an ELF that QEMU can load
+  convert coreboot to an ELF that Qemu can load
 - Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`

Documentation/mainboard/gigabyte/ga-g41m-es2l.md

@@ -142,7 +142,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
 
 ```eval_rst
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
+:doc:`../../flash_tutorial/index`.
 ```
 
 ### Do backup

Documentation/mainboard/hp/2560p.md

@@ -94,6 +94,6 @@ Schematic of this laptop can be found on [Lab One].
 
 [HP EliteBook 2560p]: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201
 [Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03011618
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [Lab One]: https://www.laboneinside.com/hp-elitebook-2560p-schematic-diagram/
 [bug #141]: https://ticket.coreboot.org/issues/141

Documentation/mainboard/index.md

@@ -48,11 +48,10 @@ This section contains documentation about coreboot on specific mainboards.
 The boards in this section are not real mainboards, but emulators.
 
 - [Spike RISC-V emulator](emulation/spike-riscv.md)
-- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
+- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
-- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
+- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
-- [QEMU x86 Q35](emulation/qemu-q35.md)
+- [Qemu x86 Q35](emulation/qemu-q35.md)
-- [QEMU x86 PC](emulation/qemu-i440fx.md)
+- [Qemu x86 PC](emulation/qemu-i440fx.md)
-- [QEMU POWER9](emulation/qemu-power9.md)
 
 ## Facebook
 
@@ -180,14 +179,10 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Star Labs Systems
 
-- [LabTop Mk IV](starlabs/labtop_cml.md)
-- [StarLite Mk III](starlabs/lite_glk.md)
-- [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
 
 ## Supermicro
 
-- [X9SAE](supermicro/x9sae.md)
 - [X10SLM+-F](supermicro/x10slm-f.md)
 - [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
 - [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -38,7 +38,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
 * ROM chip size should be set to 12MiB.
 
 ```eval_rst
-Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
+Please also have a look at :doc:`../../flash_tutorial/index`.
 ```
 
 ## Splitting the coreboot.rom
@@ -90,4 +90,4 @@ Tests on Lenovo W530 showed no issues with a stripped and shrunken ME firmware.
 
 
 [me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
-[external programmer]: ../../tutorial/flashing_firmware/index.md
+[external programmer]: ../../flash_tutorial/index.md

Documentation/mainboard/lenovo/Sandy_Bridge_series.md

@@ -70,5 +70,5 @@ the remaining space for the `bios` partition.
 
 
 [me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
-[external programmer]: ../../tutorial/flashing_firmware/index.md
+[external programmer]: ../../flash_tutorial/index.md
-[flashing tutorial]: ../../tutorial/flashing_firmware/index.md
+[flashing tutorial]: ../../flash_tutorial/index.md

Documentation/mainboard/lenovo/ivb_internal_flashing.md

@@ -353,12 +353,9 @@ Verify that it worked:
 
 Bingo!
 
-Now you can [flash internally]. Remember to flash only the `bios` region
+Now you can [flash internally](/flash_tutorial/int_flashrom.md).
-(use `--ifd -i bios -N` flashrom arguments). `fd` and `me` are still
+Remember to flash only the `bios` region (use `--ifd -i bios -N`
-locked.
+flashrom arguments). `fd` and `me` are still locked.
 
 Note that you should have an external SPI programmer as a backup method.
 It will help you recover if you flash non-working ROM by mistake.
-
-
-[flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md

Documentation/mainboard/lenovo/t410.md

@@ -37,7 +37,7 @@ The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG.
 Do not rely on dots painted in the corner of the chip (such as the blue dot
 pictured) to orient the pins!
 
-[Flashing tutorial](../../tutorial/flashing_firmware/no_ext_power.md)
+[Flashing tutorial](../../flash_tutorial/no_ext_power.md)
 
 Steps to access the flash IC are described here [T4xx series].
 

Documentation/mainboard/lenovo/t420.md

@@ -53,5 +53,5 @@ Steps to access the flash IC are described here [T4xx series].
  * Suspend (Windows 10)
 
 [T4xx series]: t4xx_series.md
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md

Documentation/mainboard/lenovo/t430.md

@@ -9,6 +9,6 @@ the general [flashing tutorial].
 
 Steps to access the flash IC are described here [T4xx series].
 
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T4xx series]: t4xx_series.md
 [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md

Documentation/mainboard/lenovo/w530.md

@@ -22,5 +22,5 @@ the general [flashing tutorial].
 
 [w530-2]: w530-2.jpg
 
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md

Documentation/mainboard/lenovo/x1.md

@@ -18,5 +18,5 @@ the general [flashing tutorial].
 Steps to access the flash IC are described here [X2xx series].
 
 [X2xx series]: x2xx_series.md
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md

Documentation/mainboard/lenovo/x230s.md

@@ -16,4 +16,4 @@ is located at the circled place.
 
 Unlike [most Ivy Bridge ThinkPads](Ivy_Bridge_series.md), X230s has a single 16MiB SPI flash chip.
 
-The general [flashing tutorial](../../tutorial/flashing_firmware/index.md) has more details.
+The general [flashing tutorial](../../flash_tutorial/index.md) has more details.

Documentation/mainboard/lenovo/x301.md

@@ -43,5 +43,5 @@ Tested:
   Linux payload (Heads) and SeaBIOS.
 
 
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 

Documentation/mainboard/msi/ms7707/ms7707.md

@@ -74,7 +74,7 @@ seconds. Setting the jumper alone is not enough (the Fintek is VBAT backed).
 Put all back in place and restart the board. It might need 1-2 AC power cycles
 to reinitialize (running at full fan speed - don't panic).
 * External flashing has been tested with RPi2 without main power connected.
-3.3V provided by RPi2. Read more about [flashing methods].
+3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html).
 * In case of going back to proprietary BIOS create/save CMOS settings as early
 as possible (do not leave BIOS on first start without saving settings).
 The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state
@@ -110,4 +110,3 @@ needed (internally re-routed already).
 [Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
 [Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html
 [flashlayout]: flashlayout.svg
-[flashing methods]: ../../../tutorial/flashing_firmware/index.md

Documentation/mainboard/prodrive/hermes.md

@@ -49,6 +49,6 @@ The board features:
 ## Extra links
 
 [flashrom]: https://flashrom.org/Flashrom
-[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
 [Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
 [AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440

Documentation/mainboard/starlabs/common/flashing.md

@@ -1,71 +0,0 @@
-# Flashing with fwupd
-
-#### **Requirements:**
-
-* fwupd version 1.5.6 or later
-* The battery must be charged to at least 30%
-* The charger must be connected (either USB-C or DC Jack)
-* BIOS Lock must be disabled
-* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)
-
-**fwupd 1.5.6 or later**
-To check the version of **fwupd** you have installed, open a terminal window and enter the below command:
-
-```
-fwupdmgr --version
-```
-
-This will show the version number. **1.5.6** or greater will work.
-![fwupd version](fwupdVersion.png)
-On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
-
-```
-sudo add-apt-repository ppa:starlabs/ppa
-sudo apt update
-sudo apt install fwupd
-```
-
-On Manjaro:
-
-```
-sudo pacman -Sy fwupd-git flashrom-starlabs
-```
-
-Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.
-
-**Disable BIOS Lock**
-BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:
-
-1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
-2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
-3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
-
-![Disable BIOS Lock](BiosLock.jpg)
-
-4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
-
-#### **Switching Branch**
-
-Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
-
-First, check for new firmware files with the below terminal command:
-
-```
-fwupdmgr refresh --force
-```
-
-Then, to change branch, enter the below terminal command:
-
-```
-fwupdmgr switch-branch
-```
-
-You can then select which branch you would like to use, by typing in the corresponding number:
-![Switch Branch](SwitchBranch.png)
-You will be prompted to confirm, press `y` to continue or `n` to cancel.
-
-Once the switch has been completed, you will be prompted to restart.
-
-The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.
-
-You can switch branch at any time.

Documentation/mainboard/starlabs/labtop_cml.md

@@ -1,87 +0,0 @@
-# Star LabTop Mk IV
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-10710U (Comet Lake)
-    - Intel i3-10110U (Comet Lake)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 620
-    - GOP driver is recommended, VBT is provided
-    - eDP 13-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 16GB on-board *1
-- Networking
-    - AX201 CNVi WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - USB 3.1 Gen 2 Type-C (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c`
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 16 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glk.md

@@ -1,83 +0,0 @@
-# StarLite Mk III
-
-## Specs
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel N5000 (Gemini Lake)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 605
-    - GOP driver is recommended, VBT is provided
-    - eDP 11.6-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 9462 CNVi WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC269
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 SATA SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 640x480 CCD camera
-    - USB 3.1 Gen 1 Type-C (left)
-    - USB 3.1 Gen 1 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | GD25LQ64(B)|
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glkr.md

@@ -1,82 +0,0 @@
-# StarLite Mk III
-
-## Specs
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel N5030 (Gemini Lake Refresh)
-- EC
-    - Nuvoton NPCE985P/G
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 605
-    - GOP driver is recommended, VBT is provided
-    - eDP 11.6-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 9461 CNVi WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC269
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 SATA SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1200x1600 CCD camera
-    - USB 3.1 Gen 1 Type-C (left)
-    - USB 3.1 Gen 1 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* IFWI Image (ifwi.rom)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | GD25LQ64(B)|
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -83,4 +83,72 @@ make
 | External flashing   | yes        |
 +---------------------+------------+
 
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
+#### **Requirements:**
+
+* fwupd version 1.5.6 or later
+* The battery must be charged to at least 30%
+* The charger must be connected (either USB-C or DC Jack)
+* BIOS Lock must be disabled
+* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)
+
+**fwupd 1.5.6 or later**
+To check the version of **fwupd** you have installed, open a terminal window and enter the below command:
+
+```
+fwupdmgr --version
+```
+
+This will show the version number. **1.5.6** or greater will work.
+![fwupd version](fwupdVersion.png)
+On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
+
+```
+sudo add-apt-repository ppa:starlabs/ppa
+sudo apt update
+sudo apt install fwupd
+```
+
+On Manjaro:
+
+```
+sudo pacman -Sy fwupd-git flashrom-starlabs
+```
+
+Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.
+
+**Disable BIOS Lock**
+BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:
+
+1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
+2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
+3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
+
+![Disable BIOS Lock](BiosLock.jpg)
+
+4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
+
+#### **Switching Branch**
+
+Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
+
+First, check for new firmware files with the below terminal command:
+
+```
+fwupdmgr refresh --force
+```
+
+Then, to change branch, enter the below terminal command:
+
+```
+fwupdmgr switch-branch
+```
+
+You can then select which branch you would like to use, by typing in the corresponding number:
+![Switch Branch](SwitchBranch.png)
+You will be prompted to confirm, press `y` to continue or `n` to cancel.
+
+Once the switch has been completed, you will be prompted to restart.
+
+The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.
+
+You can switch branch at any time.

Documentation/mainboard/supermicro/x10slm-f.md

@@ -42,7 +42,7 @@ Now, run `make` to build the coreboot image.
 
 ```eval_rst
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
+:doc:`../../flash_tutorial/index`.
 ```
 
 ### Internal programming

Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md

@@ -56,6 +56,6 @@ These issues apply to all boards. Have a look at the board-specific issues, too.
 [Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
 [OpenBMC]: https://www.openbmc.org/
 [flashrom]: https://flashrom.org/Flashrom
-[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
 [Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
 [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376

Documentation/mainboard/supermicro/x9sae.md

@@ -41,9 +41,10 @@ first, otherwise ME may write something back and break the firmware you write.
 The following command may be used to flash coreboot. (To do so, linux kernel
 could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module)
 
-Now you can [flash internally]. It is recommended to flash only the `bios`
+Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is
-region (use `--ifd -i bios -N` flashrom arguments), in order to minimize the
+recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom
-chances of messing something up in the beginning.
+arguments), in order to minimize the chances of messing something up in the
+beginning.
 
 The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy
 to do in-system programming, or remove and flash externally if it is socketed.
@@ -105,4 +106,3 @@ seems that it shall not appear on X9SAE even if it is defined.
 [X9SAE-V]:  https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
 [W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
 [flashrom]: https://flashrom.org/Flashrom
-[flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md

Documentation/mainboard/system76/oryp8.md

@@ -10,14 +10,14 @@
   - ITE IT570E running [System76 EC](https://github.com/system76/ec)
 - Graphics
   - dGPU options
-    - NVIDIA GeForce RTX 3070 (Max-Q)
+    - NVIDIA GeForce RTX 3070
-    - NVIDIA GeForce RTX 3080 (Max-Q)
+    - NVIDIA GeForce RTX 3080
   - eDP options
-    - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
+    - 15.6" 1920x1080@144Hz LCD
-    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
+    - 17.3" 1920x1080@144Hz LCD
-  - 1x HDMI 2.1
+  - 1x HDMI
-  - 1x Mini DisplayPort 1.4
+  - 1x Mini DisplayPort
-  - 1x DisplayPort 1.4 over USB-C
+  - 1x DisplayPort over USB-C
 - Memory
   - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
 - Networking
@@ -26,13 +26,13 @@
     - Intel Wi-Fi 6 AX200/AX201
 - Power
   - 180W (19.5V, 9.23A) AC barrel adapter
-    - Lite-On PA-1181-16, using a C5 power cord
+    - Lite-On PA-1181-16
   - 73Wh 3-cell battery
 - Sound
   - Realtek ALC1220 codec
   - TI TAS5825M smart amp
   - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm headphone/microphone jack
   - Combined 3.5mm microphone & S/PDIF jack
   - HDMI, mDP, USB-C DP audio
 - Storage
@@ -41,9 +41,6 @@
 - USB
   - 1x USB Type-C with Thunderbolt 4
   - 3x USB 3.0 Type-A
-- Dimensions
-  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
-  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
 
 ## Flashing coreboot
 

Documentation/mainboard/ti/beaglebone-black.md

@@ -127,5 +127,5 @@ ROM.
   hang on a bad SD card or when the SD card is removed during boot.
 
 
-[Beaglebone Black]: https://beagleboard.org/black
+[Beaglebone Black]: https://beagleboard.org/black [U-Boot Falcon mode]:
-[U-Boot Falcon mode]: https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon
+https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon

Documentation/northbridge/intel/sandybridge/me_cleaner.md

@@ -81,4 +81,4 @@ Make sure to include all partitions into the ROM:
 * ME
 * BIOS
 
-[external programmer]: ../../../tutorial/flashing_firmware/index.md
+[external programmer]: ../../../flash_tutorial/index.md

Documentation/releases/checklist.md

@@ -1,7 +1,3 @@
-```eval_rst
-:orphan:
-```
-
 # coreboot Release Process
 
 This document describes our release process and all prerequisites to implement

Documentation/releases/coreboot-4.15-relnotes.md

@@ -25,7 +25,7 @@ New mainboards
 * Google nipperkin
 * Lenovo w541
 * Siemens mc_ehl
-* Supermicro x9sae
+* SuperMicro x9sae
 * System76 addw1
 * System76 addw2
 * System76 bonw14

Documentation/releases/index.md

@@ -1,37 +1,36 @@
-# Release notes
+Release notes for previous releases
+===================================
 
-## Upcoming release
+* [4.1 - July 2015](coreboot-4.1-relnotes.md)
+* [4.2 - October 2015](coreboot-4.2-relnotes.md)
+* [4.3 - January 2016](coreboot-4.3-relnotes.md)
+* [4.4 - May 2016](coreboot-4.4-relnotes.md)
+* [4.5 - October 2016](coreboot-4.5-relnotes.md)
+* [4.6 - April 2017](coreboot-4.6-relnotes.md)
+* [4.7 - January 2018](coreboot-4.7-relnotes.md)
+* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.9 - December 2018](coreboot-4.9-relnotes.md)
+* [4.10 - July 2019](coreboot-4.10-relnotes.md)
+* [4.11 - November 2019](coreboot-4.11-relnotes.md)
+* [4.12 - May 2020](coreboot-4.12-relnotes.md)
+* [4.13 - November 2020](coreboot-4.13-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)
+* [4.15 - November 2021](coreboot-4.15-relnotes.md)
+* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 
-Please add to the release notes as changes are added:
+The checklist contains instructions to ensure that a release covers all
-* [4.17 - May 2022](coreboot-4.17-relnotes.md)
-
-The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
 names etc.
 
-For release related communications consider using a [template] so everything
+* [checklist](checklist.md)
+
+For release related communications consider using a template so everything
 important is taken care of.
 
+* [templates](templates.md)
 
-## Previous releases
+Upcoming release
+----------------
 
-* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
+Please add to the release notes as changes are added:
-* [4.15 - November 2021](coreboot-4.15-relnotes.md)
+* [4.17 - May 2022](coreboot-4.17-relnotes.md)
-* [4.14 - May 2021](coreboot-4.14-relnotes.md)
-* [4.13 - November 2020](coreboot-4.13-relnotes.md)
-* [4.12 - May 2020](coreboot-4.12-relnotes.md)
-* [4.11 - November 2019](coreboot-4.11-relnotes.md)
-* [4.10 - July 2019](coreboot-4.10-relnotes.md)
-* [4.9 - December 2018](coreboot-4.9-relnotes.md)
-* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
-* [4.7 - January 2018](coreboot-4.7-relnotes.md)
-* [4.6 - April 2017](coreboot-4.6-relnotes.md)
-* [4.5 - October 2016](coreboot-4.5-relnotes.md)
-* [4.4 - May 2016](coreboot-4.4-relnotes.md)
-* [4.3 - January 2016](coreboot-4.3-relnotes.md)
-* [4.2 - October 2015](coreboot-4.2-relnotes.md)
-* [4.1 - July 2015](coreboot-4.1-relnotes.md)
-
-
-[checklist]: checklist.md
-[template]: templates.md

Documentation/releases/templates.md

@@ -1,7 +1,3 @@
-```eval_rst
-:orphan:
-```
-
 # Communication templates related to release management
 
 ## Deprecation notices

Documentation/security/vboot/list_vboot.md

@@ -206,7 +206,6 @@
 - Stout (Lenovo Thinkpad X131e Chromebook)
 - Bubs
 - Coachz
-- Gelarshie
 - Homestar
 - Kingoftown
 - Lazor

Documentation/tutorial/index.md

@@ -4,4 +4,3 @@
 * [Part 2: Submitting a patch to coreboot.org](part2.md)
 * [Part 3: Writing unit tests](part3.md)
 * [Managing local additions](managing_local_additions.md)
-* [Flashing firmware](flashing_firmware/index.md)

Documentation/tutorial/part1.md

@@ -12,7 +12,7 @@ Download, configure, and build coreboot
 ### Step 1 - Install tools and libraries needed for coreboot
     $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
     $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib
-    $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel patch
+    $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel
 
 ### Step 2 - Download coreboot source tree
     $ git clone https://review.coreboot.org/coreboot

MAINTAINERS

@@ -298,14 +298,6 @@ M:	Damien Zammit <damien@zamaudio.com>
 S:	Odd Fixes
 F:	src/mainboard/intel/d510mo/
 
-INTEL HARCUVAR_CRB MAINBOARD
-M:	Jeff Daly <jeffd@silicom-usa.com>
-M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
-M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
-M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
-S:	Maintained
-F:	src/mainboard/intel/harcuvar/
-
 INTEL STRAGO MAINBOARD
 M:	Hannah Williams <hannah.williams@intel.com>
 S:	Supported
@@ -330,6 +322,7 @@ F:	src/mainboard/kontron/mal10/
 
 LENOVO MAINBOARDS
 M:	Alexander Couzens <lynxis@fe80.eu>
+M:	Patrick Rudolph <siro@das-labor.org>
 S:	Maintained
 F:	src/mainboard/lenovo/
 
@@ -450,7 +443,6 @@ SIEMENS MC_xxxx MAINBOARDS
 M:	Werner Zeh <werner.zeh@siemens.com>
 S:	Maintained
 F:	src/mainboard/siemens/mc_apl1/
-F:	src/mainboard/siemens/mc_ehl/
 
 
 
@@ -582,6 +574,7 @@ F:	src/southbridge/amd/
 F:	src/include/cpu/amd/
 
 INTEL SUPPORT
+M:	Patrick Rudolph <siro@das-labor.org>
 S:	Maintained
 F:	src/vendorcode/intel/
 F:	src/cpu/intel/
@@ -591,6 +584,15 @@ F:	src/soc/intel/
 F:	src/drivers/intel/
 F:	src/include/cpu/intel/
 
+INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
+M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
+M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
+M:	Michal Motyl <michalx.motyl@intel.com>
+M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
+S:	Maintained
+F:	src/mainboard/intel/harcuvar/
+F:	src/soc/intel/denverton_ns/
+
 INTEL FSP 1.1
 M:	Lee Leahy <leroy.p.leahy@intel.com>
 M:	Huang Jin <huang.jin@intel.com>
@@ -670,14 +672,6 @@ S:	Maintained
 F:	/src/soc/intel/braswell/
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
 
-INTEL DENVERTON-NS SOC
-M:	Jeff Daly <jeffd@silicom-usa.com>
-M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
-M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
-M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
-S:	Maintained
-F:	src/soc/intel/denverton_ns/
-
 INTEL TIGERLAKE SOC
 M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
@@ -881,7 +875,7 @@ F:	src/security/tpm/
 
 SUPERIOS & SUPERIOTOOL
 M:	Felix Held <felix-coreboot@felixheld.de>
-S:	Odd Fixes
+S:	Maintained
 F:	src/superio/
 F:	util/superiotool/
 

Makefile

@@ -193,7 +193,6 @@ strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
 real-all: real-target
 
 # must come rather early
-.SECONDARY:
 .SECONDEXPANSION:
 .DELETE_ON_ERROR:
 
@@ -470,10 +469,10 @@ doxyclean: doxygen-clean
 doxygen-clean:
 	rm -rf $(DOXYGEN_OUTPUT_DIR)
 
-clean-for-update: doxygen-clean
+clean-for-update: doxygen-clean clean-for-update-target
 	rm -rf $(obj) .xcompile
 
-clean: clean-for-update clean-utils clean-payloads
+clean: clean-for-update clean-target clean-utils
 	rm -f .ccwrap
 
 clean-cscope:

Makefile.inc

@@ -81,9 +81,8 @@ PHONY+= clean-abuild coreboot check-style build_complete
 # root source directories of coreboot
 subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
-subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
+subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
-subdirs-y += $(wildcard src/northbridge/*/*)
+subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*)
-subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildcard src/superio/*/*)
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*)
 subdirs-y += src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool
@@ -261,6 +260,9 @@ endef
 # ResourceTemplate is the correct code.
 # As it's valid ASL, disable the warning.
 EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
+# Redundant offset remarks are not useful in any way and are masking useful
+# ones that might indicate an issue so it is better to hide them.
+REDUNDANT_OFFSET_REMARK = 2158
 # IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
 #	1) If _PRS is present, must have _CRS and _SRS
 #	2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
@@ -277,8 +279,8 @@ ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
 build_complete::
 	printf "*** WARNING: The ASL code for this platform is incomplete.  Please fix it. ***\n"
 	printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
-	printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
+	printf "*** If _SRS is present, must have _PRS, _CRS, and _SRS ***\n"
-	printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
+	printf "*** If _DIS is present, must have _SRS, _PRS, _CRS, and _SRS ***\n"
 endif
 
 IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
@@ -337,7 +339,7 @@ endef
 # arg1: C source file
 # arg2: binary file
 cbfs-files-processor-struct= \
-	$(eval $(2): $(1) $(obj)/build.h $(obj)/fmap_config.h $(KCONFIG_AUTOHEADER); \
+	$(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
 		printf "    CC+STRIP   $(1)\n"; \
 		$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) --param asan-globals=0 $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
 		$(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
@@ -673,6 +675,19 @@ decompressor-y += $(CONFIG_MEMLAYOUT_LD_FILE)
 clean-abuild:
 	rm -rf coreboot-builds
 
+clean-for-update-target: clean-payloads
+	rm -f $(obj)/ramstage?* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
+	rm -rf $(obj)/bootblock?* $(obj)/romstage?* $(obj)/location.*
+	rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/dsdt.*
+	rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm
+
+clean-target:
+	rm -f $(obj)/coreboot*
+
 #######################################################################
 # Development utilities
 printcrt0s:
@@ -776,14 +791,11 @@ endif
 $(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
 	cp $< $@
 
-$(objcbfs)/%.map: $(objcbfs)/%.debug
+$(objcbfs)/%.elf: $(objcbfs)/%.debug
-	$(eval class := $(call find-class,$(@F)))
-	$(NM_$(class)) -n $< | sort > $(basename $@).map
-
-$(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
 	$(eval class := $(call find-class,$(@F)))
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
 	cp $< $@.tmp
+	$(NM_$(class)) -n $@.tmp | sort > $(basename $@).map
 	$(OBJCOPY_$(class)) --strip-debug $@.tmp
 	$(OBJCOPY_$(class)) --add-gnu-debuglink=$< $@.tmp
 	mv $@.tmp $@
@@ -1100,10 +1112,6 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
 endif
 
-# coreboot.pre doesn't follow the standard Make conventions. It gets modified
-# by multiple rules, and thus we can't compute the dependencies correctly.
-$(shell rm -f $(obj)/coreboot.pre)
-
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)

payloads/coreinfo/coreboot_module.c

@@ -94,8 +94,10 @@ static int coreboot_module_redraw(WINDOW *win)
 			mvwprintw(win, row++, 3, "   Table: ");
 		}
 
-		wprintw(win, "%16.16llx - %16.16llx", cb_info.range[i].start,
+		wprintw(win, "%16.16llx - %16.16llx",
-			cb_info.range[i].start + cb_info.range[i].size - 1);
+			cb_unpack64(cb_info.range[i].start),
+			cb_unpack64(cb_info.range[i].start) +
+			cb_unpack64(cb_info.range[i].size) - 1);
 	}
 
 	return 0;

payloads/external/LinuxBoot/Kconfig

@@ -177,15 +177,15 @@ if LINUXBOOT_UROOT
 
 choice
 	prompt "U-root version"
-	default LINUXBOOT_UROOT_MAIN
+	default LINUXBOOT_UROOT_MASTER
 
 config LINUXBOOT_UROOT_CUSTOM
 	bool "custom"
 	help
 	  choose a custom u-root branch
 
-config LINUXBOOT_UROOT_MAIN
+config LINUXBOOT_UROOT_MASTER
-	bool "main"
+	bool "master"
 	help
 	  Latest u-root version
 
@@ -207,7 +207,7 @@ config LINUXBOOT_UROOT_CHECKOUT
 config LINUXBOOT_UROOT_VERSION
 	string
 	default LINUXBOOT_UROOT_CHECKOUT if LINUXBOOT_UROOT_CUSTOM
-	default "main" if LINUXBOOT_UROOT_MAIN
+	default "master" if LINUXBOOT_UROOT_MASTER
 	default "v3.0.0" if LINUXBOOT_UROOT_V3_0_0
 	default "v2.0.0" if LINUXBOOT_UROOT_V2_0_0
 	default "v1.0.0" if LINUXBOOT_UROOT_V1_0_0

payloads/external/LinuxBoot/targets/u-root.mk

@@ -39,7 +39,7 @@ endif
 
 get: version
 	if [ -d "$(go_path_dir)/src/$(uroot_package)" ]; then \
-	git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet main; \
+	git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet master; \
 	GOPATH=$(go_path_dir) go get -d -u -v $(uroot_package) || \
 	echo -e "\n<<u-root package update failed>>\n"; \
 	else \

payloads/external/SeaBIOS/Kconfig

@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.16.0"
+	bool "1.14.0"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER

payloads/external/SeaBIOS/Makefile

@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=d239552ce7220e448ae81f41515138f7b9e3c4db
+TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://review.coreboot.org/seabios.git

payloads/external/depthcharge/Makefile

@@ -68,8 +68,6 @@ $(libpayload_install_dir): $(project_dir)
 		false)
 	echo $(DEPTHCHARGE_LIBPAYLOAD_MSG)
 	cp $(libpayload_config) $(libpayload_dir)/.config
-	(grep -q '^\s*CONFIG_LP_CHROMEOS=' $(libpayload_dir)/.config) || \
-		(echo "CONFIG_LP_CHROMEOS=y" >> $(libpayload_dir)/.config)
 	$(MAKE) -C $(libpayload_dir) olddefconfig
 	$(MAKE) -C $(libpayload_dir)
 	$(MAKE) -C $(libpayload_dir) install DESTDIR=$(libpayload_install_dir)

payloads/external/iPXE/Kconfig

@@ -31,12 +31,12 @@ choice
 	depends on BUILD_IPXE
 
 config IPXE_STABLE
-	bool "2022.1"
+	bool "2019.3"
 	help
 	  iPXE uses a rolling release with no stable version, for
 	  reproducibility, use the last commit of a given month as the
 	  'stable' version.
-	  This is iPXE from the end of January, 2022.
+	  This is iPXE from the end of March, 2019.
 
 config IPXE_MASTER
 	bool "master"

payloads/external/iPXE/Makefile

@@ -1,8 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-# 2022.1 - Last commit of January 2022
+# 2019.3 - Last commit of March 2019
 # When updating, change the name both here and in payloads/external/iPXE/Kconfig
-STABLE_COMMIT_ID=6ba671acd922ee046b257c5119b8a0f64d275473
+STABLE_COMMIT_ID=ebf2eaf515e46abd43bc798e7e4ba77bfe529218
 
 TAG-$(CONFIG_IPXE_MASTER)=origin/master
 TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID)

payloads/external/tianocore/Kconfig

@@ -127,7 +127,7 @@ config TIANOCORE_BOOT_MANAGER_ESCAPE
 	  the default key of F2.
 
 config TIANOCORE_BOOT_TIMEOUT
-	int "Set the timeout for boot menu prompt"
+	int
 	default 2
 	help
 	  The length of time in seconds for which the boot splash/menu prompt will be displayed.

payloads/external/tianocore/Makefile

@@ -49,7 +49,7 @@ ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
 BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
 endif
 # PLATFORM_BOOT_TIMEOUT		= 3
-ifneq ($(CONFIG_TIANOCORE_BOOT_TIMEOUT),)
+ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
 BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
 endif
 # SIO_BUS_ENABLE		= FALSE
@@ -82,6 +82,8 @@ endif
 
 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
 
+export EDK_TOOLS_PATH=$(project_dir)/BaseTools
+
 all: clean build
 
 $(project_dir):

payloads/libpayload/bin/lpgcc

@@ -182,14 +182,6 @@ trygccoption -fno-stack-protector
 _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
 _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
 
-if [ "$CONFIG_LP_VBOOT_LIB" = y ]; then
-	if [ "$CONFIG_LP_VBOOT_TPM2_MODE" = y ]; then
-		_CFLAGS="$_CFLAGS -DTPM2_MODE"
-	else
-		_CFLAGS="$_CFLAGS -DTPM1_MODE"
-	fi
-fi
-
 _LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections"
 
 if [ $DOLINK -eq 0 ]; then

payloads/libpayload/drivers/cbmem_console.c

@@ -80,28 +80,11 @@ void cbmem_console_write(const void *buffer, size_t count)
 	do_write(buffer, count);
 }
 
-static void snapshot_putc(char *console, uint32_t *cursor, char c)
-{
-	/* This is BIOS_LOG_IS_MARKER() from coreboot. Due to stupid
-	   licensing restrictions, we can't use it directly. */
-	if (c >= 0x10 && c <= 0x18)
-		return;
-
-	/* Slight memory corruption may occur between reboots and give us a few
-	   unprintable characters like '\0'. Replace them with '?' on output. */
-	if (!isprint(c) && !isspace(c))
-		console[*cursor] = '?';
-	else
-		console[*cursor] = c;
-
-	*cursor += 1;
-}
-
 char *cbmem_console_snapshot(void)
 {
 	const struct cbmem_console *const console_p = phys_to_virt(cbmem_console_p);
 	char *console_c;
-	uint32_t size, cursor, overflow, newc, oldc;
+	uint32_t size, cursor, overflow;
 
 	if (!console_p) {
 		printf("ERROR: No cbmem console found in coreboot table\n");
@@ -121,19 +104,24 @@ char *cbmem_console_snapshot(void)
 		       size);
 		return NULL;
 	}
+	console_c[size] = '\0';
 
-	newc = 0;
 	if (overflow) {
 		if (cursor >= size) {
 			printf("ERROR: CBMEM console struct is corrupted\n");
 			return NULL;
 		}
-		for (oldc = cursor; oldc < size; oldc++)
+		memcpy(console_c, console_p->body + cursor, size - cursor);
-			snapshot_putc(console_c, &newc, console_p->body[oldc]);
+		memcpy(console_c + size - cursor, console_p->body, cursor);
+	} else {
+		memcpy(console_c, console_p->body, size);
 	}
-	for (oldc = 0; oldc < size && oldc < cursor; oldc++)
+
-		snapshot_putc(console_c, &newc, console_p->body[oldc]);
+	/* Slight memory corruption may occur between reboots and give us a few
-	console_c[newc] = '\0';
+	   unprintable characters like '\0'. Replace them with '?' on output. */
+	for (cursor = 0; cursor < size; cursor++)
+		if (!isprint(console_c[cursor]) && !isspace(console_c[cursor]))
+			console_c[cursor] = '?';
 
 	return console_c;
 }

payloads/libpayload/drivers/video/graphics.c

@@ -57,6 +57,7 @@ static const struct cb_framebuffer *fbinfo;
 #define PIVOT_H_MASK	(PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT)
 #define PIVOT_V_MASK	(PIVOT_V_TOP|PIVOT_V_CENTER|PIVOT_V_BOTTOM)
 #define ROUNDUP(x, y)	((((x) + ((y) - 1)) / (y)) * (y))
+#define ABS(x)		((x) < 0 ? -(x) : (x))
 
 static char initialized = 0;
 

payloads/libpayload/include/coreboot_tables.h

@@ -83,7 +83,6 @@ enum {
 	CB_TAG_BOARD_CONFIG		= 0x0040,
 	CB_TAG_ACPI_CNVS		= 0x0041,
 	CB_TAG_TYPE_C_INFO		= 0x0042,
-	CB_TAG_ACPI_RSDP                = 0x0043,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
@@ -91,7 +90,10 @@ enum {
 	CB_TAG_OPTION_CHECKSUM		= 0x00cc,
 };
 
-typedef __aligned(4) uint64_t cb_uint64_t;
+struct cbuint64 {
+	u32 lo;
+	u32 hi;
+};
 
 struct cb_header {
 	u8 signature[4];
@@ -108,8 +110,8 @@ struct cb_record {
 };
 
 struct cb_memory_range {
-	cb_uint64_t start;
+	struct cbuint64 start;
-	cb_uint64_t size;
+	struct cbuint64 size;
 	u32 type;
 };
 
@@ -268,14 +270,14 @@ struct cb_gpios {
 struct lb_range {
 	uint32_t tag;
 	uint32_t size;
-	cb_uint64_t range_start;
+	uint64_t range_start;
 	uint32_t range_size;
 };
 
 struct cb_cbmem_tab {
 	uint32_t tag;
 	uint32_t size;
-	cb_uint64_t cbmem_tab;
+	uint64_t cbmem_tab;
 };
 
 struct cb_x86_rom_mtrr {
@@ -313,10 +315,10 @@ struct cb_boot_media_params {
 	uint32_t tag;
 	uint32_t size;
 	/* offsets are relative to start of boot media */
-	cb_uint64_t fmap_offset;
+	uint64_t fmap_offset;
-	cb_uint64_t cbfs_offset;
+	uint64_t cbfs_offset;
-	cb_uint64_t cbfs_size;
+	uint64_t cbfs_size;
-	cb_uint64_t boot_media_size;
+	uint64_t boot_media_size;
 };
 
 
@@ -324,7 +326,7 @@ struct cb_cbmem_entry {
 	uint32_t tag;
 	uint32_t size;
 
-	cb_uint64_t address;
+	uint64_t address;
 	uint32_t entry_size;
 	uint32_t id;
 };
@@ -366,7 +368,7 @@ struct cb_board_config {
 	uint32_t tag;
 	uint32_t size;
 
-	cb_uint64_t fw_config;
+	struct cbuint64 fw_config;
 	uint32_t board_id;
 	uint32_t ram_code;
 	uint32_t sku_id;
@@ -420,18 +422,13 @@ struct	cb_cmos_checksum {
 	u32 type;
 };
 
-/*
- * Handoff the ACPI RSDP
- */
-struct cb_acpi_rsdp {
-	uint32_t tag;
-	uint32_t size;
-	cb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */
-};
-
-
 /* Helpful inlines */
 
+static inline u64 cb_unpack64(struct cbuint64 val)
+{
+	return (((u64) val.hi) << 32) | val.lo;
+}
+
 static inline u16 cb_checksum(const void *ptr, unsigned len)
 {
 	return ipchksum(ptr, len);

payloads/libpayload/include/fmap.h

@@ -7,6 +7,6 @@
 #include <stddef.h>
 
 /* Looks for area with |name| in FlashMap. Requires lib_sysinfo.fmap_cache. */
-enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size);
+cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size);
 
 #endif /* _FMAP_H */

payloads/libpayload/include/libpayload.h

@@ -46,8 +46,6 @@
 #include <libpayload-config.h>
 #include <cbgfx.h>
 #include <commonlib/bsd/fmap_serialized.h>
-#include <commonlib/bsd/helpers.h>
-#include <commonlib/bsd/mem_chip_info.h>
 #include <ctype.h>
 #include <die.h>
 #include <endian.h>
@@ -68,8 +66,33 @@
 #include <pci.h>
 #include <archive.h>
 
+/* Double-evaluation unsafe min/max, for bitfields and outside of functions */
+#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b))
+#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <)
+#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >)
+
+#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \
+	__TYPEOF_UNLESS_CONST(a, b) var_a = (a); \
+	__TYPEOF_UNLESS_CONST(b, a) var_b = (b); \
+	var_a op var_b ? var_a : var_b; \
+})
+
+#define __CMP(a, b, op) __builtin_choose_expr( \
+	__builtin_constant_p(a) && __builtin_constant_p(b), \
+	__CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME))
+
+#define MIN(a, b) __CMP(a, b, <)
+#define MAX(a, b) __CMP(a, b, >)
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define BIT(x)	(1ul << (x))
 
+#define DIV_ROUND_UP(x, y) ({ \
+	typeof(x) _div_local_x = (x); \
+	typeof(y) _div_local_y = (y); \
+	(_div_local_x + _div_local_y - 1) / _div_local_y; \
+})
+
 static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; }
 
 #define LITTLE_ENDIAN	1234

payloads/libpayload/include/stddef.h

@@ -2,7 +2,6 @@
 #define _STDDEF_H
 
 #include <arch/types.h>
-#include <commonlib/bsd/helpers.h>
 
 #ifndef __WCHAR_TYPE__
 #define __WCHAR_TYPE__ int
@@ -23,6 +22,22 @@ typedef __SIZE_TYPE__ size_t;
 typedef __SIZE_TYPE__ ssize_t;
 #undef unsigned
 
+#define offsetof(TYPE, MEMBER)	((size_t) &((TYPE *) 0)->MEMBER)
+#define member_size(TYPE, MEMBER)	(sizeof(((TYPE *) 0)->MEMBER))
+
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset)
+
+/* Standard units. */
+#define KiB (1 << 10)
+#define MiB (1 << 20)
+#define GiB (1 << 30)
+
+#define KHz (1000)
+#define MHz (1000*KHz)
+#define GHz (1000*MHz)
+
 #define NSECS_PER_SEC 1000000000
 #define USECS_PER_SEC 1000000
 #define MSECS_PER_SEC 1000

payloads/libpayload/include/stdlib.h

@@ -34,6 +34,12 @@
 #include <stddef.h>
 #include <string.h>
 
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a)           ALIGN((x),(a))
+#define ALIGN_DOWN(x,a)         ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a)         (((x) & ((typeof(x))(a)-1UL)) == 0)
+
 /**
  * @defgroup malloc Memory allocation functions
  * @{

payloads/libpayload/include/sysinfo.h

@@ -83,7 +83,6 @@ struct sysinfo_t {
 	uintptr_t compiler;
 	uintptr_t linker;
 	uintptr_t assembler;
-	uintptr_t mem_chip_base;
 
 	uintptr_t cb_version;
 
@@ -111,7 +110,6 @@ struct sysinfo_t {
 	uintptr_t mrc_cache;
 	uintptr_t acpi_gnvs;
 	uintptr_t acpi_cnvs;
-	uintptr_t acpi_rsdp;
 
 #define UNDEFINED_STRAPPING_ID	(~0)
 #define UNDEFINED_FW_CONFIG	~((uint64_t)0)

payloads/libpayload/libc/coreboot.c

@@ -61,8 +61,12 @@ static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 			continue;
 #endif
 
-		info->memrange[info->n_memranges].base = range->start;
+		info->memrange[info->n_memranges].base =
-		info->memrange[info->n_memranges].size = range->size;
+		    cb_unpack64(range->start);
+
+		info->memrange[info->n_memranges].size =
+		    cb_unpack64(range->size);
+
 		info->memrange[info->n_memranges].type = range->type;
 
 		info->n_memranges++;
@@ -117,7 +121,7 @@ static void cb_parse_mac_addresses(unsigned char *ptr,
 static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_board_config *const config = (struct cb_board_config *)ptr;
-	info->fw_config = config->fw_config;
+	info->fw_config = cb_unpack64(config->fw_config);
 	info->board_id = config->board_id;
 	info->ram_code = config->ram_code;
 	info->sku_id = config->sku_id;
@@ -256,20 +260,11 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 	case CBMEM_ID_TYPE_C_INFO:
 		info->type_c_info = cbmem_entry->address;
 		break;
-	case CBMEM_ID_MEM_CHIP_INFO:
-		info->mem_chip_base = cbmem_entry->address;
-		break;
 	default:
 		break;
 	}
 }
 
-static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info)
-{
-	const struct cb_acpi_rsdp *cb_acpi_rsdp = ptr;
-	info->acpi_rsdp = cb_acpi_rsdp->rsdp_pointer;
-}
-
 int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 {
 	struct cb_header *header;
@@ -410,9 +405,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 			cb_parse_tsc_info(ptr, info);
 			break;
 #endif
-		case CB_TAG_ACPI_RSDP:
-			cb_parse_rsdp(ptr, info);
-			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;

payloads/libpayload/libc/fmap.c

@@ -38,8 +38,8 @@
 /* Private fmap cache. */
 static struct fmap *_fmap_cache;
 
-static enum cb_err fmap_find_area(struct fmap *fmap, const char *name, size_t *offset,
+static cb_err_t fmap_find_area(struct fmap *fmap, const char *name, size_t *offset,
-				  size_t *size)
+			       size_t *size)
 {
 	for (size_t i = 0; i < le32toh(fmap->nareas); ++i) {
 		if (strncmp((const char *)fmap->areas[i].name, name, FMAP_STRLEN) != 0)
@@ -71,7 +71,7 @@ static bool fmap_setup_cache(void)
 	return false;
 }
 
-enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size)
+cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
 {
 	if (!_fmap_cache && !fmap_setup_cache())
 		return CB_ERR;

payloads/libpayload/libcbfs/cbfs.c

@@ -48,7 +48,7 @@ ssize_t _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mda
 		return CB_ERR;
 
 	size_t data_offset;
-	enum cb_err err = CB_CBFS_CACHE_FULL;
+	cb_err_t err = CB_CBFS_CACHE_FULL;
 	if (cbd->mcache_size)
 		err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size, name, mdata,
 					 &data_offset);

payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c

@@ -40,7 +40,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
 
 static size_t test_fmap_offset = 0;
 static size_t test_fmap_size = 0;
-static enum cb_err test_fmap_result = CB_SUCCESS;
+static cb_err_t test_fmap_result = CB_SUCCESS;
 
 static void set_fmap_locate_area_results(size_t offset, size_t size, size_t result)
 {
@@ -49,15 +49,15 @@ static void set_fmap_locate_area_results(size_t offset, size_t size, size_t resu
 	test_fmap_result = result;
 }
 
-enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size)
+cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
 {
 	*offset = test_fmap_offset;
 	*size = test_fmap_size;
 	return test_fmap_result;
 }
 
-enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
+cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
-			       union cbfs_mdata *mdata_out, size_t *data_offset_out)
+			    union cbfs_mdata *mdata_out, size_t *data_offset_out)
 {
 	assert_non_null(mcache);
 	assert_true(mcache_size > 0 && mcache_size % CBFS_MCACHE_ALIGNMENT == 0);
@@ -66,7 +66,7 @@ enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const cha
 
 	check_expected(name);
 
-	enum cb_err ret = mock_type(enum cb_err);
+	cb_err_t ret = mock_type(cb_err_t);
 	if (ret != CB_SUCCESS)
 		return ret;
 
@@ -75,7 +75,7 @@ enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const cha
 	return CB_SUCCESS;
 }
 
-static void expect_cbfs_mcache_lookup(const char *name, enum cb_err err,
+static void expect_cbfs_mcache_lookup(const char *name, cb_err_t err,
 				      const union cbfs_mdata *mdata, size_t data_offset_out)
 {
 	expect_string(cbfs_mcache_lookup, name, name);
@@ -87,13 +87,13 @@ static void expect_cbfs_mcache_lookup(const char *name, enum cb_err err,
 	}
 }
 
-enum cb_err cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
+cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
-			size_t *data_offset_out, struct vb2_hash *metadata_hash)
+		     size_t *data_offset_out, struct vb2_hash *metadata_hash)
 {
 	assert_non_null(dev);
 	check_expected(name);
 
-	enum cb_err ret = mock_type(enum cb_err);
+	cb_err_t ret = mock_type(cb_err_t);
 	if (ret != CB_SUCCESS)
 		return ret;
 
@@ -102,7 +102,7 @@ enum cb_err cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdat
 	return CB_SUCCESS;
 }
 
-static void expect_cbfs_lookup(const char *name, enum cb_err err, const union cbfs_mdata *mdata,
+static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata,
 			       size_t data_offset_out)
 {
 	expect_string(cbfs_lookup, name, name);