Add board.fmd and update amdfw

Change-Id: I455a6610810e00dcf44bcf9e88117bd85cd04ed6

Documentation/mainboard/system76/oryp8.md

@@ -10,14 +10,14 @@
   - ITE IT570E running [System76 EC](https://github.com/system76/ec)
 - Graphics
   - dGPU options
-    - NVIDIA GeForce RTX 3070 (Max-Q)
-    - NVIDIA GeForce RTX 3080 (Max-Q)
+    - NVIDIA GeForce RTX 3070
+    - NVIDIA GeForce RTX 3080
   - eDP options
-    - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
-    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
+    - 15.6" 1920x1080@144Hz LCD
+    - 17.3" 1920x1080@144Hz LCD
+  - 1x HDMI
+  - 1x Mini DisplayPort
+  - 1x DisplayPort over USB-C
 - Memory
   - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
 - Networking
@@ -26,13 +26,13 @@
     - Intel Wi-Fi 6 AX200/AX201
 - Power
   - 180W (19.5V, 9.23A) AC barrel adapter
-    - Lite-On PA-1181-16, using a C5 power cord
+    - Lite-On PA-1181-16
   - 73Wh 3-cell battery
 - Sound
   - Realtek ALC1220 codec
   - TI TAS5825M smart amp
   - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm headphone/microphone jack
   - Combined 3.5mm microphone & S/PDIF jack
   - HDMI, mDP, USB-C DP audio
 - Storage
@@ -41,9 +41,6 @@
 - USB
   - 1x USB Type-C with Thunderbolt 4
   - 3x USB 3.0 Type-A
-- Dimensions
-  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
-  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
 
 ## Flashing coreboot
 

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus with GC6 3.0
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/gpu.asl

@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEGP) {
+	Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
+		}
+
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
+		}
+	}
+
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
+}
+
+Device (\_SB.PCI0.PEGP.DEV0) {
+	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+        // TODO: use GPU config to generate address
+	OperationRegion (RPCX, SystemMemory, CONFIG_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
+
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
+
+				Debug = "    Sleep 16"
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
+	}
+
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
+}

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!dev->enabled || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus graphics device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n",
+		__func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n",
+		__func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}

src/include/cpu/intel/cpu_ids.h

@@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1

src/mainboard/system76/addw1/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
@@ -26,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR

src/mainboard/system76/addw1/Makefile.inc

@@ -1,4 +1,5 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/dgpu.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>

src/mainboard/system76/addw1/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Disable
+ime_mode=Disable

src/mainboard/system76/addw1/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/addw1/devicetree.cb

@@ -58,6 +58,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device

src/mainboard/system76/addw1/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/dgpu.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Allow higher memory speeds
 	memupd->FspmConfig.SaOcSupport = 1;
 

src/mainboard/system76/addw1/variants/addw1/include/variant/dgpu.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_DGPU_H
+#define VARIANT_DGPU_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+
+#endif

src/mainboard/system76/addw1/variants/addw2/include/variant/dgpu.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_DGPU_H
+#define VARIANT_DGPU_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+
+#endif

src/mainboard/system76/bonw14/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_BONW14
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
@@ -22,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR

src/mainboard/system76/bonw14/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Disable
+ime_mode=Disable

src/mainboard/system76/bonw14/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/bonw14/devicetree.cb

@@ -62,10 +62,12 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
 
-			device pci 00.0 on end # VGA controller
-			device pci 00.1 on end # Audio device
-			device pci 00.2 on end # USB xHCI Host controller
-			device pci 00.3 on end # USB Type-C UCSI controller
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		# TODO: is this enough to disable iGPU?
 		device pci 02.0 off end # Integrated Graphics Device

src/mainboard/system76/cml-u/Kconfig

@@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/cml-u"

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -6,6 +6,9 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/cml-u/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Disable
+ime_mode=Disable

src/mainboard/system76/cml-u/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/cml-u/dsdt.asl

@@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/darp7/Kconfig

@@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR

src/mainboard/system76/darp7/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/darp7/acpi/mainboard.asl

@@ -6,4 +6,7 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/darp7/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Enable
+ime_mode=Enable

src/mainboard/system76/darp7/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/darp7/devicetree.cb

@@ -105,7 +105,9 @@ chip soc/intel/tigerlake
 
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf on end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
 		device ref peg on
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
@@ -113,7 +115,8 @@ chip soc/intel/tigerlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
-				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				# TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # SSD1_CLKREQ#
 				device generic 0 on end
 			end
 		end
@@ -241,7 +244,10 @@ chip soc/intel/tigerlake
 			# TODO: USB-PD?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
 		end
-		device ref heci1 on end
+		device ref heci1 on
+			# TODO Disable ME and HECI
+			register "HeciEnabled" = "1"
+		end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
@@ -282,7 +288,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "1"
 			register "PcieClkSrcUsage[1]" = "7"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[7]" = "1"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 4 (SSD0)
@@ -290,7 +295,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
@@ -315,8 +319,8 @@ chip soc/intel/tigerlake
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
 						# J_TYPEC2
-						use usb2_port6 as usb2_port
-						use tcss_usb3_port1 as usb3_port
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "1"
 						# SBU & HSL follow CC
 						device generic 0 alias conn0 on end
 					end
@@ -326,7 +330,9 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+		end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/darp7/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/galp5/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GALP5
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
@@ -23,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/galp5"
@@ -59,4 +60,7 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	default 0x1c
+
 endif

src/mainboard/system76/galp5/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/galp5/acpi/dgpu.asl

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.RP05)
+{
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve)
+		{
+			Offset (0x40),
+			SSID, 32
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0)
+		{
+			Name (_STA, 1)
+
+			Method (_ON)
+			{
+				^^SSID = 0x40181558
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF)
+			{
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}

src/mainboard/system76/galp5/acpi/mainboard.asl

@@ -1,9 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "dgpu.asl"
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/galp5/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Enable
+ime_mode=Enable

src/mainboard/system76/galp5/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/galp5/devicetree.cb

@@ -105,7 +105,9 @@ chip soc/intel/tigerlake
 
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf on end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
 		device ref peg on
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
@@ -113,7 +115,8 @@ chip soc/intel/tigerlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
-				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				# TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # SSD1_CLKREQ#
 				device generic 0 on end
 			end
 		end
@@ -252,7 +255,10 @@ chip soc/intel/tigerlake
 			# TODO: Pantone ROM?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
 		end
-		device ref heci1 on end
+		device ref heci1 on
+			# TODO Disable ME and HECI
+			register "HeciEnabled" = "1"
+		end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
@@ -273,6 +279,13 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "2" # PEG_CLKREQ#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x1, Clock 3 (CARD)
@@ -300,7 +313,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[10]" = "1"
 			register "PcieClkSrcUsage[1]" = "10"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[10]" = "1"
 		end
 		device ref pch_espi on
 			register "gen1_dec" = "0x00040069"
@@ -318,8 +330,8 @@ chip soc/intel/tigerlake
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
 						# J_TYPEC2
-						use usb2_port6 as usb2_port
-						use tcss_usb3_port1 as usb3_port
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "1"
 						# SBU & HSL follow CC
 						device generic 0 alias conn0 on end
 					end
@@ -329,7 +341,9 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+		end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/galp5/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/galp5/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_U4
+#define DGPU_PWR_EN	GPP_U5
+#define DGPU_GC6	GPP_D2
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
@@ -222,4 +228,6 @@ static const struct pad_config gpio_table[] = {
 	//PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
 };
 
+#endif /* __ACPI__ */
+
 #endif /* MAINBOARD_GPIO_H */

src/mainboard/system76/galp5/romstage.c

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "gpio.h"
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
@@ -18,5 +20,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	// Allow memory clocks higher than 2933 MHz
+	mupd->FspmConfig.SaOcSupport = 1;
+
 	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/gaze15/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
@@ -23,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR

src/mainboard/system76/gaze15/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,11 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/gaze15/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Disable
+ime_mode=Disable

src/mainboard/system76/gaze15/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/gaze15/devicetree.cb

@@ -57,6 +57,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/gaze15/dsdt.asl

@@ -18,7 +18,6 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze15/include/variant/gpio.h

@@ -3,7 +3,15 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/gaze15/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb

@@ -13,7 +13,6 @@ chip soc/intel/cannonlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PNP0C50""
 				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.uid" = "0"
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
 				register "generic.probed" = "1"
 				register "hid_desc_reg_offset" = "0x01"
@@ -22,7 +21,6 @@ chip soc/intel/cannonlake
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PNP0C50""
 				register "generic.desc" = ""Synaptics Touchpad""
-				register "generic.uid" = "1"
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
 				register "generic.probed" = "1"
 				register "hid_desc_reg_offset" = "0x20"

src/mainboard/system76/gaze16/Kconfig

@@ -1,8 +1,9 @@
-if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B
+if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
@@ -23,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR

src/mainboard/system76/gaze16/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/gaze16/acpi/dgpu.asl

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.PEG1)
+{
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve)
+		{
+			Offset (0x40),
+			SSID, 32
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0)
+		{
+			Name (_STA, 1)
+
+			Method (_ON)
+			{
+				^^SSID = 0x40181558
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF)
+			{
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}

src/mainboard/system76/gaze16/acpi/mainboard.asl

@@ -1,9 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "dgpu.asl"
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/gaze16/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Disable
+ime_mode=Disable

src/mainboard/system76/gaze16/cmos.layout

@@ -12,8 +12,7 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations

src/mainboard/system76/gaze16/devicetree.cb

@@ -96,7 +96,9 @@ chip soc/intel/tigerlake
 			register "DdiPortBHpd" = "1"
 			register "DdiPortBDdc" = "1"
 		end
-		device ref dptf on end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
 		device ref gna on end
 		device ref north_xhci on
 			# TODO: No TBT, but needed for USB 2.0 on Type-C port?
@@ -141,7 +143,9 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+		end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/gaze16/dsdt.asl

@@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze16/romstage.c

@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include "variant.h"
 
 static const struct mb_cfg board_cfg = {
@@ -22,9 +24,21 @@ static const struct mem_spd spd_info = {
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
 	variant_memory_init_params(mupd);
 
-	const bool half_populated = false;
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
 
 	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
@@ -285,4 +291,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
 };
 
+#endif /* __ACPI__ */
+
 #endif /* VARIANT_GPIO_H */

src/mainboard/system76/gaze16/variants/3050/overridetree.cb

@@ -13,9 +13,17 @@ chip soc/intel/tigerlake
 				register "enable_off_delay_ms" = "4"
 				register "reset_delay_ms" = "10"
 				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "0" # GFX_CLKREQ0#
+				# TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # GFX_CLKREQ0#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref peg0 on
 			# PCIe PEG0 x4, Clock 4 (SSD2)
@@ -61,7 +69,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "1"
 			register "PcieClkSrcUsage[8]" = "7"
 			register "PcieClkSrcClkReq[8]" = "8"
-			register "PcieRpSlotImplemented[7]" = "1"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 9 (SSD1)
@@ -69,7 +76,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[8]" = "1"
 		end
 	end
 end

src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
@@ -285,4 +291,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
 };
 
+#endif /* __ACPI__ */
+
 #endif /* VARIANT_GPIO_H */

src/mainboard/system76/gaze16/variants/3060/overridetree.cb

@@ -13,9 +13,17 @@ chip soc/intel/tigerlake
 				register "enable_off_delay_ms" = "4"
 				register "reset_delay_ms" = "10"
 				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
+				# TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # PEG_CLKREQ#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref peg0 on
 			# PCIe PEG0 x4, Clock 7 (SSD1)
@@ -61,7 +69,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "1"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x4, Clock 10 (SSD2)
@@ -69,7 +76,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[8]" = "1"
 		end
 		device ref gbe on end
 	end

src/mainboard/system76/kbl-u/Kconfig

@@ -17,10 +17,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_KABYLAKE
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
-
-config DISABLE_HECI1_AT_PRE_BOOT
-	default y
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/kbl-u"

src/mainboard/system76/kbl-u/cmos.layout

@@ -11,6 +11,7 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
 984	16	h	0	check_sum
 
@@ -29,6 +30,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/kudu6/Kconfig

@@ -0,0 +1,88 @@
+if BOARD_SYSTEM76_KUDU6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select AMD_SOC_CONSOLE_UART
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_COMMON_CLOCK
+	select PCIEXP_L1_SUB_STATE
+	select NO_UART_ON_SUPERIO
+	select SOC_AMD_CEZANNE
+	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/kudu6"
+
+config MAINBOARD_PART_NUMBER
+	default "kudu6"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Kudu"
+
+config MAINBOARD_VERSION
+	default "kudu6"
+
+config AMD_FWM_POSITION_INDEX
+	default 3
+
+config AMDFW_CONFIG_FILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/amdfw.cfg"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_MAX
+	default 4
+
+config DIMM_SPD_SIZE
+	default 512
+
+config EFS_SPI_READ_MODE
+	default 5          # Quad IO (1-4-4)
+
+config EFS_SPI_SPEED
+	default 0	# 66MHz
+
+config EFS_SPI_MICRON_FLAG
+	default 2
+
+config NORMAL_READ_SPI_SPEED
+	default 1	# 33MHz
+
+config ALT_SPI_SPEED
+	default 0	# 66MHz
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config PSP_LOAD_MP2_FW
+	default y
+
+config PSP_POSTCODES_ON_ESPI
+	default n
+
+config UART_FOR_CONSOLE
+	default 0
+
+endif

src/mainboard/system76/kudu6/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_KUDU6
+	bool "kudu6"

src/mainboard/system76/kudu6/Makefile.inc

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += early_gpio.c
+
+romstage-y += port_descriptors.c
+
+APCB_SOURCES = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb
+APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb_recovery
+APCB_SOURCES_68 = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb_68

src/mainboard/system76/kudu6/amdfw.cfg

@@ -0,0 +1,38 @@
+# PSP fw config file
+
+FIRMWARE_LOCATION      3rdparty/amd_blobs/cezanne/PSP
+
+# type                    file
+# PSP
+AMD_PUBKEY_FILE         TypeId0x00_CezannePublicKey.tkn
+PSPBTLDR_FILE           TypeId0x01_PspBootLoader_CZN.sbin
+PSPSECUREOS_FILE        TypeId0x02_PspOS_CZN.sbin
+PSPRCVR_FILE            TypeId0x03_PspRecoveryBootLoader_CZN.sbin
+PSP_SMUFW1_SUB0_FILE    TypeId0x08_SmuFirmware_CZN.csbin
+PSPSECUREDEBUG_FILE     TypeId0x09_SecureDebugUnlockKey_CZN.stkn
+PSPTRUSTLETS_FILE       TypeId0x0C_FtpmDrv_CZN.csbin
+PSP_SMUFW2_SUB0_FILE    TypeId0x12_SmuFirmware2_CZN.csbin
+PSP_SEC_DEBUG_FILE      TypeId0x13_PspEarlyUnlock_CZN.sbin
+PSP_HW_IPCFG_FILE       TypeId0x20_HwIpCfg_CZN_A0.sbin
+PSP_IKEK_FILE           TypeId0x21_PspIkek_CZN.bin
+PSP_SECG0_FILE          TypeId0x24_SecurePolicyL0_CZN.sbin
+PSP_MP2FW0_FILE         TypeId0x25_Mp2Fw_CZN.sbin
+AMD_DRIVER_ENTRIES      TypeId0x28_PspSystemDriver_CZN.sbin
+PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
+PSP_S0I3_FILE           TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
+PSP_ABL0_FILE           TypeId0x30_AgesaBootloaderU_CZN.csbin
+VBIOS_BTLOADER_FILE       TypeId0x3C_VbiosBootLoader_CZN.sbin
+UNIFIEDUSB_FILE         TypeId0x44_UnifiedUsb_CZN.sbin
+SECURE_POLICY_L1_FILE   TypeId0x45_SecurePolicyL1_CZN.sbin
+DRTMTA_FILE             TypeId0x47_DrtmTA_CZN.sbin
+KEYDBBL_FILE            TypeId0x50_KeyDbBl_CZN.sbin
+KEYDB_TOS_FILE          TypeId0x51_KeyDbTos_CZN.sbin
+DMCUERAMDCN21_FILE      TypeId0x58_DmcuEramDcn21.sbin
+DMCUINTVECTORSDCN21_FILE  TypeId0x59_DmcuIntvectorsDcn21.sbin
+
+# BDT
+PSP_PMUI_FILE1  TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE1  TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin
+PSP_PMUI_FILE2  TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE2  TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin
+PSP_MP2CFG_FILE MP2FWConfig.sbin

src/mainboard/system76/kudu6/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: kudu6
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/kudu6/bootblock.c

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <amdblocks/lpc.h>
+#include <console/console.h>
+#include "gpio.h"
+
+void bootblock_mainboard_early_init(void)
+{
+	post_code(0x76);
+	post_code(0x01);
+
+	mainboard_program_early_gpios();
+
+	post_code(0x76);
+	post_code(0x02);
+
+	// AP/EC command
+	lpc_set_wideio_range(0xE00, 256);
+
+	// AP/EC debug
+	lpc_set_wideio_range(0xF00, 256);
+
+	post_code(0x76);
+	post_code(0x03);
+}
+
+void bootblock_mainboard_init(void)
+{
+	post_code(0x76);
+	post_code(0x10);
+}

src/mainboard/system76/kudu6/devicetree.cb

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/cezanne
+
+	register "common_config.acp_config" = "{
+		.acp_pin_cfg = I2S_PINS_I2S_TDM,
+		.acp_i2s_wake_enable = 0,
+		.acp_pme_enable = 0,
+		.dmic_present = 1,
+	}"
+
+	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+	# I2C Pad Control RX Select Configuration
+	register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Trackpad
+	register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # NC
+	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # DDR4
+	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # USB-PD
+
+
+	register "s0ix_enable" = "true"
+
+	register "pspp_policy" = "DXIO_PSPP_BALANCED"
+
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[2]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[4]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[5]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[6]" = "GPP_CLK_REQ"
+
+	#TODO: USB?
+
+	device domain 0 on
+		device ref iommu on end
+		device ref gpp_gfx_bridge_0 on end # DGPU
+		device ref gpp_bridge_0 on end # LAN
+		device ref gpp_bridge_1 on end # WLAN
+		device ref gpp_bridge_2 on end # SSD2
+		device ref gpp_bridge_3 on end # SSD1
+		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
+			device ref gfx on end # Internal GPU (GFX)
+			device ref gfx_hda on end # GFX HD Audio Controller
+			device ref crypto on end # Crypto Coprocessor
+			device ref xhci_0 on end # USB 3.1 (USB0)
+			device ref xhci_1 on end # USB 3.1 (USB1)
+			device ref acp on end # Audio Processor
+			device ref hda on end # HD Audio Controller
+		end
+		device ref gpp_bridge_b on  # Internal GPP Bridge 1 to Bus B
+			device ref sata_0 on end # SATA
+			device ref sata_1 on end # SATA
+		end
+	end
+
+	device ref uart_0 on end # UART0
+
+end

src/mainboard/system76/kudu6/dsdt.asl

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include <soc.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#define EC_GPE_SCI 0x6E
+	#define EC_GPE_SWI 0x6B
+	#include <ec/system76/ec/acpi/ec.asl>
+}

src/mainboard/system76/kudu6/early_gpio.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "gpio.h"
+
+/* GPIO pins used by coreboot should be initialized in bootblock */
+
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+	PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), // APU_SMB0_CLK
+	PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), // APU_SMB0_DATA
+	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), // SMC_7411
+	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), // SMD_7411
+};
+
+void mainboard_program_early_gpios(void)
+{
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+}

src/mainboard/system76/kudu6/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
+
+#endif  /* MAINBOARD_GPIO_H */

src/mainboard/system76/kudu6/mainboard.c

@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/amd_pci_util.h>
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <soc/acpi.h>
+#include <string.h>
+#include <types.h>
+
+/*
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system.  It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair.  These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ */
+static uint8_t fch_pic_routing[0x80];
+static uint8_t fch_apic_routing[0x80];
+
+_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
+	"PIC and APIC FCH interrupt tables must be the same size");
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ *  0: timer < soc/amd/common/acpi/lpc.asl
+ *  1: i8042 - Keyboard
+ *  2: cascade
+ *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ *  9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+static const struct fch_irq_routing {
+	uint8_t intr_index;
+	uint8_t pic_irq_num;
+	uint8_t apic_irq_num;
+} kudu6_fch[] = {
+	{ PIRQ_A,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_B,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_C,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_D,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_E,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_F,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_G,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_H,	PIRQ_NC,	PIRQ_NC },
+
+	{ PIRQ_SCI,	ACPI_SCI_IRQ,	ACPI_SCI_IRQ },
+	{ PIRQ_SD,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_SDIO,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_SATA,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_EMMC,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_GPIO,	7,		7 },
+	{ PIRQ_I2C2,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_I2C3,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_UART0,	 4,		 4 },
+	{ PIRQ_UART1,	 3,		 3 },
+
+	/* The MISC registers are not interrupt numbers */
+	{ PIRQ_MISC,	0xfa,		0x00 },
+	{ PIRQ_MISC0,	0x91,		0x00 },
+	{ PIRQ_HPET_L,	0x00,		0x00 },
+	{ PIRQ_HPET_H,	0x00,		0x00 },
+};
+
+static void init_tables(void)
+{
+	const struct fch_irq_routing *entry;
+	int i;
+
+	memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
+	memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
+
+	for (i = 0; i < ARRAY_SIZE(kudu6_fch); i++) {
+		entry = kudu6_fch + i;
+		fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
+		fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
+	}
+}
+
+static void pirq_setup(void)
+{
+	intr_data_ptr = fch_apic_routing;
+	picr_data_ptr = fch_pic_routing;
+}
+
+static void mainboard_init(void *chip_info)
+{
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	init_tables();
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/system76/kudu6/port_descriptors.c

@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/platform_descriptors.h>
+#include <types.h>
+
+static const fsp_dxio_descriptor kudu6_dxio_descriptors[] = {
+	{ /* DGPU */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 16,
+		.end_logical_lane = 23,
+		.device_number = 1,
+		.function_number = 1,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* LAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
+		.device_number = 2,
+		.function_number = 1,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* WLAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 1,
+		.end_logical_lane = 1,
+		.device_number = 2,
+		.function_number = 2,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ6,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* SSD2 */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 4,
+		.end_logical_lane = 7,
+		.device_number = 2,
+		.function_number = 3,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ4_GFX,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* SSD1 */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 8,
+		.end_logical_lane = 11,
+		.device_number = 2,
+		.function_number = 4,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ5,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* HDD */
+		.engine_type = SATA_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
+		.channel_type = SATA_CHANNEL_LONG,
+	}
+};
+
+static const fsp_ddi_descriptor kudu6_ddi_descriptors[] = {
+	{ /* DDI0 - eDP */
+		.connector_type = DDI_EDP,
+		.aux_index = DDI_AUX1,
+		.hdp_index = DDI_HDP1
+	},
+	{ /* DDI1 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX2,
+		.hdp_index = DDI_HDP2
+	},
+	{ /* DDI2 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI3 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI4 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX4,
+		.hdp_index = DDI_HDP4,
+	}
+};
+
+void mainboard_get_dxio_ddi_descriptors(
+		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+	*dxio_descs = kudu6_dxio_descriptors;
+	*dxio_num = ARRAY_SIZE(kudu6_dxio_descriptors);
+	*ddi_descs = kudu6_ddi_descriptors;
+	*ddi_num = ARRAY_SIZE(kudu6_ddi_descriptors);
+}

src/mainboard/system76/lemp10/Kconfig

@@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR

src/mainboard/system76/lemp10/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/lemp10/acpi/mainboard.asl

@@ -6,4 +6,7 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/lemp10/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Enable
+ime_mode=Enable

src/mainboard/system76/lemp10/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/lemp10/devicetree.cb

@@ -105,7 +105,9 @@ chip soc/intel/tigerlake
 
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf on end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
 		device ref peg on
 			# PCIe PEG0 x4, Clock 3 (SSD1)
 			# Despite the name, SSD2_CLKREQ# is used for SSD1
@@ -114,7 +116,8 @@ chip soc/intel/tigerlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
-				register "srcclk_pin" = "3" # SSD2_CLKREQ#
+				# TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # SSD2_CLKREQ#
 				device generic 0 on end
 			end
 		end
@@ -222,7 +225,10 @@ chip soc/intel/tigerlake
 			# TODO: USB-PD?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
 		end
-		device ref heci1 on end
+		device ref heci1 on
+			# TODO Disable ME and HECI
+			register "HeciEnabled" = "1"
+		end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
@@ -240,7 +246,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[2]" = "1"
 			register "PcieClkSrcUsage[1]" = "2"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[2]" = "1"
 		end
 		device ref pcie_rp6 on
 			# PCIe root port #6 x1, Clock 2 (CARD)
@@ -256,7 +261,6 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "1"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[8]" = "1"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)
@@ -280,8 +284,8 @@ chip soc/intel/tigerlake
 				device generic 0 on
 					chip drivers/intel/pmc_mux/conn
 						# J_TYPEC1
-						use usb2_port3 as usb2_port
-						use tcss_usb3_port1 as usb3_port
+						register "usb2_port_number" = "3"
+						register "usb3_port_number" = "1"
 						# SBU & HSL follow CC
 						device generic 0 alias conn0 on end
 					end
@@ -291,7 +295,9 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+		end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/lemp10/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/lemp10/romstage.c

@@ -13,6 +13,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		.topo = MEM_TOPO_MIXED,
 		.cbfs_index = 0,
 		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
 			[1] = { .addr_dimm[0] = 0x52, },
 		},
 	};

src/mainboard/system76/lemp9/Kconfig

@@ -21,8 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
-	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/lemp9"
@@ -60,10 +59,6 @@ config VGA_BIOS_ID
 	string
 	default "8086,9b41"
 
-config TPM_PIRQ
-	hex
-	default 0x10 # GPP_A7/PIRQA#
-
 config POST_DEVICE
 	bool
 	default n

src/mainboard/system76/lemp9/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		 5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/lemp9/acpi/mainboard.asl

@@ -6,6 +6,9 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/lemp9/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Disable
+ime_mode=Disable

src/mainboard/system76/lemp9/cmos.layout

@@ -11,9 +11,9 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
@@ -34,6 +34,10 @@ enumerations
 6	7	Debug
 6	8	Spew
 
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
 checksums
 
 checksum 408 983 984

src/mainboard/system76/lemp9/gpio.h

@@ -10,7 +10,7 @@
 
 /* Name format: <pad name> / <net/pin name in schematics> */
 
-/* Early pad configuration in bootblock */
+/* Early pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),		/* UART2_RXD */
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),		/* UART2_TXD */
@@ -74,7 +74,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_B2, UP_20K),				/* CNVI_WAKE#
 							   (UART_WAKE# in M.2 spec; unused)
 							 */
-	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),	/* GPP_B3 (touchpad interrupt) */
+	PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),/* GPP_B3 (touchpad interrupt) */
 	PAD_NC(GPP_B4, UP_20K),
 	PAD_NC(GPP_B5, UP_20K),
 	PAD_NC(GPP_B6, UP_20K),

src/mainboard/system76/oryp5/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ORYP5
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
@@ -23,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/oryp5"