Compare commits
1 Commits
system76-4
...
2023-09-08
Author | SHA1 | Date | |
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705e7fd610 |
@@ -108,10 +108,6 @@ config MAINBOARD_VERSION
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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config CMOS_DEFAULT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
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default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
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config CONSOLE_POST
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config CONSOLE_POST
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default y
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default y
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@@ -1,3 +0,0 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@@ -1,6 +1,4 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "s0ix_enable" = "1"
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register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
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register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 56,
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.tdp_pl2_override = 56,
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@@ -133,10 +133,6 @@ config MAINBOARD_VERSION
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "serw13" if BOARD_SYSTEM76_SERW13
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default "serw13" if BOARD_SYSTEM76_SERW13
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config CMOS_DEFAULT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9
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default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
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config CONSOLE_POST
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config CONSOLE_POST
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default y
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default y
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@@ -1,3 +0,0 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@@ -1,6 +1,6 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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# Support 5600 MT/s memory
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# Support 5200 MT/s memory
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register "max_dram_speed_mts" = "5600"
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register "max_dram_speed_mts" = "5200"
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device domain 0 on
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device domain 0 on
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subsystemid 0x1558 0xa671 inherit
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subsystemid 0x1558 0xa671 inherit
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@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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@@ -1,6 +1,6 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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# Support 5600 MT/s memory
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# Support 5200 MT/s memory
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register "max_dram_speed_mts" = "5600"
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register "max_dram_speed_mts" = "5200"
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device domain 0 on
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device domain 0 on
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subsystemid 0x1558 0x3702 inherit
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subsystemid 0x1558 0x3702 inherit
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@@ -1,6 +1,4 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "s0ix_enable" = "1"
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register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
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register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 56,
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.tdp_pl2_override = 56,
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@@ -16,11 +14,6 @@ chip soc/intel/alderlake
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.clk_req = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST#
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register "srcclk_pin" = "0" # SSD2_CLKREQ#
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device generic 0 on end
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end
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end
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end
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device ref pcie4_1 on
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device ref pcie4_1 on
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# CPU RP#3 x4, Clock 4 (SSD1)
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# CPU RP#3 x4, Clock 4 (SSD1)
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@@ -29,11 +22,6 @@ chip soc/intel/alderlake
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.clk_req = 4,
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.clk_req = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
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register "srcclk_pin" = "4" # SSD1_CLKREQ#
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device generic 0 on end
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end
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end
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end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp0 on end
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device ref tcss_xhci on
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device ref tcss_xhci on
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@@ -77,6 +77,7 @@ chip soc/intel/alderlake
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.clk_src = 1,
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.clk_src = 1,
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.clk_req = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR,
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.flags = PCIE_RP_LTR,
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.pcie_rp_detect_timeout_ms = 50,
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}"
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}"
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end
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end
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end
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end
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@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050027, 0x02040010, 0x02050028, 0x02040000,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
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0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x02050028, 0x02040000, 0x02050029, 0x0204c206,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
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@@ -1,6 +1,6 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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# Support 5600 MT/s memory
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# Support 5200 MT/s memory
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register "max_dram_speed_mts" = "5600"
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register "max_dram_speed_mts" = "5200"
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device domain 0 on
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device domain 0 on
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subsystemid 0x1558 0xd502 inherit
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subsystemid 0x1558 0xd502 inherit
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@@ -3,7 +3,6 @@ if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_CBFS_SERIAL
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select DRIVERS_GENERIC_CBFS_SERIAL
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select DRIVERS_GENERIC_CBFS_UUID
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select DRIVERS_GENERIC_CBFS_UUID
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select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
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select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
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