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2 Commits

Author SHA1 Message Date
Jeremy Soller
6648fefb14 soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.

Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-05-31 19:23:25 -06:00
Jeremy Soller
67a7ee7eb8 soc/common/smbus: Support reading SPD5 hubs for DDR5
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).

Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-05-31 19:17:10 -06:00
4 changed files with 110 additions and 41 deletions

View File

@@ -36,6 +36,18 @@
#define DDR4_SPD_PART_OFF 329
#define DDR4_SPD_PART_LEN 20
#define DDR4_SPD_SN_OFF 325
#define MAX_SPD_PAGE_SIZE_SPD5 128
#define MAX_SPD_SIZE (SPD_PAGE_LEN * 4)
#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr)))
#define SPD5_MR11 0x0B
#define SPD5_MR0 0x00
#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr)))
#define SPD5_MR0_SPD5_HUB_DEV 0x51
struct spd_offset_table {
u16 start; /* Offset 0 */
u16 end; /* Offset 2 */
};
struct spd_block {
u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */

View File

@@ -209,7 +209,9 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
if (dram_type == SPD_DRAM_DDR4)
if (dram_type == SPD_DRAM_DDR5)
blk->len = CONFIG_DIMM_SPD_SIZE;
else if (dram_type == SPD_DRAM_DDR4)
blk->len = SPD_PAGE_LEN_DDR4;
else
blk->len = SPD_PAGE_LEN;

View File

@@ -118,7 +118,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
},
};
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
bool expand_channels)
{
uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
@@ -151,7 +152,16 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
uint32_t *spd_ptr = spd_upds[ch][dimm];
*spd_ptr = data->spd[ch][dimm];
// In DDR5 systems, we need to copy the SPD data such that:
// Channel 0 data is used by channel 0 and 1
// Channel 2 data is used by channel 2 and 3
// Channel 4 data is used by channel 4 and 5
// Channel 6 data is used by channel 6 and 7
if (expand_channels)
*spd_ptr = data->spd[ch & 6][dimm];
else
*spd_ptr = data->spd[ch][dimm];
if (*spd_ptr)
enable_channel = 1;
}
@@ -217,27 +227,12 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
}
#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
const struct mem_spd *spd_info)
{
for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
spd_info->smbus[ch].addr_dimm[dimm] << 1;
}
}
mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
}
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
const struct mem_spd *spd_info, bool half_populated)
{
struct mem_channel_data data;
bool dq_dqs_auto_detect = false;
bool expand_channels = false;
FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)
@@ -261,14 +256,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
case MEM_TYPE_DDR5:
meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
dq_dqs_auto_detect = true;
/*
* TODO: Drop this workaround once SMBus driver in coreboot is updated to
* support DDR5 EEPROM reading.
*/
if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
return;
}
expand_channels = true;
break;
case MEM_TYPE_LP4X:
meminit_lp4x(mem_cfg);
@@ -282,7 +270,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated,
&data);
mem_init_spd_upds(mem_cfg, &data);
mem_init_spd_upds(mem_cfg, &data, expand_channels);
mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
}

View File

@@ -13,8 +13,11 @@ static void update_spd_len(struct spd_block *blk)
if (blk->spd_array[i] != NULL)
j |= blk->spd_array[i][SPD_DRAM_TYPE];
/* If spd used is DDR5, then its length is 1024 byte. */
if (j == SPD_DRAM_DDR5)
blk->len = CONFIG_DIMM_SPD_SIZE;
/* If spd used is DDR4, then its length is 512 byte. */
if (j == SPD_DRAM_DDR4)
else if (j == SPD_DRAM_DDR4)
blk->len = SPD_PAGE_LEN_DDR4;
else
blk->len = SPD_PAGE_LEN;
@@ -37,6 +40,61 @@ static void smbus_read_spd(u8 *spd, u8 addr)
}
}
static void switch_page(u8 spd_addr, u8 new_page)
{
u32 offset;
/*
* By default,an SPD5 hub accepts 1 byte addressing pointing
* to the first 128 bytes of memory. MR11[2:0] selects the page
* pointer to address the entire 1024 bytes of non-volatile memory.
*/
offset = SPD5_MEMREG_REG(SPD5_MR11);
smbus_write_byte(spd_addr, offset, new_page);
}
/*
* Read the SPD data over the SMBus, at the specified SPD address,
* starting at the specified starting offset and read the given amount of data.
*/
static void smbus_read_spd5(u8 *spd, u8 spd_addr, u16 size)
{
u8 page = ~0;
u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5;
if (size > MAX_SPD_SIZE) {
printk(BIOS_ERR, "Maximum SPD size reached\n");
return;
}
for (int i = 0; i < size; i++) {
u8 next_page = (u8) (i / max_page_size);
if (next_page != page) {
switch_page(spd_addr, next_page);
page = next_page;
}
unsigned int byte_addr = SPD_HUB_MEMREG(i % max_page_size);
spd[i] = smbus_read_byte(spd_addr, byte_addr);
}
}
/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/
static int is_spd5_hub(u8 spd_addr)
{
u8 spd_hub_byte;
spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0));
return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV;
}
/*
* Reset the SPD page back to page 0 on an SPD5 Hub device at the
* input SPD SMbus address.
*/
static void reset_page_spd5(u8 spd_addr)
{
/* Set SPD5 MR11[2:0] = 0 (Page 0) */
smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), 0);
}
/* return -1 if SMBus errors otherwise return 0 */
static int get_spd(u8 *spd, u8 addr)
{
@@ -52,22 +110,31 @@ static int get_spd(u8 *spd, u8 addr)
return -1;
}
if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
smbus_read_spd(spd, addr);
}
if (is_spd5_hub(addr)) {
smbus_read_spd5(spd, addr, CONFIG_DIMM_SPD_SIZE);
/* Check if module is DDR4, DDR4 spd is 512 byte. */
if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
/* Switch to page 1 */
smbus_write_byte(SPD_PAGE_1, 0, 0);
/* Reset the page for the next loop iteration */
reset_page_spd5(addr);
} else {
if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) {
if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
smbus_read_spd(spd + SPD_PAGE_LEN, addr);
smbus_read_spd(spd, addr);
}
/* Check if module is DDR4, DDR4 spd is 512 byte. */
if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
/* Switch to page 1 */
smbus_write_byte(SPD_PAGE_1, 0, 0);
if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) {
printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
smbus_read_spd(spd + SPD_PAGE_LEN, addr);
}
/* Restore to page 0 */
smbus_write_byte(SPD_PAGE_0, 0, 0);
}
/* Restore to page 0 */
smbus_write_byte(SPD_PAGE_0, 0, 0);
}
return 0;
}