mb/system76/gaze16: 3060: Add variant for I219-V GbE

Some models use Intel I219-V instead of the Realtek RTL8111 controller.
Introduce a new variant so the IFD of the Realtek board does not have
the onboard LAN enabled when it is not connected.

Change-Id: I1961a7a8fac2dc6e81ebae013ff62cd491fba43c
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.gitmodules

@@ -1,60 +1,60 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

src/drivers/i2c/tas5825m/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_I2C_TAS5825M
+	bool
+	default n
+	help
+	  Enable support for TI TAS5825M Amplifier.

src/drivers/i2c/tas5825m/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += tas5825m.c

src/drivers/i2c/tas5825m/chip.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+struct drivers_i2c_tas5825m_config {
+    // Used to uniquely identify the AMP
+    int id;
+};

src/drivers/i2c/tas5825m/tas5825m.c

@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include "chip.h"
+#include "tas5825m.h"
+
+int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) {
+	return smbus_write_byte(dev, addr, value);
+}
+
+//TODO: use I2C block write for better performance
+int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length) {
+	int res = 0;
+	for (uint8_t i = 0; i < length; i++) {
+		res = smbus_write_byte(dev, addr + i, values[i]);
+		if (res < 0) return res;
+	}
+	return (int)length;
+}
+
+int tas5825m_set_page(struct device *dev, uint8_t page) {
+	return tas5825m_write_at(dev, 0x00, page);
+}
+
+int tas5825m_set_book(struct device *dev, uint8_t book) {
+	int res = tas5825m_set_page(dev, 0x00);
+	if (res < 0) return res;
+	return tas5825m_write_at(dev, 0x7F, book);
+}
+
+__weak int tas5825m_setup(struct device *dev, int id) {
+	printk(BIOS_ERR, "tas5825m: setup not implemented\n");
+	return -1;
+}
+
+static void tas5825m_init(struct device *dev) {
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C &&
+		ops_smbus_bus(get_pbus_smbus(dev))) {
+		printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev));
+
+		struct drivers_i2c_tas5825m_config *config = dev->chip_info;
+		if (config) {
+			printk(BIOS_DEBUG, "tas5825m id %d\n", config->id);
+			int res = tas5825m_setup(dev, config->id);
+			if (res) {
+				printk(BIOS_ERR, "tas5825m init failed: %d\n", res);
+			} else {
+				printk(BIOS_DEBUG, "tas5825m init successful\n");
+			}
+		} else {
+			printk(BIOS_ERR, "tas5825m: failed to find config\n");
+		}
+
+	}
+}
+
+static struct device_operations tas5825m_operations = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.init			= tas5825m_init,
+};
+
+static void tas5825m_enable_dev(struct device *dev) {
+	dev->ops = &tas5825m_operations;
+}
+
+struct chip_operations drivers_i2c_tas5825m_ops = {
+	CHIP_NAME("TI TAS5825M Amplifier")
+	.enable_dev = tas5825m_enable_dev,
+};

src/drivers/i2c/tas5825m/tas5825m.h

@@ -0,0 +1,12 @@
+#ifndef TAS5825M_H
+#define TAS5825M_H
+
+#include <device/device.h>
+
+int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value);
+int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length);
+int tas5825m_set_page(struct device *dev, uint8_t page);
+int tas5825m_set_book(struct device *dev, uint8_t book);
+int tas5825m_setup(struct device *dev, int id);
+
+#endif // TAS5825M_H

src/drivers/intel/gma/acpi/configure_brightness_levels.asl

@@ -148,7 +148,7 @@
 	{
 		If (LEqual(^BOX3.XBCM (Arg0), Ones))
 		{
-			^LEGA.XBCM (Arg0)
+			//TODO: fix Windows initial setup ^LEGA.XBCM (Arg0)
 		}
 	}
 

src/drivers/intel/ish/ish.c

@@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_ISHB,
 	PCI_DEVICE_ID_INTEL_CML_ISHB,
 	PCI_DEVICE_ID_INTEL_TGL_ISHB,
+	PCI_DEVICE_ID_INTEL_TGL_H_ISHB,
 	0
 };
 

src/drivers/smmstore/smi.c

@@ -143,7 +143,7 @@ static uint32_t smmstorev2_exec(uint8_t command, void *param)
 
 uint32_t smmstore_exec(uint8_t command, void *param)
 {
-	if (!param)
+	if (command != SMMSTORE_CMD_CLEAR && !param)
 		return SMMSTORE_RET_FAILURE;
 
 	if (CONFIG(SMMSTORE_V2))

src/drivers/smmstore/store.c

@@ -8,6 +8,8 @@
 #include <console/console.h>
 #include <smmstore.h>
 #include <types.h>
+#include <bootstate.h>
+#include <option.h>
 
 /*
  * The region format is still not finalized, but so far it looks like this:
@@ -459,3 +461,28 @@ int smmstore_rawclear_region(uint32_t block_id)
 
 	return 0;
 }
+
+static void clear_store_on_reset(void *unused)
+{
+	int preserve = 1;
+	int ret;
+
+	ret = get_option(&preserve, "preserve_smmstore");
+	if (ret != CB_SUCCESS) {
+		/*
+		 * If the RTC cleared the CMOS earlier we will get an invalid
+		 * checksum error.
+		 */
+		preserve = ret != CB_CMOS_CHECKSUM_INVALID;
+	}
+
+	if (!preserve) {
+		printk(BIOS_DEBUG, "SMMSTORE: CMOS reset, clearing store\n");
+		if (smmstore_clear_region() == 0) {
+			preserve = 1;
+			set_option("preserve_smmstore", &preserve);
+		}
+	}
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, clear_store_on_reset, NULL);

src/drivers/system76/dgpu/Kconfig

@@ -0,0 +1,12 @@
+config DRIVERS_SYSTEM76_DGPU
+	bool
+	default n
+	help
+		System76 switchable graphics support
+
+#TODO: make this cleaner, use device tree?
+config DRIVERS_SYSTEM76_DGPU_DEVICE
+	hex
+	default 0x01
+	help
+		System76 switchable graphics root device number

src/drivers/system76/dgpu/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_SYSTEM76_DGPU) += ramstage.c

src/drivers/system76/dgpu/acpi/dgpu.asl

@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEGP) {
+	Name (_ADR, CONFIG_DRIVERS_SYSTEM76_DGPU_DEVICE << 16)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
+		}
+
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
+		}
+	}
+
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
+}
+
+Device (\_SB.PCI0.PEGP.DEV0) {
+	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+        //TODO: use DGPU_DEVICE to generate address
+	OperationRegion (RPCX, SystemMemory, CONFIG_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
+
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
+
+				Debug = "    Sleep 16"
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
+	}
+
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
+}

src/drivers/system76/dgpu/bootblock.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: do not require this to be included in mainboard bootblock.c
+
+#include <console/console.h>
+#include <delay.h>
+#include <gpio.h>
+
+static void dgpu_power_enable(int onoff) {
+	printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff);
+	if (onoff) {
+		gpio_set(DGPU_RST_N, 0);
+		mdelay(4);
+		gpio_set(DGPU_PWR_EN, 1);
+		mdelay(4);
+		gpio_set(DGPU_RST_N, 1);
+	} else {
+		gpio_set(DGPU_RST_N, 0);
+		mdelay(4);
+		gpio_set(DGPU_PWR_EN, 0);
+	}
+	mdelay(50);
+}

src/drivers/system76/dgpu/ramstage.c

@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/pci.h>
+
+static void dgpu_read_resources(struct device *dev) {
+	printk(BIOS_INFO, "system76: dgpu_read_resources %s\n", dev_path(dev));
+
+    pci_dev_read_resources(dev);
+
+	int bar;
+	// Find all BARs on DGPU, mark them above 4g if prefetchable
+	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		printk(BIOS_INFO, "  BAR at 0x%02x\n", bar);
+
+	    struct resource *res;
+		res = probe_resource(dev, bar);
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "    marked above 4g\n");
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_INFO, "    not prefetch\n");
+			}
+		} else {
+			printk(BIOS_INFO, "    not found\n");
+		}
+	}
+}
+
+static void dgpu_enable_resources(struct device *dev) {
+	printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev));
+
+	dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID;
+	dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID;
+	printk(BIOS_INFO, "  subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device);
+	pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff));
+
+	pci_dev_enable_resources(dev);
+}
+
+static struct device_operations dgpu_pci_ops_dev = {
+	.read_resources   = dgpu_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = dgpu_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &pci_dev_ops_pci,
+};
+
+static void dgpu_above_4g(void *unused) {
+	struct device *pdev;
+
+	// Find PEGP
+	pdev = pcidev_on_root(CONFIG_DRIVERS_SYSTEM76_DGPU_DEVICE, 0);
+	if (!pdev) {
+		printk(BIOS_ERR, "system76: failed to find PEGP\n");
+		return;
+	}
+	printk(BIOS_INFO, "system76: PEGP at %p, %04x:%04x\n", pdev, pdev->vendor, pdev->device);
+
+    int fn;
+    for (fn = 0; fn < 8; fn++) {
+	    struct device *dev;
+
+        // Find DGPU functions
+        dev = pcidev_path_behind(pdev->link_list, PCI_DEVFN(0, fn));
+        if (dev) {
+            printk(BIOS_INFO, "system76: DGPU fn %d at %p, %04x:%04x\n", fn, dev, dev->vendor, dev->device);
+            dev->ops = &dgpu_pci_ops_dev;
+        } else {
+            printk(BIOS_ERR, "system76: failed to find DGPU fn %d\n", fn);
+        }
+    }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, dgpu_above_4g, NULL);

src/ec/system76/ec/Kconfig

@@ -12,3 +12,13 @@ config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	depends on EC_SYSTEM76_EC
 	bool
 	default n
+
+config EC_SYSTEM76_EC_DGPU
+	depends on EC_SYSTEM76_EC
+	bool
+	default n
+
+config EC_SYSTEM76_EC_OLED
+	depends on EC_SYSTEM76_EC
+	bool
+	default n

src/ec/system76/ec/acpi/battery.asl

@@ -30,29 +30,29 @@ Device (BAT0)
 
 	Name (PBIF, Package (0x0D)
 	{
-		One,
-		0xFFFFFFFF,
-		0xFFFFFFFF,
-		One,
-		0x39D0,
-		Zero,
-		Zero,
-		0x40,
-		0x40,
-		"BAT",
-		"0001",
-		"LION",
-		"Notebook"
+		One, // 0 - Power Unit
+		0xFFFFFFFF, // 1 - Design Capacity
+		0xFFFFFFFF, // 2 - Last Full Charge Capacity
+		One, // 3 - Battery Technology
+		0xFFFFFFFF, // 4 - Design Voltage
+		Zero, // 5 - Design Capacity of Warning
+		Zero, // 6 - Design Capacity of Low
+		0x40, // 7 - Battery Capacity Granularity 1
+		0x40, // 8 - Battery Capacity Granularity 2
+		" ", // 9 - Model Number
+		" ", // 10 - Serial Number
+		" ", // 11 - Battery Type
+		" " // 12 - OEM Information
 	})
 	Method (IVBI, 0, NotSerialized)
 	{
-		PBIF [One] = 0xFFFFFFFF
-		PBIF [0x02] = 0xFFFFFFFF
-		PBIF [0x04] = 0xFFFFFFFF
-		PBIF [0x09] = " "
-		PBIF [0x0A] = " "
-		PBIF [0x0B] = " "
-		PBIF [0x0C] = " "
+		PBIF [1] = 0xFFFFFFFF
+		PBIF [2] = 0xFFFFFFFF
+		PBIF [4] = 0xFFFFFFFF
+		PBIF [9] = " "
+		PBIF [10] = " "
+		PBIF [11] = " "
+		PBIF [12] = " "
 		BFCC = Zero
 	}
 
@@ -61,20 +61,20 @@ Device (BAT0)
 		If (^^PCI0.LPCB.EC0.BAT0)
 		{
 			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
-			PBIF [One] = Local0
+			PBIF [1] = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
-			PBIF [0x02] = Local0
+			PBIF [2] = Local0
 			BFCC = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
-			PBIF [0x04] = Local0
+			PBIF [4] = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
-			PBIF [0x05] = Local0
+			PBIF [5] = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
-			PBIF [0x06] = Local0
-			PBIF [0x09] = "BAT"
-			PBIF [0x0A] = "0001"
-			PBIF [0x0B] = "LION"
-			PBIF [0x0C] = "Notebook"
+			PBIF [6] = Local0
+			PBIF [9] = "BAT"
+			PBIF [10] = "0001"
+			PBIF [11] = "LION"
+			PBIF [12] = "Notebook"
 		}
 		Else
 		{
@@ -96,19 +96,96 @@ Device (BAT0)
 		Return (PBIF) /* \_SB_.BAT0.PBIF */
 	}
 
+	Name (PBIX, Package (0x14)
+	{
+		Zero, // 0 - Revision
+		One, // 1 - Power Unit
+		0xFFFFFFFF, // 2 - Design Capacity
+		0xFFFFFFFF, // 3 - Last Full Charge Capacity
+		One, // 4 - Battery Technology
+		0xFFFFFFFF, // 5 - Design Voltage
+		Zero, // 6 - Design Capacity of Warning
+		Zero, // 7 - Design Capacity of Low
+		Zero, // 8 - Cycle Count
+		98000, // 9 - Measurement Accuracy
+		0xFFFFFFFF, // 10 - Max Sampling Time
+		0xFFFFFFFF, // 11 - Min Sampling Time
+		0xFFFFFFFF, // 12 - Max Averaging Interval
+		0xFFFFFFFF, // 13 - Min Averaging Interval
+		0x40, // 14 - Battery Capacity Granularity 1
+		0x40, // 15 - Battery Capacity Granularity 2
+		" ", // 16 - Model Number
+		" ", // 17 - Serial Number
+		" ", // 18 - Battery Type
+		" " // 19 - OEM Information
+	})
+
+	Method (IVBX, 0, NotSerialized)
+	{
+		PBIX [2] = 0xFFFFFFFF
+		PBIX [3] = 0xFFFFFFFF
+		PBIX [5] = 0xFFFFFFFF
+		PBIX [16] = " "
+		PBIX [17] = " "
+		PBIX [18] = " "
+		PBIX [19] = " "
+		BFCC = Zero
+	}
+
+	Method (UPBX, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
+			PBIX [2] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
+			PBIX [3] = Local0
+			BFCC = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
+			PBIX [5] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
+			PBIX [6] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
+			PBIX [7] = Local0
+			LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
+			PBIX [8] = LOCAL0
+			PBIX [16] = "BAT"
+			PBIX [17] = "0001"
+			PBIX [18] = "LION"
+			PBIX [19] = "Notebook"
+		}
+		Else
+		{
+			IVBX ()
+		}
+	}
+
+	Method (_BIX, 0, NotSerialized)  // _BIX: Battery Information Extended
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBX ()
+		}
+		Else
+		{
+			IVBX ()
+		}
+		Return (PBIX) /* \_SB_.BAT0.PBIX */
+	}
+
 	Name (PBST, Package (0x04)
 	{
-		Zero,
-		0xFFFFFFFF,
-		0xFFFFFFFF,
-		0x3D90
+		Zero, // 0 - Battery state
+		0xFFFFFFFF, // 1 - Battery present rate
+		0xFFFFFFFF, // 2 - Battery remaining capacity
+		0xFFFFFFFF // 3 - Battery present voltage
 	})
 	Method (IVBS, 0, NotSerialized)
 	{
-		PBST [Zero] = Zero
-		PBST [One] = 0xFFFFFFFF
-		PBST [0x02] = 0xFFFFFFFF
-		PBST [0x03] = 0x2710
+		PBST [0] = Zero
+		PBST [1] = 0xFFFFFFFF
+		PBST [2] = 0xFFFFFFFF
+		PBST [3] = 0xFFFFFFFF
 	}
 
 	Method (UPBS, 0, NotSerialized)
@@ -139,10 +216,10 @@ Device (BAT0)
 
 			Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
 			Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
-			PBST [Zero] = Local0
-			PBST [One] = Local1
-			PBST [0x02] = Local2
-			PBST [0x03] = Local3
+			PBST [0] = Local0
+			PBST [1] = Local1
+			PBST [2] = Local2
+			PBST [3] = Local3
 			If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
 			{
 				Notify (BAT0, 0x81) // Information Change

src/ec/system76/ec/acpi/ec.asl

@@ -62,9 +62,13 @@ Device (\_SB.PCI0.LPCB.EC0)
 		}
 	}
 
+	Name (S3OS, Zero)
 	Method (PTS, 1, Serialized) {
 		Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
 		If (ECOK) {
+			// Save ECOS during sleep
+			S3OS = ECOS
+
 			// Clear wake cause
 			WFNO = Zero
 		}
@@ -73,6 +77,9 @@ Device (\_SB.PCI0.LPCB.EC0)
 	Method (WAK, 1, Serialized) {
 		Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
 		If (ECOK) {
+			// Restore ECOS after sleep
+			ECOS = S3OS
+
 			// Set current AC state
 			^^^^AC.ACFG = ADP
 
@@ -97,6 +104,9 @@ Device (\_SB.PCI0.LPCB.EC0)
 	Method (_Q0B, 0, NotSerialized) // Screen Toggle
 	{
 		Debug = "EC: Screen Toggle"
+#if CONFIG(EC_SYSTEM76_EC_OLED)
+		Notify (^^^^S76D, 0x85)
+#endif // CONFIG(EC_SYSTEM76_EC_OLED)
 	}
 
 	Method (_Q0C, 0, NotSerialized)  // Mute

src/ec/system76/ec/acpi/ec_ram.asl

@@ -28,6 +28,7 @@ Field (ERAM, ByteAcc, Lock, Preserve)
 	Offset (0x3A),
 	BCW0, 32,
 	BCL0, 32,
+	CYC0, 16,	// Battery cycle count
 	Offset (0x68),
 	ECOS, 8,	// Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
 	Offset (0xC8),

src/ec/system76/ec/acpi/s76.asl

@@ -6,6 +6,7 @@
 //   0x82 - backlight down
 //   0x83 - backlight up
 //   0x84 - backlight color change
+//   0x85 - OLED screen toggle
 Device (S76D) {
 	Name (_HID, "17761776")
 	Name (_UID, 0)
@@ -111,4 +112,57 @@ Device (S76D) {
 		}
 	}
 #endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+
+	// Fan names
+	Method (NFAN, 0, Serialized) {
+		Return (Package (2) {
+			"CPU fan",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU fan",
+#endif // CONFIG(EC_SYSTEM76_EC_DGPU)
+		})
+	}
+
+	// Get fan duty and RPM as a single value
+	Method (GFAN, 1, Serialized) {
+		Local0 = 0
+		Local1 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT1
+				Local1 = ^^PCI0.LPCB.EC0.RPM1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT2
+				Local1 = ^^PCI0.LPCB.EC0.RPM2
+			}
+		}
+		If (Local1 != 0) {
+			// 60 * (EC frequency / 120) / 2
+			Local1 = 2156250 / Local1
+		}
+		Return ((Local1 << 8) | Local0)
+	}
+
+	// Temperature names
+	Method (NTMP, 0, Serialized) {
+		Return (Package (2) {
+			"CPU temp",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU temp",
+#endif // CONFIG(EC_SYSTEM76_EC_DGPU)
+		})
+	}
+
+	// Get temperature
+	Method (GTMP, 1, Serialized) {
+		Local0 = 0;
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP2
+			}
+		}
+		Return (Local0)
+	}
 }

src/include/device/pci_ids.h

@@ -2155,6 +2155,7 @@
 #define PCI_DEVICE_ID_INTEL_CNL_ISHB	0x9dfc
 #define PCI_DEVICE_ID_INTEL_CML_ISHB	0x02fc
 #define PCI_DEVICE_ID_INTEL_TGL_ISHB	0xa0fc
+#define PCI_DEVICE_ID_INTEL_TGL_H_ISHB	0x43fc
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DEVICE_ID_INTEL_82371FB_ISA		0x122e
@@ -2917,6 +2918,7 @@
 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24	0xA09D
 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25	0xA09E
 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26	0xA09F
+#define PCI_DEVICE_ID_INTEL_TGP_H_ESPI_HM570	0x438B
 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_0			0x4b00
 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_1			0x4b04
 #define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI		0x4b03
@@ -3161,6 +3163,31 @@
 #define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15		0xa0b6
 #define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16		0xa0b7
 
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP1		0x43b8
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP2		0x43b9
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP3		0x43ba
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP4		0x43bb
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP5		0x43bc
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP6		0x43bd
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP7		0x43be
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP8		0x43bf
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP9		0x43b0
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP10		0x43b1
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP11		0x43b2
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP12		0x43b3
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP13		0x43b4
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP14		0x43b5
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP15		0x43b6
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP16		0x43b7
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP17		0x43c0
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP18		0x43c1
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP19		0x43c2
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP20		0x43c3
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP21		0x43c4
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP22		0x43c5
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP23		0x43c6
+#define PCI_DEVICE_ID_INTEL_TGP_H_PCIE_RP24		0x43c7
+
 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1		0xa338
 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2		0xa339
 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3		0xa33a
@@ -3338,6 +3365,7 @@
 #define PCI_DEVICE_ID_INTEL_TGP_SATA		0xa0d5
 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA	0xa0d7
 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA	0x282a
+#define PCI_DEVICE_ID_INTEL_TGP_H_SATA	0x43d3
 #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA	0x4b60
 #define PCI_DEVICE_ID_INTEL_JSP_SATA_1		0x4dd2
 #define PCI_DEVICE_ID_INTEL_JSP_SATA_2		0x4dd3
@@ -3368,6 +3396,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_PMC		0x02a1
 #define PCI_DEVICE_ID_INTEL_CMP_H_PMC		0x06a1
 #define PCI_DEVICE_ID_INTEL_TGP_PMC		0xa0a1
+#define PCI_DEVICE_ID_INTEL_TGP_H_PMC		0x43a1
 #define PCI_DEVICE_ID_INTEL_MCC_PMC		0x4b21
 #define PCI_DEVICE_ID_INTEL_JSP_PMC		0x4da1
 #define PCI_DEVICE_ID_INTEL_ADP_P_PMC		0x7a21
@@ -3436,6 +3465,13 @@
 #define PCI_DEVICE_ID_INTEL_TGP_I2C5		0xa0c6
 #define PCI_DEVICE_ID_INTEL_TGP_I2C6		0xa0d8
 #define PCI_DEVICE_ID_INTEL_TGP_I2C7		0xa0d9
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C0		0x43e8
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C1		0x43e9
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C2		0x43ea
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C3		0x43eb
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C4		0x43ad
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C5		0x43ae
+#define PCI_DEVICE_ID_INTEL_TGP_H_I2C6		0x43d8
 #define PCI_DEVICE_ID_INTEL_MCC_I2C0		0x4b78
 #define PCI_DEVICE_ID_INTEL_MCC_I2C1		0x4b79
 #define PCI_DEVICE_ID_INTEL_MCC_I2C2		0x4b7a
@@ -3504,6 +3540,10 @@
 #define PCI_DEVICE_ID_INTEL_TGP_UART0		0xa0a8
 #define PCI_DEVICE_ID_INTEL_TGP_UART1		0xa0a9
 #define PCI_DEVICE_ID_INTEL_TGP_UART2		0xa0c7
+#define PCI_DEVICE_ID_INTEL_TGP_H_UART0		0x43a8
+#define PCI_DEVICE_ID_INTEL_TGP_H_UART1		0x43a9
+#define PCI_DEVICE_ID_INTEL_TGP_H_UART2		0x43a7
+#define PCI_DEVICE_ID_INTEL_TGP_H_UART3		0x43da
 #define PCI_DEVICE_ID_INTEL_MCC_UART0		0x4b28
 #define PCI_DEVICE_ID_INTEL_MCC_UART1		0x4b29
 #define PCI_DEVICE_ID_INTEL_MCC_UART2		0x4b4d
@@ -3570,6 +3610,11 @@
 #define PCI_DEVICE_ID_INTEL_TGP_GSPI4		0xa0fe
 #define PCI_DEVICE_ID_INTEL_TGP_GSPI5		0xa0de
 #define PCI_DEVICE_ID_INTEL_TGP_GSPI6		0xa0df
+#define PCI_DEVICE_ID_INTEL_TGP_H_SPI0		0x43a4
+#define PCI_DEVICE_ID_INTEL_TGP_H_GSPI0		0x43aa
+#define PCI_DEVICE_ID_INTEL_TGP_H_GSPI1		0x43ab
+#define PCI_DEVICE_ID_INTEL_TGP_H_GSPI2		0x43fb
+#define PCI_DEVICE_ID_INTEL_TGP_H_GSPI3		0x43fd
 #define PCI_DEVICE_ID_INTEL_MCC_SPI0		0x4b24
 #define PCI_DEVICE_ID_INTEL_MCC_GSPI0		0x4b2a
 #define PCI_DEVICE_ID_INTEL_MCC_GSPI1		0x4b2b
@@ -3697,6 +3742,8 @@
 #define PCI_DEVICE_ID_INTEL_TGL_GT2			0xFF20
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_Y			0x9A40
 #define PCI_DEVICE_ID_INTEL_TGL_GT0			0x9A7F
+#define PCI_DEVICE_ID_INTEL_TGL_GT1_H_32			0x9A60
+#define PCI_DEVICE_ID_INTEL_TGL_GT1_H_16			0x9A68
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT			0x9A49
 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT			0x9A52
 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX			0x9A40
@@ -3784,6 +3831,8 @@
 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2	0x9A14
 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2	0x9A02
 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2	0x9A12
+#define PCI_DEVICE_ID_INTEL_TGL_ID_H_6_1	0x9A26
+#define PCI_DEVICE_ID_INTEL_TGL_ID_H_8_1	0x9A36
 #define PCI_DEVICE_ID_INTEL_JSL_EHL		0x4532
 #define PCI_DEVICE_ID_INTEL_EHL_ID_1		0x4510
 #define PCI_DEVICE_ID_INTEL_EHL_ID_2		0x4522
@@ -3842,6 +3891,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS			0x02a3
 #define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS			0x06a3
 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS		0xa0a3
+#define PCI_DEVICE_ID_INTEL_TGP_H_SMBUS		0x43a3
 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS			0x4b23
 #define PCI_DEVICE_ID_INTEL_JSP_SMBUS			0x4da3
 #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS			0xa0a3
@@ -3869,6 +3919,8 @@
 #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI		0x06ed
 #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI		0xa0ed
 #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI	0x9a13
+#define PCI_DEVICE_ID_INTEL_TGP_H_XHCI		0x43ed
+#define PCI_DEVICE_ID_INTEL_TGP_H_TCSS_XHCI	0x9a17
 #define PCI_DEVICE_ID_INTEL_MCC_XHCI		0x4b7d
 #define PCI_DEVICE_ID_INTEL_JSP_XHCI		0x4ded
 #define PCI_DEVICE_ID_INTEL_ADP_P_XHCI		0x51ed
@@ -3889,6 +3941,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_P2SB		0x02a0
 #define PCI_DEVICE_ID_INTEL_CMP_H_P2SB		0x06a0
 #define PCI_DEVICE_ID_INTEL_TGL_P2SB		0xa0a0
+#define PCI_DEVICE_ID_INTEL_TGL_H_P2SB		0x43a0
 #define PCI_DEVICE_ID_INTEL_EHL_P2SB		0x4b20
 #define PCI_DEVICE_ID_INTEL_JSP_P2SB		0x4da0
 #define PCI_DEVICE_ID_INTEL_ADP_P_P2SB		0x7a20
@@ -3903,6 +3956,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_SRAM		0x02ef
 #define PCI_DEVICE_ID_INTEL_CMP_H_SRAM		0x06ef
 #define PCI_DEVICE_ID_INTEL_TGL_SRAM		0xa0ef
+#define PCI_DEVICE_ID_INTEL_TGL_H_SRAM		0x43ef
 #define PCI_DEVICE_ID_INTEL_MCC_SRAM		0x4b7f
 #define PCI_DEVICE_ID_INTEL_JSP_SRAM		0x4def
 #define PCI_DEVICE_ID_INTEL_ADP_P_SRAM		0x7a6f
@@ -3925,6 +3979,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO		0x06c8
 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO		0x2284
 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO		0xa0c8
+#define PCI_DEVICE_ID_INTEL_TGL_H_AUDIO		0x43c8
 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO		0x4b55
 #define PCI_DEVICE_ID_INTEL_JSP_AUDIO		0x4dc8
 #define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1	0x7ad0
@@ -3955,6 +4010,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_CSE0		0x02e0
 #define PCI_DEVICE_ID_INTEL_CMP_H_CSE0		0x06e0
 #define PCI_DEVICE_ID_INTEL_TGL_CSE0		0xa0e0
+#define PCI_DEVICE_ID_INTEL_TGL_H_CSE0		0x43e0
 #define PCI_DEVICE_ID_INTEL_MCC_CSE0		0x4b70
 #define PCI_DEVICE_ID_INTEL_MCC_CSE1		0x4b71
 #define PCI_DEVICE_ID_INTEL_MCC_CSE2		0x4b74
@@ -3983,6 +4039,7 @@
 #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI		0x06ee
 #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI		0xa0ee
 #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI	0x9a15
+#define PCI_DEVICE_ID_INTEL_TGP_H_XDCI		0x43ee
 #define PCI_DEVICE_ID_INTEL_MCC_XDCI		0x4b7e
 #define PCI_DEVICE_ID_INTEL_JSP_XDCI		0x4dee
 #define PCI_DEVICE_ID_INTEL_ADP_P_XDCI		0x51ee
@@ -4012,12 +4069,18 @@
 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1		0x9a25
 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2		0x9a27
 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3		0x9a29
+#define PCI_DEVICE_ID_INTEL_TGL_H_TBT_RP0		0x9a2b
+#define PCI_DEVICE_ID_INTEL_TGL_H_TBT_RP1		0x9a2d
+#define PCI_DEVICE_ID_INTEL_TGL_H_TBT_RP2		0x9a2f
+#define PCI_DEVICE_ID_INTEL_TGL_H_TBT_RP3		0x9a31
 #define PCI_DEVICE_ID_INTEL_ADL_TBT_RP0		0x466e
 #define PCI_DEVICE_ID_INTEL_ADL_TBT_RP1		0x463f
 #define PCI_DEVICE_ID_INTEL_ADL_TBT_RP2		0x462f
 #define PCI_DEVICE_ID_INTEL_ADL_TBT_RP3		0x461f
 #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0	0x9a1b
 #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1	0x9a1d
+#define PCI_DEVICE_ID_INTEL_TGL_H_TBT_DMA0	0x9a1f
+#define PCI_DEVICE_ID_INTEL_TGL_H_TBT_DMA1	0x9a21
 #define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA0	0x463e
 #define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA1	0x466d
 
@@ -4054,6 +4117,7 @@
 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI	0x7af0
 
 #define PCI_DEVICE_ID_INTEL_TGL_IPU		0x9a19
+#define PCI_DEVICE_ID_INTEL_TGL_H_IPU		0x9a39
 #define PCI_DEVICE_ID_INTEL_JSL_IPU		0x4e19
 #define PCI_DEVICE_ID_INTEL_ADL_IPU		0x465d
 
@@ -4082,6 +4146,13 @@
 #define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1	0xa0f6
 #define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2	0xa0f7
 #define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3	0xa0f8
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_0	0x43f0
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_1	0x43f1
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_2	0x43f2
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_3	0x43f3
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_0	0x43f5
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_1	0x43f6
+#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_2	0x43f7
 
 #define PCI_VENDOR_ID_COMPUTONE		0x8e0e
 #define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291

src/mainboard/system76/addw1/Kconfig

@@ -0,0 +1,81 @@
+if BOARD_SYSTEM76_ADDW1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_OLED
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COFFEELAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+	select USE_OPTION_TABLE
+
+config MAINBOARD_DIR
+	string
+	default "system76/addw1"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "addw1"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Adder WS"
+
+config MAINBOARD_VERSION
+	string
+	default "addw1"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 16
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/addw1/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ADDW1
+	bool "addw1"

src/mainboard/system76/addw1/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/addw1/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/addw1/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/addw1/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: addw1
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/addw1/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/addw1/cmos.default

@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
+preserve_smmstore=0

src/mainboard/system76/addw1/cmos.layout

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+408	1	h	1	preserve_smmstore
+409	2	e	7	power_on_after_fail
+412	4	e	6	debug_level
+984	16	h	0	check_sum
+
+enumerations
+
+1	0	Disable
+1	1	Enable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+checksums
+
+checksum 408 983 984

src/mainboard/system76/addw1/devicetree.cb

@@ -0,0 +1,224 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x65e1 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on      # GPU Port
+			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+			register "PcieClkSrcUsage[8]" = "0x40"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device pci 02.0 on end  # Integrated Graphics Device
+		device pci 04.0 on      # SA Thermal device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+		end
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		device pci 14.3 on      # CNVi wifi
+			#chip drivers/intel/wifi
+			#	register "wake" = "PME_B0_EN_BIT"
+			#end
+		end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+			register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+		end
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on      # PCI Express Port 17
+			# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
+			register "PcieRpEnable[16]" = "1"
+			register "PcieRpLtrEnable[16]" = "1"
+			register "PcieRpHotPlug[16]" = "1"
+			register "PcieClkSrcUsage[0]" = "16"
+			register "PcieClkSrcClkReq[0]" = "0"
+		end
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on      # PCI Express Port 21
+			# PCI Express root port #21 x4, Clock 10 (SSD2)
+			register "PcieRpEnable[20]" = "1"
+			register "PcieRpLtrEnable[20]" = "1"
+			register "PcieClkSrcUsage[10]" = "20"
+			register "PcieClkSrcClkReq[10]" = "10"
+			register "PcieRpSlotImplemented[20]" = "1"
+		end
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express root port #9 x4, Clock 9 (SSD1)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[9]" = "8"
+			register "PcieClkSrcClkReq[9]" = "9"
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on      # PCI Express Port 14
+			# PCI Express root port #14 x1, Clock 5 (GLAN)
+			register "PcieRpEnable[13]" = "1"
+			register "PcieRpLtrEnable[13]" = "1"
+			register "PcieClkSrcUsage[5]" = "13"
+			register "PcieClkSrcClkReq[5]" = "5"
+			register "PcieRpSlotImplemented[13]" = "1"
+		end
+		device pci 1d.6 on      # PCI Express Port 15
+			# PCI Express root port #15 x1, Clock 7 (Card Reader)
+			register "PcieRpEnable[14]" = "1"
+			register "PcieRpLtrEnable[14]" = "1"
+			register "PcieClkSrcUsage[7]" = "14"
+			register "PcieClkSrcClkReq[7]" = "7"
+			register "PcieRpSlotImplemented[14]" = "1"
+		end
+		device pci 1d.7 on      # PCI Express Port 16
+			# PCI Express root port #16 x1, Clock 6 (WLAN)
+			register "PcieRpEnable[15]" = "1"
+			register "PcieRpLtrEnable[15]" = "1"
+			register "PcieClkSrcUsage[6]" = "15"
+			register "PcieClkSrcClkReq[6]" = "6"
+			register "PcieRpSlotImplemented[15]" = "1"
+		end
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			register "gen1_dec" = "0x000c0081"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x00fc0e01"
+			register "gen4_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on      # SMBus
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/addw1/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/addw1/gpio.h

@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_C12
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
+	PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, NONE),
+	PAD_NC(GPD7, NONE), // RESERVED STRAP
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE),
+	PAD_NC(GPD10, NONE),
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, DN_20K),
+	PAD_NC(GPP_A11, UP_20K),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+	PAD_NC(GPP_A14, NONE),
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#
+	PAD_NC(GPP_A16, DN_20K),
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
+	PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
+	PAD_NC(GPP_A19, NONE),
+	PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // PEX_WAKE#
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SMARTAMP_SW
+	PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V)
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), // PCH_GPP_B3 (touchpad interrupt)
+	PAD_NC(GPP_B4, NONE),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
+	PAD_NC(GPP_B19, NONE),
+	PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE#
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_C10, NONE, DEEP), //  BOARD_ID1
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
+	PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+	PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET
+	PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT#
+	PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
+	PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
+	PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_NC(GPP_E2, NONE),
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
+	PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP), // PCH_MUTE#
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
+	PAD_NC(GPP_E9, NONE), // USB_OC0# (test point)
+	PAD_NC(GPP_E10, NONE), // USB_OC1# (test point)
+	PAD_NC(GPP_E11, NONE), // USB_OC2# (test point)
+	PAD_NC(GPP_E12, NONE), // USB_OC3# (test point)
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP), // GPP_F3_LAN_RST#
+	PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP), // GPP_F4_TBT_RST#
+	PAD_NC(GPP_F5, NONE),
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F7, NONE),
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
+	PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
+	PAD_NC(GPP_F15, NONE), // USB_OC4# (test point)
+	PAD_NC(GPP_F16, NONE), // USB_OC5# (test point)
+	PAD_NC(GPP_F17, NONE), // USB_OC6# (test point)
+	PAD_NC(GPP_F18, NONE), // USB_OC7# (test point)
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
+	PAD_NC(GPP_G1, NONE),
+	PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET#
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
+	PAD_NC(GPP_G7, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
+	PAD_NC(GPP_H5, NONE),
+	PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
+	PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
+	PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
+	PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE#
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
+	PAD_NC(GPP_H14, NONE),
+	PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
+	_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN
+	PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_H18, NONE),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP
+	PAD_NC(GPP_H22, NONE),
+	_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD
+	PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
+	PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP), // TBT_GPIO_RST#
+	PAD_NC(GPP_I6, NONE),
+	PAD_NC(GPP_I7, NONE),
+	PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
+	PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
+	PAD_NC(GPP_I10, NONE),
+	PAD_NC(GPP_I11, NONE),
+	PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
+	PAD_NC(GPP_J2, NONE),
+	PAD_NC(GPP_J3, NONE),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_J10, NONE),
+	PAD_NC(GPP_J11, DN_20K),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE
+	PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE
+	PAD_NC(GPP_K2, NONE),
+	_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
+	PAD_NC(GPP_K4, NONE),
+	PAD_NC(GPP_K5, NONE),
+	_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
+	PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
+	PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // GPP_K8_LAN_RTD3
+	PAD_NC(GPP_K9, NONE),
+	PAD_NC(GPP_K10, NONE),
+	PAD_NC(GPP_K11, NONE),
+	PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP), // PCH_GPP_K12
+	PAD_NC(GPP_K13, NONE),
+	PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
+	_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
+	PAD_NC(GPP_K16, NONE),
+	PAD_NC(GPP_K17, NONE),
+	PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE#
+	_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19
+	PAD_NC(GPP_K20, NONE),
+	PAD_NC(GPP_K21, NONE),
+	PAD_NC(GPP_K22, NONE),
+	PAD_NC(GPP_K23, NONE),
+};
+
+#endif
+
+#endif

src/mainboard/system76/addw1/hda_verb.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865d1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865d1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/addw1/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/addw1/romstage.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.rcomp_resistor = { 121, 75, 100 },
+	.rcomp_targets = { 50, 25, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/addw2/Kconfig

@@ -0,0 +1,89 @@
+if BOARD_SYSTEM76_ADDW2
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_OLED
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+	select USE_OPTION_TABLE
+
+config MAINBOARD_DIR
+	string
+	default "system76/addw2"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "addw2"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Adder WS"
+
+config MAINBOARD_VERSION
+	string
+	default "addw2"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 16
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9bc4.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9bc4"
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/addw2/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ADDW2
+	bool "addw2"

src/mainboard/system76/addw2/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/addw2/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/addw2/acpi/mainboard.asl

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/addw2/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/addw2/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: addw2
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/addw2/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/addw2/cmos.default

@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+preserve_smmstore=0

src/mainboard/system76/addw2/cmos.layout

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+408	1	h	1	preserve_smmstore
+#409	2	e	7	power_on_after_fail
+412	4	e	6	debug_level
+984	16	h	0	check_sum
+
+enumerations
+
+1	0	Disable
+1	1	Enable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+checksums
+
+checksum 408 983 984

src/mainboard/system76/addw2/devicetree.cb

@@ -0,0 +1,218 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x65e1 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on      # GPU Port
+			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+			register "PcieClkSrcUsage[8]" = "0x40"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on      # SA Thermal device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+		end
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A14_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+			register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+		end
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on      # PCI Express Port 17
+			# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
+			register "PcieRpEnable[16]" = "1"
+			register "PcieRpLtrEnable[16]" = "1"
+			register "PcieRpHotPlug[16]" = "1"
+			register "PcieClkSrcUsage[0]" = "16"
+			register "PcieClkSrcClkReq[0]" = "0"
+		end
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on      # PCI Express Port 21
+			# PCI Express root port #21 x4, Clock 10 (SSD2)
+			register "PcieRpEnable[20]" = "1"
+			register "PcieRpLtrEnable[20]" = "1"
+			register "PcieClkSrcUsage[10]" = "20"
+			register "PcieClkSrcClkReq[10]" = "10"
+		end
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express root port #9 x4, Clock 9 (SSD1)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[9]" = "8"
+			register "PcieClkSrcClkReq[9]" = "9"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on      # PCI Express Port 14
+			# PCI Express root port #14 x1, Clock 5 (GLAN)
+			register "PcieRpEnable[13]" = "1"
+			register "PcieRpLtrEnable[13]" = "1"
+			register "PcieClkSrcUsage[5]" = "13"
+			register "PcieClkSrcClkReq[5]" = "5"
+		end
+		device pci 1d.6 on      # PCI Express Port 15
+			# PCI Express root port #15 x1, Clock 7 (Card Reader)
+			register "PcieRpEnable[14]" = "1"
+			register "PcieRpLtrEnable[14]" = "1"
+			register "PcieClkSrcUsage[7]" = "14"
+			register "PcieClkSrcClkReq[7]" = "7"
+		end
+		device pci 1d.7 on      # PCI Express Port 16
+			# PCI Express root port #16 x1, Clock 6 (WLAN)
+			register "PcieRpEnable[15]" = "1"
+			register "PcieRpLtrEnable[15]" = "1"
+			register "PcieClkSrcUsage[6]" = "15"
+			register "PcieClkSrcClkReq[6]" = "6"
+		end
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			register "gen1_dec" = "0x000c0081"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x00fc0e01"
+			register "gen4_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end # tas5825m
+		end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/addw2/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/addw2/gpio.h

@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_K21
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
+	PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, NONE),
+	PAD_NC(GPD7, NONE), // RESERVED STRAP
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE),
+	PAD_NC(GPD10, NONE),
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_NC(GPP_A0, NONE),
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_A10, DN_20K),
+	PAD_NC(GPP_A11, UP_20K),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+	PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT#
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PW_ACK#
+	PAD_NC(GPP_A16, DN_20K),
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
+	PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
+	PAD_NC(GPP_A19, NONE),
+	PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
+	_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000), // EAPD_MODE
+	PAD_NC(GPP_A22, NONE),
+	PAD_CFG_GPI(GPP_A23, NONE, DEEP), // DGPU BOARD_ID
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
+	PAD_NC(GPP_B4, NONE),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_NC(GPP_B6, NONE),
+	PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP), // GPP_B7_CR_RST#
+	PAD_CFG_GPI(GPP_B8, NONE, DEEP), // GPP_B8_CR_WAKE#
+	PAD_NC(GPP_B9, NONE),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
+	PAD_NC(GPP_B19, NONE),
+	_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000), // SMI#_GPP_B20
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BIOS BOOT STRAP
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE#
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
+	PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+	PAD_CFG_GPI(GPP_C13, NONE, PLTRST), // TPM_DET
+	PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT#
+	PAD_CFG_GPI(GPP_C15, NONE, DEEP), // GPP_C15
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
+	PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
+	PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_NC(GPP_E2, NONE),
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
+	PAD_NC(GPP_E9, NONE), //  USB_OC0# (test point)
+	PAD_NC(GPP_E10, NONE), //  USB_OC1# (test point)
+	PAD_NC(GPP_E11, NONE), //  USB_OC2# (test point)
+	PAD_NC(GPP_E12, NONE), //  USB_OC3# (test point)
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP), // GPP_F3_LAN_RST#
+	PAD_CFG_GPI(GPP_F4, NONE, DEEP), // GPP_F4_TBT_RST#
+	PAD_NC(GPP_F5, NONE),
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F7, NONE),
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
+	PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY STRAP
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
+	PAD_NC(GPP_F15, NONE), // USB_OC4# (test point)
+	PAD_NC(GPP_F16, NONE), // USB_OC5# (test point)
+	PAD_NC(GPP_F17, NONE), // USB_OC6# (test point)
+	PAD_NC(GPP_F18, NONE), // USB_OC7# (test point)
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
+	PAD_NC(GPP_G1, NONE),
+	PAD_CFG_GPI(GPP_G2, NONE, DEEP), // DDS_DET
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
+	PAD_NC(GPP_G7, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CR_CLKREQ#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
+	PAD_NC(GPP_H5, NONE),
+	PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
+	PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
+	PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
+	_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000), // GPP_H9_TBT_WAKE#
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE STRAP
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
+	PAD_NC(GPP_H14, NONE),
+	PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
+	PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, DEEP), // TBT_RTD3_PWR_EN_R
+	PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
+	PAD_NC(GPP_H18, NONE),
+	PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP), // GPP_H19_CR_AUX33
+	PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP), // GPP_H20_CR_MV33
+	PAD_CFG_GPI(GPP_H21, NONE, DEEP), // 100k pull up, 10k pull down
+	PAD_NC(GPP_H22, NONE),
+	_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
+
+	/* ------- GPIO Group GPP_I ------- */
+	_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // MDP_B_HPD
+	_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // MDP_E_HPD
+	_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // PS8330B_HPD
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
+	PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST#
+	PAD_NC(GPP_I6, NONE),
+	PAD_NC(GPP_I7, NONE),
+	PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
+	PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
+	PAD_NC(GPP_I10, NONE),
+	PAD_NC(GPP_I11, NONE),
+	PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
+	PAD_NC(GPP_J2, NONE),
+	PAD_NC(GPP_J3, NONE),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_J10, NONE),
+	PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // 75k pull down
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE
+	PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE
+	PAD_NC(GPP_K2, NONE),
+	_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
+	PAD_NC(GPP_K4, NONE),
+	PAD_NC(GPP_K5, NONE),
+	_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
+	PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
+	PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // GPP_K8_LAN_RTD3
+	PAD_NC(GPP_K9, NONE),
+	PAD_NC(GPP_K10, NONE),
+	PAD_NC(GPP_K11, NONE),
+	PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP), // GPP_K12_PLVDD_SEL
+	PAD_NC(GPP_K13, NONE),
+	PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
+	_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
+	PAD_NC(GPP_K16, NONE),
+	PAD_NC(GPP_K17, NONE),
+	PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE#
+	PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_GPP_K19
+	PAD_NC(GPP_K20, NONE),
+	PAD_NC(GPP_K21, NONE),
+	PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP), // DGPU_OVRM
+	PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWR_OK
+};
+
+#endif
+
+#endif

src/mainboard/system76/addw2/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865e1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/addw2/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/addw2/romstage.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.rcomp_resistor = { 121, 75, 100 },
+	.rcomp_targets = { 50, 25, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/bonw14/Kconfig

@@ -0,0 +1,72 @@
+if BOARD_SYSTEM76_BONW14
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE_S
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/bonw14"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "bonw14"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Bonobo WS"
+
+config MAINBOARD_VERSION
+	string
+	default "bonw14"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 20
+
+config DIMM_MAX
+	int
+	default 4
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/bonw14/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_BONW14
+	bool "bonw14"

src/mainboard/system76/bonw14/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/bonw14/acpi/dgpu.asl

@@ -0,0 +1,113 @@
+Device (\_SB.PCI0.PEG0) {
+	Name (_ADR, 0x00010000)
+
+	Device (PEGP) {
+		Name (_ADR, Zero)
+
+		// Convert a byte to a hex string, trimming extra parts
+		Method (BHEX, 1) {
+			Local0 = ToHexString(Arg0)
+			Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+		}
+
+		// UUID to string
+		Method (IDST, 1) {
+			Local0 = ""
+			Fprintf(
+				Local0,
+				"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+				BHEX(DerefOf(Arg0[3])),
+				BHEX(DerefOf(Arg0[2])),
+				BHEX(DerefOf(Arg0[1])),
+				BHEX(DerefOf(Arg0[0])),
+				BHEX(DerefOf(Arg0[5])),
+				BHEX(DerefOf(Arg0[4])),
+				BHEX(DerefOf(Arg0[7])),
+				BHEX(DerefOf(Arg0[6])),
+				BHEX(DerefOf(Arg0[8])),
+				BHEX(DerefOf(Arg0[9])),
+				BHEX(DerefOf(Arg0[10])),
+				BHEX(DerefOf(Arg0[11])),
+				BHEX(DerefOf(Arg0[12])),
+				BHEX(DerefOf(Arg0[13])),
+				BHEX(DerefOf(Arg0[14])),
+				BHEX(DerefOf(Arg0[15]))
+			)
+			Return (Local0)
+		}
+
+		// Safe hex conversion, checks type first
+		Method (SFST, 1) {
+			Local0 = ObjectType(Arg0)
+			If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+				Return (ToHexString(Arg0))
+			} Else {
+				Return (Concatenate("Type: ", Arg0))
+			}
+		}
+
+        Method (_DSM, 4, Serialized) {
+            Debug = "NVIDIA _DSM"
+            Printf("  Arg0: %o", IDST(Arg0))
+            Printf("  Arg1: %o", SFST(Arg1))
+            Printf("  Arg2: %o", SFST(Arg2))
+            Printf("  Arg3: %o", SFST(Arg3))
+
+            If (Arg0 == ToUUID ("d4a50b75-65c7-46f7-bfb7-41514cea0244")) {
+                If (Arg1 != 0x0102) {
+                    Printf("  Invalid Arg1, return 0x80000002")
+                    Return (0x80000002)
+                }
+
+                If (Arg2 == 0) {
+                    Printf("  Arg2 == 0x00, return supported functions")
+                    Return (Buffer (4) {
+                         0x01, 0x00, 0x10, 0x00
+                    })
+                }
+
+                If (Arg2 == 0x14) {
+                    Printf("  Arg2 == 0x14, return backlight package")
+					Return (Package (9) {
+						0x8000A450,
+						0x0200,
+						Zero,
+						Zero,
+						One,
+						One,
+						200,
+						32,
+						1000
+					})
+                }
+
+                Printf("  Unknown Arg2, return 0x80000002")
+                Return (0x80000002)
+            }
+
+            Printf("  Unknown Arg0, return 0x80000001")
+            Return (0x80000001)
+        }
+
+        Method (_DOD, 0, NotSerialized)  // _DOD: Display Output Devices
+        {
+            Return (Package (3) {
+                0x80008320,
+                0x80006330,
+                0x8000A450
+            })
+		}
+
+        Device (HDM0) {
+            Name (_ADR, 0x80008320)
+        }
+
+        Device (DSP0) {
+            Name (_ADR, 0x80006330)
+        }
+
+        Device (DSP1) {
+            Name (_ADR, 0x8000A450)
+        }
+	}
+}

src/mainboard/system76/bonw14/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/bonw14/acpi/mainboard.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}
+
+#include "dgpu.asl"

src/mainboard/system76/bonw14/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/bonw14/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: bonw14
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/bonw14/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/bonw14/cmos.default

@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+preserve_smmstore=0

src/mainboard/system76/bonw14/cmos.layout

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+408	1	h	1	preserve_smmstore
+#409	2	e	7	power_on_after_fail
+412	4	e	6	debug_level
+984	16	h	0	check_sum
+
+enumerations
+
+1	0	Disable
+1	1	Enable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+checksums
+
+checksum 408 983 984

src/mainboard/system76/bonw14/devicetree.cb

@@ -0,0 +1,232 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 125,
+		.tdp_pl2_override = 160,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	register "tcc_offset" = "13"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x7714 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on      # GPU Port
+			# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
+			register "PcieClkSrcUsage[7]" = "0x40"
+			register "PcieClkSrcClkReq[7]" = "7"
+		end
+		device pci 02.0 off end # Integrated Graphics Device # TODO: is this enough to disable iGPU?
+		device pci 04.0 on      # SA Thermal device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
+		end
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		device pci 14.3 on      # CNVi wifi
+			#chip drivers/intel/wifi
+			#	register "wake" = "PME_B0_EN_BIT"
+			#end
+		end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
+			register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
+			register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
+		end
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on      # PCI Express Port 17
+			# PCI Express root port #17 x4, Clock 14 (SSD2)
+			register "PcieRpEnable[16]" = "1"
+			register "PcieRpLtrEnable[16]" = "1"
+			register "PcieClkSrcUsage[14]" = "16"
+			register "PcieClkSrcClkReq[14]" = "14"
+		end
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on      # PCI Express Port 21
+			# PCI Express root port #21 x4, Clock 15 (SSD3)
+			register "PcieRpEnable[20]" = "1"
+			register "PcieRpLtrEnable[20]" = "1"
+			register "PcieClkSrcUsage[15]" = "20"
+			register "PcieClkSrcClkReq[15]" = "15"
+		end
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 on      # PCI Express Port 1
+			# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			register "PcieRpHotPlug[0]" = "1"
+			register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
+			register "PcieClkSrcClkReq[6]" = "6"
+		end
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on      # PCI Express Port 5
+			# PCI Express root port #5 x4, Clock 10 (USB 3.2)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieClkSrcUsage[10]" = "4"
+			register "PcieClkSrcClkReq[10]" = "10"
+		end
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express root port #9 x4, Clock 8 (SSD)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[8]" = "8"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on      # PCI Express Port 13
+			# PCI Express root port #13 x1, Clock 0 (WLAN)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[0]" = "12"
+		end
+		device pci 1d.5 on      # PCI Express Port 14
+			# PCI Express root port #14 x1, Clock 1 (GLAN)
+			register "PcieRpEnable[13]" = "1"
+			register "PcieRpLtrEnable[13]" = "1"
+			register "PcieClkSrcUsage[1]" = "13"
+			register "PcieClkSrcClkReq[1]" = "1"
+		end
+		device pci 1d.6 on      # PCI Express Port 15
+			# PCI Express root port #15 x1, Clock 4 (Card Reader)
+			register "PcieRpEnable[14]" = "1"
+			register "PcieRpLtrEnable[14]" = "1"
+			register "PcieClkSrcUsage[4]" = "14"
+			register "PcieClkSrcClkReq[4]" = "4"
+		end
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on      # LPC Interface
+			register "gen1_dec" = "0x000c0081"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x00fc0e01"
+			register "gen4_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on      # SMBus
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+			chip drivers/i2c/tas5825m
+				register "id" = "1"
+				device i2c 4f on end # (8bit address: 0x9e)
+			end
+		end
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/bonw14/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/bonw14/gpio.h

@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	//TODO: add early GPIO settings
+	PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // BATLOW_N
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // PCH_LAN_WAKE#
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, UP_20K),
+	PAD_CFG_GPI(GPD7, UP_20K, PWROK),
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE),
+	PAD_NC(GPD10, NONE),
+	PAD_CFG_GPI(GPD11, UP_20K, PWROK), // LANPHYPC
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // 10k pull up
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, UP_20K),
+	_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
+	PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // 10k pull up
+	PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUS_PWR_ACK
+	PAD_NC(GPP_A14, UP_20K),
+	PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUSACK#
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), // XFI_GAIN
+	PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // GPP_A20 (MB det)
+	PAD_NC(GPP_A21, UP_20K),
+	PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), // GPP_A22 (MB det)
+	PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPP_A23 (MB det)
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_B1, UP_20K),
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // BT_UART_WAKE_N
+	PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
+	PAD_NC(GPP_B4, UP_20K),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R
+	PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ#
+	PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT#
+	PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP), // PCIE_GLAN_RESET
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
+	PAD_NC(GPP_B15, UP_20K),
+	PAD_NC(GPP_B16, UP_20K),
+	PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // LPSS_GSPI0_MISO
+	PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI
+	PAD_NC(GPP_B19, UP_20K),
+	_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI#_3242
+	PAD_NC(GPP_B21, UP_20K),
+	PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // EXI BOOT STALL STRAP
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // TLS CONFIDENTIALITY STRAP
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SMLINK0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SMLINK0_DATA
+	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // ESPI/LPC SELECT STRAP
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SMC_CPU_THERM_R
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SMD_CPU_THERM
+	PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET#
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // GSYNC_ID
+	PAD_NC(GPP_C10, DN_20K),
+	PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP), // FW_RST#
+	PAD_NC(GPP_C12, UP_20K),
+	PAD_NC(GPP_C13, UP_20K),
+	PAD_NC(GPP_C14, UP_20K),
+	PAD_NC(GPP_C15, UP_20K),
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // T_SDA
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // T_SCL
+	PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411
+	PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411
+	PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, UP_20K),
+	PAD_NC(GPP_C23, UP_20K),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, UP_20K),
+	PAD_NC(GPP_D1, UP_20K),
+	PAD_NC(GPP_D2, UP_20K),
+	PAD_NC(GPP_D3, UP_20K),
+	PAD_NC(GPP_D4, UP_20K),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0
+	PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), // M.2_BT_PCMIN
+	PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), // M.2_BT_PCMCLK
+	PAD_NC(GPP_D9, UP_20K),
+	PAD_NC(GPP_D10, UP_20K),
+	PAD_NC(GPP_D11, UP_20K),
+	PAD_NC(GPP_D12, UP_20K),
+	PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 5825_I2C_DAT
+	PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 5825_I2C_CLK
+	PAD_NC(GPP_D15, UP_20K),
+	PAD_NC(GPP_D16, UP_20K),
+	PAD_NC(GPP_D17, UP_20K),
+	PAD_NC(GPP_D18, UP_20K),
+	PAD_NC(GPP_D19, UP_20K),
+	PAD_NC(GPP_D20, UP_20K),
+	PAD_NC(GPP_D21, UP_20K),
+	PAD_NC(GPP_D22, UP_20K),
+	PAD_NC(GPP_D23, UP_20K),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL
+	PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI#
+	PAD_NC(GPP_E4, UP_20K),
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SSD1_SATA_DEVSLP
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // SSD3_SATA_DEVSLP
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+	PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // RING OSCILLATOR BYPASS STRAP
+	PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP
+	PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP
+	PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // DFX TEST MODE
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST#
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD4_SATA_DEVSLP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // SSD2_SATA_DEVSLP
+	PAD_NC(GPP_F7, UP_20K),
+	PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // GPU_PWR_EN#
+	PAD_NC(GPP_F9, UP_20K),
+	PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER
+	PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP), // SSD1_PWR_DN#
+	PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, UP_20K),
+	PAD_NC(GPP_F16, UP_20K),
+	PAD_NC(GPP_F17, UP_20K),
+	PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // GPIO_PCIESLOT_RST_R
+	PAD_NC(GPP_F19, UP_20K),
+	PAD_NC(GPP_F20, UP_20K),
+	PAD_NC(GPP_F21, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // GC_OFF_EN
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, UP_20K),
+	PAD_NC(GPP_G1, UP_20K),
+	PAD_NC(GPP_G2, UP_20K),
+	PAD_NC(GPP_G3, UP_20K),
+	PAD_NC(GPP_G4, UP_20K),
+	PAD_NC(GPP_G5, UP_20K),
+	PAD_NC(GPP_G6, UP_20K),
+	PAD_NC(GPP_G7, UP_20K),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ#
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ#
+	PAD_NC(GPP_H5, NONE),
+	PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N
+	PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP), // PCIE_SSD2_RESET
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ#
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ#
+	PAD_NC(GPP_H10, NONE),
+	PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP), // SSD3_PWR_DN#
+	PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12
+	PAD_NC(GPP_H13, UP_20K),
+	PAD_NC(GPP_H14, UP_20K),
+	_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000), // GPP_H15_TBT_WAKE#
+	PAD_NC(GPP_H16, UP_20K),
+	PAD_NC(GPP_H17, UP_20K),
+	PAD_NC(GPP_H18, UP_20K),
+	PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD_AUX
+	PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD
+	PAD_NC(GPP_H21, UP_20K),
+	PAD_NC(GPP_H22, UP_20K),
+	PAD_NC(GPP_H23, UP_20K),
+
+	/* ------- GPIO Group GPP_I ------- */
+	_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // GPPDPA_I0
+	_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // GPPDPB_I1
+	_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // DP_F_HPD
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // 100k pull down
+	PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP), // GPIO_TBT_RESET
+	PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // MXM_GPIO0
+	PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // 10k pull up
+	PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // GPIO_WIFI_RESET_R
+	PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // WLAN_EN
+	PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP), // SSD2_PWR_DN#
+	PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N
+	PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP), // PCIE_SSD3_RESET
+	PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP), // PCIE_SSD1_RESET
+	PAD_NC(GPP_I14, UP_20K),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // CPI_C10_GATE_N (VCCIO_3P3_PWRGATE)
+	PAD_NC(GPP_J2, UP_20K),
+	PAD_NC(GPP_J3, UP_20K),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT_R
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT_R
+	PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // EDP_OD_EN
+	PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // GPP_J11
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE
+	PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE
+	PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD
+	_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
+	PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R
+	PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP), // DP_MUX_SW
+	_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
+	PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN
+	PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // SSD4_PWR_DN#
+	PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET
+	PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH
+	PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH
+	_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT#
+	PAD_NC(GPP_K13, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // 7411_TEST_R
+	PAD_NC(GPP_K15, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R
+	PAD_NC(GPP_K17, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // PCH_MUTE#
+	PAD_NC(GPP_K19, UP_20K),
+	PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // TEST_SETUP_MENU
+	PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN
+	PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
+	PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
+};
+
+#endif
+
+#endif

src/mainboard/system76/bonw14/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15587714, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4094022d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451120),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/bonw14/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/bonw14/romstage.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa2},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa6},
+	},
+	.rcomp_resistor = { 121, 75, 100 },
+	.rcomp_targets = { 50, 26, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to PCIe graphics
+	memupd->FspmConfig.PrimaryDisplay = 1;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/bonw14/tas5825m-normal.c

@@ -0,0 +1,971 @@
+static int tas5825m_setup_normal(struct device * dev) {
+	int res = 0;
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x02);
+		amp_write_at(0x01, 0x11);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x46, 0x11);
+	}
+
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x02, 0x00);
+		amp_write_at(0x53, 0x00);
+		amp_write_at(0x54, 0x00);
+		amp_write_at(0x29, 0x7C);
+		amp_write_at(0x03, 0x02);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x29, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x12);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x48, 0x0C);
+	}
+
+	amp_set_book(0x64);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
+			0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
+			0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
+			0x60, 0x00, 0x01
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
+		});
+		amp_write_block_at(0x27, {
+			0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
+			0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
+			0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
+			0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
+			0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
+			0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
+			0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
+			0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
+			0x1C, 0x11, 0xAB
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
+			0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
+			0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
+			0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
+		});
+		amp_write_block_at(0x46, {
+			0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
+			0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
+			0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
+			0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
+		});
+		amp_write_block_at(0x65, {
+			0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
+			0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
+			0x1C, 0x51, 0xBB
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
+			0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
+			0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
+			0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
+		});
+		amp_write_block_at(0x46, {
+			0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
+			0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
+			0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
+			0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
+			0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
+			0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
+			0x27, 0x80, 0xEA
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
+			0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
+			0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
+			0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
+			0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
+			0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
+			0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
+		});
+		amp_write_block_at(0x65, {
+			0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
+			0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
+			0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
+			0xC1, 0x01, 0x9D
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
+			0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
+			0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
+			0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
+			0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
+			0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
+			0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
+			0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
+			0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
+			0x82, 0x04, 0x07
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
+			0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
+			0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
+			0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
+		});
+		amp_write_block_at(0x46, {
+			0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
+			0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
+			0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
+			0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
+			0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
+			0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
+			0x1F, 0x31, 0xA8
+		});
+	}
+
+	amp_set_page(0x08);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
+			0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
+			0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
+			0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
+		});
+		amp_write_block_at(0x46, {
+			0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
+			0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
+			0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
+			0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
+			0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
+			0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
+			0xA1, 0x01, 0xC6
+		});
+	}
+
+	amp_set_page(0x09);
+	{
+		amp_write_block_at(0x08, {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
+			0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
+			0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
+			0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
+			0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
+			0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
+			0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
+		});
+		amp_write_block_at(0x65, {
+			0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
+			0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
+			0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
+			0xC3, 0x03, 0x5F
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
+			0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
+			0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
+			0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
+		});
+		amp_write_block_at(0x46, {
+			0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
+			0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
+			0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
+			0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
+		});
+		amp_write_block_at(0x65, {
+			0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
+			0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
+			0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
+			0xD0, 0x04, 0x09
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
+			0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
+			0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
+			0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
+		});
+		amp_write_block_at(0x46, {
+			0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
+			0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
+			0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
+			0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
+			0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
+			0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
+			0x60, 0x06, 0x12
+		});
+	}
+
+	amp_set_page(0x0C);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
+		});
+		amp_write_block_at(0x27, {
+			0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
+			0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
+			0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
+			0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
+			0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
+			0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
+			0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
+		});
+		amp_write_block_at(0x65, {
+			0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
+			0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
+			0xC2, 0x04, 0x00
+		});
+	}
+
+	amp_set_page(0x0D);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
+		});
+		amp_write_block_at(0x27, {
+			0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
+			0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
+			0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
+			0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
+		});
+		amp_write_block_at(0x46, {
+			0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
+			0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
+			0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
+			0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x18);
+	{
+		amp_write_block_at(0x30, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1B);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x54, {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x74, {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x5B, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x7A, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x0C, {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x24, {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x44, {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+
+		});
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
+		});
+		amp_write_block_at(0x7B, {
+			0xC1, 0xF8, 0x59, 0x7F, 0x63
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
+		});
+		amp_write_block_at(0x27, {
+			0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
+			0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
+			0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
+			0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
+		});
+		amp_write_block_at(0x46, {
+			0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
+			0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
+			0xBB, 0x98, 0xC8
+		});
+	}
+
+	amp_set_page(0x10);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x40, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_block_at(0x7D, {
+			0x11, 0xFF
+		});
+	}
+
+	amp_set_page(0x01);
+	{
+		amp_write_at(0x51, 0x05);
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_at(0x19, 0xDF);
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x2C, {
+			0x00, 0x71, 0x94, 0x9A
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x0C, 0xCC, 0xCD,
+			0x00, 0x0C, 0xCC, 0xCD, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00
+		});
+		amp_write_block_at(0x28, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xA9, 0x15, 0xB8,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x5C, {
+			0x7F, 0xF9, 0x2C, 0x60, 0x01, 0x33, 0x51, 0x50,
+
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00
+		});
+		amp_write_block_at(0x6C, {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0xAA);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x30, {
+			0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85,
+			0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E,
+			0xF8, 0x5C, 0x9F, 0x28, 0x07, 0xD1, 0x27, 0x3E,
+			0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27
+		});
+		amp_write_block_at(0x4F, {
+			0x3E, 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F,
+			0x28, 0x08, 0x00, 0x00, 0x00, 0xF0, 0x71, 0x4C,
+			0x87, 0x07, 0x91, 0xC6, 0x22, 0x0F, 0x8E, 0xB3,
+			0x79, 0xF8, 0x6E, 0x39, 0xDE, 0x08, 0x00
+		});
+		amp_write_block_at(0x6E, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B,
+			0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5,
+			0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57,
+			0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51
+		});
+		amp_write_block_at(0x27, {
+			0x2E, 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0,
+			0x7B, 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92,
+			0xE5, 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D,
+			0x1B, 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F
+		});
+		amp_write_block_at(0x46, {
+			0x71, 0xB3, 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0,
+			0x4E, 0xFB, 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0,
+			0x3F, 0x52, 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50,
+			0x29, 0xD7, 0x05, 0x3A, 0xF8, 0x0F, 0x0C
+		});
+		amp_write_block_at(0x65, {
+			0xAF, 0xD6, 0x29, 0xFB, 0x3E, 0x46, 0x00, 0x08,
+			0x17, 0x5D, 0x4C, 0xF0, 0xBC, 0xDB, 0x13, 0x07,
+			0x34, 0x29, 0xCB, 0x0F, 0x43, 0x24, 0xED, 0xF8,
+			0xB4, 0x78, 0xEA
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xFC, 0xDB, 0x0F, 0xF0, 0x3A, 0xC4, 0xBE,
+			0x07, 0xC9, 0x51, 0x50, 0x0F, 0xC5, 0x3B, 0x42,
+			0xF8, 0x39, 0xD3, 0xA1, 0x07, 0xFC, 0x38, 0xBF,
+			0xF0, 0x47, 0x14, 0xF2, 0x07, 0xBE, 0x4A
+		});
+		amp_write_block_at(0x27, {
+			0x80, 0x0F, 0xB8, 0xEB, 0x0E, 0xF8, 0x45, 0x7C,
+			0xC1, 0x07, 0xEB, 0xF6, 0xEF, 0xF1, 0x08, 0x7E,
+			0x56, 0x07, 0x17, 0x63, 0xC3, 0x0E, 0xF7, 0x81,
+			0xAA, 0xF8, 0xFC, 0xA5, 0x4E, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+			0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, 0x07,
+			0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, 0xF8,
+			0x5C, 0x9F, 0x28
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85,
+			0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E,
+			0xF8, 0x5C, 0x9F, 0x28, 0x08, 0x00, 0x00, 0x00,
+			0xF0, 0x71, 0x4C, 0x87, 0x07, 0x91, 0xC6
+		});
+		amp_write_block_at(0x27, {
+			0x22, 0x0F, 0x8E, 0xB3, 0x79, 0xF8, 0x6E, 0x39,
+			0xDE, 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7,
+			0x0B, 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08,
+			0xF5, 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58
+		});
+		amp_write_block_at(0x46, {
+			0xFE, 0x57, 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4,
+			0x51, 0x2E, 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2,
+			0xB0, 0x7B, 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE,
+			0x92, 0xE5, 0xFE, 0xEA, 0x2A, 0xF4, 0x05
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x6D, 0x1B, 0xFE, 0x8A, 0x4B, 0xFE, 0x09,
+			0x6F, 0x71, 0xB3, 0xF4, 0xC9, 0x2E, 0xBA, 0x02,
+			0xE0, 0x4E, 0xFB, 0x0B, 0x36, 0xD1, 0x46, 0xFB,
+			0xB0, 0x3F, 0x52
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7,
+			0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29,
+			0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C,
+			0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29
+		});
+		amp_write_block_at(0x27, {
+			0xCB, 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78,
+			0xEA, 0x07, 0xFB, 0x25, 0x84, 0xF0, 0x49, 0xA3,
+			0xCE, 0x07, 0xC7, 0xA6, 0xCB, 0x0F, 0xB6, 0x5C,
+			0x32, 0xF8, 0x3D, 0x33, 0xB1, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x86, 0x43, 0x99, 0xFF, 0x02, 0xE6, 0x50,
+			0x00, 0x77, 0xAC, 0xFD, 0x0F, 0xD7, 0xE6, 0xBF,
+			0xF8, 0x27, 0x42, 0x5B
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49
+		});
+		amp_write_block_at(0x27, {
+			0x81, 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB,
+			0xA1, 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18,
+			0x9F, 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A,
+			0x64, 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
+			0x71, 0xC7
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x30, 0x00);
+		amp_write_at(0x60, 0x02);
+		amp_write_at(0x62, 0x09);
+		amp_write_at(0x4C, 0x30);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x60, 0x00);
+		amp_write_at(0x64, 0x02);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x4E, 0xBB);
+		amp_write_at(0x4F, 0xB0);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	return 0;
+}

src/mainboard/system76/bonw14/tas5825m-sub.c

@@ -0,0 +1,971 @@
+static int tas5825m_setup_sub(struct device * dev) {
+	int res = 0;
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x02);
+		amp_write_at(0x01, 0x11);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x46, 0x11);
+	}
+
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x02, 0x04);
+		amp_write_at(0x53, 0x00);
+		amp_write_at(0x54, 0x00);
+		amp_write_at(0x29, 0x7C);
+		amp_write_at(0x03, 0x02);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x29, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x12);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x48, 0x0C);
+	}
+
+	amp_set_book(0x64);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
+			0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
+			0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
+			0x60, 0x00, 0x01
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
+		});
+		amp_write_block_at(0x27, {
+			0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
+			0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
+			0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
+			0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
+			0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
+			0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
+			0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
+			0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
+			0x1C, 0x11, 0xAB
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
+			0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
+			0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
+			0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
+		});
+		amp_write_block_at(0x46, {
+			0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
+			0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
+			0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
+			0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
+		});
+		amp_write_block_at(0x65, {
+			0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
+			0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
+			0x1C, 0x51, 0xBB
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
+			0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
+			0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
+			0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
+		});
+		amp_write_block_at(0x46, {
+			0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
+			0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
+			0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
+			0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
+			0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
+			0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
+			0x27, 0x80, 0xEA
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
+			0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
+			0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
+			0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
+			0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
+			0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
+			0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
+		});
+		amp_write_block_at(0x65, {
+			0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
+			0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
+			0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
+			0xC1, 0x01, 0x9D
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
+			0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
+			0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
+			0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
+			0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
+			0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
+			0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
+			0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
+			0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
+			0x82, 0x04, 0x07
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
+			0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
+			0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
+			0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
+		});
+		amp_write_block_at(0x46, {
+			0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
+			0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
+			0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
+			0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
+			0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
+			0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
+			0x1F, 0x31, 0xA8
+		});
+	}
+
+	amp_set_page(0x08);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
+			0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
+			0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
+			0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
+		});
+		amp_write_block_at(0x46, {
+			0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
+			0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
+			0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
+			0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
+			0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
+			0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
+			0xA1, 0x01, 0xC6
+		});
+	}
+
+	amp_set_page(0x09);
+	{
+		amp_write_block_at(0x08, {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
+			0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
+			0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
+			0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
+			0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
+			0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
+			0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
+		});
+		amp_write_block_at(0x65, {
+			0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
+			0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
+			0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
+			0xC3, 0x03, 0x5F
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
+			0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
+			0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
+			0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
+		});
+		amp_write_block_at(0x46, {
+			0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
+			0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
+			0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
+			0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
+		});
+		amp_write_block_at(0x65, {
+			0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
+			0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
+			0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
+			0xD0, 0x04, 0x09
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
+			0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
+			0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
+			0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
+		});
+		amp_write_block_at(0x46, {
+			0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
+			0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
+			0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
+			0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
+			0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
+			0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
+			0x60, 0x06, 0x12
+		});
+	}
+
+	amp_set_page(0x0C);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
+		});
+		amp_write_block_at(0x27, {
+			0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
+			0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
+			0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
+			0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
+			0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
+			0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
+			0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
+		});
+		amp_write_block_at(0x65, {
+			0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
+			0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
+			0xC2, 0x04, 0x00
+		});
+	}
+
+	amp_set_page(0x0D);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
+		});
+		amp_write_block_at(0x27, {
+			0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
+			0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
+			0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
+			0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
+		});
+		amp_write_block_at(0x46, {
+			0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
+			0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
+			0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
+			0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x18);
+	{
+		amp_write_block_at(0x30, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1B);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x54, {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x74, {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x5B, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x7A, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x0C, {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x24, {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x44, {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+
+		});
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
+		});
+		amp_write_block_at(0x7B, {
+			0xC1, 0xF8, 0x59, 0x7F, 0x63
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
+		});
+		amp_write_block_at(0x27, {
+			0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
+			0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
+			0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
+			0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
+		});
+		amp_write_block_at(0x46, {
+			0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
+			0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
+			0xBB, 0x98, 0xC8
+		});
+	}
+
+	amp_set_page(0x10);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x40, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_block_at(0x7D, {
+			0x11, 0xFF
+		});
+	}
+
+	amp_set_page(0x01);
+	{
+		amp_write_at(0x51, 0x05);
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_at(0x19, 0xDF);
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x2C, {
+			0x00, 0x71, 0x94, 0x9A
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x5A, 0x84,
+			0x00, 0x1E, 0x5A, 0x84, 0x00, 0x40, 0x26, 0xE7,
+			0x00, 0x40, 0x26, 0xE7, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x28, {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xEB, 0x8F, 0xA8,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x5C, {
+			0x7F, 0xF9, 0x2C, 0x60, 0x01, 0xEB, 0x55, 0xAC,
+
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00
+		});
+		amp_write_block_at(0x6C, {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0xAA);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x30, {
+			0x00, 0x01, 0x0A, 0x7A, 0x00, 0x02, 0x14, 0xF5,
+			0x00, 0x01, 0x0A, 0x7A, 0x0F, 0x7B, 0xDB, 0x58,
+			0xF8, 0x7F, 0xFA, 0xBE, 0x00, 0x01, 0x0A, 0x7A,
+			0x00, 0x02, 0x14, 0xF5, 0x00, 0x01, 0x0A
+		});
+		amp_write_block_at(0x4F, {
+			0x7A, 0x0F, 0x7B, 0xDB, 0x58, 0xF8, 0x7F, 0xFA,
+			0xBE, 0x07, 0xFD, 0xF9, 0x62, 0xF0, 0x25, 0x7A,
+			0x1B, 0x07, 0xDC, 0xC4, 0xC6, 0x0F, 0xDA, 0x85,
+			0xE5, 0xF8, 0x25, 0x41, 0xD8, 0x08, 0x00
+		});
+		amp_write_block_at(0x6E, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xF7, 0xFF, 0xB5, 0xF0, 0x4F, 0x8C, 0x33,
+			0x07, 0xBA, 0x32, 0x37, 0x0F, 0xB0, 0x73, 0xCD,
+			0xF8, 0x4D, 0xCE, 0x15, 0x07, 0xFA, 0x6B, 0x45,
+			0xF0, 0x68, 0xC7, 0x1B, 0x07, 0x9E, 0xF0
+		});
+		amp_write_block_at(0x27, {
+			0xFB, 0x0F, 0x97, 0x38, 0xE5, 0xF8, 0x66, 0xA3,
+			0xC0, 0x07, 0xFE, 0x8C, 0x9C, 0xF0, 0x34, 0xCF,
+			0xDE, 0x07, 0xCD, 0x94, 0xFF, 0x0F, 0xCB, 0x30,
+			0x22, 0xF8, 0x33, 0xDE, 0x65, 0x07, 0xFE
+		});
+		amp_write_block_at(0x46, {
+			0x73, 0xDB, 0xF0, 0x38, 0x93, 0x60, 0x07, 0xCA,
+			0x38, 0xAE, 0x0F, 0xC7, 0x6C, 0xA0, 0xF8, 0x37,
+			0x53, 0x77, 0x07, 0xF8, 0xC1, 0xBE, 0xF0, 0x88,
+			0xCB, 0x7D, 0x07, 0x82, 0x08, 0xA9, 0x0F
+		});
+		amp_write_block_at(0x65, {
+			0x77, 0x34, 0x83, 0xF8, 0x85, 0x35, 0x99, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4,
+			0xF0, 0x22, 0x72, 0x97, 0x07, 0xEE, 0xC6
+		});
+		amp_write_block_at(0x27, {
+			0xB4, 0x0F, 0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C,
+			0xCB, 0x07, 0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67,
+			0xAD, 0x07, 0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98,
+			0x53, 0xF8, 0x33, 0xBE, 0x30, 0x08, 0x13
+		});
+		amp_write_block_at(0x46, {
+			0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C, 0x07, 0xDE,
+			0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85, 0xF8, 0x0E,
+			0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4, 0xF0, 0x22,
+			0x72, 0x97, 0x07, 0xEE, 0xC6, 0xB4, 0x0F
+		});
+		amp_write_block_at(0x65, {
+			0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C, 0xCB, 0x07,
+			0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67, 0xAD, 0x07,
+			0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98, 0x53, 0xF8,
+			0x33, 0xBE, 0x30
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x13, 0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C,
+			0x07, 0xDE, 0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85,
+			0xF8, 0x0E, 0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x85, 0xC0, 0x8D, 0xFF, 0x02, 0x2B, 0x75,
+			0x00, 0x78, 0xBE, 0x6E, 0x0F, 0xE2, 0x46, 0xF6,
+			0xF8, 0x1D, 0x0E, 0x9A
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xAA, 0xC3,
+			0xFF, 0xFD, 0x55, 0x85, 0xFF, 0xFE, 0xAA
+		});
+		amp_write_block_at(0x27, {
+			0xC3, 0x0F, 0x2F, 0x01, 0x62, 0xF8, 0xCB, 0xA9,
+			0xA8, 0x07, 0x98, 0xD5, 0xEF, 0xF0, 0xCE, 0x54,
+			0x23, 0x07, 0x98, 0xD5, 0xEF, 0x0F, 0x2F, 0x01,
+			0x62, 0xF8, 0xCB, 0xA9, 0xA8, 0x00, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
+			0x71, 0xC7
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x30, 0x00);
+		amp_write_at(0x60, 0x02);
+		amp_write_at(0x62, 0x09);
+		amp_write_at(0x4C, 0x30);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x60, 0x00);
+		amp_write_at(0x64, 0x02);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x4E, 0xBB);
+		amp_write_at(0x4F, 0xB0);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	return 0;
+}

src/mainboard/system76/bonw14/tas5825m.c

@@ -0,0 +1,31 @@
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+#define R(F) { \
+	res = F; \
+	if (res < 0) return res; \
+}
+
+#define amp_write_at(A, V) R(tas5825m_write_at(dev, A, V))
+
+#define amp_write_block_at(A, ...) { \
+	const uint8_t _values[] = __VA_ARGS__; \
+	R(tas5825m_write_block_at(dev, A, _values, ARRAY_SIZE(_values))); \
+}
+
+#define amp_set_page(P) R(tas5825m_set_page(dev, P))
+
+#define amp_set_book(B) R(tas5825m_set_book(dev, B))
+
+#include "tas5825m-normal.c"
+#include "tas5825m-sub.c"
+
+int tas5825m_setup(struct device * dev, int id) {
+	if (id == 0) {
+		return tas5825m_setup_normal(dev);
+	} else if (id == 1) {
+		return tas5825m_setup_sub(dev);
+	} else {
+		return -1;
+	}
+}

src/mainboard/system76/cml-u/Kconfig

@@ -0,0 +1,101 @@
+if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP6
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs
+	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_OPTION_TABLE
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/cml-u"
+
+config VARIANT_DIR
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Galago Pro" if BOARD_SYSTEM76_GALP4
+	default "Darter Pro" if BOARD_SYSTEM76_DARP6
+
+config MAINBOARD_VERSION
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 8
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9b41.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9b41"
+
+config PXE_ROM_ID
+	string
+	default "10ec,8168"
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/cml-u/Kconfig.name

@@ -0,0 +1,5 @@
+config BOARD_SYSTEM76_GALP4
+	bool "galp4"
+
+config BOARD_SYSTEM76_DARP6
+	bool "darp6"

src/mainboard/system76/cml-u/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/cml-u/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_D9 SCI
+Method (_L29, 0, Serialized) {
+	Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x50 /* GPP_E16 */
+#define EC_GPE_SWI 0x29 /* GPP_D9 */
+
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/cml-u/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/cml-u/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: cml-u
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/cml-u/bootblock.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/cml-u/cmos.default

@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Debug
+DisplayPort_Output=Mini_DisplayPort
+preserve_smmstore=0

src/mainboard/system76/cml-u/cmos.layout

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+408	1	h	1	preserve_smmstore
+#409	2	e	7	power_on_after_fail
+411	1	e	8	DisplayPort_Output
+412	4	e	6	debug_level
+984	16	h	0	check_sum
+
+enumerations
+
+1	0	Disable
+1	1	Enable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+8	0	Mini_DisplayPort
+8	1	USB-C
+
+checksums
+
+checksum 408 983 984

src/mainboard/system76/cml-u/devicetree.cb

@@ -0,0 +1,180 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		/* Touchpad */
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 30,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3"	# 50ms
+	register "PchPmSlpS4MinAssert" = "1"	# 1s
+	register "PchPmSlpSusMinAssert" = "2"	# 500ms
+	register "PchPmSlpAMinAssert" = "4"	# 2s
+
+	# Thermal
+	register "tcc_offset" = "12"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_C"
+	register "gpe0_dw1" = "PMC_GPP_D"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on      # Integrated Graphics Device
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device pci 04.0 on      # SA Thermal device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"		# 3G / LTE
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"		# Type-C port 3
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# USB Board port 4
+			register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"		# Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# 4G
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type C port 3
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# USB Board port 4
+			register "usb3_ports[4]" = "USB3_PORT_EMPTY"			# Used by TBT
+			register "usb3_ports[5]" = "USB3_PORT_EMPTY"			# Used by TBT
+		end
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.3 on      # CNVi wifi
+			#chip drivers/intel/wifi
+			#	register "wake" = "PME_B0_EN_BIT"
+			#end
+		end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[2]" = "1"
+		end
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on      # PCI Express Port 5
+			# PCI Express Root port #5 x4, Clock 4 (TBT)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieRpHotPlug[4]" = "1"
+			register "PcieClkSrcUsage[4]" = "4"
+			register "PcieClkSrcClkReq[4]" = "4"
+		end
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express Root port #9 x1, Clock 3 (LAN)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[3]" = "8"
+			register "PcieClkSrcClkReq[3]" = "3"
+		end
+		device pci 1d.1 on      # PCI Express Port 10
+			# PCI Express Root port #10 x1, Clock 2 (WLAN)
+			register "PcieRpEnable[9]" = "1"
+			register "PcieRpLtrEnable[9]" = "0"
+			register "PcieClkSrcUsage[2]" = "9"
+			register "PcieClkSrcClkReq[2]" = "2"
+		end
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on      # PCI Express Port 13
+			# PCI Express Root port #13 x4, Clock 5 (NVMe)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[5]" = "12"
+			register "PcieClkSrcClkReq[5]" = "5"
+		end
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on      # LPC Interface
+			register "gen1_dec" = "0x000c0081"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x00fc0e01"
+			register "gen4_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkHda" = "1"
+			register "PchHdaAudioLinkDmic0" = "1"
+			register "PchHdaAudioLinkDmic1" = "1"
+		end
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/cml-u/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/cml-u/gpio.h

@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE), // NC
+	PAD_NC(GPP_C23, NONE), // NC
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_NC(GPD0, NONE), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE), // NC
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE), // NC
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE), // GPD9_RTD3
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
+	PAD_NC(GPD11, NONE), // NC
+
+	/* ------- GPIO Group A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with pull up
+	PAD_NC(GPP_A7, NONE), // TPM_PIRQ#
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with pull-up
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
+	PAD_NC(GPP_A11, NONE), // NC
+	PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
+	PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
+	PAD_NC(GPP_A16, NONE), // NC
+	PAD_NC(GPP_A17, NONE), // LIGHT_KB_DET#
+	PAD_NC(GPP_A18, NONE), // NC
+	PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_A20, NONE), // NC
+	PAD_NC(GPP_A21, NONE), // NC
+	PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // PS8338B_SW
+	PAD_NC(GPP_A23, NONE), // PS8338B_PCH
+
+	/* ------- GPIO Group B ------- */
+	PAD_NC(GPP_B0, NONE), // CORE_VID0
+	PAD_NC(GPP_B1, NONE), // CORE_VID1
+	PAD_NC(GPP_B2, NONE), // CNVI_WAKE#
+	PAD_NC(GPP_B3, NONE), // NC
+	PAD_NC(GPP_B4, NONE), // NC
+	PAD_NC(GPP_B5, NONE), // NC
+	PAD_NC(GPP_B6, NONE), // NC
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
+	PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE), // NC
+	PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
+	PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
+	PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
+	PAD_NC(GPP_B19, NONE), // NC
+	PAD_NC(GPP_B20, NONE), // NC
+	PAD_NC(GPP_B21, NONE), // NC
+	PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
+	PAD_NC(GPP_B23, NONE), // NC
+
+	/* ------- GPIO Group C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
+	PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with pull-up
+	PAD_NC(GPP_C3, NONE), // NC
+	PAD_NC(GPP_C4, NONE), // NC
+	PAD_NC(GPP_C5, NONE), // NC
+	PAD_NC(GPP_C6, NONE), // LAN_WAKEUP#
+	PAD_NC(GPP_C7, NONE), // NC
+	PAD_NC(GPP_C8, NONE), // NC
+	_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
+	PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
+	PAD_NC(GPP_C11, NONE), // NC
+	PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), // GPP_C12_RTD3
+	PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), // SSD_PWR_DN#
+	PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), // TBTA_HRESET
+	PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // TBT_PERST_N
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
+	PAD_NC(GPP_C18, NONE), // NC
+	PAD_NC(GPP_C19, NONE), // SWI
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE), // NC
+	PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
+
+	/* ------- GPIO Group D ------- */
+	PAD_NC(GPP_D0, NONE), // NC
+	PAD_NC(GPP_D1, NONE), // NC
+	PAD_NC(GPP_D2, NONE), // NC
+	PAD_NC(GPP_D3, NONE), // NC
+	PAD_NC(GPP_D4, NONE), // NC
+	PAD_NC(GPP_D5, NONE), // NC
+	PAD_NC(GPP_D6, NONE), // NC
+	PAD_NC(GPP_D7, NONE), // NC
+	PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), // SB_BLON
+	_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
+	PAD_NC(GPP_D10, NONE), // NC
+	_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
+	PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
+	PAD_NC(GPP_D13, NONE), // NC
+	PAD_NC(GPP_D14, NONE), // NC
+	PAD_NC(GPP_D15, NONE), // NC
+	PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), // RTD3_3G_PW R_EN
+	PAD_NC(GPP_D17, NONE), // NC
+	PAD_NC(GPP_D18, NONE), // NC
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
+	PAD_NC(GPP_D21, NONE), // TPM_DET#
+	PAD_NC(GPP_D22, NONE), // TPM_TCM_Detect
+	PAD_NC(GPP_D23, NONE), // NC
+
+	/* ------- GPIO Group E ------- */
+	PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with pull-up
+	PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
+	PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
+	PAD_NC(GPP_E3, NONE), // NC
+	PAD_NC(GPP_E4, NONE), // NC
+	PAD_NC(GPP_E5, NONE), // NC
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
+	PAD_NC(GPP_E7, NONE), // NC
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+	PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
+	PAD_NC(GPP_E10, NONE), // GPP_E10
+	PAD_NC(GPP_E11, NONE), // GPP_E11
+	PAD_NC(GPP_E12, NONE), // USB_OC#78
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
+	_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_NC(GPP_E22, NONE), // NC
+	PAD_NC(GPP_E23, NONE), // NC
+
+	/* ------- GPIO Group F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F1, NONE), // NC
+	PAD_NC(GPP_F2, NONE), // NC
+	PAD_NC(GPP_F3, NONE), // NC
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_F10, NONE), // NC
+	PAD_NC(GPP_F11, NONE), // NC
+	PAD_NC(GPP_F12, NONE), // NC
+	PAD_NC(GPP_F13, NONE), // NC
+	PAD_NC(GPP_F14, NONE), // NC
+	PAD_NC(GPP_F15, NONE), // NC
+	PAD_NC(GPP_F16, NONE), // NC
+	PAD_NC(GPP_F17, NONE), // NC
+	PAD_NC(GPP_F18, NONE), // NC
+	PAD_NC(GPP_F19, NONE), // NC
+	PAD_NC(GPP_F20, NONE), // NC
+	PAD_NC(GPP_F21, NONE), // NC
+	PAD_NC(GPP_F22, NONE), // NC
+	PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), // A4WP_PRESENT
+
+	/* ------- GPIO Group G ------- */
+	PAD_NC(GPP_G0, NONE), // EDP_DET
+	PAD_NC(GPP_G1, NONE), // NC
+	PAD_NC(GPP_G2, NONE), // NC
+	PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
+	PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
+	PAD_NC(GPP_G5, NONE), // BOARD_ID
+	PAD_NC(GPP_G6, NONE), // NC
+	PAD_NC(GPP_G7, NONE), // TBT_Detect
+
+	/* ------- GPIO Group H ------- */
+	PAD_NC(GPP_H0, NONE), // NC
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_H3, NONE), // NC
+	PAD_NC(GPP_H4, NONE), // T23
+	PAD_NC(GPP_H5, NONE), // T22
+	PAD_NC(GPP_H6, NONE), // NC
+	PAD_NC(GPP_H7, NONE), // NC
+	PAD_NC(GPP_H8, NONE), // NC
+	PAD_NC(GPP_H9, NONE), // NC
+	PAD_NC(GPP_H10, NONE), // NC
+	PAD_NC(GPP_H11, NONE), // NC
+	PAD_NC(GPP_H12, NONE), // NC
+	PAD_NC(GPP_H13, NONE), // NC
+	PAD_NC(GPP_H14, NONE), // G_INT1
+	PAD_NC(GPP_H15, NONE), // NC
+	PAD_NC(GPP_H16, NONE), // NC
+	PAD_NC(GPP_H17, NONE), // NC
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE), // NC
+	PAD_NC(GPP_H20, NONE), // NC
+	PAD_NC(GPP_H21, NONE), // GPPC_H21
+	PAD_NC(GPP_H22, NONE), // TBT_RTD3_PWR_EN_R
+	PAD_NC(GPP_H23, NONE), // NC, WIGIG_PEWAKE
+};
+
+#endif
+
+#endif

src/mainboard/system76/cml-u/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/cml-u/romstage.c

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.rcomp_resistor = { 121, 81, 100 },
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/cml-u/variants/darp6/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581404, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581404),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11050),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x02451130),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/cml-u/variants/darp6/overridetree.cb

@@ -0,0 +1,15 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		subsystemid 0x1558 0x1404 inherit
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+	end
+end

src/mainboard/system76/cml-u/variants/galp4/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581403, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581403),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

@@ -0,0 +1,8 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		subsystemid 0x1558 0x1403 inherit
+		device pci 15.0 on
+			# I2C HID not supported on galp4
+		end # I2C #0
+	end
+end

src/mainboard/system76/darp7/Kconfig

@@ -0,0 +1,74 @@
+if BOARD_SYSTEM76_DARP7
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_OPTION_TABLE
+
+config MAINBOARD_DIR
+	string
+	default "system76/darp7"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "darp7"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Darter Pro"
+
+config MAINBOARD_VERSION
+	string
+	default "darp7"
+
+#TODO: subsystem IDs
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config DIMM_MAX
+	int
+	default 4 # Hack to make soc code work
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config MAX_CPUS
+	int
+	default 8
+
+config POST_DEVICE
+	bool
+	default n
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+endif