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UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/

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The patch moves all files under UefiCpuPkg/Include/Register/ to
MdePkg/Include/Register using following detailed approaches:
1. Move UefiCpuPkg/Include/Register/Amd/ to
   MdePkg/Include/Register/Amd folder.
2. Move remaining in UefiCpuPkg/Include/Register/ to
   MdePkg/Include/Register/Intel folder.
3. Create wrapper header files under UefiCpuPkg/Include/Register/
   to include the accordingly files in MdePkg/Include/Register/Intel.
   This is to avoid build break because code in other repos like
   edk2-platform includes the file from UefiCpuPkg.

The wrapper header files will be removed after all consumers code
is updated.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ni, Ray
2019-08-01 17:58:30 +08:00
committed by Eric Dong
parent b3527dedc3
commit e057908f8d
39 changed files with 8194 additions and 8119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

737
UefiCpuPkg/Include/Register/Amd/Cpuid.h
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@@ -1,737 +0,0 @@
/** @file
CPUID leaf definitions.
Provides defines for CPUID leaf indexes. Data structures are provided for
registers returned by a CPUID leaf that contain one or more bit fields.
If a register returned is a single 32-bit value, then a data structure is
not provided for that register.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
**/
#ifndef __AMD_CPUID_H__
#define __AMD_CPUID_H__
/**
CPUID Signature Information
@param EAX CPUID_SIGNATURE (0x00)
@retval EAX Returns the highest value the CPUID instruction recognizes for
returning basic processor information. The value is returned is
processor specific.
@retval EBX First 4 characters of a vendor identification string.
@retval ECX Last 4 characters of a vendor identification string.
@retval EDX Middle 4 characters of a vendor identification string.
**/
///
/// @{ CPUID signature values returned by AMD processors
///
#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')
#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')
#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')
///
/// @}
///
/**
CPUID Extended Processor Signature and Features
@param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
@retval EAX Extended Family, Model, Stepping Identifiers
described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
@retval EBX Brand Identifier
described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
@retval ECX Extended Feature Identifiers
described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
@retval EDX Extended Feature Identifiers
described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
**/
/**
CPUID Extended Processor Signature and Features EAX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 3:0] Stepping.
///
UINT32 Stepping:4;
///
/// [Bits 7:4] Base Model.
///
UINT32 BaseModel:4;
///
/// [Bits 11:8] Base Family.
///
UINT32 BaseFamily:4;
///
/// [Bit 15:12] Reserved.
///
UINT32 Reserved1:4;
///
/// [Bits 19:16] Extended Model.
///
UINT32 ExtModel:4;
///
/// [Bits 27:20] Extended Family.
///
UINT32 ExtFamily:8;
///
/// [Bit 31:28] Reserved.
///
UINT32 Reserved2:4;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
/**
CPUID Extended Processor Signature and Features EBX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 27:0] Reserved.
///
UINT32 Reserved:28;
///
/// [Bit 31:28] Package Type.
///
UINT32 PkgType:4;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
/**
CPUID Extended Processor Signature and Features ECX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] LAHF/SAHF available in 64-bit mode.
///
UINT32 LAHF_SAHF:1;
///
/// [Bit 1] Core multi-processing legacy mode.
///
UINT32 CmpLegacy:1;
///
/// [Bit 2] Secure Virtual Mode feature.
///
UINT32 SVM:1;
///
/// [Bit 3] Extended APIC register space.
///
UINT32 ExtApicSpace:1;
///
/// [Bit 4] LOCK MOV CR0 means MOV CR8.
///
UINT32 AltMovCr8:1;
///
/// [Bit 5] LZCNT instruction support.
///
UINT32 LZCNT:1;
///
/// [Bit 6] SSE4A instruction support.
///
UINT32 SSE4A:1;
///
/// [Bit 7] Misaligned SSE Mode.
///
UINT32 MisAlignSse:1;
///
/// [Bit 8] ThreeDNow Prefetch instructions.
///
UINT32 PREFETCHW:1;
///
/// [Bit 9] OS Visible Work-around support.
///
UINT32 OSVW:1;
///
/// [Bit 10] Instruction Based Sampling.
///
UINT32 IBS:1;
///
/// [Bit 11] Extended Operation Support.
///
UINT32 XOP:1;
///
/// [Bit 12] SKINIT and STGI support.
///
UINT32 SKINIT:1;
///
/// [Bit 13] Watchdog Timer support.
///
UINT32 WDT:1;
///
/// [Bit 14] Reserved.
///
UINT32 Reserved1:1;
///
/// [Bit 15] Lightweight Profiling support.
///
UINT32 LWP:1;
///
/// [Bit 16] 4-Operand FMA instruction support.
///
UINT32 FMA4:1;
///
/// [Bit 17] Translation Cache Extension.
///
UINT32 TCE:1;
///
/// [Bit 21:18] Reserved.
///
UINT32 Reserved2:4;
///
/// [Bit 22] Topology Extensions support.
///
UINT32 TopologyExtensions:1;
///
/// [Bit 23] Core Performance Counter Extensions.
///
UINT32 PerfCtrExtCore:1;
///
/// [Bit 25:24] Reserved.
///
UINT32 Reserved3:2;
///
/// [Bit 26] Data Breakpoint Extension.
///
UINT32 DataBreakpointExtension:1;
///
/// [Bit 27] Performance Time-Stamp Counter.
///
UINT32 PerfTsc:1;
///
/// [Bit 28] L3 Performance Counter Extensions.
///
UINT32 PerfCtrExtL3:1;
///
/// [Bit 29] MWAITX and MONITORX capability.
///
UINT32 MwaitExtended:1;
///
/// [Bit 31:30] Reserved.
///
UINT32 Reserved4:2;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
/**
CPUID Extended Processor Signature and Features EDX for CPUID leaf
#CPUID_EXTENDED_CPU_SIG.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] x87 floating point unit on-chip.
///
UINT32 FPU:1;
///
/// [Bit 1] Virtual-mode enhancements.
///
UINT32 VME:1;
///
/// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
///
UINT32 DE:1;
///
/// [Bit 3] Page-size extensions (4 MB pages).
///
UINT32 PSE:1;
///
/// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
///
UINT32 TSC:1;
///
/// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
///
UINT32 MSR:1;
///
/// [Bit 6] Physical-address extensions (PAE).
///
UINT32 PAE:1;
///
/// [Bit 7] Machine check exception, CR4.MCE.
///
UINT32 MCE:1;
///
/// [Bit 8] CMPXCHG8B instruction.
///
UINT32 CMPXCHG8B:1;
///
/// [Bit 9] APIC exists and is enabled.
///
UINT32 APIC:1;
///
/// [Bit 10] Reserved.
///
UINT32 Reserved1:1;
///
/// [Bit 11] SYSCALL and SYSRET instructions.
///
UINT32 SYSCALL_SYSRET:1;
///
/// [Bit 12] Memory-type range registers.
///
UINT32 MTRR:1;
///
/// [Bit 13] Page global extension, CR4.PGE.
///
UINT32 PGE:1;
///
/// [Bit 14] Machine check architecture, MCG_CAP.
///
UINT32 MCA:1;
///
/// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
///
UINT32 CMOV:1;
///
/// [Bit 16] Page attribute table.
///
UINT32 PAT:1;
///
/// [Bit 17] Page-size extensions.
///
UINT32 PSE36 : 1;
///
/// [Bit 19:18] Reserved.
///
UINT32 Reserved2:2;
///
/// [Bit 20] No-execute page protection.
///
UINT32 NX:1;
///
/// [Bit 21] Reserved.
///
UINT32 Reserved3:1;
///
/// [Bit 22] AMD Extensions to MMX instructions.
///
UINT32 MmxExt:1;
///
/// [Bit 23] MMX instructions.
///
UINT32 MMX:1;
///
/// [Bit 24] FXSAVE and FXRSTOR instructions.
///
UINT32 FFSR:1;
///
/// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
///
UINT32 FFXSR:1;
///
/// [Bit 26] 1-GByte large page support.
///
UINT32 Page1GB:1;
///
/// [Bit 27] RDTSCP intructions.
///
UINT32 RDTSCP:1;
///
/// [Bit 28] Reserved.
///
UINT32 Reserved4:1;
///
/// [Bit 29] Long Mode.
///
UINT32 LM:1;
///
/// [Bit 30] 3DNow! instructions.
///
UINT32 ThreeDNow:1;
///
/// [Bit 31] AMD Extensions to 3DNow! instructions.
///
UINT32 ThreeDNowExt:1;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
/**
CPUID Linear Physical Address Size
@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
@retval EAX Linear/Physical Address Size described by the type
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
@retval EBX Linear/Physical Address Size described by the type
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
@retval ECX Linear/Physical Address Size described by the type
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
@retval EDX Reserved.
**/
/**
CPUID Linear Physical Address Size EAX for CPUID leaf
#CPUID_VIR_PHY_ADDRESS_SIZE.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Maximum physical byte address size in bits.
///
UINT32 PhysicalAddressBits:8;
///
/// [Bits 15:8] Maximum linear byte address size in bits.
///
UINT32 LinearAddressBits:8;
///
/// [Bits 23:16] Maximum guest physical byte address size in bits.
///
UINT32 GuestPhysAddrSize:8;
///
/// [Bit 31:24] Reserved.
///
UINT32 Reserved:8;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
/**
CPUID Linear Physical Address Size EBX for CPUID leaf
#CPUID_VIR_PHY_ADDRESS_SIZE.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 0] Clear Zero Instruction.
///
UINT32 CLZERO:1;
///
/// [Bits 1] Instructions retired count support.
///
UINT32 IRPerf:1;
///
/// [Bits 2] Restore error pointers for XSave instructions.
///
UINT32 XSaveErPtr:1;
///
/// [Bit 31:3] Reserved.
///
UINT32 Reserved:29;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
/**
CPUID Linear Physical Address Size ECX for CPUID leaf
#CPUID_VIR_PHY_ADDRESS_SIZE.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Number of threads - 1.
///
UINT32 NC:8;
///
/// [Bit 11:8] Reserved.
///
UINT32 Reserved1:4;
///
/// [Bits 15:12] APIC ID size.
///
UINT32 ApicIdCoreIdSize:4;
///
/// [Bits 17:16] Performance time-stamp counter size.
///
UINT32 PerfTscSize:2;
///
/// [Bit 31:18] Reserved.
///
UINT32 Reserved2:14;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
/**
CPUID AMD Processor Topology
@param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
@retval EAX Extended APIC ID described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
@retval EBX Core Indentifiers described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
@retval ECX Node Indentifiers described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
@retval EDX Reserved.
**/
#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
/**
CPUID AMD Processor Topology EAX for CPUID leaf
#CPUID_AMD_PROCESSOR_TOPOLOGY.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 31:0] Extended APIC Id.
///
UINT32 ExtendedApicId;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
/**
CPUID AMD Processor Topology EBX for CPUID leaf
#CPUID_AMD_PROCESSOR_TOPOLOGY.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Core Id.
///
UINT32 CoreId:8;
///
/// [Bits 15:8] Threads per core.
///
UINT32 ThreadsPerCore:8;
///
/// [Bit 31:16] Reserved.
///
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
/**
CPUID AMD Processor Topology ECX for CPUID leaf
#CPUID_AMD_PROCESSOR_TOPOLOGY.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Node Id.
///
UINT32 NodeId:8;
///
/// [Bits 10:8] Nodes per processor.
///
UINT32 NodesPerProcessor:3;
///
/// [Bit 31:11] Reserved.
///
UINT32 Reserved:21;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
/**
CPUID Memory Encryption Information
@param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
@retval EAX Returns the memory encryption feature support status.
@retval EBX If memory encryption feature is present then return
the page table bit number used to enable memory encryption support
and reducing of physical address space in bits.
@retval ECX Returns number of encrypted guest supported simultaneously.
@retval EDX Returns minimum SEV enabled and SEV disabled ASID.
<b>Example usage</b>
@code
UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
@endcode
**/
#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F
/**
CPUID Memory Encryption support information EAX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Secure Memory Encryption (Sme) Support
///
UINT32 SmeBit:1;
///
/// [Bit 1] Secure Encrypted Virtualization (Sev) Support
///
UINT32 SevBit:1;
///
/// [Bit 2] Page flush MSR support
///
UINT32 PageFlushMsrBit:1;
///
/// [Bit 3] Encrypted state support
///
UINT32 SevEsBit:1;
///
/// [Bit 31:4] Reserved
///
UINT32 ReservedBits:28;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_EAX;
/**
CPUID Memory Encryption support information EBX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 5:0] Page table bit number used to enable memory encryption
///
UINT32 PtePosBits:6;
///
/// [Bit 11:6] Reduction of system physical address space bits when
/// memory encryption is enabled
///
UINT32 ReducedPhysBits:5;
///
/// [Bit 31:12] Reserved
///
UINT32 ReservedBits:21;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_EBX;
/**
CPUID Memory Encryption support information ECX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 31:0] Number of encrypted guest supported simultaneously
///
UINT32 NumGuests;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_ECX;
/**
CPUID Memory Encryption support information EDX for CPUID leaf
#CPUID_MEMORY_ENCRYPTION_INFO.
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
///
UINT32 MinAsid;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
} CPUID_MEMORY_ENCRYPTION_INFO_EDX;
#endif

56
UefiCpuPkg/Include/Register/Amd/Fam17Msr.h
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@@ -1,56 +0,0 @@
/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
**/
#ifndef __FAM17_MSR_H__
#define __FAM17_MSR_H__
/**
Secure Encrypted Virtualization (SEV) status register
**/
#define MSR_SEV_STATUS 0xc0010131
/**
MSR information returned for #MSR_SEV_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
///
UINT32 SevBit:1;
///
/// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
///
UINT32 SevEsBit:1;
UINT32 Reserved:30;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_SEV_STATUS_REGISTER;
#endif

23
UefiCpuPkg/Include/Register/Amd/Msr.h
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@@ -1,23 +0,0 @@
/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
**/
#ifndef __AMD_MSR_H__
#define __AMD_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Amd/Fam17Msr.h>
#endif

6565
UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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File diff suppressed because it is too large Load Diff

5
UefiCpuPkg/Include/Register/Cpuid.h
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@@ -3,11 +3,6 @@
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
November 2018, CPUID instruction.
**/
#ifndef __CPUID_H__

175
UefiCpuPkg/Include/Register/LocalApic.h
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@@ -1,183 +1,14 @@
/** @file
IA32 Local APIC Definitions.
Wrapper header file to include <Register/Intel/LocalApic.h> in MdePkg.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __LOCAL_APIC_H__
#define __LOCAL_APIC_H__
//
// Definition for Local APIC registers and related values
//
#define XAPIC_ID_OFFSET 0x20
#define XAPIC_VERSION_OFFSET 0x30
#define XAPIC_EOI_OFFSET 0x0b0
#define XAPIC_ICR_DFR_OFFSET 0x0e0
#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
#define XAPIC_ICR_LOW_OFFSET 0x300
#define XAPIC_ICR_HIGH_OFFSET 0x310
#define XAPIC_LVT_TIMER_OFFSET 0x320
#define XAPIC_LVT_LINT0_OFFSET 0x350
#define XAPIC_LVT_LINT1_OFFSET 0x360
#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
#define X2APIC_MSR_BASE_ADDRESS 0x800
#define X2APIC_MSR_ICR_ADDRESS 0x830
#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
#define LOCAL_APIC_DELIVERY_MODE_SMI 2
#define LOCAL_APIC_DELIVERY_MODE_NMI 4
#define LOCAL_APIC_DELIVERY_MODE_INIT 5
#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
//
// Local APIC Version Register.
//
typedef union {
struct {
UINT32 Version:8; ///< The version numbers of the local APIC.
UINT32 Reserved0:8; ///< Reserved.
UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.
UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.
UINT32 Reserved1:7; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_VERSION;
//
// Low half of Interrupt Command Register (ICR).
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
UINT32 Reserved0:1; ///< Reserved.
UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
UINT32 Reserved1:2; ///< Reserved.
UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
UINT32 Reserved2:12; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_ICR_LOW;
//
// High half of Interrupt Command Register (ICR)
//
typedef union {
struct {
UINT32 Reserved0:24; ///< Reserved.
UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
} Bits;
UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
} LOCAL_APIC_ICR_HIGH;
//
// Spurious-Interrupt Vector Register (SVR)
//
typedef union {
struct {
UINT32 SpuriousVector:8; ///< Spurious Vector.
UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
UINT32 Reserved0:2; ///< Reserved.
UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
UINT32 Reserved1:19; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_SVR;
//
// Divide Configuration Register (DCR)
//
typedef union {
struct {
UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
UINT32 Reserved0:1; ///< Always 0.
UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
UINT32 Reserved1:28; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_DCR;
//
// LVT Timer Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 Reserved0:4; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 Reserved1:3; ///< Reserved.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
UINT32 Reserved2:14; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_TIMER;
//
// LVT LINT0/LINT1 Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:1; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
UINT32 TriggerMode:1; ///< 0:edge, 1:level.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 Reserved1:15; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_LINT;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Reserved0:2; ///< Reserved
UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
UINT32 Reserved1:8; ///< Reserved.
UINT32 DestinationId:8; ///< Specifies the Destination ID.
UINT32 BaseAddress:12; ///< Must be 0FEEH
} Bits;
UINT32 Uint32;
} LOCAL_APIC_MSI_ADDRESS;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:3; ///< Reserved.
UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
UINT32 Reserved1:16; ///< Reserved.
UINT32 Reserved2:32; ///< Reserved.
} Bits;
UINT64 Uint64;
} LOCAL_APIC_MSI_DATA;
#include <Register/Intel/LocalApic.h>
#endif

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UefiCpuPkg/Include/Register/Microcode.h
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@@ -1,194 +1,13 @@
/** @file
Microcode Definitions.
Wrapper header file to include <Register/Intel/Microcode.h> in MdePkg.
Microcode Definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3A, Section 9.11 Microcode Definitions
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
**/
#ifndef __MICROCODE_H__
#define __MICROCODE_H__
///
/// CPU Microcode Date in BCD format
///
typedef union {
struct {
UINT32 Year:16;
UINT32 Day:8;
UINT32 Month:8;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_DATE;
///
/// CPU Microcode Processor Signature format
///
typedef union {
struct {
UINT32 Stepping:4;
UINT32 Model:4;
UINT32 Family:4;
UINT32 Type:2;
UINT32 Reserved1:2;
UINT32 ExtendedModel:4;
UINT32 ExtendedFamily:8;
UINT32 Reserved2:4;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_PROCESSOR_SIGNATURE;
#pragma pack (1)
///
/// Microcode Update Format definition
///
typedef struct {
///
/// Version number of the update header
///
UINT32 HeaderVersion;
///
/// Unique version number for the update, the basis for the update
/// signature provided by the processor to indicate the current update
/// functioning within the processor. Used by the BIOS to authenticate
/// the update and verify that the processor loads successfully. The
/// value in this field cannot be used for processor stepping identification
/// alone. This is a signed 32-bit number.
///
UINT32 UpdateRevision;
///
/// Date of the update creation in binary format: mmddyyyy (e.g.
/// 07/18/98 is 07181998H).
///
CPU_MICROCODE_DATE Date;
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Checksum of Update Data and Header. Used to verify the integrity of
/// the update header and data. Checksum is correct when the
/// summation of all the DWORDs (including the extended Processor
/// Signature Table) that comprise the microcode update result in
/// 00000000H.
///
UINT32 Checksum;
///
/// Version number of the loader program needed to correctly load this
/// update. The initial version is 00000001H
///
UINT32 LoaderRevision;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlags;
///
/// Specifies the size of the encrypted data in bytes, and must be a
/// multiple of DWORDs. If this value is 00000000H, then the microcode
/// update encrypted data is 2000 bytes (or 500 DWORDs).
///
UINT32 DataSize;
///
/// Specifies the total size of the microcode update in bytes. It is the
/// summation of the header size, the encrypted data size and the size of
/// the optional extended signature table. This value is always a multiple
/// of 1024.
///
UINT32 TotalSize;
///
/// Reserved fields for future expansion.
///
UINT8 Reserved[12];
} CPU_MICROCODE_HEADER;
///
/// Extended Signature Table Header Field Definitions
///
typedef struct {
///
/// Specifies the number of extended signature structures (Processor
/// Signature[n], processor flags[n] and checksum[n]) that exist in this
/// microcode update
///
UINT32 ExtendedSignatureCount;
///
/// Checksum of update extended processor signature table. Used to
/// verify the integrity of the extended processor signature table.
/// Checksum is correct when the summation of the DWORDs that
/// comprise the extended processor signature table results in
/// 00000000H.
///
UINT32 ExtendedChecksum;
///
/// Reserved fields.
///
UINT8 Reserved[12];
} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
///
/// Extended Signature Table Field Definitions
///
typedef struct {
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlag;
///
/// Used by utility software to decompose a microcode update into
/// multiple microcode updates where each of the new updates is
/// constructed without the optional Extended Processor Signature
/// Table.
/// To calculate the Checksum, substitute the Primary Processor
/// Signature entry and the Processor Flags entry with the
/// corresponding Extended Patch entry. Delete the Extended Processor
/// Signature Table entries. The Checksum is correct when the
/// summation of all DWORDs that comprise the created Extended
/// Processor Patch results in 00000000H.
///
UINT32 Checksum;
} CPU_MICROCODE_EXTENDED_TABLE;
#pragma pack ()
#include <Register/Intel/Microcode.h>
#endif

36
UefiCpuPkg/Include/Register/Msr.h
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@@ -1,44 +1,14 @@
/** @file
MSR Definitions.
Wrapper header file to include <Register/Intel/Msr.h> in MdePkg.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __MSR_H__
#define __MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Msr/Core2Msr.h>
#include <Register/Msr/AtomMsr.h>
#include <Register/Msr/SilvermontMsr.h>
#include <Register/Msr/GoldmontMsr.h>
#include <Register/Msr/GoldmontPlusMsr.h>
#include <Register/Msr/NehalemMsr.h>
#include <Register/Msr/Xeon5600Msr.h>
#include <Register/Msr/XeonE7Msr.h>
#include <Register/Msr/SandyBridgeMsr.h>
#include <Register/Msr/IvyBridgeMsr.h>
#include <Register/Msr/HaswellMsr.h>
#include <Register/Msr/HaswellEMsr.h>
#include <Register/Msr/BroadwellMsr.h>
#include <Register/Msr/XeonDMsr.h>
#include <Register/Msr/SkylakeMsr.h>
#include <Register/Msr/XeonPhiMsr.h>
#include <Register/Msr/Pentium4Msr.h>
#include <Register/Msr/CoreMsr.h>
#include <Register/Msr/PentiumMMsr.h>
#include <Register/Msr/P6Msr.h>
#include <Register/Msr/PentiumMsr.h>
#include <Register/Intel/Msr.h>
#endif

784
UefiCpuPkg/Include/Register/Msr/AtomMsr.h
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@@ -1,784 +0,0 @@
/** @file
MSR Definitions for the Intel(R) Atom(TM) Processor Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __ATOM_MSR_H__
#define __ATOM_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Atom(TM) Processor Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x1C || \
DisplayModel == 0x26 || \
DisplayModel == 0x27 || \
DisplayModel == 0x35 || \
DisplayModel == 0x36 \
) \
)
/**
Shared. Model Specific Platform ID (R).
@param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PLATFORM_ID_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
@endcode
@note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
**/
#define MSR_ATOM_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:8;
///
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
///
UINT32 MaximumQualifiedRatio:5;
UINT32 Reserved2:19;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PLATFORM_ID_REGISTER;
/**
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
processor features; (R) indicates current processor configuration.
@param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
@endcode
@note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 DataErrorCheckingEnable:1;
///
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 ResponseErrorCheckingEnable:1;
///
/// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
///
UINT32 AERR_DriveEnable:1;
///
/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
/// Disabled Always 0.
///
UINT32 BERR_Enable:1;
UINT32 Reserved2:1;
UINT32 Reserved3:1;
///
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
///
UINT32 BINIT_DriverEnable:1;
UINT32 Reserved4:1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 ExecuteBIST:1;
///
/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 AERR_ObservationEnabled:1;
UINT32 Reserved5:1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 BINIT_ObservationEnabled:1;
UINT32 Reserved6:1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
///
UINT32 ResetVector:1;
UINT32 Reserved7:1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
///
UINT32 APICClusterID:2;
UINT32 Reserved8:2;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
///
UINT32 SymmetricArbitrationID:2;
///
/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
///
UINT32 IntegerBusFrequencyRatio:5;
UINT32 Reserved9:5;
UINT32 Reserved10:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_EBL_CR_POWERON_REGISTER;
/**
Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The From_IP part of the
stack contains pointers to the source instruction . See also: - Last Branch
Record Stack TOS at 1C9H - Section 17.5.
@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
@{
**/
#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
/// @}
/**
Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The To_IP part of the
stack contains pointers to the destination instruction.
@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
@{
**/
#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
/// @}
/**
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
bus clock speed for processors based on Intel Atom microarchitecture:.
@param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_FSB_FREQ_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
@endcode
@note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
**/
#define MSR_ATOM_FSB_FREQ 0x000000CD
/**
MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 2:0] - Scalable Bus Speed
///
/// Atom Processor Family
/// ---------------------
/// 111B: 083 MHz (FSB 333)
/// 101B: 100 MHz (FSB 400)
/// 001B: 133 MHz (FSB 533)
/// 011B: 167 MHz (FSB 667)
///
/// 133.33 MHz should be utilized if performing calculation with
/// System Bus Speed when encoding is 001B.
/// 166.67 MHz should be utilized if performing calculation with
/// System Bus Speed when
/// encoding is 011B.
///
UINT32 ScalableBusSpeed:3;
UINT32 Reserved1:29;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_FSB_FREQ_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
@endcode
@note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
#define MSR_ATOM_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
UINT32 L2HardwareEnabled:1;
UINT32 Reserved1:7;
///
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
UINT32 L2Enabled:1;
UINT32 Reserved2:14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
UINT32 L2NotPresent:1;
UINT32 Reserved3:8;
UINT32 Reserved4:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_BBL_CR_CTL3_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_PERF_STATUS (0x00000198)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PERF_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
@endcode
@note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
**/
#define MSR_ATOM_PERF_STATUS 0x00000198
/**
MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 15:0] Current Performance State Value.
///
UINT32 CurrentPerformanceStateValue:16;
UINT32 Reserved1:16;
UINT32 Reserved2:8;
///
/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
/// configured for the processor.
///
UINT32 MaximumBusRatio:5;
UINT32 Reserved3:19;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PERF_STATUS_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_THERM2_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
@endcode
@note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
#define MSR_ATOM_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
///
UINT32 TM_SELECT:1;
UINT32 Reserved2:15;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_THERM2_CTL_REGISTER;
/**
Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
@note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 2-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
UINT32 Reserved4:1;
///
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
/// the processor to indicate a pending break event within the processor 0
/// = Indicates compatible FERR# signaling behavior This bit must be set
/// to 1 to support XAPIC interrupt model usage.
///
UINT32 FERR:1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 2-2.
///
UINT32 PEBS:1;
///
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
/// thermal sensor indicates that the die temperature is at the
/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
/// TM2 will reduce the bus to core ratio and voltage according to the
/// value last written to MSR_THERM2_CTL bits 15:0.
/// When this bit is clear (0, default), the processor does not change
/// the VID signals or the bus to core ratio when the processor enters a
/// thermally managed state. The BIOS must enable this feature if the
/// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
/// not set, this feature is not supported and BIOS must not alter the
/// contents of the TM2 bit location. The processor is operating out of
/// specification if both this bit and the TM1 bit are set to 0.
///
UINT32 TM2:1;
UINT32 Reserved5:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved6:1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
///
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
/// (R/WO) When set, this bit causes the following bits to become
/// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
/// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
/// be set before an Enhanced Intel SpeedStep Technology transition is
/// requested. This bit is cleared on reset.
///
UINT32 EISTLock:1;
UINT32 Reserved8:1;
///
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved9:8;
UINT32 Reserved10:2;
///
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
/**
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
that points to the MSR containing the most recent branch record. See
MSR_LASTBRANCH_0_FROM_IP (at 40H).
@param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
/**
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
@param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
@endcode
@note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_ATOM_LER_FROM_LIP 0x000001DD
/**
Unique. Last Exception Record To Linear IP (R) This area contains a pointer
to the target of the last branch instruction that the processor executed
prior to the last exception that was generated or the last interrupt that
was handled.
@param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
@endcode
@note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_ATOM_LER_TO_LIP 0x000001DE
/**
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
@endcode
@note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
#define MSR_ATOM_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
///
UINT32 Enable:1;
UINT32 Reserved1:31;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PEBS_ENABLE_REGISTER;
/**
Package. Package C2 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C2 Residency Counter. (R/O) Time that this
package is in processor-specific C2 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
/**
Package. Package C4 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C4 Residency Counter. (R/O) Time that this
package is in processor-specific C4 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
/**
Package. Package C6 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C6 Residency Counter. (R/O) Time that this
package is in processor-specific C6 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
#endif

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UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
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@@ -1,354 +0,0 @@
/** @file
MSR Definitions for Intel processors based on the Broadwell microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __BROADWELL_MSR_H__
#define __BROADWELL_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Broadwell microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3D || \
DisplayModel == 0x47 || \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)
/**
Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
Facilities.".
@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
@endcode
@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Ovf_PMC0.
///
UINT32 Ovf_PMC0:1;
///
/// [Bit 1] Ovf_PMC1.
///
UINT32 Ovf_PMC1:1;
///
/// [Bit 2] Ovf_PMC2.
///
UINT32 Ovf_PMC2:1;
///
/// [Bit 3] Ovf_PMC3.
///
UINT32 Ovf_PMC3:1;
UINT32 Reserved1:28;
///
/// [Bit 32] Ovf_FixedCtr0.
///
UINT32 Ovf_FixedCtr0:1;
///
/// [Bit 33] Ovf_FixedCtr1.
///
UINT32 Ovf_FixedCtr1:1;
///
/// [Bit 34] Ovf_FixedCtr2.
///
UINT32 Ovf_FixedCtr2:1;
UINT32 Reserved2:20;
///
/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
/// Addresses (ToPA).".
///
UINT32 Trace_ToPA_PMI:1;
UINT32 Reserved3:5;
///
/// [Bit 61] Ovf_Uncore.
///
UINT32 Ovf_Uncore:1;
///
/// [Bit 62] Ovf_BufDSSAVE.
///
UINT32 OvfBuf:1;
///
/// [Bit 63] CondChgd.
///
UINT32 CondChgd:1;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
@endcode
@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
/// processor-specific C-state code name (consuming the least power) for
/// the package. The default is set as factory-configured package C-state
/// limit. The following C-state code name encodings are supported: 0000b:
/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
///
UINT32 Limit:4;
UINT32 Reserved1:6;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
///
UINT32 IO_MWAIT:1;
UINT32 Reserved2:4;
///
/// [Bit 15] CFG Lock (R/WO).
///
UINT32 CFGLock:1;
UINT32 Reserved3:9;
///
/// [Bit 25] C3 State Auto Demotion Enable (R/W).
///
UINT32 C3AutoDemotion:1;
///
/// [Bit 26] C1 State Auto Demotion Enable (R/W).
///
UINT32 C1AutoDemotion:1;
///
/// [Bit 27] Enable C3 Undemotion (R/W).
///
UINT32 C3Undemotion:1;
///
/// [Bit 28] Enable C1 Undemotion (R/W).
///
UINT32 C1Undemotion:1;
///
/// [Bit 29] Enable Package C-State Auto-demotion (R/W).
///
UINT32 CStateAutoDemotion:1;
///
/// [Bit 30] Enable Package C-State Undemotion (R/W).
///
UINT32 CStateUndemotion:1;
UINT32 Reserved4:1;
UINT32 Reserved5:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
@endcode
@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
UINT32 Maximum1C:8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
UINT32 Maximum2C:8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
UINT32 Maximum3C:8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
UINT32 Maximum4C:8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5core active.
///
UINT32 Maximum5C:8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6core active.
///
UINT32 Maximum6C:8;
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
/**
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum
frequency that hardware will select.
@param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
@endcode
**/
#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620
/**
MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
/// LLC/Ring.
///
UINT32 MAX_RATIO:7;
UINT32 Reserved2:1;
///
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
/// possible ratio of the LLC/Ring.
///
UINT32 MIN_RATIO:7;
UINT32 Reserved3:17;
UINT32 Reserved4:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
@endcode
@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639
#endif

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UefiCpuPkg/Include/Register/Msr/Core2Msr.h
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/** @file
MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __GOLDMONT_PLUS_MSR_H__
#define __GOLDMONT_PLUS_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel Atom processors based on the Goldmont plus microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x7A \
) \
)
/**
Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
Sampling (PEBS).".
@param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
@endcode
**/
#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC0.
///
UINT32 Fix_Me_1:1;
///
/// [Bit 1] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC1.
///
UINT32 Fix_Me_2:1;
///
/// [Bit 2] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC2.
///
UINT32 Fix_Me_3:1;
///
/// [Bit 3] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC3.
///
UINT32 Fix_Me_4:1;
UINT32 Reserved1:28;
///
/// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
///
UINT32 Fix_Me_5:1;
///
/// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
///
UINT32 Fix_Me_6:1;
///
/// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
///
UINT32 Fix_Me_7:1;
UINT32 Reserved2:29;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
/**
Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
the first entry of the 32-entry LBR stack. The From_IP part of the stack
contains pointers to the source instruction. See also: - Last Branch Record
Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and
.. Exception Recording for Processors based on Goldmont Plus
Microarchitecture.".
@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
@endcode
**/
#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680
#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681
#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682
#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683
#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684
#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685
#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686
#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687
#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688
#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689
#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A
#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B
#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C
#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D
#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E
#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F
#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690
#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691
#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692
#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693
#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694
#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695
#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696
#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697
#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698
#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699
#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A
#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B
#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C
#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D
#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E
#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F
/**
Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
the first entry of the 32-entry LBR stack. The To_IP part of the stack
contains pointers to the Destination instruction. See also: - Section 17.7,
"Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
based on Goldmont Plus Microarchitecture.".
@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
@endcode
**/
#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF
#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF
/**
Core. Last Branch Record N Additional Information (R/W) One of the three
MSRs that make up the first entry of the 32-entry LBR stack. This part of
the stack contains flag and elapsed cycle information. See also: - Last
Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".
@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
@endcode
**/
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF
#endif

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/** @file
MSR Definitions for Pentium M Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __PENTIUM_M_MSR_H__
#define __PENTIUM_M_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Pentium M Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0D \
) \
)
/**
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
/**
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
@endcode
@note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
/**
Processor Hard Power-On Configuration (R/W) Enables and disables processor
features. (R) Indicates current processor configuration.
@param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
/// Pentium M processor.
///
UINT32 DataErrorCheckingEnable:1;
///
/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
/// the Pentium M processor.
///
UINT32 ResponseErrorCheckingEnable:1;
///
/// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
UINT32 MCERR_DriveEnable:1;
///
/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
UINT32 AddressParityEnable:1;
UINT32 Reserved2:2;
///
/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
/// the Pentium M processor.
///
UINT32 BINIT_DriverEnable:1;
///
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 OutputTriStateEnable:1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 ExecuteBIST:1;
///
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
UINT32 MCERR_ObservationEnabled:1;
UINT32 Reserved3:1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
UINT32 BINIT_ObservationEnabled:1;
UINT32 Reserved4:1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
/// Always 0 on the Pentium M processor.
///
UINT32 ResetVector:1;
UINT32 Reserved5:1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
/// processor.
///
UINT32 APICClusterID:2;
///
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
/// 0 on the Pentium M processor.
///
UINT32 SystemBusFrequency:1;
UINT32 Reserved6:1;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
/// M processor.
///
UINT32 SymmetricArbitrationID:2;
///
/// [Bits 26:22] Clock Frequency Ratio (R/O).
///
UINT32 ClockFrequencyRatio:5;
UINT32 Reserved7:5;
UINT32 Reserved8:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
/**
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_n
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
@endcode
@note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
@{
**/
#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
/// @}
/**
Reserved.
@param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
**/
#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
/**
@param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
UINT32 L2HardwareEnabled:1;
UINT32 Reserved1:4;
///
/// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
/// cache data bus. ECC is always generated on write cycles. 1. = Disabled
/// (default) 2. = Enabled For the Pentium M processor, ECC checking on
/// the cache data bus is always enabled.
///
UINT32 ECCCheckEnable:1;
UINT32 Reserved2:2;
///
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
UINT32 L2Enabled:1;
UINT32 Reserved3:14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
UINT32 L2NotPresent:1;
UINT32 Reserved4:8;
UINT32 Reserved5:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
/**
@param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
///
UINT32 TM_SELECT:1;
UINT32 Reserved2:15;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
/**
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:3;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
/// this bit enables the thermal control circuit (TCC) portion of the
/// Intel Thermal Monitor feature. This allows processor clocks to be
/// automatically modulated based on the processor's thermal sensor
/// operation. 0 = Disabled (default). The automatic thermal control
/// circuit enable bit determines if the thermal control circuit (TCC)
/// will be activated when the processor's internal thermal sensor
/// determines the processor is about to exceed its maximum operating
/// temperature. When the TCC is activated and TM1 is enabled, the
/// processors clocks will be forced to a 50% duty cycle. BIOS must enable
/// this feature. The bit should not be confused with the on-demand
/// thermal control circuit enable bit.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
/// monitoring enabled 0 = Performance monitoring disabled.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:2;
///
/// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
/// processor to indicate a pending break event within the processor 0 =
/// Indicates compatible FERR# signaling behavior This bit must be set to
/// 1 to support XAPIC interrupt model usage.
/// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
/// support branch trace storage (BTS) 0 = BTS is supported
///
UINT32 FERR:1;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO)
/// 1 = Processor doesn't support branch trace storage (BTS)
/// 0 = BTS is supported
///
UINT32 BTS:1;
///
/// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
/// Processor does not support processor event based sampling (PEBS); 0 =
/// PEBS is supported. The Pentium M processor does not support PEBS.
///
UINT32 PEBS:1;
UINT32 Reserved5:3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
/// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
/// processor, this bit may be configured to be read-only.
///
UINT32 EIST:1;
UINT32 Reserved6:6;
///
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
/// disabled. xTPR messages are optional messages that allow the processor
/// to inform the chipset of its priority. The default is processor
/// specific.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
/**
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
to the MSR containing the most recent branch record. See also: -
MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
and Exception Recording (Pentium M Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
@endcode
@note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
/**
Debug Control (R/W) Controls how several debug features are used. Bit
definitions are discussed in the referenced section. See Section 17.15,
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
@endcode
@note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
**/
#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
/**
Last Exception Record To Linear IP (R) This area contains a pointer to the
target of the last branch instruction that the processor executed prior to
the last exception that was generated or the last interrupt that was
handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
MSRs.".
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
@endcode
@note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
/**
Last Exception Record From Linear IP (R) Contains a pointer to the last
branch instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled. See Section
17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
@endcode
@note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
**/
#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
**/
#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear. When not implemented in the processor, all
reads and writes to this MSR will cause a general-protection exception.
@param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
**/
#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
**/
#define MSR_PENTIUM_M_MC3_CTL 0x00000410
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
**/
#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear. When not implemented in the processor, all
reads and writes to this MSR will cause a general-protection exception.
@param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
**/
#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
#endif

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/** @file
MSR Definitions for Pentium Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __PENTIUM_MSR_H__
#define __PENTIUM_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Pentium Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x05 && \
( \
DisplayModel == 0x01 || \
DisplayModel == 0x02 || \
DisplayModel == 0x04 \
) \
)
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
@endcode
@note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
@endcode
@note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
/**
See Section 17.17, "Time-Stamp Counter.".
@param ECX MSR_PENTIUM_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
@endcode
@note MSR_PENTIUM_TSC is defined as TSC in SDM.
**/
#define MSR_PENTIUM_TSC 0x00000010
/**
See Section 18.6.9.1, "Control and Event Select Register (CESR).".
@param ECX MSR_PENTIUM_CESR (0x00000011)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
@endcode
@note MSR_PENTIUM_CESR is defined as CESR in SDM.
**/
#define MSR_PENTIUM_CESR 0x00000011
/**
Section 18.6.9.3, "Events Counted.".
@param ECX MSR_PENTIUM_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
@endcode
@note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
@{
**/
#define MSR_PENTIUM_CTR0 0x00000012
#define MSR_PENTIUM_CTR1 0x00000013
/// @}
#endif

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/** @file
MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __XEON_5600_MSR_H__
#define __XEON_5600_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor Series 5600?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x25 || \
DisplayModel == 0x2C \
) \
)
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
@endcode
@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
/// MSR, the configuration of AES instruction set availability is as
/// follows: 11b: AES instructions are not available until next RESET.
/// otherwise, AES instructions are available. Note, AES instruction set
/// is not available if read is unsuccessful. If the configuration is not
/// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
UINT32 AESConfiguration:2;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
/**
Thread. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
@endcode
@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
@endcode
@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
UINT32 Maximum1C:8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
UINT32 Maximum2C:8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
UINT32 Maximum3C:8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
UINT32 Maximum4C:8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5 core active.
///
UINT32 Maximum5C:8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6 core active.
///
UINT32 Maximum6C:8;
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
/**
Package. See Table 2-2.
@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
@endcode
@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
**/
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
#endif

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UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
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367
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
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@@ -1,367 +0,0 @@
/** @file
MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __XEON_E7_MSR_H__
#define __XEON_E7_MSR_H__
#include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor E7 Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x2F \
) \
)
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
@endcode
@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
/// MSR, the configuration of AES instruction set availability is as
/// follows: 11b: AES instructions are not available until next RESET.
/// otherwise, AES instructions are available. Note, AES instruction set
/// is not available if read is unsuccessful. If the configuration is not
/// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
UINT32 AESConfiguration:2;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
/**
Thread. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
@endcode
@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7
/**
Package. Reserved Attempt to read/write will cause #UD.
@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
@endcode
@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
/**
Package. Uncore C-box 8 perfmon local box control MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
/**
Package. Uncore C-box 8 perfmon local box status MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
/**
Package. Uncore C-box 8 perfmon local box overflow control MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
/**
Package. Uncore C-box 8 perfmon event select MSR.
@param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
@{
**/
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
/// @}
/**
Package. Uncore C-box 8 perfmon counter MSR.
@param ECX MSR_XEON_E7_C8_PMON_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
@{
**/
#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
/// @}
/**
Package. Uncore C-box 9 perfmon local box control MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
/**
Package. Uncore C-box 9 perfmon local box status MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
/**
Package. Uncore C-box 9 perfmon local box overflow control MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
/**
Package. Uncore C-box 9 perfmon event select MSR.
@param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
@{
**/
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
/// @}
/**
Package. Uncore C-box 9 perfmon counter MSR.
@param ECX MSR_XEON_E7_C9_PMON_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
@{
**/
#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB
/// @}
#endif

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UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
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UefiCpuPkg/Include/Register/SmramSaveStateMap.h
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/** @file
SMRAM Save State Map Definitions.
SMRAM Save State Map definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3C, Section 34.4 SMRAM
Volume 3C, Section 34.5 SMI Handler Execution Environment
Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
Wrapper header file to include <Register/Intel/SmramSaveStateMap.h> in MdePkg.
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __SMRAM_SAVE_STATE_MAP_H__
#define __SMRAM_SAVE_STATE_MAP_H__
///
/// Default SMBASE address
///
#define SMM_DEFAULT_SMBASE 0x30000
///
/// Offset of SMM handler from SMBASE
///
#define SMM_HANDLER_OFFSET 0x8000
///
/// Offset of SMRAM Save State Map from SMBASE
///
#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00
#pragma pack (1)
///
/// 32-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved[0x200]; // 7c00h
// Padded an extra 0x200 bytes so 32-bit and 64-bit
// SMRAM Save State Maps are the same size
UINT8 Reserved1[0xf8]; // 7e00h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved2[0x9C]; // 7f08h
UINT32 IOMemAddr; // 7fa0h
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS; // 7fach
UINT32 _SS; // 7fb0h
UINT32 _DS; // 7fb4h
UINT32 _FS; // 7fb8h
UINT32 _GS; // 7fbch
UINT32 Reserved3; // 7fc0h
UINT32 _TR; // 7fc4h
UINT32 _DR7; // 7fc8h
UINT32 _DR6; // 7fcch
UINT32 _EAX; // 7fd0h
UINT32 _ECX; // 7fd4h
UINT32 _EDX; // 7fd8h
UINT32 _EBX; // 7fdch
UINT32 _ESP; // 7fe0h
UINT32 _EBP; // 7fe4h
UINT32 _ESI; // 7fe8h
UINT32 _EDI; // 7fech
UINT32 _EIP; // 7ff0h
UINT32 _EFLAGS; // 7ff4h
UINT32 _CR3; // 7ff8h
UINT32 _CR0; // 7ffch
} SMRAM_SAVE_STATE_MAP32;
///
/// 64-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved1[0x1d0]; // 7c00h
UINT32 GdtBaseHiDword; // 7dd0h
UINT32 LdtBaseHiDword; // 7dd4h
UINT32 IdtBaseHiDword; // 7dd8h
UINT8 Reserved2[0xc]; // 7ddch
UINT64 IO_EIP; // 7de8h
UINT8 Reserved3[0x50]; // 7df0h
UINT32 _CR4; // 7e40h
UINT8 Reserved4[0x48]; // 7e44h
UINT32 GdtBaseLoDword; // 7e8ch
UINT32 Reserved5; // 7e90h
UINT32 IdtBaseLoDword; // 7e94h
UINT32 Reserved6; // 7e98h
UINT32 LdtBaseLoDword; // 7e9ch
UINT8 Reserved7[0x38]; // 7ea0h
UINT64 EptVmxControl; // 7ed8h
UINT32 EnEptVmxControl; // 7ee0h
UINT8 Reserved8[0x14]; // 7ee4h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved9[0x18]; // 7f04h
UINT64 _R15; // 7f1ch
UINT64 _R14;
UINT64 _R13;
UINT64 _R12;
UINT64 _R11;
UINT64 _R10;
UINT64 _R9;
UINT64 _R8;
UINT64 _RAX; // 7f5ch
UINT64 _RCX;
UINT64 _RDX;
UINT64 _RBX;
UINT64 _RSP;
UINT64 _RBP;
UINT64 _RSI;
UINT64 _RDI;
UINT64 IOMemAddr; // 7f9ch
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS;
UINT32 _SS;
UINT32 _DS;
UINT32 _FS;
UINT32 _GS;
UINT32 _LDTR; // 7fc0h
UINT32 _TR;
UINT64 _DR7; // 7fc8h
UINT64 _DR6;
UINT64 _RIP; // 7fd8h
UINT64 IA32_EFER; // 7fe0h
UINT64 _RFLAGS; // 7fe8h
UINT64 _CR3; // 7ff0h
UINT64 _CR0; // 7ff8h
} SMRAM_SAVE_STATE_MAP64;
///
/// Union of 32-bit and 64-bit SMRAM Save State Maps
///
typedef union {
SMRAM_SAVE_STATE_MAP32 x86;
SMRAM_SAVE_STATE_MAP64 x64;
} SMRAM_SAVE_STATE_MAP;
///
/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
///
#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004
///
/// SMRAM Save State Map IOMisc I/O Length Values
///
#define SMM_IO_LENGTH_BYTE 0x01
#define SMM_IO_LENGTH_WORD 0x02
#define SMM_IO_LENGTH_DWORD 0x04
///
/// SMRAM Save State Map IOMisc I/O Instruction Type Values
///
#define SMM_IO_TYPE_IN_IMMEDIATE 0x9
#define SMM_IO_TYPE_IN_DX 0x1
#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8
#define SMM_IO_TYPE_OUT_DX 0x0
#define SMM_IO_TYPE_INS 0x3
#define SMM_IO_TYPE_OUTS 0x2
#define SMM_IO_TYPE_REP_INS 0x7
#define SMM_IO_TYPE_REP_OUTS 0x6
///
/// SMRAM Save State Map IOMisc structure
///
typedef union {
struct {
UINT32 SmiFlag:1;
UINT32 Length:3;
UINT32 Type:4;
UINT32 Reserved1:8;
UINT32 Port:16;
} Bits;
UINT32 Uint32;
} SMRAM_SAVE_STATE_IOMISC;
#pragma pack ()
#include <Register/Intel/SmramSaveStateMap.h>
#endif

941
UefiCpuPkg/Include/Register/StmApi.h
View File

@@ -1,948 +1,13 @@
/** @file
STM API definition
Wrapper header file to include <Register/Intel/StmApi.h> in MdePkg.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_API_H_
#define _STM_API_H_
#include <Register/StmStatusCode.h>
#include <Register/StmResourceDescriptor.h>
#include <Register/ArchitecturalMsr.h>
#pragma pack (1)
/**
STM Header Structures
**/
typedef struct {
UINT32 Intel64ModeSupported :1; ///> bitfield
UINT32 EptSupported :1; ///> bitfield
UINT32 Reserved :30; ///> must be 0
} STM_FEAT;
#define STM_SPEC_VERSION_MAJOR 1
#define STM_SPEC_VERSION_MINOR 0
typedef struct {
UINT8 StmSpecVerMajor;
UINT8 StmSpecVerMinor;
///
/// Must be zero
///
UINT16 Reserved;
UINT32 StaticImageSize;
UINT32 PerProcDynamicMemorySize;
UINT32 AdditionalDynamicMemorySize;
STM_FEAT StmFeatures;
UINT32 NumberOfRevIDs;
UINT32 StmSmmRevID[1];
///
/// The total STM_HEADER should be 4K.
///
} SOFTWARE_STM_HEADER;
typedef struct {
MSEG_HEADER HwStmHdr;
SOFTWARE_STM_HEADER SwStmHdr;
} STM_HEADER;
/**
VMCALL API Numbers
API number convention: BIOS facing VMCALL interfaces have bit 16 clear
**/
/**
StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to
physical mapping of an address range into the SMM guest's virtual
memory space.
@param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)
@param EBX Low 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be 0.
@note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They
are not modified by StmMapAddressRange.
@retval CF 0
No error, EAX set to STM_SUCCESS.
The memory range was mapped as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested mapping contains a protected resource.
@retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED
The requested cache type could not be satisfied.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
Page count must not be zero.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmMapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_MAP_ADDRESS_RANGE 0x00000001
/**
STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 PhysicalAddress;
UINT64 VirtualAddress;
UINT32 PageCount;
UINT32 PatCacheType;
} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR
@{
**/
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF
/// @}
/**
StmUnmapAddressRange enables a SMM guest to remove mappings from its page
table.
If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can
control its own page tables. In this case, the STM implementation may
optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.
@param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)
@param EBX Low 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. The memory range was unmapped
as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmUnmapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002
/**
STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 VirtualAddress;
UINT32 Length;
} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Since the normal OS environment runs with a different set of page tables than
the SMM guest, virtual mappings will certainly be different. In order to do a
guest virtual to host physical translation of an address from the normal OS
code (EIP for example), it is necessary to walk the page tables governing the
OS page mappings. Since the SMM guest has no direct access to the page tables,
it must ask the STM to do this page table walk. This is supported via the
StmAddressLookup VMCALL. All OS page table formats need to be supported,
(e.g. PAE, PSE, Intel64, EPT, etc.)
StmAddressLookup takes a CR3 value and a virtual address from the interrupted
code as input and returns the corresponding physical address. It also
optionally maps the physical address into the SMM guest's virtual address
space. This new mapping persists ONLY for the duration of the SMI and if
needed in subsequent SMIs it must be remapped. PAT cache types follow the
interrupted environment's page table.
If EPT is enabled, OS CR3 only provides guest physical address information,
but the SMM guest might also need to know the host physical address. Since
SMM does not have direct access rights to EPT (it is protected by the STM),
SMM can input InterruptedEptp to let STM help to walk through it, and output
the host physical address.
@param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)
@param EBX Low 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. PhysicalAddress contains the
host physical address determined by walking the interrupted SMM
guest's page tables. SmmGuestVirtualAddress contains the SMM
guest's virtual mapping of the requested address.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested page was a protected page.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The requested virtual address did not exist in the page given
page table.
@retval EAX #ERROR_STM_BAD_CR3
The CR3 input was invalid. CR3 values must be from one of the
interrupted guest, or from the interrupted guest of another
processor.
@retval EAX #ERROR_STM_PHYSICAL_OVER_4G
The resulting physical address is greater than 4G and no virtual
address was supplied. The STM could not determine what address
within the SMM guest's virtual address space to do the mapping.
STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the
physical address determined by walking the interrupted
environment's page tables.
@retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL
A specific virtual mapping was requested, but
SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler
is running in 32 bit mode.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_ADDRESS_LOOKUP 0x00000003
/**
STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL
**/
typedef struct {
UINT64 InterruptedGuestVirtualAddress;
UINT32 Length;
UINT64 InterruptedCr3;
UINT64 InterruptedEptp;
UINT32 MapToSmmGuest:2;
UINT32 InterruptedCr4Pae:1;
UINT32 InterruptedCr4Pse:1;
UINT32 InterruptedIa32eMode:1;
UINT32 Reserved1:27;
UINT32 Reserved2;
UINT64 PhysicalAddress;
UINT64 SmmGuestVirtualAddress;
} STM_ADDRESS_LOOKUP_DESCRIPTOR;
/**
Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR
@{
**/
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3
/// @}
/**
When returning from a protection exception (see section 6.2), the SMM guest
can instruct the STM to take one of two paths. It can either request a value
be logged to the TXT.ERRORCODE register and subsequently reset the machine
(indicating it couldn't resolve the problem), or it can request that the STM
resume the SMM guest again with the specified register state.
Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more
like a jump or an IRET instruction than a "call". It does not return directly
to the caller, but indirectly to a different location specified on the
caller's stack (see section 6.2) or not at all.
If the SMM guest STM protection exception handler itself causes a protection
exception (e.g. a single nested exception), or more than 100 un-nested
exceptions occur within the scope of a single SMI event, the STM must write
STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and
assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify
the code requirements while still enabling a reasonable debugging capability.
@param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)
@param EBX If 0, resume SMM guest using register state found on exception
stack. If in range 0x01..0x0F, EBX contains a BIOS error code
which the STM must record in the TXT.ERRORCODE register and
subsequently reset the system via TXT.CMD.SYS_RESET. The value
of the TXT.ERRORCODE register is calculated as follows:
TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
Values 0x10..0xFFFFFFFF are reserved, do not use.
**/
#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004
/**
VMCALL API Numbers
API number convention: MLE facing VMCALL interfaces have bit 16 set.
The STM configuration lifecycle is as follows:
1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for
setup of initial protection profile. This is done on a single CPU and
has global effect.
3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial
protection profile. The protection profile is global across all CPUs.
4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving
SMI events. This must be done on every logical CPU.
5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or
#STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as
necessary.
6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked
following #STM_API_STOP VMCALL.
**/
/**
StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs
should remain disabled from the invocation of GETSEC[SENTER] until they are
re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is
enabled and the STM has been started and is active. Prior to invoking
StartStmVMCALL(), the MLE root should first invoke
InitializeProtectionVMCALL() followed by as many iterations of
ProtectResourceVMCALL() as necessary to establish the initial protection
profile. StartStmVmcall() must be invoked on all processor threads.
@param EAX #STM_API_START (0x00010001)
@param EDX STM configuration options. These provide the MLE with the
ability to pass configuration parameters to the STM.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been configured
and is now active and the guarding all requested resources.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. STM remains active and
guarding previously enabled resource list.
@retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED
The StartStmVMCALL() was invoked from VMX root mode, but outside
of SMX. This error code indicates the STM or platform does not
support the STM outside of SMX. The SMI handler remains active
and operates in legacy mode. See Appendix C
@retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT
The CPU doesn't support the MSR bit. The STM is not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_START (BIT16 | 1)
/**
Bit values for EDX input parameter to #STM_API_START VMCALL
@{
**/
#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0
/// @}
/**
The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is
normally done as part of a full teardown of the SMX environment when the
system is being shut down. At the time the call is invoked, SMI is enabled
and the STM is active. When the call returns, the STM has been stopped and
all STM context is discarded and SMI is disabled.
@param EAX #STM_API_STOP (0x00010002)
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been stopped and
is no longer processing SMI events. SMI is blocked.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_STOPPED
The STM was not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_STOP (BIT16 | 2)
/**
The ProtectResourceVMCALL() is invoked by the MLE root to request protection
of specific resources. The request is defined by a STM_RESOURCE_LIST, which
may contain more than one resource descriptor. Each resource descriptor is
processed separately by the STM. Whether or not protection for any specific
resource is granted is returned by the STM via the ReturnStatus bit in the
associated STM_RSC_DESC_HEADER.
@param EAX #STM_API_PROTECT_RESOURCE (0x00010003)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource request granted,
and clear for each resource request denied. There are no other fields
modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be
contained entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has successfully
merged the entire protection request into the active protection
profile. There is therefore no need to check the ReturnStatus
bits in the STM_RESOURCE_LIST.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE
At least one of the requested resource protections intersects a
BIOS required resource. Therefore, the caller must walk through
the STM_RESOURCE_LIST to determine which of the requested
resources was not granted protection. The entire list must be
traversed since there may be multiple failures.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources was not granted protection. The entire list
must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_OUT_OF_RESOURCES
The STM has encountered an internal error and cannot complete
the request.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_PROTECT_RESOURCE (BIT16 | 3)
/**
The UnProtectResourceVMCALL() is invoked by the MLE root to request that the
STM allow the SMI handler access to the specified resources.
@param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource processed. For
a properly formed STM_RESOURCE_LIST, this should be all resources
listed. There are no other fields modified by
UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained
entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The requested resources are
not being guarded by the STM.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources were not able to be unprotected. The entire
list must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)
/**
The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list
of BIOS required resources from the STM.
@param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)
@param EBX Low 32 bits of physical address of caller allocated destination
buffer. Bits 11:0 are ignored and assumed to be zero, making the
buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated destination
buffer.
@param EDX Indicates which page of the BIOS resource list to copy into the
destination buffer. The first page is indicated by 0, the second
page by 1, etc.
@retval CF 0
No error, EAX set to STM_SUCCESS. The destination buffer
contains the BIOS required resources. If the page retrieved is
the last page, EDX will be cleared to 0. If there are more pages
to retrieve, EDX is incremented to the next page index. Calling
software should iterate on GetBiosResourcesVMCALL() until EDX is
returned cleared to 0.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The page index supplied in EDX input was out of range.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@retval EDX Page index of next page to read. A return of EDX=0 signifies
that the entire list has been read.
@note EDX is both an input and an output register.
@note All other registers unmodified.
**/
#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)
/**
The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an
MLE guest (including the MLE root) from the list of protected domains.
@param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)
@param EBX Low 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to
be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST.
@note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not
modified by ManageVmcsDatabaseVMCALL().
@retval CF 0
No error, EAX set to STM_SUCCESS.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_INVALID_VMCS
Indicates a request to remove a VMCS from the database was made,
but the referenced VMCS was not found in the database.
@retval EAX #ERROR_STM_VMCS_PRESENT
Indicates a request to add a VMCS to the database was made, but
the referenced VMCS was already present in the database.
@retval EAX #ERROR_INVALID_PARAMETER
Indicates non-zero reserved field.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred
@note All other registers unmodified.
**/
#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)
/**
STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL
**/
typedef struct {
///
/// bits 11:0 are reserved and must be 0
///
UINT64 VmcsPhysPointer;
UINT32 DomainType :4;
UINT32 XStatePolicy :2;
UINT32 DegradationPolicy :4;
///
/// Must be 0
///
UINT32 Reserved1 :22;
UINT32 AddOrRemove;
} STM_VMCS_DATABASE_REQUEST;
/**
Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define DOMAIN_UNPROTECTED 0
#define DOMAIN_DISALLOWED_IO_OUT BIT0
#define DOMAIN_DISALLOWED_IO_IN BIT1
#define DOMAIN_INTEGRITY BIT2
#define DOMAIN_CONFIDENTIALITY BIT3
#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
/// @}
/**
Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define XSTATE_READWRITE 0x00
#define XSTATE_READONLY 0x01
#define XSTATE_SCRUB 0x03
/// @}
/**
Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define STM_VMCS_DATABASE_REQUEST_ADD 1
#define STM_VMCS_DATABASE_REQUEST_REMOVE 0
/// @}
/**
InitializeProtectionVMCALL() prepares the STM for setup of the initial
protection profile which is subsequently communicated via one or more
invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().
It is only necessary to invoke InitializeProtectionVMCALL() on one processor
thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked
or unmasked. The STM should return back to the MLE with "Blocking by SMI" set
to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the
MLE guest.
@param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)
@retval CF 0
No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM
capabilities as defined below. The STM has set up an empty
protection profile, except for the resources that it sets up to
protect itself. The STM must not allow the SMI handler to map
any pages from the MSEG Base to the top of TSEG. The STM must
also not allow SMI handler access to those MSRs which the STM
requires for its own protection.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. The STM remains active
and guarding the previously enabled resource list.
@retval EAX #ERROR_STM_UNPROTECTABLE
The STM determines that based on the platform configuration, the
STM is unable to protect itself. For example, the BIOS required
resource list contains memory pages in MSEG.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)
/**
Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION
@{
**/
#define STM_RSC_BGI BIT1
#define STM_RSC_BGM BIT2
#define STM_RSC_MSR BIT3
/// @}
/**
The ManageEventLogVMCALL() is invoked by the MLE root to control the logging
feature. It consists of several sub-functions to facilitate establishment of
the log itself, configuring what events will be logged, and functions to
start, stop, and clear the log.
@param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)
@param EBX Low 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and
assumed to be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST.
@retval CF=0
No error, EAX set to STM_SUCCESS.
@retval CF=1
An error occurred, EAX holds relevant error value. See subfunction
descriptions below for details.
@note All other registers unmodified.
**/
#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)
///
/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL
///
typedef struct {
UINT32 SubFunctionIndex;
union {
struct {
UINT32 PageCount;
//
// number of elements is PageCount
//
UINT64 Pages[];
} LogBuffer;
//
// bitmap of EVENT_TYPE
//
UINT32 EventEnableBitmap;
} Data;
} STM_EVENT_LOG_MANAGEMENT_REQUEST;
/**
Defines values for the SubFunctionIndex field of
#STM_EVENT_LOG_MANAGEMENT_REQUEST
@{
**/
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6
/// @}
/**
Log Entry Header
**/
typedef struct {
UINT32 EventSerialNumber;
UINT16 Type;
UINT16 Lock :1;
UINT16 Valid :1;
UINT16 ReadByMle :1;
UINT16 Wrapped :1;
UINT16 Reserved :12;
} LOG_ENTRY_HEADER;
/**
Enum values for the Type field of #LOG_ENTRY_HEADER
**/
typedef enum {
EvtLogStarted,
EvtLogStopped,
EvtLogInvalidParameterDetected,
EvtHandledProtectionException,
///
/// unhandled protection exceptions result in reset & cannot be logged
///
EvtBiosAccessToUnclaimedResource,
EvtMleResourceProtectionGranted,
EvtMleResourceProtectionDenied,
EvtMleResourceUnprotect,
EvtMleResourceUnprotectError,
EvtMleDomainTypeDegraded,
///
/// add more here
///
EvtMleMax,
///
/// Not used
///
EvtInvalid = 0xFFFFFFFF,
} EVENT_TYPE;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STARTED;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STOPPED;
typedef struct {
UINT32 VmcallApiNumber;
} ENTRY_EVT_LOG_INVALID_PARAM;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_DENIED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
typedef struct {
UINT64 VmcsPhysPointer;
UINT8 ExpectedDomainType;
UINT8 DegradedDomainType;
} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
typedef union {
ENTRY_EVT_LOG_STARTED Started;
ENTRY_EVT_LOG_STOPPED Stopped;
ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;
ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;
ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;
ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;
ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;
} LOG_ENTRY_DATA;
typedef struct {
LOG_ENTRY_HEADER Hdr;
LOG_ENTRY_DATA Data;
} STM_LOG_ENTRY;
/**
Maximum STM Log Entry Size
**/
#define STM_LOG_ENTRY_SIZE 256
/**
STM Protection Exception Stack Frame Structures
**/
typedef struct {
UINT32 Rdi;
UINT32 Rsi;
UINT32 Rbp;
UINT32 Rdx;
UINT32 Rcx;
UINT32 Rbx;
UINT32 Rax;
UINT32 Cr3;
UINT32 Cr2;
UINT32 Cr0;
UINT32 VmcsExitInstructionInfo;
UINT32 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT32 ErrorCode;
UINT32 Rip;
UINT32 Cs;
UINT32 Rflags;
UINT32 Rsp;
UINT32 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
typedef struct {
UINT64 R15;
UINT64 R14;
UINT64 R13;
UINT64 R12;
UINT64 R11;
UINT64 R10;
UINT64 R9;
UINT64 R8;
UINT64 Rdi;
UINT64 Rsi;
UINT64 Rbp;
UINT64 Rdx;
UINT64 Rcx;
UINT64 Rbx;
UINT64 Rax;
UINT64 Cr8;
UINT64 Cr3;
UINT64 Cr2;
UINT64 Cr0;
UINT64 VmcsExitInstructionInfo;
UINT64 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT64 ErrorCode;
UINT64 Rip;
UINT64 Cs;
UINT64 Rflags;
UINT64 Rsp;
UINT64 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
typedef union {
STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;
} STM_PROTECTION_EXCEPTION_STACK_FRAME;
/**
Enum values for the ErrorCode field in
#STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and
#STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
**/
typedef enum {
TxtSmmPageViolation = 1,
TxtSmmMsrViolation,
TxtSmmRegisterViolation,
TxtSmmIoViolation,
TxtSmmPciViolation
} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
/**
TXT Pocessor SMM Descriptor (PSD) structures
**/
typedef struct {
UINT64 SpeRip;
UINT64 SpeRsp;
UINT16 SpeSs;
UINT16 PageViolationException:1;
UINT16 MsrViolationException:1;
UINT16 RegisterViolationException:1;
UINT16 IoViolationException:1;
UINT16 PciViolationException:1;
UINT16 Reserved1:11;
UINT32 Reserved2;
} STM_PROTECTION_EXCEPTION_HANDLER;
typedef struct {
UINT8 ExecutionDisableOutsideSmrr:1;
UINT8 Intel64Mode:1;
UINT8 Cr4Pae : 1;
UINT8 Cr4Pse : 1;
UINT8 Reserved1 : 4;
} STM_SMM_ENTRY_STATE;
typedef struct {
UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint
UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request
UINT8 Reserved2 : 6;
} STM_SMM_RESUME_STATE;
typedef struct {
UINT8 DomainType : 4; ///> STM input to BIOS on each SMI
UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI
UINT8 EptEnabled : 1;
UINT8 Reserved3 : 1;
} STM_SMM_STATE;
#define TXT_SMM_PSD_OFFSET 0xfb00
#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0
typedef struct {
UINT64 Signature;
UINT16 Size;
UINT8 SmmDescriptorVerMajor;
UINT8 SmmDescriptorVerMinor;
UINT32 LocalApicId;
STM_SMM_ENTRY_STATE SmmEntryState;
STM_SMM_RESUME_STATE SmmResumeState;
STM_SMM_STATE StmSmmState;
UINT8 Reserved4;
UINT16 SmmCs;
UINT16 SmmDs;
UINT16 SmmSs;
UINT16 SmmOtherSegment;
UINT16 SmmTr;
UINT16 Reserved5;
UINT64 SmmCr3;
UINT64 SmmStmSetupRip;
UINT64 SmmStmTeardownRip;
UINT64 SmmSmiHandlerRip;
UINT64 SmmSmiHandlerRsp;
UINT64 SmmGdtPtr;
UINT32 SmmGdtSize;
UINT32 RequiredStmSmmRevId;
STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;
UINT64 Reserved6;
UINT64 BiosHwResourceRequirementsPtr;
// extend area
UINT64 AcpiRsdp;
UINT8 PhysicalAddressBits;
} TXT_PROCESSOR_SMM_DESCRIPTOR;
#pragma pack ()
#include <Register/Intel/StmApi.h>
#endif

222
UefiCpuPkg/Include/Register/StmResourceDescriptor.h
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/** @file
STM Resource Descriptor
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_RESOURCE_DESCRIPTOR_H_
#define _STM_RESOURCE_DESCRIPTOR_H_
#pragma pack (1)
/**
STM Resource Descriptor Header
**/
typedef struct {
UINT32 RscType;
UINT16 Length;
UINT16 ReturnStatus:1;
UINT16 Reserved:14;
UINT16 IgnoreResource:1;
} STM_RSC_DESC_HEADER;
/**
Define values for the RscType field of #STM_RSC_DESC_HEADER
@{
**/
#define END_OF_RESOURCES 0
#define MEM_RANGE 1
#define IO_RANGE 2
#define MMIO_RANGE 3
#define MACHINE_SPECIFIC_REG 4
#define PCI_CFG_RANGE 5
#define TRAPPED_IO_RANGE 6
#define ALL_RESOURCES 7
#define REGISTER_VIOLATION 8
#define MAX_DESC_TYPE 8
/// @}
/**
STM Resource End Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT64 ResourceListContinuation;
} STM_RSC_END;
/**
STM Resource Memory Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT64 Base;
UINT64 Length;
UINT32 RWXAttributes:3;
UINT32 Reserved:29;
UINT32 Reserved_2;
} STM_RSC_MEM_DESC;
/**
Define values for the RWXAttributes field of #STM_RSC_MEM_DESC
@{
**/
#define STM_RSC_MEM_R 0x1
#define STM_RSC_MEM_W 0x2
#define STM_RSC_MEM_X 0x4
/// @}
/**
STM Resource I/O Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT16 Base;
UINT16 Length;
UINT32 Reserved;
} STM_RSC_IO_DESC;
/**
STM Resource MMIO Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT64 Base;
UINT64 Length;
UINT32 RWXAttributes:3;
UINT32 Reserved:29;
UINT32 Reserved_2;
} STM_RSC_MMIO_DESC;
/**
Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC
@{
**/
#define STM_RSC_MMIO_R 0x1
#define STM_RSC_MMIO_W 0x2
#define STM_RSC_MMIO_X 0x4
/// @}
/**
STM Resource MSR Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT32 MsrIndex;
UINT32 KernelModeProcessing:1;
UINT32 Reserved:31;
UINT64 ReadMask;
UINT64 WriteMask;
} STM_RSC_MSR_DESC;
/**
STM PCI Device Path node used for the PciDevicePath field of
#STM_RSC_PCI_CFG_DESC
**/
typedef struct {
///
/// Must be 1, indicating Hardware Device Path
///
UINT8 Type;
///
/// Must be 1, indicating PCI
///
UINT8 Subtype;
///
/// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6
///
UINT16 Length;
UINT8 PciFunction;
UINT8 PciDevice;
} STM_PCI_DEVICE_PATH_NODE;
/**
STM Resource PCI Configuration Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT16 RWAttributes:2;
UINT16 Reserved:14;
UINT16 Base;
UINT16 Length;
UINT8 OriginatingBusNumber;
UINT8 LastNodeIndex;
STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];
} STM_RSC_PCI_CFG_DESC;
/**
Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC
@{
**/
#define STM_RSC_PCI_CFG_R 0x1
#define STM_RSC_PCI_CFG_W 0x2
/// @}
/**
STM Resource Trapped I/O Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT16 Base;
UINT16 Length;
UINT16 In:1;
UINT16 Out:1;
UINT16 Api:1;
UINT16 Reserved1:13;
UINT16 Reserved2;
} STM_RSC_TRAPPED_IO_DESC;
/**
STM Resource All Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
} STM_RSC_ALL_RESOURCES_DESC;
/**
STM Register Volation Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
UINT32 RegisterType;
UINT32 Reserved;
UINT64 ReadMask;
UINT64 WriteMask;
} STM_REGISTER_VIOLATION_DESC;
/**
Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC
**/
typedef enum {
StmRegisterCr0,
StmRegisterCr2,
StmRegisterCr3,
StmRegisterCr4,
StmRegisterCr8,
StmRegisterMax,
} STM_REGISTER_VIOLATION_TYPE;
/**
Union of all STM resource types
**/
typedef union {
STM_RSC_DESC_HEADER Header;
STM_RSC_END End;
STM_RSC_MEM_DESC Mem;
STM_RSC_IO_DESC Io;
STM_RSC_MMIO_DESC Mmio;
STM_RSC_MSR_DESC Msr;
STM_RSC_PCI_CFG_DESC PciCfg;
STM_RSC_TRAPPED_IO_DESC TrappedIo;
STM_RSC_ALL_RESOURCES_DESC All;
STM_REGISTER_VIOLATION_DESC RegisterViolation;
} STM_RSC;
#pragma pack ()
#endif

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/** @file
STM Status Codes
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_STATUS_CODE_H_
#define _STM_STATUS_CODE_H_
/**
STM Status Codes
**/
typedef UINT32 STM_STATUS;
/**
Success code have BIT31 clear.
All error codes have BIT31 set.
STM errors have BIT16 set.
SMM errors have BIT17 set
Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set.
STM TXT.ERRORCODE codes have BIT30 set.
@{
**/
#define STM_SUCCESS 0x00000000
#define SMM_SUCCESS 0x00000000
#define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001)
#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002)
#define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003)
#define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004)
#define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005)
#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006)
#define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007)
#define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008)
#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED (BIT31 | BIT16 | 0x0009)
#define ERROR_STM_STOPPED (BIT31 | BIT16 | 0x000A)
#define ERROR_STM_BUFFER_TOO_SMALL (BIT31 | BIT16 | 0x000B)
#define ERROR_STM_INVALID_VMCS_DATABASE (BIT31 | BIT16 | 0x000C)
#define ERROR_STM_MALFORMED_RESOURCE_LIST (BIT31 | BIT16 | 0x000D)
#define ERROR_STM_INVALID_PAGECOUNT (BIT31 | BIT16 | 0x000E)
#define ERROR_STM_LOG_ALLOCATED (BIT31 | BIT16 | 0x000F)
#define ERROR_STM_LOG_NOT_ALLOCATED (BIT31 | BIT16 | 0x0010)
#define ERROR_STM_LOG_NOT_STOPPED (BIT31 | BIT16 | 0x0011)
#define ERROR_STM_LOG_NOT_STARTED (BIT31 | BIT16 | 0x0012)
#define ERROR_STM_RESERVED_BIT_SET (BIT31 | BIT16 | 0x0013)
#define ERROR_STM_NO_EVENTS_ENABLED (BIT31 | BIT16 | 0x0014)
#define ERROR_STM_OUT_OF_RESOURCES (BIT31 | BIT16 | 0x0015)
#define ERROR_STM_FUNCTION_NOT_SUPPORTED (BIT31 | BIT16 | 0x0016)
#define ERROR_STM_UNPROTECTABLE (BIT31 | BIT16 | 0x0017)
#define ERROR_STM_UNSUPPORTED_MSR_BIT (BIT31 | BIT16 | 0x0018)
#define ERROR_STM_UNSPECIFIED (BIT31 | BIT16 | 0xFFFF)
#define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
#define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
#define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
#define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
#define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
#define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
#define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
#define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
#define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
#define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
#define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
#define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
/// @}
#endif