Add power_on_s5 for DEEP_SX
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@ -87,8 +87,34 @@ void power_on_s5() {
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#if DEEP_SX
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// See Figure 12-18 in Whiskey Lake Platform Design Guide
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// TODO - signal timing graph
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// See Figure 12-24 in Whiskey Lake Platform Design Guide
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// TODO - rail timing graph
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// TODO: Must have SL_SUS# set high by PCH
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// Enable VCCPRIM_* planes - must be enabled prior to USB power in order to
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// avoid leakage
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gpio_set(&VA_EC_EN, true);
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tPCH06;
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// TODO
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// Enable VDD5
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gpio_set(&DD_ON, true);
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//TODO: Should SUS_ACK# be de-asserted here?
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tPCH03;
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// De-assert RSMRST#
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gpio_set(&EC_RSMRST_N, true);
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// Wait for PCH stability
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tPCH18;
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// Allow processor to control SUSB# and SUSC#
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gpio_set(&EC_EN, true);
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// Extra wait - TODO remove
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delay_ms(200);
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#else // DEEP_SX
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// See Figure 12-19 in Whiskey Lake Platform Design Guide
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// TODO - signal timing graph
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