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Update coreboot, ec, and configs

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This commit is contained in:
Jeremy Soller
2020-11-20 10:40:53 -07:00
parent 9bd8c7f462
commit 538861caf5
4 changed files with 8 additions and 8 deletions
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2
coreboot

Submodule coreboot updated: f786129104...5352c7b0b2

2
ec

Submodule ec updated: abc9b84368...c1b7777a8b

6
models/galp5/coreboot.config
View File

@@ -119,8 +119,8 @@ CONFIG_UART_FOR_CONSOLE=2
CONFIG_CONSOLE_POST=y
CONFIG_TPM_PIRQ=0x0
# CONFIG_POST_DEVICE is not set
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_VBOOT is not set
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfef00000
CONFIG_DCACHE_RAM_SIZE=0x80000
CONFIG_DCACHE_BSP_STACK_SIZE=0x40400
@@ -211,7 +211,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
# SoC
#
CONFIG_CPU_SPECIFIC_OPTIONS=y
CONFIG_X86_RESET_VECTOR=0xfffffff0
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_RAMBASE=0xe00000
@@ -245,8 +244,8 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0x7fff
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_UART_PCI_ADDR=0x0
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
CONFIG_UART_PCI_ADDR=0x0
CONFIG_SOC_INTEL_TIGERLAKE=y
CONFIG_CHIPSET_DEVICETREE="soc/intel/tigerlake/chipset.cb"
CONFIG_VBT_DATA_SIZE_KB=9
@@ -552,6 +551,7 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
CONFIG_PCIEXP_HOTPLUG=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G is not set

6
models/lemp10/coreboot.config
View File

@@ -119,8 +119,8 @@ CONFIG_UART_FOR_CONSOLE=2
CONFIG_CONSOLE_POST=y
CONFIG_TPM_PIRQ=0x0
# CONFIG_POST_DEVICE is not set
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_VBOOT is not set
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfef00000
CONFIG_DCACHE_RAM_SIZE=0x80000
CONFIG_DCACHE_BSP_STACK_SIZE=0x40400
@@ -211,7 +211,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
# SoC
#
CONFIG_CPU_SPECIFIC_OPTIONS=y
CONFIG_X86_RESET_VECTOR=0xfffffff0
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_RAMBASE=0xe00000
@@ -245,8 +244,8 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0x7fff
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_UART_PCI_ADDR=0x0
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
CONFIG_UART_PCI_ADDR=0x0
CONFIG_SOC_INTEL_TIGERLAKE=y
CONFIG_CHIPSET_DEVICETREE="soc/intel/tigerlake/chipset.cb"
CONFIG_VBT_DATA_SIZE_KB=9
@@ -552,6 +551,7 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
CONFIG_PCIEXP_HOTPLUG=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G is not set