coreboot: Fix OZ711LV2 LTR for galp5 3050 variant

Fix programming the LTR so that CPU can reach C-states deeper than C2. Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-10-12 11:58:39 -06:00
parent c1dafbbfad
commit 5d997d1c41
2 changed files with 2 additions and 1 deletions
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -9,6 +9,7 @@ features apply to your model and firmware version, see the
 ## unreleased

 - tgl-u: Fixed potential EC lock up during opportunistic suspend
+- galp5: Fixed CPU not going lower than C2 due to card reader LTR

 ## 2023-09-19

--- a/2
+++ b/2