coreboot: Fix USB2 on USB-C for gaze18, serw13

Signed-off-by: Tim Crawford <tcrawford@system76.com>

.gitmodules

@@ -1,15 +1,35 @@
 [submodule "edk2"]
 	path = edk2
-	url = ../system76-edk2.git
+	url = https://github.com/system76/edk2.git
 	branch = system76
 [submodule "coreboot"]
 	path = coreboot
-	url = ../system76-coreboot.git
+	url = https://github.com/system76/coreboot.git
+	branch = system76
+[submodule "edk2-platforms"]
+	path = edk2-platforms
+	url = https://github.com/system76/edk2-platforms.git
 	branch = system76
 [submodule "tools/UEFITool"]
 	path = tools/UEFITool
 	url = https://github.com/LongSoft/UEFITool.git
 	branch = new_engine
+[submodule "libs/intelflash"]
+	path = libs/intelflash
+	url = https://gitlab.redox-os.org/redox-os/intelflash.git
+	branch = master
+[submodule "libs/uefi"]
+	path = libs/uefi
+	url = https://gitlab.redox-os.org/redox-os/uefi.git
+	branch = master
+[submodule "libs/coreboot-table"]
+	path = libs/coreboot-table
+	url = https://gitlab.redox-os.org/redox-os/coreboot-table.git
+	branch = master
+[submodule "libs/intel-spi"]
+	path = libs/intel-spi
+	url = https://github.com/system76/intel-spi.git
+	branch = master
 [submodule "tools/coreboot-collector"]
 	path = tools/coreboot-collector
 	url = https://github.com/system76/coreboot-collector.git
@@ -26,23 +46,35 @@
 	path = tools/MEAnalyzer
 	url = https://github.com/platomav/MEAnalyzer.git
 	branch = master
+[submodule "libs/coreboot-fs"]
+	path = libs/coreboot-fs
+	url = https://gitlab.redox-os.org/redox-os/coreboot-fs.git
+	branch = master
 [submodule "apps/gop-policy"]
 	path = apps/gop-policy
 	url = https://github.com/system76/gop-policy.git
 	branch = master
+[submodule "edk2-non-osi"]
+	path = edk2-non-osi
+	url = https://github.com/tianocore/edk2-non-osi.git
+	branch = devel-MinPlatform
+[submodule "FSP"]
+	path = FSP
+	url = https://github.com/IntelFsp/FSP.git
+	branch = master
+[submodule "apps/firmware-smmstore"]
+	path = apps/firmware-smmstore
+	url = https://github.com/system76/firmware-smmstore.git
+	branch = master
 [submodule "tools/ipxe"]
 	path = tools/ipxe
 	url = https://github.com/ipxe/ipxe.git
 	branch = master
 [submodule "ec"]
 	path = ec
-	url = ../system76-embedded-controller.git
-	branch = main
+	url = https://github.com/system76/ec.git
+	branch = master
 [submodule "tools/apobtool"]
 	path = tools/apobtool
 	url = https://github.com/system76/apobtool.git
 	branch = master
-[submodule "tools/intel-spi"]
-	path = tools/intel-spi
-	url = https://github.com/system76/intel-spi.git
-	branch = master

CHANGELOG.md

@@ -1,209 +1,13 @@
-# System76 Open Firmware Changelog
+# Changelog
 
 Changes are identified by the date of the released firmware including them. If
 you are running System76 Open Firmware, opening the boot menu will show this
-date followed by an underscore and a short git revision. To see if specific
-features apply to your model and firmware version, see the
-[feature matrix](./docs/features.md).
+date followed by an underscore and a short git revision.
 
 ## unreleased
 
-- whl-u: Updated CSME to 12.0.95.2489v2 (12.0.94.2428)
-- cfl: Updated CSME to 12.0.94.2380v9 (12.0.94.2428)
-- mtl: Fixed detection of USB3 hubs in Type-C ports
-- darp10: Fixed reporting of the second fan
-- darp10: Fixed using USB3 devices at USB3 speeds in all ports
-- darp10: Updated fan tables
-- Fixed IT8587E hang when reading keyboard matrix
-- Changed fans to use highest reported temperature to calculate duty instead
-  of using the highest calculated duty across all fans
-- bonw15-b: Added initial release of open firmware with System76 EC
-- Changed fan mechanism from calculated interpolation/smoothing to a fixed
-  step to limit rapid changes in duty over short periods
-- Updated coreboot to 24.08
-
-## 2024-07-08
-
-- cml-h: Updated CSME to 14.1.74.2355v6 (14.1.72.2287)
-- cml-u: Updated CSME to 14.1.74.2355v6 (14.1.74.2373)
-- Reverted unlock prompt change to restore intended behavior
-
-## 2024-07-01
-
-- mtl: Updated FSP to D.0.A8.20
-- adl: Fixed USB 3.0 hubs in Type-C ports
-- rpl: Fixed USB 3.0 hubs in Type-C ports
-- Fixed touchpad in PS/2 mode
-- tgl: Updated CSME to 15.0.49.2573
-- Fixed unlock prompt showing when system is already unlocked
-- lemp13-b: Added support for units with 5600 MT/s soldered RAM
-
-## 2024-05-28
-
-- tgl: Updated Intel GOP driver to 17.0.1077
-- tgl: Updated VBT to 250
-- Updated Rust toolchain to nightly-2024-05-11
-
-## 2024-05-17
-
-- lemp13-b: Added initial release of open firmware with System76 EC
-
-## 2024-05-07
-
-- darp10: Added initial release of open firmware with System76 EC
-- darp10-b: Added initial release of open firmware with System76 EC
-
-## 2024-04-29
-
-- Fixed CMOS options not working due to invalid checksum
-
-## 2024-03-25
-
-- lemp13: Added initial release of open firmware with System76 EC
-
-## 2024-03-21
-
-- oryp12: Added initial release of open firmware with System76 EC
-
-## 2024-03-11
-
-- Updated coreboot to 24.02
-- adl-p: Updated FSP to C.1.75.10
-- adl-s: Updated FSP to C.0.75.10
-- adl: Updated microcode to revision 0x430
-- rpl-p: Updated FSP to C.1.BD.40
-- rpl-s: Updated FSP to C.0.BD.40
-- rpl: Updated microcode to revision 0x411c
-- tgl: Updated FSP to A.0.7E.70
-- tgl-u: Updated microcode to revision 0xb4
-- tgl-h: Updated microcode to revision 0x4e
-- adl: Fixed PCIe 4.0 drives in PCIe 3.0 slot failing to initialize on resume
-- rpl: Fixed PCIe 4.0 drives in PCIe 3.0 slot failing to initialize on resume
-- rpl: Fixed TCSS ACPI access
-- adl: Fixed `SLP_S0#` counter frequency
-- rpl: Fixed `SLP_S0#` counter frequency
-- tgl: Fixed TBT ACPI
-- Fixed RTC being reset on boot during February 29th
-- addw4: Added initial release of open firmware with System76 EC
-
-## 2024-01-18
-
-- darp9: Added SSD RTD3 configs to fix suspend with some drives
-
-## 2024-01-10
-
-- darp8: Fixed suspend issue on new boards by switching to S0ix by default
-- darp9: Fixed suspend issue on new boards by switching to S0ix by default
-
-## 2023-10-20
-
-- tgl-u: Fixed CPU not going lower than C2 due to card reader LTR
-- bonw15: Fixed speaker audio cutting in/out
-- oryp11: Fixed speaker audio cutting in/out
-
-## 2023-10-13
-
-- tgl-u: Fixed potential EC lock up during opportunistic suspend
-- galp5: Fixed CPU not going lower than C2 due to card reader LTR
-
-## 2023-09-19
-
-- rpl-hx: Added support for 5600 MHz RAM
-
-## 2023-09-08
-
-- adl: Updated CSME to 16.1.25.2124
-- adl,rpl: Fixed SMMSTORE init sometimes failing
-- Increased key debounce from 5ms to 10ms
-
-## 2023-08-23
-
-- rpl: Fixed RPL-S GPIO driver on Windows
-
-## 2023-08-18
-
-- cml-u: Fixed boot failing at FSP-S
-- Added KBC reset on CPU reset to prevent keyboard from being locked
-- Enabled power switch Watch Dog Timer with a timeout of 10 seconds
-- Fixed detecting if PECI is available on eSPI systems using S0ix
-- Added support for a FnLock key
-- tgl: Fixed Bluetooth performance by enabling audio offload
-- gaze16: Fixed CPU not going lower than C2 due to card reader LTR
-- adl: Fixed CPU not going lower than C2 due to card reader LTR
-- rpl: Fixed CPU not going lower than C2 due to card reader LTR
-- Changed battery charge start threshold to 90%
-- Changed charger to disable when battery is full
-
-## 2023-07-19
-
-- bonw14: Fixed loading CPU microcode
-- rpl-hx: Fixed setting PL1 and PL2 power limits
-- rpl-hx: Fixed LPM substates
-- gaze17: Removed invalid RTD3 configs
-- oryp10: Removed invalid RTD3 configs
-- galp8: Removed SATA RTD3 to fix drives being lost on suspend
-- lemp11: Removed SATA RTD3 to fix drives being lost on suspend
-- Reduced key debounce from 15ms to 5ms
-- galp6: Fixed fan tachometer GPIOs
-- lemp9: Fixed fan tachometer GPIOs
-- lemp10: Fixed fan tachometer GPIOs
-- lemp11: Fixed fan tachometer GPIOs
-
-## 2023-07-10
-
-- Updated Secure Boot DBX to version 371 (2023-05-09)
-- bonw15: Added initial release of open firmware with System76 EC
-- oryp11: Changed adapter Rsense to 10 milliohms
-- serw13: Changed adapter Rsense to 10 milliohms
-
-## 2023-06-22
-
-- addw3: Enabled support for 5200 MT/s memory
-- serw13: Enabled support for 5200 MT/s memory
-- oryp11: Added initial release of open firmware with System76 EC
-- rpl: Enabled TPM read delay to fix occasional failures with Infineon chips
-- Changed TPM behavior to perform TPM Restart if TPM Resume fails
-
-## 2023-06-08
-
-- darp9: Added initial release of open firmware with System76 EC
-- Added detection of RGB keyboards at runtime
-- oryp9: Enabled firmware security
-- oryp9: Enabled NVIDIA Dynamic Boost
-- oryp10: Enabled firmware security
-- oryp10: Enabled NVIDIA Dynamic Boost
-- Invalidated CMOS checksum after flashing to ensure default options are used
-
-## 2023-05-25
-
-- Set PL4 based on AC state for all boards
-- Increased PL4 on battery to 45W for dGPU boards
-- galp6: Enabled firmware security
-- galp7: Added initial release of open firmware with System76 EC
-
-## 2023-05-17
-
-- serw13: Added initial release of open firmware with System76 EC
-- Fixed Windows BSoD on RPL-HX
-
-## 2023-05-16
-
-- lemp12: Added initial release of open firmware with System76 EC
-
-## 2023-04-28
-
-- addw3: Added initial release of open firmware with System76 EC
-
-## 2023-03-22
-
-- Updated coreboot to upstream commit decbf7b4d975
 - Enabled support for Secure Boot
 - Enabled minimal UI for enforcing Secure Boot and resetting keys
-- Added firmware locking support
-- Enabled S3 suspend on everything but TGL-U
-- Disabled ME by default on everything but TGL-U
-- Added support for NVIDIA Dynamic Boost
-- gaze18: Added initial release of open firmware with System76 EC
 
 ## 2022-11-21
 

Jenkinsfile

@@ -1,134 +0,0 @@
-#!/usr/bin/env groovy
-
-// Required plugins:
-// - Jenkins Core
-// - AnsiColor (https://plugins.jenkins.io/ansicolor/)
-// - Git (https://plugins.jenkins.io/git/)
-// - Pipeline (https://plugins.jenkins.io/workflow-aggregator/)
-// - Slack Notification (https://plugins.jenkins.io/slack/)
-
-def all_models = 'addw2 addw3 addw4 bonw14 bonw15 darp5 darp6 darp7 darp8 darp9 darp10 darp10-b galp3-c galp4 galp5 galp6 galp7 gaze15 gaze16-3050 gaze16-3060 gaze16-3060-b gaze16-3050 gaze16-3060-b gaze17-3050 gaze17-3060-b gaze18 lemp9 lemp10 lemp11 lemp12 lemp13 lemp13-b oryp5 oryp6 oryp7 oryp8 oryp9 oryp10 oryp11 oryp12 serw13'
-
-void setBuildStatus(String state, String message) {
-    // FIXME: https://www.jenkins.io/doc/book/pipeline/jenkinsfile/#string-interpolation
-    sh """
-    curl \
-      -X POST \
-      -H \'Accept: application/vnd.github+json\' \
-      -H \'Authorization: Bearer ${GITHUB_TOKEN}\' \
-      -H \'X-GitHub-Api-Version: 2022-11-28\' \
-      https://api.github.com/repos/system76/firmware-open/statuses/${GIT_COMMIT} \
-      -d \'{\"state\": \"${state}\", \"target_url\": \"${BUILD_URL}\", \"description\": \"${message}\"}\'
-    """
-}
-
-pipeline {
-    agent {
-        label 'warp.pop-os.org'
-    }
-
-    environment {
-        GITHUB_TOKEN = credentials('github-commit-status')
-    }
-
-    options {
-        buildDiscarder(logRotator(numToKeepStr: '16', artifactNumToKeepStr: '1'))
-        disableConcurrentBuilds()
-        timeout(time: 1, unit: 'HOURS')
-        timestamps()
-        ansiColor('xterm')
-    }
-
-    parameters {
-        string(name: 'MODELS', defaultValue: "$all_models", description: 'Space separated list of models to build', trim: true)
-        string(name: 'SOURCE_BRANCH', defaultValue: 'master', description: 'Git branch or revision to build', trim: true)
-    }
-
-    triggers {
-        pollSCM('')
-    }
-
-    stages {
-        stage('Prepare') {
-            steps {
-                setBuildStatus("pending", "Pending")
-                slackSend(color: "good", message: "${env.JOB_NAME} - #${env.BUILD_ID} started (<${env.BUILD_URL}|Open>)")
-
-                sh """#!/bin/bash
-                    # Update submodule URLs because of coreboot
-                    git submodule sync --recursive
-                """
-
-                // https://www.jenkins.io/doc/pipeline/steps/params/scmgit/
-                checkout scmGit(
-                    branches: [[name: '${SOURCE_BRANCH}']],
-                    extensions: [
-                        lfs(),
-                        pruneStaleBranch(),
-                        pruneTags(true),
-                        submodule(
-                            parentCredentials: true,
-                            recursiveSubmodules: true,
-                            reference: ''
-                        ),
-                    ],
-                    userRemoteConfigs: [[url: 'https://github.com/system76/firmware-open.git']]
-                )
-
-                sh """#!/bin/bash
-                    # Install dependencies
-                    #./scripts/install-deps.sh
-                    . "${HOME}/.cargo/env"
-
-                    # Reset
-                    git submodule update --init --recursive --checkout
-                    git reset --hard
-                    git submodule foreach --recursive git reset --hard
-
-                    # Clean
-                    git clean -dffx
-                    git submodule foreach --recursive git clean -dff
-
-                    # EDK2 builds fail if file paths in INFs change from what's in the build cache
-                    pushd edk2; git clean -dffx; popd
-                """
-            }
-        }
-        stage('Build') {
-            steps {
-                // The workspace is reused, so must build models sequentially.
-                script {
-                    def list = params.MODELS.tokenize()
-                    list.each { model ->
-                        stage(model) {
-                            sh """#!/bin/bash
-                                . "${HOME}/.cargo/env"
-                                # WORSKSPACE is set by Jenkins, but EDK2 uses it
-                                env --unset=WORKSPACE \
-                                ./scripts/build.sh "${model}"
-                            """
-                        }
-                    }
-                }
-            }
-        }
-    }
-
-    post {
-        always {
-            archiveArtifacts artifacts: 'build/*/*', allowEmptyArchive: true
-        }
-        success {
-            setBuildStatus("success", "Successful")
-            slackSend(color: "good", message: "${env.JOB_NAME} - #${env.BUILD_ID} successful after ${currentBuild.durationString} (<${env.BUILD_URL}|Open>)")
-        }
-        failure {
-            setBuildStatus("failure", "Failed")
-            slackSend(color: "danger", message: "${env.JOB_NAME} - #${env.BUILD_ID} failed after ${currentBuild.durationString} (<${env.BUILD_URL}|Open>)")
-        }
-        aborted {
-            setBuildStatus("failure", "Failed")
-            slackSend(color: "warning", message: "${env.JOB_NAME} - #${env.BUILD_ID} aborted after ${currentBuild.durationString} (<${env.BUILD_URL}|Open>)")
-        }
-    }
-}

LICENSE.md

@@ -33,7 +33,7 @@ The license for the embedded controller firmware depends on the binary used.
 
 #### Intel binaries
 
-Intel provides binaries under a redistributable license, which may be
+Intel provides biniaries under a redistributable license, which may be
 different per binary.
 
 - `me.rom`: Intel CSME

README.md

@@ -3,10 +3,81 @@
 An open source distribution of firmware utilizing coreboot, EDK2, and System76
 firmware applications.
 
-## Resources
+## Supported models
 
-- [Project site](https://github.com/system76/firmware-open)
-- [Documentation](./docs/index.md)
-- [Issue tracker](https://github.com/system76/firmware-open/issues/)
-- [Changelog](./CHANGELOG.md)
-- [Legal information](./LICENSE.md)
+These models are supported and will receive updates through the firmware
+manager:
+
+- addw2
+- bonw14
+- darp6
+- darp7
+- darp8
+- galp4
+- galp5
+- galp6
+- gaze15
+- gaze16-3050
+- gaze16-3060
+- gaze16-3060-b
+- gaze17-3050
+- gaze17-3060-b
+- lemp9
+- lemp10
+- lemp11
+- oryp6
+- oryp7
+- oryp8
+- oryp9
+- oryp10
+
+Other models may be in development or available without support, and can be
+seen in the `models/` directory.
+
+If the device becomes bricked it will require restoring the current firmware
+using an external programmer. See [flashing](./docs/flashing.md) for details.
+
+### Schematics
+
+System76 customers may request board schematics for their system by sending an
+email to firmware@system76.com with the subject line  "Schematics for _model_",
+where _model_ is one of the supported models listed above. Please include the
+serial number of your system for verification.
+
+You may not share these without explicit permission from System76.
+
+## Changelog
+
+For a list of important changes please see the [changelog](./CHANGELOG.md).
+
+## Building
+
+Dependencies can be installed with the provided script.
+
+```
+./scripts/deps.sh
+```
+
+If rustup was installed for the first time, it will be required to source the
+environment file it installed to use the correct Rust toolchain.
+
+```
+source ~/.cargo/env
+```
+
+A script is provided to build the firmware. The available targets for building
+are the model folders in `models/`. For example, to build for QEMU:
+
+```
+./scripts/build.sh qemu
+```
+
+Once built, the firmware must be flashed to use. Several scripts are available
+to flash the new firmware, depending on how it is going to be written.
+
+- `scripts/qemu.sh`: [Run the firmware in QEMU](./docs/debugging.md#using-qemu) (specific to the QEMU model)
+- `scripts/flash.sh`: Flash using the internal flasher
+- `scripts/ch341a-flash.sh`: Flash using a CH341A programmer
+- `scripts/spipi-flash.sh`: Flash using a Raspberry Pi
+
+See [Flashing firmware](./docs/flashing.md) for more details.

apps/README.md

@@ -3,5 +3,6 @@
 ## Contents
 
 - [firmware-setup](https://github.com/system76/firmware-setup.git) - System76 Firmware Setup
+- [firmware-smmstore](https://github.com/system76/firmware-smmstore.git) - System76 Firmware SMMSTORE
 - [firmware-update](https://github.com/system76/firmware-update.git) - System76 Firmware Update
 - [gop-policy](https://github.com/system76/gop-policy.git) - System76 Platform GOP Policy

docker/Dockerfile

@@ -1,67 +0,0 @@
-FROM ubuntu:20.04
-
-# Install most dependencies
-USER root
-ARG TZ="America/New_York"
-ARG DEBIAN_FRONTEND=noninteractive
-RUN apt-get update && \
-    apt-get upgrade -y && \
-    apt-get install -y --no-install-recommends \
-    adduser \
-    sudo \
-    tzdata \
-    build-essential \
-    ccache \
-    cmake \
-    curl \
-    dosfstools \
-    flashrom \
-    git-lfs \
-    libncurses-dev \
-    libssl-dev \
-    libudev-dev \
-    mtools \
-    parted \
-    pkgconf \
-    python-is-python3 \
-    python3-distutils \
-    uuid-dev \
-    zlib1g-dev \
-    bison \
-    bzip2 \
-    ca-certificates \
-    flex \
-    g++ \
-    gcc \
-    gnat \
-    libnss3-dev \
-    patch \
-    tar \
-    xz-utils \
-    avr-libc \
-    avrdude \
-    clang-format \
-    gcc-avr \
-    libc-dev \
-    libhidapi-dev \
-    libudev-dev \
-    sdcc \
-    shellcheck \
-    xxd
-
-# Create non-root user with disabled password and sudo privileges
-ARG USER=docker
-RUN adduser --disabled-password --gecos '' ${USER}
-RUN adduser ${USER} sudo
-RUN echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers
-
-# Enter build directory in user's home
-USER ${USER}
-ARG BUILD_DIR=/home/${USER}/firmware-open
-WORKDIR ${BUILD_DIR}
-
-# Set git configuration (required by some scripts)
-ARG GIT_NAME="Docker User"
-ARG GIT_EMAIL="docker@gmail.com"
-RUN git config --global user.name "${GIT_NAME}"
-RUN git config --global user.email "${GIT_EMAIL}"

docs/README.md

@@ -0,0 +1 @@
+# System76 Open Firmware Documentation

docs/SUMMARY.md

@@ -1,11 +0,0 @@
-# Summary
-
-- [Index](./index.md)
-- [Firmware features](./features.md)
-- [Building firmware](./building.md)
-- [Flashing firmware](./flashing.md)
-- [Debugging](./debugging.md)
-- [Adding a new board](./adding-a-new-board.md)
-- [Intel CSME](./intel-me.md)
-- [UEFI](./uefi.md)
-- [Schematics](./schematics.md)

docs/adding-a-new-board.md

@@ -71,10 +71,16 @@ Other things that should be dumped before porting/flashing are:
 
 To port coreboot to a new board, see the coreboot documentation.
 
-Add a `coreboot.config` file to the model directory. This can be copied from
-another similar board as a reference, just updating the name. Typically, the
-only special cases that need to be handled are when an FSP or microcode is
-used that are not part of coreboot.
+Once coreboot is ported, add its configuration.
+
+```
+cp coreboot/.config models/<model>/coreboot.config
+```
+
+### devicetree
+
+`generate.sh` does not create `devicetree.cb`. Some values for this file can be
+produced using the `devicetree.py` script.
 
 ### Smart amp
 

docs/book.toml

@@ -1,18 +0,0 @@
-[book]
-title = "System76 Open Firmware"
-description = "System76 Open Firmware documentation"
-language = "en"
-src = "."
-
-[build]
-build-dir = "../build/docs"
-create-missing = false
-
-[output.html]
-default-theme = "rust"
-preferred-dark-theme = "coal"
-no-section-label = true
-git-repository-url = "https://github.com/system76/firmware-open"
-
-[output.html.print]
-enable = false

docs/building.md

@@ -1,31 +0,0 @@
-# Building
-
-Dependencies can be installed with the provided script.
-
-```
-./scripts/install-deps.sh
-```
-
-If rustup was installed for the first time, it will be required to source the
-environment file it installed to use the correct Rust toolchain.
-
-```
-. ~/.cargo/env
-```
-
-A script is provided to build the firmware. The available targets for building
-are the model folders in `models/`. For example, to build for QEMU:
-
-```
-./scripts/build.sh qemu
-```
-
-Once built, the firmware must be flashed to use. Several scripts are available
-to flash the new firmware, depending on how it is going to be written.
-
-- `scripts/qemu.sh`: [Run the firmware in QEMU](./debugging.md#using-qemu) (specific to the QEMU model)
-- `scripts/flash.sh`: Flash using firmware-update
-- `scripts/ch341a-flash.sh`: Flash using a CH341A programmer
-- `scripts/spipi-flash.sh`: Flash using a Raspberry Pi
-
-See [Flashing firmware](./flashing.md) for more details.

docs/debugging.md

@@ -52,8 +52,8 @@ A couple of methods can be used to get debug logging.
 
 This method requires no soldering of board components.
 
-See [Debugging the EC firmware](https://github.com/system76/ec/blob/master/docs/debugging.md)
-for details on setting up EC debugging over the parallel port.
+See [Debugging the EC firmware](./ec/doc/debugging.md) for details on setting
+up EC debugging over the parallel port.
 
 cbmem output can be passed through the EC by enabling the driver in coreboot.
 Uncomment the config in `models/<model>/coreboot.config` to enable logging the

docs/features.md

@@ -1,190 +0,0 @@
-# System76 Open Firmware Feature Matrix
-
-This lists important features provided by System76 Open Firmware. Your system
-must be updated to at least the firmware version specified in the following
-[platform tables](#platforms) to include all specified [features](#features).
-To see the changes in specific firmware versions, see the
-[changelog](./../CHANGELOG.md).
-
-## Platforms
-
-- [Intel 13th Gen (Raptor Lake)](#intel-13th-gen-raptor-lake)
-- [Intel 12th Gen (Alder Lake)](#intel-12th-gen-alder-lake)
-- [Intel 11th Gen (Tiger Lake)](#intel-11th-gen-tiger-lake)
-- [Intel 10th Gen (Comet Lake)](#intel-10th-gen-comet-lake)
-
-### Intel 13th Gen (Raptor Lake)
-
-This generation universally supports these features with up-to-date firmware:
-
-- [Intel VT-x](#intel-vt-x)
-- [Intel VT-d](#intel-vt-d)
-- [Disabled Management Engine](#disabled-management-engine)
-- [TPM 2.0 Support](#tpm-20-support)
-- [Battery Charging Thresholds](#battery-charging-thresholds)
-- [Keyboard Customization](#keyboard-customization)
-- [Measured Boot](#measured-boot)
-- [Firmware Security System](#firmware-security-system)
-- [Secure Boot Support](#secure-boot-support)
-
-| System76 Model (Version) | Firmware Version    | SoC    | [Windows 11 Support](#windows-11-support) | [NVIDIA Dynamic Boost](#nvidia-dynamic-boost) |
-|--------------------------|---------------------|--------|-----|-----|
-| Adder WS (addw3)         | 2023-05-17\_9560b2e | RPL-HX | ✔   | ✔   |
-| Bonobo WS (bonw15)       | 2023-07-10\_0e4a64a | RPL-HX | ✔   | ✔   |
-| Darter Pro (darp9)       | 2023-06-08\_a8590a5 | RPL-P  | ✔   | N/A |
-| Galago Pro (galp7)       | 2023-05-25\_5608a8d | RPL-H  | ✔   | N/A |
-| Gazelle (gaze18)         | 2023-03-22\_799ed79 | RPL-H  | ✔   | ✔   |
-| Lemur Pro (lemp12)       | 2023-05-16\_e9b9ea8 | RPL-U  | ✔   | N/A |
-| Oryx Pro (oryp11)        | 2023-06-22\_e5c3632 | RPL-H  | ✔   | ✔   |
-| Serval WS (serw13)       | 2023-05-17\_9560b2e | RPL-HX | ✔   | ✔   |
-
-### Intel 12th Gen (Alder Lake)
-
-This generation universally supports these features with up-to-date firmware:
-
-- [Intel VT-x](#intel-vt-x)
-- [Intel VT-d](#intel-vt-d)
-- [TPM 2.0 Support](#tpm-20-support)
-- [Battery Charging Thresholds](#battery-charging-thresholds)
-- [Keyboard Customization](#keyboard-customization)
-- [Measured Boot](#measured-boot)
-
-| System76 Model (Version) | Firmware Version    | SoC    |
-|--------------------------|---------------------|--------|
-| Darter Pro (darp8)       | 2022-11-21\_b337ac6 | ADL-P  |
-| Galago Pro (galp6)       | 2022-11-21\_b337ac6 | ADL-P  |
-| Gazelle (gaze17-3050)    | 2022-11-21\_b337ac6 | ADL-H  |
-| Gazelle (gaze17-3060-b)  | 2022-06-07\_090f9e0 | ADL-H  |
-| Lemur Pro (lemp11)       | 2022-11-21\_b337ac6 | ADL-U  |
-| Oryx Pro (oryp9)         | 2022-07-20\_ae6aa72 | ADL-H  |
-| Oryx Pro (oryp10)        | 2022-09-26\_aa797d2 | ADL-H  |
-
-### Intel 11th Gen (Tiger Lake)
-
-This generation universally supports these features with up-to-date firmware:
-
-- [Intel VT-x](#intel-vt-x)
-- [Intel VT-d](#intel-vt-d)
-- [TPM 2.0 Support](#tpm-20-support)
-- [Battery Charging Thresholds](#battery-charging-thresholds)
-- [Keyboard Customization](#keyboard-customization)
-
-| System76 Model (Version) | Firmware Version    | SoC    | [Measured Boot](#measured-boot) |
-|--------------------------|---------------------|--------|----|
-| Darter Pro (darp7)       | 2022-11-21\_b337ac6 | TGL-U  | ✔️  |
-| Galago Pro (galp5)       | 2022-11-21\_b337ac6 | TGL-U  | ✔️  |
-| Gazelle (gaze16-3050)    | 2022-11-21\_b337ac6 | TGL-H  | ✔️  |
-| Gazelle (gaze16-3060)    | 2021-09-30\_14b8a6e | TGL-H  | ❌ |
-| Gazelle (gaze16-3060-b)  | 2021-11-01\_fb9d759 | TGL-H  | ❌ |
-| Lemur Pro (lemp10)       | 2022-11-21\_b337ac6 | TGL-U  | ✔️  |
-| Oryx Pro (oryp8)         | 2022-10-14\_4136ef8 | TGL-H  | ✔️  |
-
-### Intel 10th Gen (Comet Lake)
-
-This generation universally supports these features with up-to-date firmware:
-
-- [Intel VT-x](#intel-vt-x)
-- [Intel VT-d](#intel-vt-d)
-- [Disabled Management Engine](#disabled-management-engine)
-- [TPM 2.0 Support](#tpm-20-support)
-- [Battery Charging Thresholds](#battery-charging-thresholds)
-- [Keyboard Customization](#keyboard-customization)
-
-| System76 Model (Version) | Firmware Version    | SoC    | [Measured Boot](#measured-boot) |
-|--------------------------|---------------------|--------|----|
-| Adder WS (addw2)         | 2022-11-21\_b337ac6 | CML-H  | ✔️  |
-| Bonobo WS (bonw14)       | 2021-07-20\_93c2809 | CML-S  | ❌ |
-| Darter Pro (darp6)       | 2021-07-20\_93c2809 | CML-U  | ❌ |
-| Gazelle (gaze15)         | 2022-11-21\_b337ac6 | CML-H  | ✔️  |
-| Lemur Pro (lemp9)        | 2021-07-20\_93c2809 | CML-U  | ❌ |
-| Oryx Pro (oryp6)         | 2021-07-20\_93c2809 | CML-H  | ❌ |
-| Oryx Pro (oryp7)         | 2022-11-21\_b337ac6 | CML-H  | ✔️  |
-
-## Features
-
-### Intel VT-x
-
-Intel Virtualization Technology is enabled, which provides support for high
-performance virtual machines.
-
-### Intel VT-d
-
-Intel Virtualization Technology for Directed I/O is enabled, which provides
-support for passing PCIe devices to virtual machines, and for protecting against
-PCIe device craches and DMA attacks.
-
-### Disabled Management Engine
-
-The Intel Management Engine is disabled at runtime to improve security.
-
-### TPM 2.0 Support
-
-**Introduced in firmware version 2020-08-13.**
-
-A discrete TPM 2.0 is available for use.
-
-### Battery Charging Thresholds
-
-**Introduced in firmware version 2020-10-19.**
-
-Battery charging thresholds extend the life of the battery by reducing the
-maximum charge that the battery is charged to, as well as the minimum charge
-when charging the battery begins.
-
-### Keyboard Customization
-
-**Introduced in firmware version 2020-10-19.**
-
-Keyboard customization allows the keyboard layout to be modified at runtime
-using the
-[System76 Keyboard Configurator](https://github.com/pop-os/keyboard-configurator/).
-
-### Measured Boot
-
-**Introduced in firmware version 2022-01-06.**
-
-Measured boot uses the TPM to maintain hashes of all binaries used in the boot
-process. This allows for detecting changes to the firmware, which can be used
-by a system such as TPM2-TOTP or BitLocker to improve security.
-
-### Firmware Security System
-
-**Introduced in firmware version 2023-04-03.**
-
-The firmware security system ensures both SoC and EC firmware is read-only at
-runtime. Unlocking the firmware requires the system to reboot and physical
-presence is required. The user must enter in a secure, randomly generated number
-before the system can boot any third-party code while unlocked. Both EC firmware
-and system firmware are locked on any boots where the prompt is not shown. For
-screenshots showing this prompt, see the pull request here:
-https://github.com/system76/firmware-setup/pull/18
-
-### Secure Boot Support
-
-**Introduced in firmware version 2023-04-03.**
-
-A new firmware setup menu allows enabling and disabling Secure Boot and also
-allows for entering setup mode for custom key enrollment. Work is being done in
-Pop!\_OS to enable the use of custom secure boot keys, in addition to adding
-TPM2-TOTP authentication of the firmware boot path. For screenshots showing the
-new menus, see the pull request here:
-https://github.com/system76/edk2/pull/38
-
-### Windows 11 Support
-
-**Introduced in firmware version 2023-04-03.**
-
-Windows 11 requires [TPM 2.0 Support](#tpm-20-support) and
-[Secure Boot Support](#secure-boot-support). For users wanting to use Windows, the use of Windows 11 is
-recommended for Intel 12th Generation (Alder Lake) and newer systems, as it
-includes a new scheduler that supports the efficiency cores.
-
-### NVIDIA Dynamic Boost
-
-**Introduced in firmware version 2023-04-03.**
-
-On new systems with the NVIDIA 4000 series GPUs, NVIDIA Dynamic Boost has been
-enabled with new code in coreboot. This allows power to be shared between the
-CPU and GPU, diverting power to the subsystem that needs it most. This can
-provide an additional 25W boost split between the CPU and GPU depending on the
-task, significantly improving throughput and framerates.

docs/flashing.md

@@ -13,44 +13,16 @@ coreboot's `cbmem` tool can be used to verify this. The call to
 `FspMemoryInit()` can report 20+ seconds on the first boot, and a few hundred
 milliseconds on subsequent boots.
 
-## UEFI application
-
-This is the default method for flashing firmware (using firmware-update). When
-used from this repo, it only works with systems running System76 open firmware.
-
-```
-./scripts/flash.sh <model>
-```
-
-By default the script will attempt to flash both the BIOS and the EC. Their
-respective file can be deleted to skip flashing them.
-
-If the EC is flashed, the system will immediately power off.
-
 ## Internal programmer
 
-### Availability
-
-This method is only possible when firmware is unlocked. Firmware is unlocked by
-one of two methods:
-
-- The EC feature `CONFIG_SECURITY` is unset/disabled
-- The EC is unlock for a single boot (via firmware-update or ectool)
-
-The current state can be determined using ectool:
+Use this method for flashing a system already running System76 Open Firmware.
 
 ```
-./ec/scripts/ectool.sh security
+./scripts/flash.sh <model> [--without-ec]
 ```
 
-- `Lock`: This method can't be used
-- `Unlock`: This method can be used
-
-### flashrom
-
-```
-sudo flashrom -p internal -w build/<model>/firmware.rom
-```
+By default the script will attempt to flash the EC. If the EC is flashed, the
+system will immediately power off.
 
 ## External programmer
 
@@ -59,14 +31,13 @@ Use one of these methods for first-time flashing or flashing a bricked system.
 ### Identifying the BIOS chip
 
 The packaging and protocol can be determined by `board_info.txt` in coreboot.
-Pin 1 is sometimes marked by a small dot indent and a white paint mark. The
-silkscreen may also indicate pin 1.
+Pin 1 is marked by a small dot indent and a white paint mark. The silkscreen
+may also indicate pin 1.
 
 ### CH341A USB programmer - slower, but easier to set up
 
 These can be purchased from many places for around 15 USD. Make sure that the
 one you get has a ROM clip. Here are some examples:
-
 - [Amazon.com, Organizer.](https://www.amazon.com/Organizer-Socket-Adpter-Programmer-CH341A/dp/B07R5LPTYM)
 - [Amazon.com, KeeYees.](https://www.amazon.com/KeeYees-SOIC8-EEPROM-CH341A-Programmer/dp/B07SHSL9X9) 
 - [AliExpress.com, TZT.](https://aliexpress.com/item/32725360255.html)

docs/index.md

@@ -1,9 +0,0 @@
-# Documentation
-
-This is the documentation for System76 Open Firmware. It is set up to be used
-with [mdBook](https://github.com/rust-lang/mdBook), which can generate HTML
-output for easy navigation.
-
-```
-mdbook build --open docs/
-```

docs/intel-me.md

@@ -27,46 +27,15 @@ A restart is required for the change to take effect. On the boot after changing
 the value, the system will perform a global reset (power off again) to complete
 the change and ensure the IME is operating in a valid state.
 
-### Checking the state
+## Tiger Lake-U
 
-coreboot will log some IME data to cbmem during startup. This can be used to
-check if it is in the correct state.
-
-```
-make -C coreboot/util/cbmem
-sudo ./coreboot/util/cbmem/cbmem -c
-```
-
-When disabled it will report:
-
-```
-ME: Current Working State       : 4
-ME: Current Operation State     : 1
-ME: Current Operation Mode      : 3
-ME: Error Code                  : 2
-```
-
-When enabled it will report:
-
-```
-ME: Current Working State       : 5
-ME: Current Operation State     : 1
-ME: Current Operation Mode      : 0
-ME: Error Code                  : 0
-```
-
-## S0ix
-
-S0ix (Modern Standby, s2idle) requires all CPU, PCH, and PCIe devices to have
-ACPI defined low power states. The CPU has numerous states for low power, with
-the lowest being C10. In order to reach this C10 state, the CSME must report
-that it is in a low power state.
-
-Disabling the CSME with the HAP bit or HECI command keeps the CPU in the C8
-state. This nearly triples the power usage in S0ix suspend, from around 1 watt
-to around 3 watts.
-
-TGL-U removed support for S3 and requires S0ix.
+Models using TGL-U processors default to having the IME enabled. TGL-U removes
+support for S3 and requires S0ix. This requires all CPU, PCH, and PCIe devices
+to have ACPI defined low power states. With S0ix, the CPU has numerous states
+for low power, with the lowest being C10. In order to reach this C10 state, the
+IME must report that it is in a low power state. Disabling the ME with the HAP
+bit keeps the CPU in the C8 state. This nearly triples the power usage in S0ix
+suspend, from around 1 watt to around 3 watts.
 
 
 [wiki]: https://en.wikipedia.org/wiki/Intel_Management_Engine

docs/schematics.md

@@ -1,18 +0,0 @@
-# Schematics
-
-## Systems using System76 Open Firmware
-
-System76 customers may request board schematics for their system by sending an
-email to `firmware@system76.com` with the subject line:
-
-> Schematics for <model>
-
-where `<model>` is a model that uses firmware-open. Include the serial number
-of your system for verification.
-
-You may not share these without explicit permission from System76.
-
-## Other models and components
-
-System76 cannot provide schematics for models not using firmware-open, nor
-datasheets for any components that are not already publicly available.

docs/uefi.md

@@ -14,15 +14,12 @@ Network functionality is disabled. Native PXE booting is not supported.
 
 ### Secure Boot
 
-Secure Boot support is enabled since system76/firmware-open@105e74b14613
-(2023-04-03).
+Secure Boot support is currently disabled.
 
-A minimal firmware UI is available to delete all keys and enroll the default
-keys. It is intended that most management is done from the OS.
+The implementation from 9elements is in development. If building a custom
+image, the edk2 config `SECURE_BOOT_ENABLE` can be set to enable support.
 
-Note that the Secure Boot support present is only intended for allowing
-Microsoft Windows installation checks to pass. It should not be relied on for
-system security due to limitations of the implementation.
+There is currently no firmware UI to view or configure Secure Boot.
 
 ## Shell
 

fsp/mtl/4122.12/MeteorLakeFspBinPkg/Include/FspProducerDataHeader.h

@@ -1,80 +0,0 @@
-/** @file
-
-  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-#ifndef _FSP_PRODUCER_DATA_HEADER_H_
-#define _FSP_PRODUCER_DATA_HEADER_H_
-
-#include <Guid/FspHeaderFile.h>
-
-#define BUILD_TIME_STAMP_SIZE 12
-
-//
-// FSP Header Data structure from FspHeader driver.
-//
-#pragma pack(1)
-///
-/// FSP Producer Data Subtype - 1
-///
-typedef struct {
-  ///
-  /// Byte 0x00: Length of this FSP producer data type record.
-  ///
-  UINT16  Length;
-  ///
-  /// Byte 0x02: FSP producer data type.
-  ///
-  UINT8   Type;
-  ///
-  /// Byte 0x03: Revision of this FSP producer data type.
-  ///
-  UINT8   Revision;
-  ///
-  /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
-  ///
-  UINT32  RcVersion;
-  ///
-  /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
-  ///
-  UINT8  BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
-} FSP_PRODUCER_DATA_TYPE1;
-
-///
-/// FSP Producer Data Subtype - 2
-///
-typedef struct {
-  ///
-  /// Byte 0x00: Length of this FSP producer data type record.
-  ///
-  UINT16  Length;
-  ///
-  /// Byte 0x02: FSP producer data type.
-  ///
-  UINT8   Type;
-  ///
-  /// Byte 0x03: Revision of this FSP producer data type.
-  ///
-  UINT8   Revision;
-  ///
-  /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
-  ///
-  UINT8  MrcVersion [4];
-} FSP_PRODUCER_DATA_TYPE2;
-
-typedef struct {
-  FSP_INFO_HEADER          FspInfoHeader;
-  FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
-  FSP_PRODUCER_DATA_TYPE1  FspProduceDataType1;
-  FSP_PRODUCER_DATA_TYPE2  FspProduceDataType2;
-  FSP_PATCH_TABLE          FspPatchTable;
-} FSP_PRODUCER_DATA_TABLES;
-#pragma pack()
-
-#endif // _FSP_PRODUCER_DATA_HEADER_H

libs/README.md

@@ -0,0 +1,9 @@
+# Libraries
+
+## Contents
+
+- [coreboot-fs](https://gitlab.redox-os.org/redox-os/coreboot-fs.git) - coreboot-fs
+- [coreboot-table](https://gitlab.redox-os.org/redox-os/coreboot-table.git) - coreboot-table
+- [intelflash](https://gitlab.redox-os.org/redox-os/intelflash.git) - intelflash
+- [intel-spi](https://github.com/system76/intel-spi.git) - intel-spi
+- [uefi](https://gitlab.redox-os.org/redox-os/uefi.git) - Redox UEFI

libs/README.md.in

@@ -0,0 +1 @@
+# Libraries

models/README.md

@@ -5,17 +5,12 @@
 - [addw1](./addw1) - System76 Adder Workstation (addw1)
 - [addw2](./addw2) - System76 Adder WS (addw2)
 - [addw3](./addw3) - System76 Adder WS (addw3)
-- [addw4](./addw4) - System76 Adder WS (addw4)
 - [bonw14](./bonw14) - System76 Bonobo WS (bonw14)
 - [bonw15](./bonw15) - System76 Bonobo WS (bonw15)
-- [bonw15-b](./bonw15-b) - System76 Bonobo WS (bonw15-b)
-- [darp10](./darp10) - System76 Darter Pro (darp10)
-- [darp10-b](./darp10-b) - System76 Darter Pro (darp10-b)
 - [darp5](./darp5) - System76 Darter Pro (darp5)
 - [darp6](./darp6) - System76 Darter Pro (darp6)
 - [darp7](./darp7) - System76 Darter Pro (darp7)
 - [darp8](./darp8) - System76 Darter Pro (darp8)
-- [darp9](./darp9) - System76 Darter Pro (darp9)
 - [galp2](./galp2) - System76 Galago Pro (galp2)
 - [galp3](./galp3) - System76 Galago Pro (galp3)
 - [galp3-b](./galp3-b) - System76 Galago Pro (galp3-b)
@@ -23,7 +18,6 @@
 - [galp4](./galp4) - System76 Galago Pro (galp4)
 - [galp5](./galp5) - System76 Galago Pro (galp5)
 - [galp6](./galp6) - System76 Galago Pro (galp6)
-- [galp7](./galp7) - System76 Galago Pro (galp7)
 - [gaze14_1650](./gaze14_1650) - System76 Gazelle (gaze14)
 - [gaze14_1660ti](./gaze14_1660ti) - System76 Gazelle (gaze14)
 - [gaze15](./gaze15) - System76 Gazelle (gaze15)
@@ -35,13 +29,9 @@
 - [gaze18](./gaze18) - System76 Gazelle (gaze18)
 - [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
 - [lemp11](./lemp11) - System76 Lemur Pro (lemp11)
-- [lemp12](./lemp12) - System76 Lemur Pro (lemp12)
-- [lemp13](./lemp13) - System76 Lemur Pro (lemp13)
-- [lemp13-b](./lemp13-b) - System76 Lemur Pro (lemp13-b)
 - [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
 - [oryp10](./oryp10) - System76 Oryx Pro (oryp10)
 - [oryp11](./oryp11) - System76 Oryx Pro (oryp11)
-- [oryp12](./oryp12) - System76 Oryx Pro (oryp12)
 - [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
 - [oryp6](./oryp6) - System76 Oryx Pro (oryp6)
 - [oryp7](./oryp7) - System76 Oryx Pro (oryp7)

models/addw1/README.md

@@ -11,4 +11,4 @@ https://system76.com/guides/addw1
   - HAP: false
 - [ME](./me.rom)
   - Size: 6140 KB
-  - Version: 12.0.94.2428
+  - Version: 12.0.85.1919

models/addw1/coreboot.config

@@ -12,6 +12,7 @@ CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
+CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
 CONFIG_SMMSTORE_V2=y
 CONFIG_USE_OPTION_TABLE=y

models/addw1/gpio.h

@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD7, NONE, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+		_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
+		PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
+		PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
+		PAD_CFG_TERM_GPO(GPP_H18, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J3, NONE, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_K16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000),
+		PAD_CFG_GPI(GPP_K20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000),
+		PAD_CFG_GPI(GPP_K23, NONE, DEEP),
+};
+
+#endif
+
+#endif

models/addw1/hda_verb.c

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865d1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865d1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+	/* Nvidia, GPU93HDMI/DP */
+	0x10de0093, /* Vendor ID */
+	0x155865d1, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865d1),
+	AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

models/addw2/README.md

@@ -11,4 +11,4 @@ https://system76.com/guides/addw2
   - HAP: false
 - [ME](./me.rom)
   - Size: 4092 KB
-  - Version: 14.1.72.2287
+  - Version: 14.0.60.1807

models/addw2/coreboot.config

@@ -12,6 +12,7 @@ CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
+CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
 CONFIG_SMMSTORE_V2=y
 CONFIG_USE_OPTION_TABLE=y

models/addw2/gpio.h

@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD7, NONE, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+		_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
+		PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A0, NONE, DEEP),
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_A14, 0x80800100, 0x0000),
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
+		PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000),
+		PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
+		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_I5, 0, UP_20K, PLTRST),
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J3, NONE, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000),
+		PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_K16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K23, NONE, DEEP),
+};
+
+#endif
+
+#endif

models/addw2/hda_verb.c

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865e1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+	/* Nvidia, GPU92HDMI/DP */
+	0x10de0092, /* Vendor ID */
+	0x155865e1, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

models/addw3/AlderLakeFspBinPkg/AlderLakeFspBinPkg.dec

@@ -1,5 +1,5 @@
 ## @file
-#  Component description file for MeteorLake Fsp Bin package.
+#  Component description file for AlderLake Fsp Bin package.
 #
 # @copyright
 #  INTEL CONFIDENTIAL
@@ -35,7 +35,7 @@
 
 [Defines]
   DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = MeteorLakeFspBinPkg
+  PACKAGE_NAME                   = AlderLakeFspBinPkg
   PACKAGE_GUID                   = 5A536013-A46E-44AD-8B30-738235F77B06
   PACKAGE_VERSION                = 1.02
 

models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfo.h

@@ -18,7 +18,6 @@
 #include <IndustryStandard/SmBios.h>
 
 #define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME    "Firmware Version Info"
-#define INTEL_FVI_SMBIOS_TYPE                     0xDD
 
 #pragma pack(1)
 

models/addw3/AlderLakeFspBinPkg/Include/FirmwareVersionInfoHob.h

@@ -0,0 +1,68 @@
+/** @file
+  Header file for Firmware Version Information
+
+ @copyright
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License which accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+  UINT8                          MajorVersion;
+  UINT8                          MinorVersion;
+  UINT8                          Revision;
+  UINT16                         BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
+  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
+  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+  UINT8                          Type;
+  UINT8                          Length;
+  UINT16                         Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
+  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
+  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_

models/addw3/AlderLakeFspBinPkg/Include/FspInfoHob.h

@@ -0,0 +1,56 @@
+/** @file
+  Header file for FSP Information HOB.
+
+@copyright
+  INTEL CONFIDENTIAL
+  Copyright 2017 - 2019 Intel Corporation.
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+
+  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+  the terms of your license agreement with Intel or your vendor. This file may
+  be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+
+#ifndef _FSP_INFO_HOB_H_
+#define _FSP_INFO_HOB_H_
+
+extern EFI_GUID gFspInfoGuid;
+
+#pragma pack (push, 1)
+
+typedef struct {
+UINT8              SiliconInitVersionMajor;
+UINT8              SiliconInitVersionMinor;
+UINT8              SiliconInitVersionRevision;
+UINT8              SiliconInitVersionBuild;
+UINT8              FspVersionRevision;
+UINT8              FspVersionBuild;
+UINT8              TimeStamp [12];
+UINT8              FspVersionMinor;
+} FSP_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _FSP_INFO_HOB_H_

models/addw3/AlderLakeFspBinPkg/Include/FspUpd.h

@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -37,11 +37,11 @@ are permitted provided that the following conditions are met:
 
 #pragma pack(1)
 
-#define FSPT_UPD_SIGNATURE               0x545F4450554C544D        /* 'MTLUPD_T' */
+#define FSPT_UPD_SIGNATURE               0x545F4450554C4441        /* 'ADLUPD_T' */
 
-#define FSPM_UPD_SIGNATURE               0x4D5F4450554C544D        /* 'MTLUPD_M' */
+#define FSPM_UPD_SIGNATURE               0x4D5F4450554C4441        /* 'ADLUPD_M' */
 
-#define FSPS_UPD_SIGNATURE               0x535F4450554C544D        /* 'MTLUPD_S' */
+#define FSPS_UPD_SIGNATURE               0x535F4450554C4441        /* 'ADLUPD_S' */
 
 #pragma pack()
 

models/addw3/AlderLakeFspBinPkg/Include/FsptUpd.h

@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -74,7 +74,8 @@ typedef struct {
   UINT8                       PcdSerialIoUartDebugEnable;
 
 /** Offset 0x0061 - PcdSerialIoUartNumber
-  Select SerialIo Uart Controller for debug.
+  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+  Core interface, it cannot be used for debug purpose.
   0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
 **/
   UINT8                       PcdSerialIoUartNumber;
@@ -86,11 +87,9 @@ typedef struct {
 **/
   UINT8                       PcdSerialIoUartMode;
 
-/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT
-  Select SerialIo Uart Controller Powergating mode
-  0:Disabled, 1:Enabled, 2:Auto
+/** Offset 0x0063
 **/
-  UINT8                       PcdSerialIoUartPowerGating;
+  UINT8                       Rsvd00;
 
 /** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
   Set default BaudRate Supported from 0 - default to 6000000
@@ -158,24 +157,19 @@ typedef struct {
 **/
   UINT32                      PcdSerialIoUartDebugMmioBase;
 
-/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT
-  Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
-**/
-  UINT32                      PcdSerialIoUartDebugPciCfgBase;
-
-/** Offset 0x0090 - PcdLpcUartDebugEnable
+/** Offset 0x008C - PcdLpcUartDebugEnable
   Enable to initialize LPC Uart device in FSP.
   0:Disable, 1:Enable
 **/
   UINT8                       PcdLpcUartDebugEnable;
 
-/** Offset 0x0091 - Debug Interfaces
+/** Offset 0x008D - Debug Interfaces
   Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
   BIT2 - Not used.
 **/
   UINT8                       PcdDebugInterfaceFlags;
 
-/** Offset 0x0092 - PcdSerialDebugLevel
+/** Offset 0x008E - PcdSerialDebugLevel
   Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
   Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
   Info & Verbose.
@@ -184,206 +178,149 @@ typedef struct {
 **/
   UINT8                       PcdSerialDebugLevel;
 
-/** Offset 0x0093 - ISA Serial Base selection
+/** Offset 0x008F - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
   0:0x3F8, 1:0x2F8
 **/
   UINT8                       PcdIsaSerialUartBase;
 
-/** Offset 0x0094 - PcdSerialIo2ndUartEnable
+/** Offset 0x0090 - PcdSerialIo2ndUartEnable
   Enable Additional SerialIo Uart device in FSP.
   0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
 **/
   UINT8                       PcdSerialIo2ndUartEnable;
 
-/** Offset 0x0095 - PcdSerialIo2ndUartNumber
+/** Offset 0x0091 - PcdSerialIo2ndUartNumber
   Select SerialIo Uart Controller Number
   0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
 **/
   UINT8                       PcdSerialIo2ndUartNumber;
 
-/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT
+/** Offset 0x0092 - PcdSerialIo2ndUartMode - FSPT
   Select SerialIo Uart Controller mode
   0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
   4:SerialIoUartSkipInit
 **/
   UINT8                       PcdSerialIo2ndUartMode;
 
-/** Offset 0x0097
+/** Offset 0x0093
 **/
-  UINT8                       Rsvd020[1];
+  UINT8                       Rsvd01;
 
-/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT
+/** Offset 0x0094 - PcdSerialIo2ndUartBaudRate - FSPT
   Set default BaudRate Supported from 0 - default to 6000000
 **/
   UINT32                      PcdSerialIo2ndUartBaudRate;
 
-/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT
+/** Offset 0x0098 - PcdSerialIo2ndUartParity - FSPT
   Set default Parity.
   0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
 **/
   UINT8                       PcdSerialIo2ndUartParity;
 
-/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT
+/** Offset 0x0099 - PcdSerialIo2ndUartDataBits - FSPT
   Set default word length. 0: Default, 5,6,7,8
 **/
   UINT8                       PcdSerialIo2ndUartDataBits;
 
-/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT
+/** Offset 0x009A - PcdSerialIo2ndUartStopBits - FSPT
   Set default stop bits.
   0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
 **/
   UINT8                       PcdSerialIo2ndUartStopBits;
 
-/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT
+/** Offset 0x009B - PcdSerialIo2ndUartAutoFlow - FSPT
   Enables UART hardware flow control, CTS and RTS lines.
   0: Disable, 1:Enable
 **/
   UINT8                       PcdSerialIo2ndUartAutoFlow;
 
-/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT
+/** Offset 0x009C - PcdSerialIo2ndUartRxPinMux - FSPT
   Select RX pin muxing for SerialIo UART
 **/
   UINT32                      PcdSerialIo2ndUartRxPinMux;
 
-/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT
+/** Offset 0x00A0 - PcdSerialIo2ndUartTxPinMux - FSPT
   Select TX pin muxing for SerialIo UART
 **/
   UINT32                      PcdSerialIo2ndUartTxPinMux;
 
-/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT
+/** Offset 0x00A4 - PcdSerialIo2ndUartRtsPinMux - FSPT
   Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
   for possible values.
 **/
   UINT32                      PcdSerialIo2ndUartRtsPinMux;
 
-/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT
+/** Offset 0x00A8 - PcdSerialIo2ndUartCtsPinMux - FSPT
   Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
   for possible values.
 **/
   UINT32                      PcdSerialIo2ndUartCtsPinMux;
 
-/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT
+/** Offset 0x00AC - PcdSerialIo2ndUartMmioBase - FSPT
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
   = SerialIoUartPci.
 **/
   UINT32                      PcdSerialIo2ndUartMmioBase;
 
-/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT
-  Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
-**/
-  UINT32                      PcdSerialIo2ndUartPciCfgBase;
-
-/** Offset 0x00B8
+/** Offset 0x00B0
 **/
   UINT32                      TopMemoryCacheSize;
 
-/** Offset 0x00BC - FspDebugHandler
+/** Offset 0x00B4 - FspDebugHandler
   <b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
 **/
   UINT32                      FspDebugHandler;
 
-/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity
+/** Offset 0x00B8 - Serial Io SPI Chip Select Polarity
   Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
   1:SerialIoSpiCsActiveHigh
 **/
   UINT8                       PcdSerialIoSpiCsPolarity[2];
 
-/** Offset 0x00C2 - Serial Io SPI Chip Select Enable
+/** Offset 0x00BA - Serial Io SPI Chip Select Enable
   0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
 **/
   UINT8                       PcdSerialIoSpiCsEnable[2];
 
-/** Offset 0x00C4 - Serial Io SPI Device Mode
+/** Offset 0x00BC - Serial Io SPI Device Mode
   When mode is set to Pci, controller is initalized in early stage. Available modes:
   0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
 **/
   UINT8                       PcdSerialIoSpiMode;
 
-/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output
+/** Offset 0x00BD - Serial Io SPI Default Chip Select Output
   Sets Default CS as Output. Available options: 0:CS0, 1:CS1
 **/
   UINT8                       PcdSerialIoSpiDefaultCsOutput;
 
-/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW
+/** Offset 0x00BE - Serial Io SPI Default Chip Select Mode HW/SW
   Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
 **/
   UINT8                       PcdSerialIoSpiCsMode;
 
-/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High
+/** Offset 0x00BF - Serial Io SPI Default Chip Select State Low/High
   Sets Default CS State Low or High. Available options: 0:Low, 1:High
 **/
   UINT8                       PcdSerialIoSpiCsState;
 
-/** Offset 0x00C8 - Serial Io SPI Device Number
+/** Offset 0x00C0 - Serial Io SPI Device Number
   Select which Serial Io SPI controller is initalized in early stage.
 **/
   UINT8                       PcdSerialIoSpiNumber;
 
-/** Offset 0x00C9
+/** Offset 0x00C1
 **/
-  UINT8                       Rsvd030[3];
+  UINT8                       Rsvd02[3];
 
-/** Offset 0x00CC - Serial Io SPI Device MMIO Base
+/** Offset 0x00C4 - Serial Io SPI Device MMIO Base
   Assigns MMIO for Serial Io SPI controller usage in early stage.
 **/
   UINT32                      PcdSerialIoSpiMmioBase;
 
-/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing
-  Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
-  possible values.
+/** Offset 0x00C8
 **/
-  UINT32                      PcdSerialIoSpiCsPinMux[2];
-
-/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing
-  Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
-  possible values.
-**/
-  UINT32                      PcdSerialIoSpiClkPinMux;
-
-/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing
-  Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
-  for possible values.
-**/
-  UINT32                      PcdSerialIoSpiMisoPinMux;
-
-/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing
-  Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
-  for possible values.
-**/
-  UINT32                      PcdSerialIoSpiMosiPinMux;
-
-/** Offset 0x00E4 - Serial Io I2C Device MMIO Base
-  Assigns MMIO for Serial Io I2C controller usage in early stage.
-**/
-  UINT32                      PcdSerialIoI2cMmioBase;
-
-/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin
-  Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values.
-**/
-  UINT32                      PcdSerialIoI2cSdaPin;
-
-/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin
-  Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values.
-**/
-  UINT32                      PcdSerialIoI2cSclPin;
-
-/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination
-  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
-  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
-  respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
-**/
-  UINT8                       PcdSerialIoI2cPadsTerm;
-
-/** Offset 0x00F1 - Serial Io I2c Controller Number
-  Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF
-  0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable
-**/
-  UINT8                       PcdSerialIoI2cNumber;
-
-/** Offset 0x00F2
-**/
-  UINT8                       ReservedFsptUpd1[6];
+  UINT8                       ReservedFsptUpd1[16];
 } FSP_T_CONFIG;
 
 /** Fsp T UPD Configuration
@@ -406,11 +343,11 @@ typedef struct {
 **/
   FSP_T_CONFIG                FsptConfig;
 
-/** Offset 0x00F8
+/** Offset 0x00D8
 **/
-  UINT8                       Rsvd3[6];
+  UINT8                       Rsvd03[6];
 
-/** Offset 0x00FE
+/** Offset 0x00DE
 **/
   UINT16                      UpdTerminator;
 } FSPT_UPD;

models/addw3/AlderLakeFspBinPkg/Include/GpioConfig.h

@@ -230,6 +230,13 @@ typedef enum {
 
 
   GpioResetDefault   = 0x00,        ///< Leave value of pad reset unmodified
+  ///
+  /// Deprecated settings. Maintained only for compatibility.
+  ///
+  GpioResetPwrGood   = 0x09,        ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
+  GpioResetDeep      = 0x0B,        ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
+  GpioResetNormal    = 0x0D,        ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
+  GpioResetResume    = 0x0F,        ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
 
   ///
   /// New GPIO reset configuration options

models/addw3/AlderLakeFspBinPkg/Include/GpioSampleDef.h

@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -209,8 +209,30 @@ are permitted provided that the following conditions are met:
 
 #define END_OF_GPIO_TABLE   0xFFFFFFFF
 
+//
+//AlderLake S GPIO PCIe SLOT RTD3 and PEG reset pins.
+//
+#define GPIO_VER4_S_GPP_E2      0x080E0002
+#define GPIO_VER4_S_GPP_E3      0x080E0003
+#define GPIO_VER4_S_GPP_F11     0x0810000B
+#define GPIO_VER4_S_GPP_F12     0x0810000C
+#define GPIO_VER4_S_GPP_F13     0x0810000D
+
 //Sample GPIO Table
 
+//
+//AlderLake S Gpio table for assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase.
+//
+static GPIO_INIT_CONFIG mAdlSPcieRstPinGpioTable[] =
+{
+  { GPIO_VER4_S_GPP_E2,   {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PEG_1 RTD3 Reset
+  { GPIO_VER4_S_GPP_E3,   {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PEG_2 RTD3 Reset Sinai DR0 (Rework)
+  { GPIO_VER4_S_GPP_F11,  {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PCIe SLOT_1 RTD3 Reset MIPI60 (Rework)
+  { GPIO_VER4_S_GPP_F12,  {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PCIe SLOT_2 RTD3 Reset MIPI60 (Rework)
+  { GPIO_VER4_S_GPP_F13,  {GpioPadModeGpio,   GpioHostOwnGpio,   GpioDirOut,   GpioOutHigh,   GpioIntDefault,   GpioPlatformReset,   GpioTermNone }},// PCIe SLOT_3 RTD3 Reset MIPI60 (Rework)
+  { 0x0 }  // terminator
+};
+
 static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
 {
 //skip for eSPI function  {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//H_RCIN_N

models/addw3/AlderLakeFspBinPkg/Include/MemInfoHob.h

@@ -5,7 +5,7 @@
 
 @copyright
   INTEL CONFIDENTIAL
-  Copyright 1999 - 2022 Intel Corporation.
+  Copyright 1999 - 2021 Intel Corporation.
 
   The source code contained or described herein and all documents related to the
   source code ("Material") are owned by Intel Corporation or its suppliers or
@@ -41,16 +41,12 @@
 #pragma pack (push, 1)
 
 extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryS3Data2Guid;
 extern EFI_GUID gSiMemoryInfoDataGuid;
 extern EFI_GUID gSiMemoryPlatformDataGuid;
 
 #define MAX_NODE        2
 #define MAX_CH          4
-#define MAX_DDR5_CH     2
 #define MAX_DIMM        2
-// Must match definitions in
-// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
 #define HOB_MAX_SAGV_POINTS 4
 
 ///
@@ -167,19 +163,11 @@ typedef enum {
 #define MRC_DDR_TYPE_UNKNOWN  4
 #endif
 
-#define MAX_PROFILE_NUM       7 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM   5 // number of XMP profiles supported
+#define MAX_PROFILE_NUM     7 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
 
-#ifndef MAX_RCOMP_TARGETS
-#define MAX_RCOMP_TARGETS     5
-#endif
-
-#ifndef MAX_ODT_ENTRIES
-#define MAX_ODT_ENTRIES       11
-#endif
-
-#define MAX_TRACE_REGION              5
-#define MAX_TRACE_CACHE_TYPE          2
+#define MAX_TRACE_REGION             5
+#define MAX_TRACE_CACHE_TYPE         2
 
 //
 // DIMM timings
@@ -192,7 +180,7 @@ typedef struct {
   UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
   UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
   UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
-  UINT32 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+  UINT16 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
   UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
   UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
   UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
@@ -206,9 +194,7 @@ typedef struct {
   UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
   UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
   UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
-  UINT16 tCCD_L;    ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-  UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
-  UINT8  Resv[2];   ///< Resv
+  UINT16 tCCD_L;  ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
 } MRC_CH_TIMING;
 
 typedef struct {
@@ -223,7 +209,7 @@ typedef struct {
   UINT8            DimmId;
   UINT32           DimmCapacity;            ///< DIMM size in MBytes.
   UINT16           MfgId;
-  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
   UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
   UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
   UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
@@ -288,26 +274,32 @@ typedef struct {
   SiMrcVersion      Version;
   BOOLEAN           EccSupport;
   UINT8             MemoryProfile;
+  UINT8             IsDMBRunning;                      ///< Deprecated.
   UINT32            TotalPhysicalMemorySize;
   UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
-  UINT8             XmpProfileEnable;                  ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+  ///
+  /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
+  /// Bit 0: XMP Profile 1 capability status
+  /// Bit 1: XMP Profile 2 capability status
+  /// Bit 2: XMP Profile 3 capability status
+  /// Bit 3: User Profile 4 capability status
+  /// Bit 4: User Profile 5 capability status
+  ///
+  UINT8             XmpProfileEnable;
   UINT8             XmpConfigWarning;                  ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
-  BOOLEAN           DynamicMemoryBoostTrainingFailed;  ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
-  UINT16            Ratio;                             ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
+  UINT8             Ratio;                             ///< DDR Frequency Ratio, Max Value 255
   UINT8             RefClk;
   UINT32            VddVoltage[MAX_PROFILE_NUM];
   UINT32            VddqVoltage[MAX_PROFILE_NUM];
   UINT32            VppVoltage[MAX_PROFILE_NUM];
-  UINT16            RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
-  UINT16            DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
   CONTROLLER_INFO   Controller[MAX_NODE];
+  UINT16            Ratio_UINT16;                      ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
   UINT32            NumPopulatedChannels;              ///< Total number of memory channels populated
   HOB_SAGV_INFO     SagvConfigInfo;                    ///< This data structure contains SAGV config values that are considered output by the MRC.
-  BOOLEAN           IsIbeccEnabled;
   UINT16            TotalMemWidth;                     ///< Total Memory Width in bits from all populated channels
-  UINT16            PprDetectedErrors;                 ///< PPR: Counts of detected bad rows
-  UINT16            PprRepairFails;                    ///< PPR: Counts of repair failure
-  UINT16            PprForceRepairStatus;              ///< PPR: Force Repair Status
+  BOOLEAN           MemorySpeedReducedWrongDimmSlot;   ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
+  BOOLEAN           MemorySpeedReducedMixedConfig;     ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
+  BOOLEAN           DynamicMemoryBoostTrainingFailed;  ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
 } MEMORY_INFO_DATA_HOB;
 
 /**

models/addw3/AlderLakeFspBinPkg/Library/FspPcdListLib/FspPcdListLibNull.inf

@@ -65,22 +65,21 @@
   # FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are
   # built into PCD database.
   #
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber            ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress                      ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength                       ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress                ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize             ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode                           ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate                       ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable                       ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress                        ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting                      ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize                     ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme                ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability                   ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                           ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr    ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                           ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled                          ## CONSUMES
-
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr     ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr  ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                            ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber             ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress                       ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength                        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress                 ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize              ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode                            ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate                        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled                           ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable                        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress                         ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting                       ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize                      ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme                 ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability                    ## CONSUMES

models/addw3/coreboot.config

@@ -19,3 +19,10 @@ CONFIG_SMMSTORE_V2=y
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
+
+# Custom FSP
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Fsp.fd"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/AlderLakeFspBinPkg/Include"
+CONFIG_FSP_USE_REPO=n

models/addw3/gpio.h

@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A7, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A13, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A14, NONE),
+	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
+	PAD_NC(GPP_B1, NONE),
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 0, DEEP),
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPP_B19, 1, DEEP),
+	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000),
+	PAD_CFG_GPO(GPP_B22, 1, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+	PAD_NC(GPP_C9, NONE),
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	PAD_CFG_GPO(GPP_C11, 1, DEEP),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	_PAD_CFG_STRUCT(GPP_E3, 0x42840101, 0x0000),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	PAD_NC(GPP_E13, NONE),
+	PAD_NC(GPP_E14, NONE),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, DN_20K, DEEP),
+	PAD_CFG_GPO(GPP_E18, 1, DEEP),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+	PAD_NC(GPP_F1, NONE),
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F3, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F4, 1, PLTRST),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPI(GPP_F7, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, PLTRST),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+	PAD_CFG_NF(GPP_G2, DN_20K, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPI(GPP_H1, NONE, DEEP),
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	PAD_CFG_NF(GPP_H13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H14, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H18, 0, DEEP),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	PAD_CFG_GPO(GPP_H22, 0, DEEP),
+	PAD_NC(GPP_H23, NONE),
+	PAD_CFG_GPI(GPP_I0, NONE, DEEP),
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I2, 0x86800100, 0x0000),
+	PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I4, 0x86800100, 0x0000),
+	PAD_CFG_GPO(GPP_I5, 1, PLTRST),
+	PAD_CFG_GPO(GPP_I6, 0, DEEP),
+	PAD_NC(GPP_I7, NONE),
+	PAD_CFG_GPO(GPP_I8, 0, DEEP),
+	PAD_NC(GPP_I9, NONE),
+	PAD_NC(GPP_I10, NONE),
+	PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
+	PAD_NC(GPP_I15, NONE),
+	PAD_NC(GPP_I16, NONE),
+	PAD_NC(GPP_I17, NONE),
+	PAD_CFG_GPO(GPP_I18, 0, DEEP),
+	PAD_NC(GPP_I19, NONE),
+	PAD_NC(GPP_I20, NONE),
+	PAD_NC(GPP_I21, NONE),
+	PAD_CFG_GPO(GPP_I22, 0, DEEP),
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+	PAD_NC(GPP_J8, NONE),
+	PAD_NC(GPP_J9, NONE),
+	PAD_CFG_NF(GPP_J10, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000),
+	PAD_NC(GPP_K1, NONE),
+	PAD_NC(GPP_K2, NONE),
+	PAD_CFG_GPO(GPP_K3, 1, PLTRST),
+	PAD_CFG_GPO(GPP_K4, 0, PWROK),
+	PAD_NC(GPP_K5, NONE),
+	PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
+	PAD_NC(GPP_K11, NONE),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+	PAD_CFG_GPI(GPP_R8, NONE, PLTRST),
+	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
+	PAD_NC(GPP_R10, NONE),
+	PAD_NC(GPP_R11, NONE),
+	PAD_NC(GPP_R12, NONE),
+	PAD_NC(GPP_R13, NONE),
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
+	PAD_CFG_GPO(GPP_R16, 1, DEEP),
+	PAD_NC(GPP_R17, NONE),
+	PAD_NC(GPP_R18, NONE),
+	PAD_NC(GPP_R19, NONE),
+	PAD_NC(GPP_R20, NONE),
+	PAD_CFG_GPO(GPP_R21, 0, DEEP),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+};
+
+#endif
+
+#endif

models/addw3/hda_verb.c

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x1558a671, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558a671),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+	/* Intel, RaptorlakeHDMI */
+	0x80862818, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	10, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+	/* Nvidia, GenericHDMI */
+	0x10de00a6, /* Vendor ID */
+	0x10de0000, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x10de0000),
+	AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x585600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

models/addw4/IntelGopDriver.inf

@@ -1,9 +0,0 @@
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = IntelGopDriver
-  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-
-[Binaries.X64]
-  PE32|IntelGopDriver.efi|*

models/addw4/README.md

@@ -1,12 +0,0 @@
-# System76 Adder WS (addw4)
-
-## Contents
-
-- [EC](./ec.rom)
-  - *Read Error: No such file or directory (os error 2)*
-- [FD](./fd.rom)
-  - Size: 4 KB
-  - HAP: false
-- [ME](./me.rom)
-  - Size: 3944 KB
-  - Version: 16.1.30.2330

models/addw4/README.md.in

@@ -1 +0,0 @@
-# System76 Adder WS (addw4)

models/addw4/chip.txt

@@ -1 +0,0 @@
-GD25Q256D

models/addw4/coreboot-collector.txt

@@ -1,326 +0,0 @@
-## PCI ##
-PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
-PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
-PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
-PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
-PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
-PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
-PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
-PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
-PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
-PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
-PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
-PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
-PCI Device: 0000:00:15.3: Class 0x000C8000, Vendor 0x8086, Device 0x7A4F, Revision 0x11
-PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
-PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3A, Revision 0x11
-PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
-PCI Device: 0000:00:1f.3: Class 0x00040380, Vendor 0x8086, Device 0x7A50, Revision 0x11
-PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
-PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
-PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2820, Revision 0xA1
-PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BD, Revision 0xA1
-PCI Device: 0000:02:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
-PCI Device: 10000:e0:1d.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
-PCI Device: 10000:e0:1d.4: Class 0x00060400, Vendor 0x8086, Device 0x7A34, Revision 0x11
-PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
-## GPIO ##
-600 Series PCH
-GPP_I0 (0x6E,0x00) 0x84000200 0x00000018 0x00000000 0x00000000
-GPP_I1 (0x6E,0x02) 0x82000500 0x00000019 0x00000000 0x00000000
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-GPP_D10 (0x69,0x34) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
-GPP_D13 (0x69,0x3A) 0x40000702 0x00003c00 0x00000000 0x00000000
-GPP_D14 (0x69,0x3C) 0x40000702 0x00003c00 0x00000000 0x00000000
-GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
-GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
-GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
-GPP_D22 (0x69,0x4C) 0x40000700 0x00000000 0x00000000 0x00000000
-GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
-## HDAUDIO ##
-hdaudioC0D0
-  vendor_name: Realtek
-  chip_name: ALC245
-  vendor_id: 0x10ec0245
-  subsystem_id: 0x15580353
-  revision_id: 0x100001
-  0x12: 0x90a60130
-  0x13: 0x40000000
-  0x14: 0x90170110
-  0x17: 0x411111f0
-  0x18: 0x411111f0
-  0x19: 0x411111f0
-  0x1a: 0x411111f0
-  0x1b: 0x411111f0
-  0x1d: 0x40689b2d
-  0x1e: 0x411111f0
-  0x21: 0x04211020
-hdaudioC0D2
-  vendor_name: Intel
-  chip_name: Raptorlake HDMI
-  vendor_id: 0x80862818
-  subsystem_id: 0x80860101
-  revision_id: 0x100000
-  0x04: 0x18560010
-  0x06: 0x18560010
-  0x08: 0x18560010
-  0x0a: 0x18560010
-  0x0b: 0x18560010
-  0x0c: 0x18560010
-  0x0d: 0x18560010
-  0x0e: 0x18560010
-  0x0f: 0x18560010
-hdaudioC1D0
-  vendor_name: Nvidia
-  chip_name: GPU a6 HDMI/DP
-  vendor_id: 0x10de00a6
-  subsystem_id: 0x10de0000
-  revision_id: 0x100100
-  0x04: 0x185600f0
-  0x05: 0x585600f0
-  0x06: 0x585600f0
-  0x07: 0x585600f0

models/addw4/coreboot.config

@@ -1,19 +0,0 @@
-CONFIG_VENDOR_SYSTEM76=y
-CONFIG_BOARD_SYSTEM76_ADDW4=y
-CONFIG_CCACHE=y
-CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_HAVE_ME_BIN=y
-CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
-CONFIG_PAYLOAD_ELF=y
-CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
-CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
-CONFIG_POST_IO=n
-CONFIG_SMMSTORE=y
-CONFIG_SMMSTORE_V2=y
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
-#CONFIG_CONSOLE_SYSTEM76_EC=y

models/addw4/ec.config

@@ -1 +0,0 @@
-BOARD=system76/addw4

models/addw4/ecspy.txt

@@ -1,89 +0,0 @@
-id 5570 rev 7
-A0: data 1 mirror 1 pot 0 control 00
-A1: data 0 mirror 0 pot 0 control 80
-A2: data 0 mirror 0 pot 0 control 00
-A3: data 1 mirror 1 pot 0 control 80
-A4: data 0 mirror 0 pot 0 control 00
-A5: data 0 mirror 0 pot 0 control 00
-A6: data 0 mirror 0 pot 0 control 00
-A7: data 1 mirror 0 pot 0 control 00
-B0: data 0 mirror 0 pot 0 control 84
-B1: data 1 mirror 1 pot 0 control 84
-B2: data 1 mirror 1 pot 0 control 80
-B3: data 1 mirror 1 pot 0 control 80
-B4: data 1 mirror 1 pot 0 control 40
-B5: data 0 mirror 0 pot 0 control 80
-B6: data 1 mirror 1 pot 0 control 44
-B7: data 1 mirror 1 pot 0 control 80
-C0: data 1 mirror 1 pot 0 control 80
-C1: data 1 mirror 1 pot 0 control 04
-C2: data 1 mirror 1 pot 0 control 04
-C3: data 1 mirror 1 pot 0 control 04
-C4: data 0 mirror 0 pot 0 control 84
-C5: data 1 mirror 1 pot 0 control 04
-C6: data 1 mirror 1 pot 0 control 40
-C7: data 1 mirror 1 pot 0 control 44
-D0: data 1 mirror 1 pot 0 control 44
-D1: data 1 mirror 1 pot 0 control 44
-D2: data 1 mirror 1 pot 0 control 00
-D3: data 0 mirror 0 pot 0 control 40
-D4: data 0 mirror 0 pot 0 control 80
-D5: data 1 mirror 1 pot 0 control 44
-D6: data 1 mirror 1 pot 0 control 02
-D7: data 1 mirror 1 pot 0 control 02
-E0: data 1 mirror 1 pot 0 control 04
-E1: data 1 mirror 1 pot 0 control 44
-E2: data 0 mirror 0 pot 0 control 84
-E3: data 1 mirror 1 pot 0 control 40
-E4: data 1 mirror 1 pot 0 control 42
-E5: data 1 mirror 1 pot 0 control 40
-E6: data 0 mirror 0 pot 0 control 80
-E7: data 1 mirror 1 pot 0 control 04
-F0: data 0 mirror 0 pot 0 control 44
-F1: data 1 mirror 1 pot 0 control 44
-F2: data 1 mirror 1 pot 0 control 44
-F3: data 1 mirror 1 pot 0 control 40
-F4: data 1 mirror 1 pot 0 control 04
-F5: data 1 mirror 1 pot 0 control 04
-F6: data 0 mirror 0 pot 0 control 40
-F7: data 0 mirror 0 pot 0 control 40
-G0: data 1 mirror 1 pot 0 control 40
-G1: data 1 mirror 1 pot 0 control 44
-G2: data 1 mirror 1 pot 0 control 80
-G3: data 0 mirror 0 pot 0 control 00
-G4: data 0 mirror 0 pot 0 control 00
-G5: data 0 mirror 0 pot 0 control 00
-G6: data 0 mirror 0 pot 0 control 40
-G7: data 0 mirror 0 pot 0 control 00
-H0: data 1 mirror 1 pot 0 control 80
-H1: data 0 mirror 0 pot 0 control 82
-H2: data 0 mirror 0 pot 0 control 40
-H3: data 1 mirror 1 pot 0 control 44
-H4: data 1 mirror 1 pot 0 control 80
-H5: data 1 mirror 1 pot 0 control 40
-H6: data 1 mirror 1 pot 0 control 80
-H7: data 1 mirror 1 pot 0 control 80
-I0: data 0 mirror 0 pot 0 control 00
-I1: data 0 mirror 0 pot 0 control 00
-I2: data 0 mirror 0 pot 0 control 80
-I3: data 0 mirror 0 pot 0 control 00
-I4: data 0 mirror 0 pot 0 control 00
-I5: data 0 mirror 0 pot 0 control 00
-I6: data 0 mirror 0 pot 0 control 00
-I7: data 0 mirror 0 pot 0 control 00
-J0: data 0 mirror 0 pot 0 control 40
-J1: data 1 mirror 1 pot 0 control 40
-J2: data 0 mirror 0 pot 0 control 40
-J3: data 0 mirror 0 pot 0 control 82
-J4: data 1 mirror 1 pot 0 control 40
-J5: data 1 mirror 1 pot 0 control 80
-J6: data 0 mirror 0 pot 0 control 44
-J7: data 1 mirror 1 pot 0 control 40
-M0: data 0 mirror 0 control 06
-M1: data 0 mirror 1 control 06
-M2: data 1 mirror 1 control 06
-M3: data 1 mirror 1 control 06
-M4: data 0 mirror 1 control 06
-M5: data 0 mirror 0 control 00
-M6: data 1 mirror 1 control 86
-M7: data 0 mirror 0 control 00

models/addw4/edk2.config

@@ -1,9 +0,0 @@
-BOOTLOADER=COREBOOT
-DISABLE_SERIAL_TERMINAL=TRUE
-PLATFORM_BOOT_TIMEOUT=2
-PS2_KEYBOARD_ENABLE=TRUE
-SECURE_BOOT_ENABLE=TRUE
-SERIAL_DRIVER_ENABLE=FALSE
-SHELL_TYPE=NONE
-TPM_ENABLE=TRUE
-#SYSTEM76_EC_LOGGING=TRUE

models/bonw14/README.md

@@ -9,4 +9,4 @@
   - HAP: false
 - [ME](./me.rom)
   - Size: 4092 KB
-  - Version: 14.1.72.2287
+  - Version: 14.0.60.1807

models/bonw14/gpio.h

@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
+		PAD_CFG_GPI(GPD7, UP_20K, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD11, UP_20K, PWROK),
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A14, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A15, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
+		PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B4, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST),
+		PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST),
+		PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST),
+		PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000),
+		PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C8, NONE, PLTRST),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C14, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C15, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_C22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D4, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D23, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
+		PAD_CFG_GPI(GPP_E3, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F2, 0, UP_20K, PLTRST),
+		PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_F7, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F8, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F10, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),
+		PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F20, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F21, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G1, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G2, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G6, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H3, NONE, PLTRST),
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H5, NONE, PLTRST),
+		PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
+		PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+		PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000),
+		PAD_CFG_GPI(GPP_H16, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H17, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H19, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H20, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
+		PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K1, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K2, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
+		PAD_CFG_GPI(GPP_K4, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K7, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K11, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000),
+		PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K16, 0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K22, 0, TODO_0x2800, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K23, 0, NONE, PLTRST),
+};
+
+#endif
+
+#endif

models/bonw14/hda.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15587714, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4094022d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451120),
+	/* Nvidia, GPU92HDMI/DP */
+	0x10de0092, /* Vendor ID */
+	0x15587714, /* Subsystem ID */
+	5, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
+	AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

models/bonw15-b/IntelGopDriver.inf

@@ -1,9 +0,0 @@
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = IntelGopDriver
-  FILE_GUID                      = 767222f4-a9f4-41ba-9faa-edaa1405a486
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-
-[Binaries.X64]
-  PE32|IntelGopDriver.efi|*

models/bonw15-b/README.md

@@ -1,12 +0,0 @@
-# System76 Bonobo WS (bonw15-b)
-
-## Contents
-
-- [EC](./ec.rom)
-  - *Read Error: No such file or directory (os error 2)*
-- [FD](./fd.rom)
-  - Size: 4 KB
-  - HAP: false
-- [ME](./me.rom)
-  - Size: 3944 KB
-  - Version: 16.1.30.2330

models/bonw15-b/README.md.in

@@ -1 +0,0 @@
-# System76 Bonobo WS (bonw15-b)

models/bonw15-b/chip.txt

@@ -1 +0,0 @@
-GD25Q256D

models/bonw15-b/coreboot-collector.txt

@@ -1,334 +0,0 @@
-## PCI ##
-PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
-PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
-PCI Device: 0000:00:01.1: Class 0x00060400, Vendor 0x8086, Device 0xA72D, Revision 0x01
-PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
-PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
-PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
-PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
-PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
-PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
-PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
-PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
-PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
-PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
-PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
-PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3E, Revision 0x11
-PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x7A30, Revision 0x11
-PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
-PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x7A50, Revision 0x11
-PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
-PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
-PCI Device: 0000:02:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x27E0, Revision 0xA1
-PCI Device: 0000:02:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BC, Revision 0xA1
-PCI Device: 0000:03:00.0: Class 0x00020000, Vendor 0x8086, Device 0x3101, Revision 0x03
-PCI Device: 0000:04:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
-PCI Device: 0000:05:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
-PCI Device: 0000:05:01.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
-PCI Device: 0000:05:02.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
-PCI Device: 0000:05:03.0: Class 0x00060400, Vendor 0x8086, Device 0x1136, Revision 0x02
-PCI Device: 0000:06:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x1137, Revision 0x00
-PCI Device: 0000:3a:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x1138, Revision 0x00
-PCI Device: 10000:e0:1b.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
-PCI Device: 10000:e0:1b.4: Class 0x00060400, Vendor 0x8086, Device 0x7A44, Revision 0x11
-PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
-## GPIO ##
-600 Series PCH
-GPP_I0 (0x6E,0x00) 0x44000200 0x00000018 0x00000000 0x00000000
-GPP_I1 (0x6E,0x02) 0x86880100 0x00000019 0x00000000 0x00000000
-GPP_I2 (0x6E,0x04) 0x86880100 0x0000001a 0x00000000 0x00000000
-GPP_I3 (0x6E,0x06) 0x86880100 0x0000001b 0x00000000 0x00000000
-GPP_I4 (0x6E,0x08) 0x86880100 0x0000001c 0x00000000 0x00000000
-GPP_I5 (0x6E,0x0A) 0x44000200 0x0000001d 0x00000000 0x00000000
-GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
-GPP_I7 (0x6E,0x0E) 0x44000200 0x00000020 0x00000000 0x00000000
-GPP_I8 (0x6E,0x10) 0x44000200 0x00000021 0x00000000 0x00000000
-GPP_I9 (0x6E,0x12) 0x44000200 0x00000022 0x00000000 0x00000000
-GPP_I10 (0x6E,0x14) 0x44000200 0x00000023 0x00000000 0x00000000
-GPP_I11 (0x6E,0x16) 0x44000300 0x00000024 0x00000000 0x00000000
-GPP_I12 (0x6E,0x18) 0x44000300 0x00000025 0x00000000 0x00000000
-GPP_I13 (0x6E,0x1A) 0x44000300 0x00000026 0x00000000 0x00000000
-GPP_I14 (0x6E,0x1C) 0x44000300 0x00000027 0x00000000 0x00000000
-GPP_I15 (0x6E,0x1E) 0x44000200 0x00000028 0x00000000 0x00000000
-GPP_I16 (0x6E,0x20) 0x44000200 0x00000029 0x00000000 0x00000000
-GPP_I17 (0x6E,0x22) 0x44000200 0x0000002a 0x00000000 0x00000000
-GPP_I18 (0x6E,0x24) 0x44000102 0x0000002b 0x00000000 0x00000000
-GPP_I19 (0x6E,0x26) 0x44000200 0x0000002c 0x00000000 0x00000000
-GPP_I20 (0x6E,0x28) 0x44000200 0x0000002d 0x00000000 0x00000000
-GPP_I21 (0x6E,0x2A) 0x44000200 0x0000002e 0x00000000 0x00000000
-GPP_I22 (0x6E,0x2C) 0x44000102 0x00000030 0x00000000 0x00000000
-GPP_R0 (0x6E,0x32) 0x44000500 0x00000031 0x00000000 0x00000000
-GPP_R1 (0x6E,0x34) 0x44000500 0x00003c32 0x00000000 0x00000000
-GPP_R2 (0x6E,0x36) 0x44000500 0x00003c33 0x00000000 0x00000000
-GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
-GPP_R4 (0x6E,0x3A) 0x44000500 0x00000035 0x00000000 0x00000000
-GPP_R5 (0x6E,0x3C) 0x44000200 0x00000036 0x00000000 0x00000000
-GPP_R6 (0x6E,0x3E) 0x44000200 0x00000037 0x00000000 0x00000000
-GPP_R7 (0x6E,0x40) 0x44000200 0x00000038 0x00000000 0x00000000
-GPP_R8 (0x6E,0x42) 0x44000102 0x00000039 0x00000000 0x00000000
-GPP_R9 (0x6E,0x44) 0x44000702 0x0000003a 0x00000000 0x00000000
-GPP_R10 (0x6E,0x46) 0x44000200 0x0000003b 0x00000000 0x00000000
-GPP_R11 (0x6E,0x48) 0x44000200 0x0000003c 0x00000000 0x00000000
-GPP_R12 (0x6E,0x4A) 0x44000200 0x0000003d 0x00000000 0x00000000
-GPP_R13 (0x6E,0x4C) 0x44000200 0x0000003e 0x00000000 0x00000000
-GPP_R14 (0x6E,0x4E) 0x44000200 0x0000003f 0x00000000 0x00000000
-GPP_R15 (0x6E,0x50) 0x44000200 0x00000040 0x00000000 0x00000000
-GPP_R16 (0x6E,0x52) 0x44000201 0x00000041 0x00000000 0x00000000
-GPP_R17 (0x6E,0x54) 0x44000200 0x00000042 0x00000000 0x00000000
-GPP_R18 (0x6E,0x56) 0x44000200 0x00000043 0x00000000 0x00000000
-GPP_R19 (0x6E,0x58) 0x44000200 0x00000044 0x00000000 0x00000000
-GPP_R20 (0x6E,0x5A) 0x44000200 0x00000045 0x00000000 0x00000000
-GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
-GPP_J0 (0x6E,0x60) 0x44000500 0x00000047 0x00000000 0x00000000
-GPP_J1 (0x6E,0x62) 0x44000700 0x00000048 0x00000000 0x00000000
-GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
-GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
-GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
-GPP_J5 (0x6E,0x6A) 0x44000500 0x0000304c 0x00000000 0x00000000
-GPP_J6 (0x6E,0x6C) 0x44000500 0x0000004d 0x00000000 0x00000000
-GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
-GPP_J8 (0x6E,0x70) 0x44000102 0x00000050 0x00000000 0x00000000
-GPP_J9 (0x6E,0x72) 0x44000200 0x00000051 0x00000000 0x00000000
-GPP_J10 (0x6E,0x74) 0x44000200 0x00000052 0x00000000 0x00000000
-GPP_J11 (0x6E,0x76) 0x44000200 0x00000053 0x00000000 0x00000000
-GPP_B0 (0x6D,0x00) 0x82900102 0x00000050 0x00000000 0x00000000
-GPP_B1 (0x6D,0x02) 0x44000200 0x00000051 0x00000000 0x00000000
-GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
-GPP_B3 (0x6D,0x06) 0x44000201 0x00000053 0x00000000 0x00000000
-GPP_B4 (0x6D,0x08) 0x44000200 0x00000054 0x00000000 0x00000000
-GPP_B5 (0x6D,0x0A) 0x44000200 0x00000055 0x00000000 0x00000000
-GPP_B6 (0x6D,0x0C) 0x44000200 0x00000056 0x00000000 0x00000000
-GPP_B7 (0x6D,0x0E) 0x44000200 0x00000057 0x00000000 0x00000000
-GPP_B8 (0x6D,0x10) 0x44000200 0x00000058 0x00000000 0x00000000
-GPP_B9 (0x6D,0x12) 0x44000200 0x00000059 0x00000000 0x00000000
-GPP_B10 (0x6D,0x14) 0x44000200 0x0000005a 0x00000000 0x00000000
-GPP_B11 (0x6D,0x16) 0x44000200 0x0000005b 0x00000000 0x00000000
-GPP_B12 (0x6D,0x18) 0x44000700 0x0000005c 0x00000000 0x00000000
-GPP_B13 (0x6D,0x1A) 0x44000700 0x0000005d 0x00000000 0x00000000
-GPP_B14 (0x6D,0x1C) 0x44000600 0x0000005e 0x00000000 0x00000000
-GPP_B15 (0x6D,0x1E) 0x44000200 0x0000005f 0x00000000 0x00000000
-GPP_B16 (0x6D,0x20) 0x44000200 0x00000060 0x00000000 0x00000000
-GPP_B17 (0x6D,0x22) 0x04000201 0x00000061 0x00000000 0x00000000
-GPP_B18 (0x6D,0x24) 0x04000702 0x00000062 0x00000000 0x00000000
-GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
-GPP_B20 (0x6D,0x28) 0x44000200 0x00000064 0x00000000 0x00000000
-GPP_B21 (0x6D,0x2A) 0x44000200 0x00000065 0x00000000 0x00000000
-GPP_B22 (0x6D,0x2C) 0x44000201 0x00000066 0x00000000 0x00000000
-GPP_B23 (0x6D,0x2E) 0x44000102 0x00000067 0x00000800 0x00000000
-GPP_G0 (0x6D,0x30) 0x04000200 0x00000068 0x00000000 0x00000000
-GPP_G1 (0x6D,0x32) 0x44000100 0x00000069 0x00000000 0x00000000
-GPP_G2 (0x6D,0x34) 0x44000100 0x0000106a 0x00000000 0x00000000
-GPP_G3 (0x6D,0x36) 0x44000102 0x0000006b 0x00000000 0x00000000
-GPP_G4 (0x6D,0x38) 0x44000100 0x0000006c 0x00000000 0x00000000
-GPP_G5 (0x6D,0x3A) 0x44000700 0x0000006d 0x00000000 0x00000000
-GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
-GPP_G7 (0x6D,0x3E) 0x42800102 0x0000006f 0x00000000 0x00000000
-GPP_H0 (0x6D,0x40) 0x44000102 0x00000070 0x00000000 0x00000000
-GPP_H1 (0x6D,0x42) 0x44000200 0x00000071 0x00000000 0x00000000
-GPP_H2 (0x6D,0x44) 0x44000100 0x00000072 0x00000000 0x00000000
-GPP_H3 (0x6D,0x46) 0x44000702 0x00000073 0x00000000 0x00000000
-GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
-GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
-GPP_H6 (0x6D,0x4C) 0x44000300 0x00000076 0x00000000 0x00000000
-GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
-GPP_H8 (0x6D,0x50) 0x44000700 0x00000018 0x00000000 0x00000000
-GPP_H9 (0x6D,0x52) 0x44000702 0x00000019 0x00000000 0x00000000
-GPP_H10 (0x6D,0x54) 0x44000502 0x00000020 0x00000000 0x00000000
-GPP_H11 (0x6D,0x56) 0x44000502 0x00000021 0x00000000 0x00000000
-GPP_H12 (0x6D,0x58) 0x44000102 0x00000022 0x00000000 0x00000000
-GPP_H13 (0x6D,0x5A) 0x44000502 0x00000023 0x00000000 0x00000000
-GPP_H14 (0x6D,0x5C) 0x44000500 0x00000024 0x00000000 0x00000000
-GPP_H15 (0x6D,0x5E) 0x44000102 0x00000025 0x00000800 0x00000000
-GPP_H16 (0x6D,0x60) 0x44000102 0x00000026 0x00000000 0x00000000
-GPP_H17 (0x6D,0x62) 0x44000201 0x00000027 0x00000000 0x00000000
-GPP_H18 (0x6D,0x64) 0x44000102 0x00000028 0x00000000 0x00000000
-GPP_H19 (0x6D,0x66) 0x44000200 0x00000029 0x00000000 0x00000000
-GPP_H20 (0x6D,0x68) 0x44000200 0x0000002a 0x00000000 0x00000000
-GPP_H21 (0x6D,0x6A) 0x44000201 0x0000002b 0x00000000 0x00000000
-GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
-GPP_H23 (0x6D,0x6E) 0x44000102 0x0000002d 0x00000000 0x00000000
-GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
-GPD1 (0x6C,0x02) 0x04000702 0x00003c61 0x00000000 0x00000000
-GPD2 (0x6C,0x04) 0x42880102 0x00000062 0x00000000 0x00000000
-GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
-GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
-GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
-GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
-GPD7 (0x6C,0x0E) 0x04000100 0x00000067 0x00000000 0x00000000
-GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
-GPD9 (0x6C,0x12) 0x04000200 0x00000069 0x00000000 0x00000000
-GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
-GPD11 (0x6C,0x16) 0x44000200 0x0000006b 0x00000000 0x00000000
-GPD12 (0x6C,0x18) 0x44000200 0x0000006c 0x00000000 0x00000000
-GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
-GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
-GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
-GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
-GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
-GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
-GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
-GPP_A7 (0x6B,0x20) 0x44000200 0x00000025 0x00000000 0x00000000
-GPP_A8 (0x6B,0x22) 0x44000200 0x00000026 0x00000000 0x00000000
-GPP_A9 (0x6B,0x24) 0x44000200 0x00000027 0x00000000 0x00000000
-GPP_A10 (0x6B,0x26) 0x44000500 0x00000028 0x00000000 0x00000000
-GPP_A11 (0x6B,0x28) 0x44000102 0x00003029 0x00000000 0x00000000
-GPP_A12 (0x6B,0x2A) 0x44000200 0x0000002a 0x00000000 0x00000000
-GPP_A13 (0x6B,0x2C) 0x44000200 0x0000002b 0x00000000 0x00000000
-GPP_A14 (0x6B,0x2E) 0x44000200 0x0000002c 0x00000000 0x00000000
-GPP_C0 (0x6B,0x32) 0x44000502 0x0000002d 0x00000000 0x00000000
-GPP_C1 (0x6B,0x34) 0x44000502 0x0000002e 0x00000000 0x00000000
-GPP_C2 (0x6B,0x36) 0x84000102 0x0000002f 0x00000800 0x00000000
-GPP_C3 (0x6B,0x38) 0x44000200 0x00000030 0x00000000 0x00000000
-GPP_C4 (0x6B,0x3A) 0x44000200 0x00000031 0x00000000 0x00000000
-GPP_C5 (0x6B,0x3C) 0x44000502 0x00000032 0x00000000 0x00000000
-GPP_C6 (0x6B,0x3E) 0x44000200 0x00000033 0x00000000 0x00000000
-GPP_C7 (0x6B,0x40) 0x44000200 0x00000034 0x00000000 0x00000000
-GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
-GPP_C9 (0x6B,0x44) 0x44000200 0x00000036 0x00000000 0x00000000
-GPP_C10 (0x6B,0x46) 0x44000200 0x00000037 0x00000000 0x00000000
-GPP_C11 (0x6B,0x48) 0x44000200 0x00000038 0x00000000 0x00000000
-GPP_C12 (0x6B,0x4A) 0x44000200 0x00000039 0x00000000 0x00000000
-GPP_C13 (0x6B,0x4C) 0x44000200 0x0000003a 0x00000000 0x00000000
-GPP_C14 (0x6B,0x4E) 0x44000200 0x0000003b 0x00000000 0x00000000
-GPP_C15 (0x6B,0x50) 0x44000200 0x0000003c 0x00000000 0x00000000
-GPP_C16 (0x6B,0x52) 0x44000502 0x0000003d 0x00000000 0x00000000
-GPP_C17 (0x6B,0x54) 0x44000502 0x0000003e 0x00000000 0x00000000
-GPP_C18 (0x6B,0x56) 0x44000502 0x0000003f 0x00000000 0x00000000
-GPP_C19 (0x6B,0x58) 0x44000502 0x00000040 0x00000000 0x00000000
-GPP_C20 (0x6B,0x5A) 0x44000102 0x00000041 0x00000000 0x00000000
-GPP_C21 (0x6B,0x5C) 0x44000102 0x00000042 0x00000000 0x00000000
-GPP_C22 (0x6B,0x5E) 0x44000200 0x00000043 0x00000000 0x00000000
-GPP_C23 (0x6B,0x60) 0x44000200 0x00000044 0x00000000 0x00000000
-GPP_S0 (0x6A,0x00) 0x44000200 0x01800030 0x00000000 0x00000000
-GPP_S1 (0x6A,0x02) 0x44000200 0x01800031 0x00000000 0x00000000
-GPP_S2 (0x6A,0x04) 0x44000200 0x01800032 0x00000000 0x00000000
-GPP_S3 (0x6A,0x06) 0x44000200 0x01800033 0x00000000 0x00000000
-GPP_S4 (0x6A,0x08) 0x44000200 0x01800034 0x00000000 0x00000000
-GPP_S5 (0x6A,0x0A) 0x44000200 0x01800035 0x00000000 0x00000000
-GPP_S6 (0x6A,0x0C) 0x44000200 0x01800036 0x00000000 0x00000000
-GPP_S7 (0x6A,0x0E) 0x44000200 0x01800037 0x00000000 0x00000000
-GPP_E0 (0x6A,0x10) 0x44000200 0x00000038 0x00000000 0x00000000
-GPP_E1 (0x6A,0x12) 0x44000200 0x00000039 0x00000000 0x00000000
-GPP_E2 (0x6A,0x14) 0x44000200 0x0000003a 0x00000000 0x00000000
-GPP_E3 (0x6A,0x16) 0x44000200 0x0000003b 0x00000000 0x00000000
-GPP_E4 (0x6A,0x18) 0x44000200 0x0000003c 0x00000000 0x00000000
-GPP_E5 (0x6A,0x1A) 0x44000200 0x0000003d 0x00000000 0x00000000
-GPP_E6 (0x6A,0x1C) 0x44000200 0x0000003e 0x00000000 0x00000000
-GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
-GPP_E8 (0x6A,0x20) 0x44000500 0x00000040 0x00000000 0x00000000
-GPP_E9 (0x6A,0x22) 0x44000300 0x00000041 0x00000800 0x00000000
-GPP_E10 (0x6A,0x24) 0x44000300 0x00000042 0x00000800 0x00000000
-GPP_E11 (0x6A,0x26) 0x44000300 0x00000043 0x00000800 0x00000000
-GPP_E12 (0x6A,0x28) 0x44000300 0x00000044 0x00000000 0x00000000
-GPP_E13 (0x6A,0x2A) 0x44000200 0x00000045 0x00000000 0x00000000
-GPP_E14 (0x6A,0x2C) 0x44000200 0x00000046 0x00000000 0x00000000
-GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
-GPP_E16 (0x6A,0x30) 0x44000200 0x00000048 0x00000000 0x00000000
-GPP_E17 (0x6A,0x32) 0x44000200 0x00000049 0x00000000 0x00000000
-GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
-GPP_E19 (0x6A,0x36) 0x44000200 0x0000004b 0x00000000 0x00000000
-GPP_E20 (0x6A,0x38) 0x44000200 0x0000004c 0x00000000 0x00000000
-GPP_E21 (0x6A,0x3A) 0x44000200 0x0000004d 0x00000000 0x00000000
-GPP_K0 (0x6A,0x3E) 0x44000200 0x0000004e 0x00000000 0x00000000
-GPP_K1 (0x6A,0x40) 0x44000200 0x00000050 0x00000000 0x00000000
-GPP_K2 (0x6A,0x42) 0x44000200 0x00000051 0x00000000 0x00000000
-GPP_K3 (0x6A,0x44) 0x44000200 0x00000052 0x00000000 0x00000000
-GPP_K4 (0x6A,0x46) 0x44000200 0x00000053 0x00000000 0x00000000
-GPP_K5 (0x6A,0x48) 0x44000200 0x00000054 0x00000000 0x00000000
-GPP_K6 (0x6A,0x4A) 0x44000a02 0x00000055 0x00000000 0x00000000
-GPP_K7 (0x6A,0x4C) 0x44000a02 0x00000056 0x00000000 0x00000000
-GPP_K8 (0x6A,0x4E) 0x44000700 0x00000057 0x00000000 0x00000000
-GPP_K9 (0x6A,0x50) 0x44000700 0x00000058 0x00000000 0x00000000
-GPP_K10 (0x6A,0x52) 0x44000a02 0x00000059 0x00000000 0x00000000
-GPP_K11 (0x6A,0x54) 0x44000200 0x0000005a 0x00000000 0x00000000
-GPP_F0 (0x6A,0x5C) 0x44000200 0x0000005b 0x00000000 0x00000000
-GPP_F1 (0x6A,0x5E) 0x44000200 0x0000005c 0x00000000 0x00000000
-GPP_F2 (0x6A,0x60) 0x44000200 0x0000005d 0x00000000 0x00000000
-GPP_F3 (0x6A,0x62) 0x44000200 0x0000005e 0x00000000 0x00000000
-GPP_F4 (0x6A,0x64) 0x44000200 0x00000060 0x00000000 0x00000000
-GPP_F5 (0x6A,0x66) 0x84000200 0x00000061 0x00000000 0x00000000
-GPP_F6 (0x6A,0x68) 0x44000200 0x00000062 0x00000000 0x00000000
-GPP_F7 (0x6A,0x6A) 0x44000200 0x00000063 0x00000000 0x00000000
-GPP_F8 (0x6A,0x6C) 0x44000100 0x00000064 0x00000000 0x00000000
-GPP_F9 (0x6A,0x6E) 0x42880102 0x00000065 0x00000000 0x00000000
-GPP_F10 (0x6A,0x70) 0x44000200 0x00000066 0x00000000 0x00000000
-GPP_F11 (0x6A,0x72) 0x44000200 0x00000067 0x00000000 0x00000000
-GPP_F12 (0x6A,0x74) 0x44000200 0x00000068 0x00000000 0x00000000
-GPP_F13 (0x6A,0x76) 0x44000200 0x00000069 0x00000000 0x00000000
-GPP_F14 (0x6A,0x78) 0x44000200 0x0000006a 0x00000000 0x00000000
-GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
-GPP_F16 (0x6A,0x7C) 0x44000200 0x0000006c 0x00000000 0x00000000
-GPP_F17 (0x6A,0x7E) 0x44000200 0x0000006d 0x00000000 0x00000000
-GPP_F18 (0x6A,0x80) 0x44000200 0x0000006e 0x00000000 0x00000000
-GPP_F19 (0x6A,0x82) 0x44000700 0x0000006f 0x00000000 0x00000000
-GPP_F20 (0x6A,0x84) 0x44000700 0x00000070 0x00000000 0x00000000
-GPP_F21 (0x6A,0x86) 0x44000700 0x00000071 0x00000000 0x00000000
-GPP_F22 (0x6A,0x88) 0x44000201 0x00000072 0x00000000 0x00000000
-GPP_F23 (0x6A,0x8A) 0x44000200 0x00000073 0x00000000 0x00000000
-GPP_D0 (0x69,0x20) 0x44000200 0x00000026 0x00000000 0x00000000
-GPP_D1 (0x69,0x22) 0x44000200 0x00000027 0x00000000 0x00000000
-GPP_D2 (0x69,0x24) 0x44000200 0x00000028 0x00000000 0x00000000
-GPP_D3 (0x69,0x26) 0x44000200 0x00000029 0x00000000 0x00000000
-GPP_D4 (0x69,0x28) 0x44000200 0x0000002a 0x00000000 0x00000000
-GPP_D5 (0x69,0x2A) 0x44000200 0x0000002b 0x00000000 0x00000000
-GPP_D6 (0x69,0x2C) 0x44000200 0x0000002c 0x00000000 0x00000000
-GPP_D7 (0x69,0x2E) 0x44000200 0x0000002d 0x00000000 0x00000000
-GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
-GPP_D9 (0x69,0x32) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D10 (0x69,0x34) 0x40000702 0x00003c00 0x00000000 0x00000000
-GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
-GPP_D13 (0x69,0x3A) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D14 (0x69,0x3C) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
-GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
-GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
-GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
-GPP_D22 (0x69,0x4C) 0x40000702 0x00000000 0x00000000 0x00000000
-GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
-## HDAUDIO ##
-hdaudioC0D0
-  vendor_name: Realtek
-  chip_name: ALC1220
-  vendor_id: 0x10ec1220
-  subsystem_id: 0x15583702
-  revision_id: 0x100101
-  0x12: 0x90a60130
-  0x14: 0x0421101f
-  0x15: 0x40000000
-  0x16: 0x411111f0
-  0x17: 0x411111f0
-  0x18: 0x04a11040
-  0x19: 0x411111f0
-  0x1a: 0x411111f0
-  0x1b: 0x90170110
-  0x1d: 0x40b7952d
-  0x1e: 0x04451150
-hdaudioC0D2
-  vendor_name: Intel
-  chip_name: Raptorlake HDMI
-  vendor_id: 0x80862818
-  subsystem_id: 0x80860101
-  revision_id: 0x100000
-  0x04: 0x18560010
-  0x06: 0x18560010
-  0x08: 0x18560010
-  0x0a: 0x18560010
-  0x0b: 0x18560010
-  0x0c: 0x18560010
-  0x0d: 0x18560010
-  0x0e: 0x18560010
-  0x0f: 0x18560010
-hdaudioC1D0
-  vendor_name: Nvidia
-  chip_name: Generic HDMI
-  vendor_id: 0x10de00a5
-  subsystem_id: 0x10de0000
-  revision_id: 0x100100
-  0x04: 0x585600f0
-  0x05: 0x185600f0
-  0x06: 0x185600f0
-  0x07: 0x185600f0