Compare commits
4 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| b7504e5e18 | |||
| 1feff769f1 | |||
| 0d76bcf960 | |||
| c89f7e266f |
1
.github/ISSUE_TEMPLATE/bug_report.md
vendored
1
.github/ISSUE_TEMPLATE/bug_report.md
vendored
@ -10,7 +10,6 @@ assignees: []
|
||||
- BIOS version: <!-- `cat /sys/class/dmi/id/bios_version` (e.g.: 2021-09-30_14b8a6e)-->
|
||||
- EC version: <!-- This will match the BIOS version unless you flashed it separately. -->
|
||||
- OS: <!-- e.g.: Pop!_OS 21.10, Fedora 35, Windows 11 -->
|
||||
- Kernel: <!-- `uname -r` (e.g.: 6.0.6-76060006-generic) -->
|
||||
|
||||
<!-- Briefly describe the problem. -->
|
||||
|
||||
|
||||
68
.gitmodules
vendored
68
.gitmodules
vendored
@ -1,15 +1,55 @@
|
||||
[submodule "edk2"]
|
||||
path = edk2
|
||||
url = ../system76-edk2.git
|
||||
url = https://github.com/system76/edk2.git
|
||||
branch = system76
|
||||
[submodule "coreboot"]
|
||||
path = coreboot
|
||||
url = ../system76-coreboot.git
|
||||
url = https://github.com/system76/coreboot.git
|
||||
branch = system76
|
||||
[submodule "edk2-platforms"]
|
||||
path = edk2-platforms
|
||||
url = https://github.com/system76/edk2-platforms.git
|
||||
branch = system76
|
||||
[submodule "tools/unME12"]
|
||||
path = tools/unME12
|
||||
url = https://github.com/ptresearch/unME12.git
|
||||
branch = master
|
||||
[submodule "tools/unME11"]
|
||||
path = tools/unME11
|
||||
url = https://github.com/ptresearch/unME11.git
|
||||
branch = master
|
||||
[submodule "tools/UEFITool"]
|
||||
path = tools/UEFITool
|
||||
url = https://github.com/LongSoft/UEFITool.git
|
||||
branch = new_engine
|
||||
[submodule "libs/intelflash"]
|
||||
path = libs/intelflash
|
||||
url = https://gitlab.redox-os.org/redox-os/intelflash.git
|
||||
branch = master
|
||||
[submodule "libs/uefi"]
|
||||
path = libs/uefi
|
||||
url = https://gitlab.redox-os.org/redox-os/uefi.git
|
||||
branch = master
|
||||
[submodule "libs/uefi_alloc"]
|
||||
path = libs/uefi_alloc
|
||||
url = https://gitlab.redox-os.org/redox-os/uefi_alloc.git
|
||||
branch = master
|
||||
[submodule "libs/uefi_std"]
|
||||
path = libs/uefi_std
|
||||
url = https://gitlab.redox-os.org/redox-os/uefi_std.git
|
||||
branch = master
|
||||
[submodule "libs/coreboot-table"]
|
||||
path = libs/coreboot-table
|
||||
url = https://gitlab.redox-os.org/redox-os/coreboot-table.git
|
||||
branch = master
|
||||
[submodule "libs/intel-spi"]
|
||||
path = libs/intel-spi
|
||||
url = https://github.com/system76/intel-spi.git
|
||||
branch = master
|
||||
[submodule "libs/ecflash"]
|
||||
path = libs/ecflash
|
||||
url = https://github.com/system76/ecflash.git
|
||||
branch = master
|
||||
[submodule "tools/coreboot-collector"]
|
||||
path = tools/coreboot-collector
|
||||
url = https://github.com/system76/coreboot-collector.git
|
||||
@ -26,23 +66,35 @@
|
||||
path = tools/MEAnalyzer
|
||||
url = https://github.com/platomav/MEAnalyzer.git
|
||||
branch = master
|
||||
[submodule "libs/coreboot-fs"]
|
||||
path = libs/coreboot-fs
|
||||
url = https://gitlab.redox-os.org/redox-os/coreboot-fs.git
|
||||
branch = master
|
||||
[submodule "apps/gop-policy"]
|
||||
path = apps/gop-policy
|
||||
url = https://github.com/system76/gop-policy.git
|
||||
branch = master
|
||||
[submodule "edk2-non-osi"]
|
||||
path = edk2-non-osi
|
||||
url = https://github.com/tianocore/edk2-non-osi.git
|
||||
branch = devel-MinPlatform
|
||||
[submodule "FSP"]
|
||||
path = FSP
|
||||
url = https://github.com/IntelFsp/FSP.git
|
||||
branch = master
|
||||
[submodule "apps/firmware-smmstore"]
|
||||
path = apps/firmware-smmstore
|
||||
url = https://github.com/system76/firmware-smmstore.git
|
||||
branch = master
|
||||
[submodule "tools/ipxe"]
|
||||
path = tools/ipxe
|
||||
url = https://github.com/ipxe/ipxe.git
|
||||
branch = master
|
||||
[submodule "ec"]
|
||||
path = ec
|
||||
url = ../system76-embedded-controller.git
|
||||
branch = main
|
||||
url = https://github.com/system76/ec.git
|
||||
branch = master
|
||||
[submodule "tools/apobtool"]
|
||||
path = tools/apobtool
|
||||
url = https://github.com/system76/apobtool.git
|
||||
branch = master
|
||||
[submodule "tools/intel-spi"]
|
||||
path = tools/intel-spi
|
||||
url = https://github.com/system76/intel-spi.git
|
||||
branch = master
|
||||
|
||||
409
CHANGELOG.md
409
CHANGELOG.md
@ -1,291 +1,8 @@
|
||||
# System76 Open Firmware Changelog
|
||||
# Changelog
|
||||
|
||||
Changes are identified by the date of the released firmware including them. If
|
||||
you are running System76 Open Firmware, opening the boot menu will show this
|
||||
date followed by an underscore and a short git revision. To see if specific
|
||||
features apply to your model and firmware version, see the
|
||||
[feature matrix](./docs/features.md).
|
||||
|
||||
## unreleased
|
||||
|
||||
- whl-u: Updated CSME to 12.0.95.2489v2 (12.0.94.2428)
|
||||
- cfl: Updated CSME to 12.0.94.2380v9 (12.0.94.2428)
|
||||
- mtl: Fixed detection of USB3 hubs in Type-C ports
|
||||
- darp10: Fixed reporting of the second fan
|
||||
- darp10: Fixed using USB3 devices at USB3 speeds in all ports
|
||||
- darp10: Updated fan tables
|
||||
- Fixed IT8587E hang when reading keyboard matrix
|
||||
- Changed fans to use highest reported temperature to calculate duty instead
|
||||
of using the highest calculated duty across all fans
|
||||
- bonw15-b: Added initial release of open firmware with System76 EC
|
||||
- Changed fan mechanism from calculated interpolation/smoothing to a fixed
|
||||
step to limit rapid changes in duty over short periods
|
||||
- Updated coreboot to 24.08
|
||||
|
||||
## 2024-07-08
|
||||
|
||||
- cml-h: Updated CSME to 14.1.74.2355v6 (14.1.72.2287)
|
||||
- cml-u: Updated CSME to 14.1.74.2355v6 (14.1.74.2373)
|
||||
- Reverted unlock prompt change to restore intended behavior
|
||||
|
||||
## 2024-07-01
|
||||
|
||||
- mtl: Updated FSP to D.0.A8.20
|
||||
- adl: Fixed USB 3.0 hubs in Type-C ports
|
||||
- rpl: Fixed USB 3.0 hubs in Type-C ports
|
||||
- Fixed touchpad in PS/2 mode
|
||||
- tgl: Updated CSME to 15.0.49.2573
|
||||
- Fixed unlock prompt showing when system is already unlocked
|
||||
- lemp13-b: Added support for units with 5600 MT/s soldered RAM
|
||||
|
||||
## 2024-05-28
|
||||
|
||||
- tgl: Updated Intel GOP driver to 17.0.1077
|
||||
- tgl: Updated VBT to 250
|
||||
- Updated Rust toolchain to nightly-2024-05-11
|
||||
|
||||
## 2024-05-17
|
||||
|
||||
- lemp13-b: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2024-05-07
|
||||
|
||||
- darp10: Added initial release of open firmware with System76 EC
|
||||
- darp10-b: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2024-04-29
|
||||
|
||||
- Fixed CMOS options not working due to invalid checksum
|
||||
|
||||
## 2024-03-25
|
||||
|
||||
- lemp13: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2024-03-21
|
||||
|
||||
- oryp12: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2024-03-11
|
||||
|
||||
- Updated coreboot to 24.02
|
||||
- adl-p: Updated FSP to C.1.75.10
|
||||
- adl-s: Updated FSP to C.0.75.10
|
||||
- adl: Updated microcode to revision 0x430
|
||||
- rpl-p: Updated FSP to C.1.BD.40
|
||||
- rpl-s: Updated FSP to C.0.BD.40
|
||||
- rpl: Updated microcode to revision 0x411c
|
||||
- tgl: Updated FSP to A.0.7E.70
|
||||
- tgl-u: Updated microcode to revision 0xb4
|
||||
- tgl-h: Updated microcode to revision 0x4e
|
||||
- adl: Fixed PCIe 4.0 drives in PCIe 3.0 slot failing to initialize on resume
|
||||
- rpl: Fixed PCIe 4.0 drives in PCIe 3.0 slot failing to initialize on resume
|
||||
- rpl: Fixed TCSS ACPI access
|
||||
- adl: Fixed `SLP_S0#` counter frequency
|
||||
- rpl: Fixed `SLP_S0#` counter frequency
|
||||
- tgl: Fixed TBT ACPI
|
||||
- Fixed RTC being reset on boot during February 29th
|
||||
- addw4: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2024-01-18
|
||||
|
||||
- darp9: Added SSD RTD3 configs to fix suspend with some drives
|
||||
|
||||
## 2024-01-10
|
||||
|
||||
- darp8: Fixed suspend issue on new boards by switching to S0ix by default
|
||||
- darp9: Fixed suspend issue on new boards by switching to S0ix by default
|
||||
|
||||
## 2023-10-20
|
||||
|
||||
- tgl-u: Fixed CPU not going lower than C2 due to card reader LTR
|
||||
- bonw15: Fixed speaker audio cutting in/out
|
||||
- oryp11: Fixed speaker audio cutting in/out
|
||||
|
||||
## 2023-10-13
|
||||
|
||||
- tgl-u: Fixed potential EC lock up during opportunistic suspend
|
||||
- galp5: Fixed CPU not going lower than C2 due to card reader LTR
|
||||
|
||||
## 2023-09-19
|
||||
|
||||
- rpl-hx: Added support for 5600 MHz RAM
|
||||
|
||||
## 2023-09-08
|
||||
|
||||
- adl: Updated CSME to 16.1.25.2124
|
||||
- adl,rpl: Fixed SMMSTORE init sometimes failing
|
||||
- Increased key debounce from 5ms to 10ms
|
||||
|
||||
## 2023-08-23
|
||||
|
||||
- rpl: Fixed RPL-S GPIO driver on Windows
|
||||
|
||||
## 2023-08-18
|
||||
|
||||
- cml-u: Fixed boot failing at FSP-S
|
||||
- Added KBC reset on CPU reset to prevent keyboard from being locked
|
||||
- Enabled power switch Watch Dog Timer with a timeout of 10 seconds
|
||||
- Fixed detecting if PECI is available on eSPI systems using S0ix
|
||||
- Added support for a FnLock key
|
||||
- tgl: Fixed Bluetooth performance by enabling audio offload
|
||||
- gaze16: Fixed CPU not going lower than C2 due to card reader LTR
|
||||
- adl: Fixed CPU not going lower than C2 due to card reader LTR
|
||||
- rpl: Fixed CPU not going lower than C2 due to card reader LTR
|
||||
- Changed battery charge start threshold to 90%
|
||||
- Changed charger to disable when battery is full
|
||||
|
||||
## 2023-07-19
|
||||
|
||||
- bonw14: Fixed loading CPU microcode
|
||||
- rpl-hx: Fixed setting PL1 and PL2 power limits
|
||||
- rpl-hx: Fixed LPM substates
|
||||
- gaze17: Removed invalid RTD3 configs
|
||||
- oryp10: Removed invalid RTD3 configs
|
||||
- galp8: Removed SATA RTD3 to fix drives being lost on suspend
|
||||
- lemp11: Removed SATA RTD3 to fix drives being lost on suspend
|
||||
- Reduced key debounce from 15ms to 5ms
|
||||
- galp6: Fixed fan tachometer GPIOs
|
||||
- lemp9: Fixed fan tachometer GPIOs
|
||||
- lemp10: Fixed fan tachometer GPIOs
|
||||
- lemp11: Fixed fan tachometer GPIOs
|
||||
|
||||
## 2023-07-10
|
||||
|
||||
- Updated Secure Boot DBX to version 371 (2023-05-09)
|
||||
- bonw15: Added initial release of open firmware with System76 EC
|
||||
- oryp11: Changed adapter Rsense to 10 milliohms
|
||||
- serw13: Changed adapter Rsense to 10 milliohms
|
||||
|
||||
## 2023-06-22
|
||||
|
||||
- addw3: Enabled support for 5200 MT/s memory
|
||||
- serw13: Enabled support for 5200 MT/s memory
|
||||
- oryp11: Added initial release of open firmware with System76 EC
|
||||
- rpl: Enabled TPM read delay to fix occasional failures with Infineon chips
|
||||
- Changed TPM behavior to perform TPM Restart if TPM Resume fails
|
||||
|
||||
## 2023-06-08
|
||||
|
||||
- darp9: Added initial release of open firmware with System76 EC
|
||||
- Added detection of RGB keyboards at runtime
|
||||
- oryp9: Enabled firmware security
|
||||
- oryp9: Enabled NVIDIA Dynamic Boost
|
||||
- oryp10: Enabled firmware security
|
||||
- oryp10: Enabled NVIDIA Dynamic Boost
|
||||
- Invalidated CMOS checksum after flashing to ensure default options are used
|
||||
|
||||
## 2023-05-25
|
||||
|
||||
- Set PL4 based on AC state for all boards
|
||||
- Increased PL4 on battery to 45W for dGPU boards
|
||||
- galp6: Enabled firmware security
|
||||
- galp7: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2023-05-17
|
||||
|
||||
- serw13: Added initial release of open firmware with System76 EC
|
||||
- Fixed Windows BSoD on RPL-HX
|
||||
|
||||
## 2023-05-16
|
||||
|
||||
- lemp12: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2023-04-28
|
||||
|
||||
- addw3: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2023-03-22
|
||||
|
||||
- Updated coreboot to upstream commit decbf7b4d975
|
||||
- Enabled support for Secure Boot
|
||||
- Enabled minimal UI for enforcing Secure Boot and resetting keys
|
||||
- Added firmware locking support
|
||||
- Enabled S3 suspend on everything but TGL-U
|
||||
- Disabled ME by default on everything but TGL-U
|
||||
- Added support for NVIDIA Dynamic Boost
|
||||
- gaze18: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2022-11-21
|
||||
|
||||
- lemp11: Added workaround to force S0ix entry on suspend
|
||||
- tgl-u: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives
|
||||
- adl-p: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives
|
||||
- adl-p: Fixed ACPI brightness controls on Windows 10 and Linux 6.1
|
||||
- adl-p: Disabled SATA DevSlp to fix S0ix entry
|
||||
- tgl-u: Disabled SATA DevSlp to fix S0ix entry
|
||||
- Updated Rust toolchain to nightly-2022-03-18
|
||||
- adl-p: Added workaround to force S0ix entry on suspend
|
||||
- adl-p: Fixed case where system gets stuck in S5 due to power loss
|
||||
- tgl-u: Fixed case where system gets stuck in S5 due to power loss
|
||||
- galp5: Fixed power off failing due to WLAN GPIO
|
||||
|
||||
## 2022-10-14
|
||||
|
||||
- Fixed smart charger values for all boards
|
||||
- Fixed keyboard backlight color with custom values
|
||||
- lemp11: Removed RTD3 config for card reader to fix suspend
|
||||
|
||||
## 2022-09-26
|
||||
|
||||
- oryp8: Fixed brightness controls on Windows
|
||||
- oryp10: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2022-09-07
|
||||
|
||||
- Updated CSME for TGL-H to 15.0.41.2158
|
||||
- Updated CSME for TGL-U to 15.0.41.2158
|
||||
- Changed build to use coreboot toolchain for edk2
|
||||
- Fixed signal used to detect S0ix
|
||||
- Fixed off-by-one for battery charging start/stop thresholds
|
||||
|
||||
## 2022-08-03
|
||||
|
||||
- Updated coreboot to upstream commit 37bf8c6dd590
|
||||
- Updated TGL-U microcode to revision 0xa4 from Intel's public repo
|
||||
- Updated TGL-H microcode to revision 0x3e from Intel's public repo
|
||||
- Updated ADL microcode to revision 0x41c from Intel's public repo
|
||||
- Updated ADL FSP to C.0.69.74 from Intel's public repo
|
||||
- Updated CSME for ADL-P to 16.0.15.1810v8 (16.0.15.1829)
|
||||
- Fixed uncommon I2C HID initialization failure on boot
|
||||
- Fixed smart charger values for all boards
|
||||
- galp6: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2022-07-27
|
||||
|
||||
- gaze17-3050: Added initial release of open firmware with System76 EC
|
||||
- gaze17-3060: Fixed suspend with WD drives
|
||||
|
||||
## 2022-07-20
|
||||
|
||||
- oryp9: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2022-07-13
|
||||
|
||||
- darp8: Fixed power off under load while on battery power
|
||||
|
||||
## 2022-07-05
|
||||
|
||||
- lemp11: Added initial release of open firmare with System76 EC
|
||||
|
||||
## 2022-06-23
|
||||
|
||||
- darp8: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2022-06-07
|
||||
|
||||
- Fixed building for QEMU
|
||||
- Updated coreboot to upstream commit 670572ff6a
|
||||
- Fixed NVIDIA subsystem ID being lost on suspend
|
||||
- TGL: Fixed Device Manager warning about missing drivers for Tiger Lake IPC
|
||||
Controller and System76 EC ACPI devices
|
||||
- Improved NVIDIA Optimus support
|
||||
- tgl-u: Fixed suspend with certain drives
|
||||
- gaze17-3060-b: Added initial release of open firmware with System76 EC
|
||||
|
||||
## 2022-02-15
|
||||
|
||||
- Updated ME for all supported systems
|
||||
- Ensured that system powers off S5 plane if it fails to reach S0
|
||||
date followed by an underscore and a short git revision.
|
||||
|
||||
## 2022-01-06
|
||||
|
||||
@ -293,7 +10,7 @@ features apply to your model and firmware version, see the
|
||||
- Enabled coreboot measured boot
|
||||
- Updated Rust toolchain to nightly-2021-06-15
|
||||
- Updated coreboot to 4.15
|
||||
- Updated EDK2 to edk2-stable202108
|
||||
- Updated EDK2 to edk2-stabke202108
|
||||
- Updated TGL-U microcode blobs to revision 0x9a
|
||||
- Updated TGL-H microcode blobs to revision 0x3c
|
||||
- Updated all other boards to use microcode blobs from Intel's public repo
|
||||
@ -302,23 +19,23 @@ features apply to your model and firmware version, see the
|
||||
|
||||
## 2021-09-30
|
||||
|
||||
- gaze16: Removed need to unplug the AC adapter after flashing
|
||||
- gaze16: Fixed using USB 2.0 devices in Type-C port
|
||||
- gaze16: Do not require unplugging the AC adapter after flashing
|
||||
- gaze16: Fix using USB 2.0 devices in Type-C port
|
||||
|
||||
## 2021-09-23
|
||||
|
||||
- oryp8: Added initial release of open firmware with System76 EC
|
||||
- gaze16: Fixed input current on 3050 variant
|
||||
- gaze16: Fixed power limit when booting on battery
|
||||
- gaze16: Fixed touchpad on newer Linux kernel and Windows
|
||||
- Fixed brightness controls on TGL platforms
|
||||
- Fixed PCIe subsystem IDs on TGL platforms
|
||||
- Fixed spurious clearing of boot options on Windows
|
||||
- Added battery cycle count
|
||||
- oryp8: Release of open firmware with System76 EC
|
||||
- gaze16: Fix input current on 3050 variant
|
||||
- gaze16: Fix power limit when booting on battery
|
||||
- gaze16: Fix touchpad on newer Linux kernel and Windows
|
||||
- Fix brightness controls on TGL platforms
|
||||
- Fix PCIe subsystem IDs on TGL platforms
|
||||
- Fix spurious clearing of boot options on Windows
|
||||
- Provide battery cycle count
|
||||
|
||||
## 2021-07-20
|
||||
|
||||
- gaze16: Added initial release of open firmware with System76 EC
|
||||
- gaze16: Release of open firmware with System76 EC
|
||||
- Improved thermals by syncing CPU and GPU fans
|
||||
- Enabled fan speed interpolation
|
||||
- Fixed ACPI timeout on S3 resume if a key is held
|
||||
@ -328,148 +45,142 @@ features apply to your model and firmware version, see the
|
||||
|
||||
## 2021-04-07
|
||||
|
||||
- tgl-u: Updated microcode
|
||||
- darp7, galp5, lemp10: Update microcode
|
||||
|
||||
## 2021-04-02
|
||||
|
||||
- Fixed fan max keeping fan on when in S0iX
|
||||
- Changed keyboard behavior to report all keys as released when lid is closed
|
||||
- Fix fan max keeping fan on when in S0iX
|
||||
- Report all keys as released when lid is closed
|
||||
|
||||
## 2021-03-19
|
||||
|
||||
- gaze15: Added initial release of open firmware with System76 EC
|
||||
- gaze15: Added ELAN touchpad settings
|
||||
- gaze15: Release of open firmware with System76 EC
|
||||
- gaze15: Add ELAN touchpad settings
|
||||
|
||||
## 2021-03-16
|
||||
|
||||
- oryp6: Fixed buzzing at lowest fan speed
|
||||
- oryp7: Fixed buzzing at lowest fan speed
|
||||
- oryp6, oryp7: Fix buzzing at lowest fan speed
|
||||
|
||||
## 2021-03-11
|
||||
|
||||
- lemp9: Fixed backlight ACPI issues and TPM interrupt
|
||||
- lemp9: Fix backlight ACPI issues and TPM interrupt
|
||||
|
||||
## 2021-03-08
|
||||
|
||||
- oryp6: Improved fan curve
|
||||
- oryp7: Improved fan curve
|
||||
- oryp6, oryp7: Improved fan curve
|
||||
|
||||
## 2021-03-03
|
||||
|
||||
- oryp7: Added initial release of open firmware with System76 EC
|
||||
- oryp7: Release of open firmware with System76 EC
|
||||
|
||||
## 2021-02-15
|
||||
|
||||
- darp7: Increased HDMI data rate to support 4K@60Hz
|
||||
- galp5: Increased HDMI data rate to support 4K@60Hz
|
||||
- darp7, galp5: Raise HDMI data rate to support 4K@60Hz
|
||||
|
||||
## 2021-02-09
|
||||
|
||||
- galp5: Fixed GPU driver crash in compute graphics mode
|
||||
- galp5: Fix GPU driver crash in compute graphics mode
|
||||
|
||||
## 2021-02-05
|
||||
|
||||
- darp7: Fixed keyboard scanning glitches
|
||||
- darp7: Fix keyboard scanning glitches
|
||||
|
||||
## 2021-01-21
|
||||
|
||||
- darp7: Added initial release of open firmware with System76 EC
|
||||
- darp7: Release of open firmware with System76 EC
|
||||
|
||||
## 2021-01-19
|
||||
|
||||
- Added behavior to update boot options on device hotplug
|
||||
- Added fan toggle key (Fn+1)
|
||||
- Added behavior to clear NVRAM when CMOS battery is removed
|
||||
- galp5: Fixed NVRAM compacting
|
||||
- lemp10: Fixed NVRAM compacting
|
||||
- Update boot options on device hotplug
|
||||
- Add fan toggle key (Fn+1)
|
||||
- Clear NVRAM when CMOS battery is removed
|
||||
- galp5, lemp10: Fix NVRAM compacting
|
||||
|
||||
## 2021-12-15
|
||||
|
||||
- galp5: Added support for variant with NVIDIA GPU
|
||||
- galp5: Support variant with NVIDIA GPU
|
||||
|
||||
## 2020-12-04
|
||||
|
||||
- galp5: Added initial release of open firmware with System76 EC
|
||||
- lemp10: Added initial release of open firmware with System76 EC
|
||||
- galp5, lemp10: Release of open firmware with System76 EC
|
||||
|
||||
## 2020-10-19
|
||||
|
||||
- Added support for customizing keyboard at runtime
|
||||
- Added battery charging thresholds
|
||||
- oryp6: Fixed smart charger values
|
||||
- Prevented wake when lid is closed
|
||||
- Support customizing keyboard at runtime
|
||||
- Add battery charging thresholds
|
||||
- oryp6: Fix smart charger values
|
||||
- Prevent wake when lid is closed
|
||||
|
||||
## 2020-09-22
|
||||
|
||||
- darp6: Added initial release of open firmware with System76 EC
|
||||
- darp6: Fixed allocation of memory type range registers
|
||||
- darp6: Release of open firmware with System76 EC
|
||||
- darp6: Fix allocation of memory type range registers
|
||||
|
||||
## 2020-09-17
|
||||
|
||||
- Enabled Wake-on-Lan (on supported models)
|
||||
- Added ACPI thermal interface
|
||||
- Fixed ESXi keyboard issue
|
||||
- Enable Wake-on-Lan (on supported models)
|
||||
- Add ACPI thermal interface
|
||||
- Fix ESXi keyboard issue
|
||||
|
||||
## 2020-09-03
|
||||
|
||||
- addw2: Added initial release of open firmware with System76 EC
|
||||
- addw2: Release of open firmware with System76 EC
|
||||
|
||||
## 2020-08-24
|
||||
|
||||
- bonw14: Added initial release of open firmware with System76 EC
|
||||
- bonw14: Release of open firmware with System76 EC
|
||||
|
||||
## 2020-08-13
|
||||
|
||||
- Added UEFI TPM2 support
|
||||
- Add UEFI TPM2 support
|
||||
|
||||
## 2020-08-06
|
||||
|
||||
- Enabled ACPI backlight
|
||||
- Added firmware configuration information
|
||||
- Enable ACPI backlight
|
||||
- Add firmware configuration information
|
||||
|
||||
## 2020-07-06
|
||||
|
||||
- oryp6: Added initial release of open firmware with System76 EC
|
||||
- oryp6: Release of open firmware with System76 EC
|
||||
|
||||
## 2020-05-20
|
||||
|
||||
- Added warning if no bootable media is found
|
||||
- Warn if no bootable media is found
|
||||
|
||||
## 2020-05-15
|
||||
|
||||
- Enabled i2c-hid touchpad interface
|
||||
- Enable i2c-hid touchpad interface
|
||||
|
||||
## 2020-05-07
|
||||
|
||||
- Fixed ghost key debouncing
|
||||
- Fix ghost key debouncing
|
||||
|
||||
## 2020-05-04
|
||||
|
||||
- Improved ghost key handling and reduce key debounce
|
||||
- Improve ghost key handling and reduce key debounce
|
||||
|
||||
## 2020-04-23
|
||||
|
||||
- Fixed duplicate release of key after release of function key
|
||||
- Fix duplicate release of key after release of function key
|
||||
|
||||
## 2020-04-18
|
||||
|
||||
- lemp9: Updated fan curve
|
||||
- lemp9: Update fan curve
|
||||
|
||||
## 2020-04-09
|
||||
|
||||
- lemp9: Added initial release of open firmware with System76 EC
|
||||
- lemp9: Release of open firmware with System76 EC
|
||||
|
||||
## 2020-02-05
|
||||
|
||||
- Changed boot manager to use descriptive device names
|
||||
- Changed boot manager to only show bootable devices
|
||||
- Use descriptive device names
|
||||
- Only show bootable devices
|
||||
|
||||
## 2020-01-13
|
||||
|
||||
- Fixed NVIDIA eGPU issues
|
||||
- Improved boot order editing
|
||||
- Fix NVIDIA eGPU issues
|
||||
- Iimprove boot order editing
|
||||
|
||||
## 2019-10-31
|
||||
|
||||
- darp6: Added intial release of open firmware with proprietary EC
|
||||
- galp4: Added intial release of open firmware with proprietary EC
|
||||
- darp6, galp4: Release of open firmware with proprietary EC
|
||||
|
||||
1
FSP
Submodule
1
FSP
Submodule
Submodule FSP added at 10eae55b8e
134
Jenkinsfile
vendored
134
Jenkinsfile
vendored
@ -1,134 +0,0 @@
|
||||
#!/usr/bin/env groovy
|
||||
|
||||
// Required plugins:
|
||||
// - Jenkins Core
|
||||
// - AnsiColor (https://plugins.jenkins.io/ansicolor/)
|
||||
// - Git (https://plugins.jenkins.io/git/)
|
||||
// - Pipeline (https://plugins.jenkins.io/workflow-aggregator/)
|
||||
// - Slack Notification (https://plugins.jenkins.io/slack/)
|
||||
|
||||
def all_models = 'addw2 addw3 addw4 bonw14 bonw15 darp5 darp6 darp7 darp8 darp9 darp10 darp10-b galp3-c galp4 galp5 galp6 galp7 gaze15 gaze16-3050 gaze16-3060 gaze16-3060-b gaze16-3050 gaze16-3060-b gaze17-3050 gaze17-3060-b gaze18 lemp9 lemp10 lemp11 lemp12 lemp13 lemp13-b oryp5 oryp6 oryp7 oryp8 oryp9 oryp10 oryp11 oryp12 serw13'
|
||||
|
||||
void setBuildStatus(String state, String message) {
|
||||
// FIXME: https://www.jenkins.io/doc/book/pipeline/jenkinsfile/#string-interpolation
|
||||
sh """
|
||||
curl \
|
||||
-X POST \
|
||||
-H \'Accept: application/vnd.github+json\' \
|
||||
-H \'Authorization: Bearer ${GITHUB_TOKEN}\' \
|
||||
-H \'X-GitHub-Api-Version: 2022-11-28\' \
|
||||
https://api.github.com/repos/system76/firmware-open/statuses/${GIT_COMMIT} \
|
||||
-d \'{\"state\": \"${state}\", \"target_url\": \"${BUILD_URL}\", \"description\": \"${message}\"}\'
|
||||
"""
|
||||
}
|
||||
|
||||
pipeline {
|
||||
agent {
|
||||
label 'warp.pop-os.org'
|
||||
}
|
||||
|
||||
environment {
|
||||
GITHUB_TOKEN = credentials('github-commit-status')
|
||||
}
|
||||
|
||||
options {
|
||||
buildDiscarder(logRotator(numToKeepStr: '16', artifactNumToKeepStr: '1'))
|
||||
disableConcurrentBuilds()
|
||||
timeout(time: 1, unit: 'HOURS')
|
||||
timestamps()
|
||||
ansiColor('xterm')
|
||||
}
|
||||
|
||||
parameters {
|
||||
string(name: 'MODELS', defaultValue: "$all_models", description: 'Space separated list of models to build', trim: true)
|
||||
string(name: 'SOURCE_BRANCH', defaultValue: 'master', description: 'Git branch or revision to build', trim: true)
|
||||
}
|
||||
|
||||
triggers {
|
||||
pollSCM('')
|
||||
}
|
||||
|
||||
stages {
|
||||
stage('Prepare') {
|
||||
steps {
|
||||
setBuildStatus("pending", "Pending")
|
||||
slackSend(color: "good", message: "${env.JOB_NAME} - #${env.BUILD_ID} started (<${env.BUILD_URL}|Open>)")
|
||||
|
||||
sh """#!/bin/bash
|
||||
# Update submodule URLs because of coreboot
|
||||
git submodule sync --recursive
|
||||
"""
|
||||
|
||||
// https://www.jenkins.io/doc/pipeline/steps/params/scmgit/
|
||||
checkout scmGit(
|
||||
branches: [[name: '${SOURCE_BRANCH}']],
|
||||
extensions: [
|
||||
lfs(),
|
||||
pruneStaleBranch(),
|
||||
pruneTags(true),
|
||||
submodule(
|
||||
parentCredentials: true,
|
||||
recursiveSubmodules: true,
|
||||
reference: ''
|
||||
),
|
||||
],
|
||||
userRemoteConfigs: [[url: 'https://github.com/system76/firmware-open.git']]
|
||||
)
|
||||
|
||||
sh """#!/bin/bash
|
||||
# Install dependencies
|
||||
#./scripts/install-deps.sh
|
||||
. "${HOME}/.cargo/env"
|
||||
|
||||
# Reset
|
||||
git submodule update --init --recursive --checkout
|
||||
git reset --hard
|
||||
git submodule foreach --recursive git reset --hard
|
||||
|
||||
# Clean
|
||||
git clean -dffx
|
||||
git submodule foreach --recursive git clean -dff
|
||||
|
||||
# EDK2 builds fail if file paths in INFs change from what's in the build cache
|
||||
pushd edk2; git clean -dffx; popd
|
||||
"""
|
||||
}
|
||||
}
|
||||
stage('Build') {
|
||||
steps {
|
||||
// The workspace is reused, so must build models sequentially.
|
||||
script {
|
||||
def list = params.MODELS.tokenize()
|
||||
list.each { model ->
|
||||
stage(model) {
|
||||
sh """#!/bin/bash
|
||||
. "${HOME}/.cargo/env"
|
||||
# WORSKSPACE is set by Jenkins, but EDK2 uses it
|
||||
env --unset=WORKSPACE \
|
||||
./scripts/build.sh "${model}"
|
||||
"""
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
post {
|
||||
always {
|
||||
archiveArtifacts artifacts: 'build/*/*', allowEmptyArchive: true
|
||||
}
|
||||
success {
|
||||
setBuildStatus("success", "Successful")
|
||||
slackSend(color: "good", message: "${env.JOB_NAME} - #${env.BUILD_ID} successful after ${currentBuild.durationString} (<${env.BUILD_URL}|Open>)")
|
||||
}
|
||||
failure {
|
||||
setBuildStatus("failure", "Failed")
|
||||
slackSend(color: "danger", message: "${env.JOB_NAME} - #${env.BUILD_ID} failed after ${currentBuild.durationString} (<${env.BUILD_URL}|Open>)")
|
||||
}
|
||||
aborted {
|
||||
setBuildStatus("failure", "Failed")
|
||||
slackSend(color: "warning", message: "${env.JOB_NAME} - #${env.BUILD_ID} aborted after ${currentBuild.durationString} (<${env.BUILD_URL}|Open>)")
|
||||
}
|
||||
}
|
||||
}
|
||||
43
LICENSE.md
43
LICENSE.md
@ -1,43 +0,0 @@
|
||||
# License
|
||||
|
||||
System76 Open Firmware consists of multiple projects under different licenses.
|
||||
|
||||
The source components are made available under the following licenses:
|
||||
|
||||
| Component | License |
|
||||
| --------- | ------- |
|
||||
| coreboot | GPL-2.0-only |
|
||||
| edk2 | BSD-2-Clause-Patent |
|
||||
| firmware-setup | GPL-3.0-only |
|
||||
| ec | GPL-3.0-only |
|
||||
| Intel CSME | Proprietary |
|
||||
| Intel FSP | Proprietary |
|
||||
| Intel microcode | Proprietary |
|
||||
|
||||
## Binaries
|
||||
|
||||
### `ec.rom`
|
||||
|
||||
The license for the embedded controller firmware depends on the binary used.
|
||||
|
||||
- System76 EC firmware: GPL-3.0-only
|
||||
- ODM-provided firmware: Proprietary
|
||||
|
||||
### `firmware.rom`
|
||||
|
||||
`firmware.rom` contains multiple projects under different licenses.
|
||||
|
||||
- coreboot: GPL-2.0-only
|
||||
- edk2-based payload: GPL-3.0-only
|
||||
- Intel binaries: Proprietary
|
||||
|
||||
#### Intel binaries
|
||||
|
||||
Intel provides binaries under a redistributable license, which may be
|
||||
different per binary.
|
||||
|
||||
- `me.rom`: Intel CSME
|
||||
- `Fsp.fd`: [Intel FSP](https://github.com/intel/fsp)
|
||||
- [`FSP_License.pdf`](https://github.com/intel/FSP/blob/master/FSP_License.pdf)
|
||||
- `microcode.rom`: [Intel microcode](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files)
|
||||
- [`license`](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/license)
|
||||
@ -1,49 +0,0 @@
|
||||
Copyright (c) <YEAR>, <COPYRIGHT HOLDERS>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
Subject to the terms and conditions of this license, each copyright holder
|
||||
and contributor hereby grants to those receiving rights under this license
|
||||
a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
(except for failure to satisfy the conditions of this license) patent
|
||||
license to make, have made, use, offer to sell, sell, import, and otherwise
|
||||
transfer this software, where such license applies only to those patent
|
||||
claims, already acquired or hereafter acquired, licensable by such copyright
|
||||
holder or contributor that are necessarily infringed by:
|
||||
|
||||
(a) their Contribution(s) (the licensed copyrights of copyright holders and
|
||||
non-copyrightable additions of contributors, in source or binary form)
|
||||
alone; or
|
||||
|
||||
(b) combination of their Contribution(s) with the work of authorship to
|
||||
which such Contribution(s) was added by such copyright holder or
|
||||
contributor, if, at the time the Contribution is added, such addition
|
||||
causes such combination to be necessarily infringed. The patent license
|
||||
shall not apply to any other combinations which include the
|
||||
Contribution.
|
||||
|
||||
Except as expressly stated above, no rights or licenses from any copyright
|
||||
holder or contributor is granted under this license, whether expressly, by
|
||||
implication, estoppel or otherwise.
|
||||
|
||||
DISCLAIMER
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
@ -1,339 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 2, June 1991
|
||||
|
||||
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The licenses for most software are designed to take away your
|
||||
freedom to share and change it. By contrast, the GNU General Public
|
||||
License is intended to guarantee your freedom to share and change free
|
||||
software--to make sure the software is free for all its users. This
|
||||
General Public License applies to most of the Free Software
|
||||
Foundation's software and to any other program whose authors commit to
|
||||
using it. (Some other Free Software Foundation software is covered by
|
||||
the GNU Lesser General Public License instead.) You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
this service if you wish), that you receive source code or can get it
|
||||
if you want it, that you can change the software or use pieces of it
|
||||
in new free programs; and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to make restrictions that forbid
|
||||
anyone to deny you these rights or to ask you to surrender the rights.
|
||||
These restrictions translate to certain responsibilities for you if you
|
||||
distribute copies of the software, or if you modify it.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must give the recipients all the rights that
|
||||
you have. You must make sure that they, too, receive or can get the
|
||||
source code. And you must show them these terms so they know their
|
||||
rights.
|
||||
|
||||
We protect your rights with two steps: (1) copyright the software, and
|
||||
(2) offer you this license which gives you legal permission to copy,
|
||||
distribute and/or modify the software.
|
||||
|
||||
Also, for each author's protection and ours, we want to make certain
|
||||
that everyone understands that there is no warranty for this free
|
||||
software. If the software is modified by someone else and passed on, we
|
||||
want its recipients to know that what they have is not the original, so
|
||||
that any problems introduced by others will not reflect on the original
|
||||
authors' reputations.
|
||||
|
||||
Finally, any free program is threatened constantly by software
|
||||
patents. We wish to avoid the danger that redistributors of a free
|
||||
program will individually obtain patent licenses, in effect making the
|
||||
program proprietary. To prevent this, we have made it clear that any
|
||||
patent must be licensed for everyone's free use or not licensed at all.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
|
||||
|
||||
0. This License applies to any program or other work which contains
|
||||
a notice placed by the copyright holder saying it may be distributed
|
||||
under the terms of this General Public License. The "Program", below,
|
||||
refers to any such program or work, and a "work based on the Program"
|
||||
means either the Program or any derivative work under copyright law:
|
||||
that is to say, a work containing the Program or a portion of it,
|
||||
either verbatim or with modifications and/or translated into another
|
||||
language. (Hereinafter, translation is included without limitation in
|
||||
the term "modification".) Each licensee is addressed as "you".
|
||||
|
||||
Activities other than copying, distribution and modification are not
|
||||
covered by this License; they are outside its scope. The act of
|
||||
running the Program is not restricted, and the output from the Program
|
||||
is covered only if its contents constitute a work based on the
|
||||
Program (independent of having been made by running the Program).
|
||||
Whether that is true depends on what the Program does.
|
||||
|
||||
1. You may copy and distribute verbatim copies of the Program's
|
||||
source code as you receive it, in any medium, provided that you
|
||||
conspicuously and appropriately publish on each copy an appropriate
|
||||
copyright notice and disclaimer of warranty; keep intact all the
|
||||
notices that refer to this License and to the absence of any warranty;
|
||||
and give any other recipients of the Program a copy of this License
|
||||
along with the Program.
|
||||
|
||||
You may charge a fee for the physical act of transferring a copy, and
|
||||
you may at your option offer warranty protection in exchange for a fee.
|
||||
|
||||
2. You may modify your copy or copies of the Program or any portion
|
||||
of it, thus forming a work based on the Program, and copy and
|
||||
distribute such modifications or work under the terms of Section 1
|
||||
above, provided that you also meet all of these conditions:
|
||||
|
||||
a) You must cause the modified files to carry prominent notices
|
||||
stating that you changed the files and the date of any change.
|
||||
|
||||
b) You must cause any work that you distribute or publish, that in
|
||||
whole or in part contains or is derived from the Program or any
|
||||
part thereof, to be licensed as a whole at no charge to all third
|
||||
parties under the terms of this License.
|
||||
|
||||
c) If the modified program normally reads commands interactively
|
||||
when run, you must cause it, when started running for such
|
||||
interactive use in the most ordinary way, to print or display an
|
||||
announcement including an appropriate copyright notice and a
|
||||
notice that there is no warranty (or else, saying that you provide
|
||||
a warranty) and that users may redistribute the program under
|
||||
these conditions, and telling the user how to view a copy of this
|
||||
License. (Exception: if the Program itself is interactive but
|
||||
does not normally print such an announcement, your work based on
|
||||
the Program is not required to print an announcement.)
|
||||
|
||||
These requirements apply to the modified work as a whole. If
|
||||
identifiable sections of that work are not derived from the Program,
|
||||
and can be reasonably considered independent and separate works in
|
||||
themselves, then this License, and its terms, do not apply to those
|
||||
sections when you distribute them as separate works. But when you
|
||||
distribute the same sections as part of a whole which is a work based
|
||||
on the Program, the distribution of the whole must be on the terms of
|
||||
this License, whose permissions for other licensees extend to the
|
||||
entire whole, and thus to each and every part regardless of who wrote it.
|
||||
|
||||
Thus, it is not the intent of this section to claim rights or contest
|
||||
your rights to work written entirely by you; rather, the intent is to
|
||||
exercise the right to control the distribution of derivative or
|
||||
collective works based on the Program.
|
||||
|
||||
In addition, mere aggregation of another work not based on the Program
|
||||
with the Program (or with a work based on the Program) on a volume of
|
||||
a storage or distribution medium does not bring the other work under
|
||||
the scope of this License.
|
||||
|
||||
3. You may copy and distribute the Program (or a work based on it,
|
||||
under Section 2) in object code or executable form under the terms of
|
||||
Sections 1 and 2 above provided that you also do one of the following:
|
||||
|
||||
a) Accompany it with the complete corresponding machine-readable
|
||||
source code, which must be distributed under the terms of Sections
|
||||
1 and 2 above on a medium customarily used for software interchange; or,
|
||||
|
||||
b) Accompany it with a written offer, valid for at least three
|
||||
years, to give any third party, for a charge no more than your
|
||||
cost of physically performing source distribution, a complete
|
||||
machine-readable copy of the corresponding source code, to be
|
||||
distributed under the terms of Sections 1 and 2 above on a medium
|
||||
customarily used for software interchange; or,
|
||||
|
||||
c) Accompany it with the information you received as to the offer
|
||||
to distribute corresponding source code. (This alternative is
|
||||
allowed only for noncommercial distribution and only if you
|
||||
received the program in object code or executable form with such
|
||||
an offer, in accord with Subsection b above.)
|
||||
|
||||
The source code for a work means the preferred form of the work for
|
||||
making modifications to it. For an executable work, complete source
|
||||
code means all the source code for all modules it contains, plus any
|
||||
associated interface definition files, plus the scripts used to
|
||||
control compilation and installation of the executable. However, as a
|
||||
special exception, the source code distributed need not include
|
||||
anything that is normally distributed (in either source or binary
|
||||
form) with the major components (compiler, kernel, and so on) of the
|
||||
operating system on which the executable runs, unless that component
|
||||
itself accompanies the executable.
|
||||
|
||||
If distribution of executable or object code is made by offering
|
||||
access to copy from a designated place, then offering equivalent
|
||||
access to copy the source code from the same place counts as
|
||||
distribution of the source code, even though third parties are not
|
||||
compelled to copy the source along with the object code.
|
||||
|
||||
4. You may not copy, modify, sublicense, or distribute the Program
|
||||
except as expressly provided under this License. Any attempt
|
||||
otherwise to copy, modify, sublicense or distribute the Program is
|
||||
void, and will automatically terminate your rights under this License.
|
||||
However, parties who have received copies, or rights, from you under
|
||||
this License will not have their licenses terminated so long as such
|
||||
parties remain in full compliance.
|
||||
|
||||
5. You are not required to accept this License, since you have not
|
||||
signed it. However, nothing else grants you permission to modify or
|
||||
distribute the Program or its derivative works. These actions are
|
||||
prohibited by law if you do not accept this License. Therefore, by
|
||||
modifying or distributing the Program (or any work based on the
|
||||
Program), you indicate your acceptance of this License to do so, and
|
||||
all its terms and conditions for copying, distributing or modifying
|
||||
the Program or works based on it.
|
||||
|
||||
6. Each time you redistribute the Program (or any work based on the
|
||||
Program), the recipient automatically receives a license from the
|
||||
original licensor to copy, distribute or modify the Program subject to
|
||||
these terms and conditions. You may not impose any further
|
||||
restrictions on the recipients' exercise of the rights granted herein.
|
||||
You are not responsible for enforcing compliance by third parties to
|
||||
this License.
|
||||
|
||||
7. If, as a consequence of a court judgment or allegation of patent
|
||||
infringement or for any other reason (not limited to patent issues),
|
||||
conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot
|
||||
distribute so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you
|
||||
may not distribute the Program at all. For example, if a patent
|
||||
license would not permit royalty-free redistribution of the Program by
|
||||
all those who receive copies directly or indirectly through you, then
|
||||
the only way you could satisfy both it and this License would be to
|
||||
refrain entirely from distribution of the Program.
|
||||
|
||||
If any portion of this section is held invalid or unenforceable under
|
||||
any particular circumstance, the balance of the section is intended to
|
||||
apply and the section as a whole is intended to apply in other
|
||||
circumstances.
|
||||
|
||||
It is not the purpose of this section to induce you to infringe any
|
||||
patents or other property right claims or to contest validity of any
|
||||
such claims; this section has the sole purpose of protecting the
|
||||
integrity of the free software distribution system, which is
|
||||
implemented by public license practices. Many people have made
|
||||
generous contributions to the wide range of software distributed
|
||||
through that system in reliance on consistent application of that
|
||||
system; it is up to the author/donor to decide if he or she is willing
|
||||
to distribute software through any other system and a licensee cannot
|
||||
impose that choice.
|
||||
|
||||
This section is intended to make thoroughly clear what is believed to
|
||||
be a consequence of the rest of this License.
|
||||
|
||||
8. If the distribution and/or use of the Program is restricted in
|
||||
certain countries either by patents or by copyrighted interfaces, the
|
||||
original copyright holder who places the Program under this License
|
||||
may add an explicit geographical distribution limitation excluding
|
||||
those countries, so that distribution is permitted only in or among
|
||||
countries not thus excluded. In such case, this License incorporates
|
||||
the limitation as if written in the body of this License.
|
||||
|
||||
9. The Free Software Foundation may publish revised and/or new versions
|
||||
of the General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the Program
|
||||
specifies a version number of this License which applies to it and "any
|
||||
later version", you have the option of following the terms and conditions
|
||||
either of that version or of any later version published by the Free
|
||||
Software Foundation. If the Program does not specify a version number of
|
||||
this License, you may choose any version ever published by the Free Software
|
||||
Foundation.
|
||||
|
||||
10. If you wish to incorporate parts of the Program into other free
|
||||
programs whose distribution conditions are different, write to the author
|
||||
to ask for permission. For software which is copyrighted by the Free
|
||||
Software Foundation, write to the Free Software Foundation; we sometimes
|
||||
make exceptions for this. Our decision will be guided by the two goals
|
||||
of preserving the free status of all derivatives of our free software and
|
||||
of promoting the sharing and reuse of software generally.
|
||||
|
||||
NO WARRANTY
|
||||
|
||||
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
|
||||
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
|
||||
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
|
||||
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
|
||||
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
|
||||
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
|
||||
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
|
||||
REPAIR OR CORRECTION.
|
||||
|
||||
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
|
||||
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
|
||||
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
|
||||
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
|
||||
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
|
||||
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
|
||||
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGES.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
convey the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program is interactive, make it output a short notice like this
|
||||
when it starts in an interactive mode:
|
||||
|
||||
Gnomovision version 69, Copyright (C) year name of author
|
||||
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, the commands you use may
|
||||
be called something other than `show w' and `show c'; they could even be
|
||||
mouse-clicks or menu items--whatever suits your program.
|
||||
|
||||
You should also get your employer (if you work as a programmer) or your
|
||||
school, if any, to sign a "copyright disclaimer" for the program, if
|
||||
necessary. Here is a sample; alter the names:
|
||||
|
||||
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
|
||||
`Gnomovision' (which makes passes at compilers) written by James Hacker.
|
||||
|
||||
<signature of Ty Coon>, 1 April 1989
|
||||
Ty Coon, President of Vice
|
||||
|
||||
This General Public License does not permit incorporating your program into
|
||||
proprietary programs. If your program is a subroutine library, you may
|
||||
consider it more useful to permit linking proprietary applications with the
|
||||
library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License.
|
||||
@ -1,674 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to prevent others from denying you
|
||||
these rights or asking you to surrender the rights. Therefore, you have
|
||||
certain responsibilities if you distribute copies of the software, or if
|
||||
you modify it: responsibilities to respect the freedom of others.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must pass on to the recipients the same
|
||||
freedoms that you received. You must make sure that they, too, receive
|
||||
or can get the source code. And you must show them these terms so they
|
||||
know their rights.
|
||||
|
||||
Developers that use the GNU GPL protect your rights with two steps:
|
||||
(1) assert copyright on the software, and (2) offer you this License
|
||||
giving you legal permission to copy, distribute and/or modify it.
|
||||
|
||||
For the developers' and authors' protection, the GPL clearly explains
|
||||
that there is no warranty for this free software. For both users' and
|
||||
authors' sake, the GPL requires that modified versions be marked as
|
||||
changed, so that their problems will not be attributed erroneously to
|
||||
authors of previous versions.
|
||||
|
||||
Some devices are designed to deny users access to install or run
|
||||
modified versions of the software inside them, although the manufacturer
|
||||
can do so. This is fundamentally incompatible with the aim of
|
||||
protecting users' freedom to change the software. The systematic
|
||||
pattern of such abuse occurs in the area of products for individuals to
|
||||
use, which is precisely where it is most unacceptable. Therefore, we
|
||||
have designed this version of the GPL to prohibit the practice for those
|
||||
products. If such problems arise substantially in other domains, we
|
||||
stand ready to extend this provision to those domains in future versions
|
||||
of the GPL, as needed to protect the freedom of users.
|
||||
|
||||
Finally, every program is threatened constantly by software patents.
|
||||
States should not allow patents to restrict development and use of
|
||||
software on general-purpose computers, but in those that do, we wish to
|
||||
avoid the special danger that patents applied to a free program could
|
||||
make it effectively proprietary. To prevent this, the GPL assures that
|
||||
patents cannot be used to render the program non-free.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
License. Each licensee is addressed as "you". "Licensees" and
|
||||
"recipients" may be individuals or organizations.
|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
in a fashion requiring copyright permission, other than the making of an
|
||||
exact copy. The resulting work is called a "modified version" of the
|
||||
earlier work or a work "based on" the earlier work.
|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
feature that (1) displays an appropriate copyright notice, and (2)
|
||||
tells the user that there is no warranty for the work (except to the
|
||||
extent that warranties are provided), that licensees may convey the
|
||||
work under this License, and how to view a copy of this License. If
|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
programs which are used unmodified in performing those activities but
|
||||
which are not part of the work. For example, Corresponding Source
|
||||
includes interface definition files associated with source files for
|
||||
the work, and the source code for shared libraries and dynamically
|
||||
linked subprograms that the work is specifically designed to require,
|
||||
such as by intimate data communication or control flow between those
|
||||
subprograms and other parts of the work.
|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<https://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<https://www.gnu.org/licenses/why-not-lgpl.html>.
|
||||
@ -1,37 +0,0 @@
|
||||
Copyright (c) <YEAR> Intel Corporation.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution.
|
||||
|
||||
Redistribution and use in binary form, without modification, are permitted,
|
||||
provided that the following conditions are met:
|
||||
|
||||
1. Redistributions must reproduce the above copyright notice and the
|
||||
following disclaimer in the documentation and/or other materials provided
|
||||
with the distribution.
|
||||
|
||||
2. Neither the name of Intel Corporation nor the names of its suppliers may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
3. No reverse engineering, decompilation, or disassembly of this software
|
||||
is permitted.
|
||||
|
||||
|
||||
"Binary form" includes any format that is commonly used for electronic
|
||||
conveyance that is a reversible, bit-exact translation of binary
|
||||
representation to ASCII or ISO text, for example "uuencode".
|
||||
|
||||
DISCLAIMER.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
66
README.md
66
README.md
@ -3,10 +3,64 @@
|
||||
An open source distribution of firmware utilizing coreboot, EDK2, and System76
|
||||
firmware applications.
|
||||
|
||||
## Resources
|
||||
## Supported models
|
||||
|
||||
- [Project site](https://github.com/system76/firmware-open)
|
||||
- [Documentation](./docs/index.md)
|
||||
- [Issue tracker](https://github.com/system76/firmware-open/issues/)
|
||||
- [Changelog](./CHANGELOG.md)
|
||||
- [Legal information](./LICENSE.md)
|
||||
These models are supported and will receive updates through the firmware
|
||||
manager:
|
||||
|
||||
- addw2
|
||||
- bonw14
|
||||
- darp6
|
||||
- darp7
|
||||
- galp4
|
||||
- galp5
|
||||
- gaze15
|
||||
- gaze16-3050
|
||||
- gaze16-3060
|
||||
- gaze16-3060-b
|
||||
- lemp9
|
||||
- lemp10
|
||||
- oryp6
|
||||
- oryp7
|
||||
- oryp8
|
||||
|
||||
Other models may be in development or available without support, and can be
|
||||
seen in the `models/` directory.
|
||||
|
||||
If the device becomes bricked it will require restoring the current firmware
|
||||
using an external programmer. See [flashing](./docs/flashing.md) for details.
|
||||
|
||||
### Schematics
|
||||
|
||||
System76 customers may request board schematics for their system by sending an
|
||||
email to firmware@system76.com with the subject line "Schematics for _model_",
|
||||
where _model_ is one of the supported models listed above. Please include the
|
||||
serial number of your system for verification.
|
||||
|
||||
You may not share these without explicit permission from System76.
|
||||
|
||||
## Changelog
|
||||
|
||||
For a list of important changes please see the [changelog](./CHANGELOG.md).
|
||||
|
||||
## Dependencies
|
||||
|
||||
### Install toolchain
|
||||
```
|
||||
./scripts/deps.sh
|
||||
```
|
||||
|
||||
### Load Rust environment (or optionally reboot)
|
||||
```
|
||||
source ~/.cargo/env
|
||||
```
|
||||
|
||||
### Build firmware, replace qemu with your model (look in the models directory for examples)
|
||||
```
|
||||
./scripts/build.sh qemu
|
||||
```
|
||||
|
||||
### Emulate firmware, only available after building the qemu model
|
||||
```
|
||||
./scripts/qemu.sh
|
||||
```
|
||||
|
||||
@ -3,5 +3,6 @@
|
||||
## Contents
|
||||
|
||||
- [firmware-setup](https://github.com/system76/firmware-setup.git) - System76 Firmware Setup
|
||||
- [firmware-smmstore](https://github.com/system76/firmware-smmstore.git) - System76 Firmware SMMSTORE
|
||||
- [firmware-update](https://github.com/system76/firmware-update.git) - System76 Firmware Update
|
||||
- [gop-policy](https://github.com/system76/gop-policy.git) - System76 Platform GOP Policy
|
||||
|
||||
Submodule apps/firmware-setup updated: 769cb382e8...58b2fe3502
1
apps/firmware-smmstore
Submodule
1
apps/firmware-smmstore
Submodule
Submodule apps/firmware-smmstore added at 00c44d42ac
Submodule apps/firmware-update updated: 6bf5268b97...daf5d5074c
Submodule apps/gop-policy updated: 61a9e9fad2...fb2f2c04cb
2
coreboot
2
coreboot
Submodule coreboot updated: d0cab058c6...6ef3822a8d
@ -1,67 +0,0 @@
|
||||
FROM ubuntu:20.04
|
||||
|
||||
# Install most dependencies
|
||||
USER root
|
||||
ARG TZ="America/New_York"
|
||||
ARG DEBIAN_FRONTEND=noninteractive
|
||||
RUN apt-get update && \
|
||||
apt-get upgrade -y && \
|
||||
apt-get install -y --no-install-recommends \
|
||||
adduser \
|
||||
sudo \
|
||||
tzdata \
|
||||
build-essential \
|
||||
ccache \
|
||||
cmake \
|
||||
curl \
|
||||
dosfstools \
|
||||
flashrom \
|
||||
git-lfs \
|
||||
libncurses-dev \
|
||||
libssl-dev \
|
||||
libudev-dev \
|
||||
mtools \
|
||||
parted \
|
||||
pkgconf \
|
||||
python-is-python3 \
|
||||
python3-distutils \
|
||||
uuid-dev \
|
||||
zlib1g-dev \
|
||||
bison \
|
||||
bzip2 \
|
||||
ca-certificates \
|
||||
flex \
|
||||
g++ \
|
||||
gcc \
|
||||
gnat \
|
||||
libnss3-dev \
|
||||
patch \
|
||||
tar \
|
||||
xz-utils \
|
||||
avr-libc \
|
||||
avrdude \
|
||||
clang-format \
|
||||
gcc-avr \
|
||||
libc-dev \
|
||||
libhidapi-dev \
|
||||
libudev-dev \
|
||||
sdcc \
|
||||
shellcheck \
|
||||
xxd
|
||||
|
||||
# Create non-root user with disabled password and sudo privileges
|
||||
ARG USER=docker
|
||||
RUN adduser --disabled-password --gecos '' ${USER}
|
||||
RUN adduser ${USER} sudo
|
||||
RUN echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers
|
||||
|
||||
# Enter build directory in user's home
|
||||
USER ${USER}
|
||||
ARG BUILD_DIR=/home/${USER}/firmware-open
|
||||
WORKDIR ${BUILD_DIR}
|
||||
|
||||
# Set git configuration (required by some scripts)
|
||||
ARG GIT_NAME="Docker User"
|
||||
ARG GIT_EMAIL="docker@gmail.com"
|
||||
RUN git config --global user.name "${GIT_NAME}"
|
||||
RUN git config --global user.email "${GIT_EMAIL}"
|
||||
1
docs/README.md
Normal file
1
docs/README.md
Normal file
@ -0,0 +1 @@
|
||||
# System76 Open Firmware Documentation
|
||||
@ -1,11 +0,0 @@
|
||||
# Summary
|
||||
|
||||
- [Index](./index.md)
|
||||
- [Firmware features](./features.md)
|
||||
- [Building firmware](./building.md)
|
||||
- [Flashing firmware](./flashing.md)
|
||||
- [Debugging](./debugging.md)
|
||||
- [Adding a new board](./adding-a-new-board.md)
|
||||
- [Intel CSME](./intel-me.md)
|
||||
- [UEFI](./uefi.md)
|
||||
- [Schematics](./schematics.md)
|
||||
@ -61,39 +61,22 @@ If the microcode blobs from coreboot will not be used, then `microcode.rom`
|
||||
must be generated for the correct CPU set from the private [intel-microcode]
|
||||
repo.
|
||||
|
||||
Other things that should be dumped before porting/flashing are:
|
||||
|
||||
- The kernel log (`dmesg`)
|
||||
- DMI info (`dmidecode`)
|
||||
- ACPI tables (`acpidump -b`)
|
||||
|
||||
## Porting coreboot
|
||||
|
||||
To port coreboot to a new board, see the coreboot documentation.
|
||||
|
||||
Add a `coreboot.config` file to the model directory. This can be copied from
|
||||
another similar board as a reference, just updating the name. Typically, the
|
||||
only special cases that need to be handled are when an FSP or microcode is
|
||||
used that are not part of coreboot.
|
||||
- [TAS5825M] smart amp
|
||||
|
||||
### Smart amp
|
||||
Once coreboot is ported, add its configuration.
|
||||
|
||||
Boards may have a smart amp, which must be configured for speaker output to
|
||||
work.
|
||||
```
|
||||
cp coreboot/.config models/<model>/coreboot.config
|
||||
```
|
||||
|
||||
The initialization data for Realtek smart amps can be dumped from the module
|
||||
that does the codec init in proprietary firmware. The correct module can be
|
||||
found using UEFITool by searching for the vendor/device ID of the codec, such
|
||||
as "10ec1220" for the ALC1220. This is the start of the `cim_verb_data` array
|
||||
in coreboot.
|
||||
### devicetree
|
||||
|
||||
For info on the TI TAS5825M smart amp, see the [smart-amp] repo.
|
||||
|
||||
## Configuring Intel CSME
|
||||
|
||||
The CSME image may need to be regenerated. Common changes that may be required
|
||||
are disabling Platform Trust Technology (PTT) so the discrete TPM device will
|
||||
work, and changing the Boot Guard profile to disable verified boot.
|
||||
`generate.sh` does not create `devicetree.cb`. Some values for this file can be
|
||||
produced using the `devicetree.py` script.
|
||||
|
||||
## Porting System76 EC
|
||||
|
||||
@ -111,4 +94,4 @@ READMEs.
|
||||
[external-programmer]: ./flashing.md#external-programmer
|
||||
[intel-microcode]: https://github.com/system76/intel-microcode
|
||||
[mega2560]: https://github.com/system76/ec/blob/master/doc/mega2560.md
|
||||
[smart-amp]: https://github.com/system76/smart-amp
|
||||
[TAS5825M]: https://github.com/system76/smart-amp
|
||||
|
||||
@ -1,18 +0,0 @@
|
||||
[book]
|
||||
title = "System76 Open Firmware"
|
||||
description = "System76 Open Firmware documentation"
|
||||
language = "en"
|
||||
src = "."
|
||||
|
||||
[build]
|
||||
build-dir = "../build/docs"
|
||||
create-missing = false
|
||||
|
||||
[output.html]
|
||||
default-theme = "rust"
|
||||
preferred-dark-theme = "coal"
|
||||
no-section-label = true
|
||||
git-repository-url = "https://github.com/system76/firmware-open"
|
||||
|
||||
[output.html.print]
|
||||
enable = false
|
||||
@ -1,31 +0,0 @@
|
||||
# Building
|
||||
|
||||
Dependencies can be installed with the provided script.
|
||||
|
||||
```
|
||||
./scripts/install-deps.sh
|
||||
```
|
||||
|
||||
If rustup was installed for the first time, it will be required to source the
|
||||
environment file it installed to use the correct Rust toolchain.
|
||||
|
||||
```
|
||||
. ~/.cargo/env
|
||||
```
|
||||
|
||||
A script is provided to build the firmware. The available targets for building
|
||||
are the model folders in `models/`. For example, to build for QEMU:
|
||||
|
||||
```
|
||||
./scripts/build.sh qemu
|
||||
```
|
||||
|
||||
Once built, the firmware must be flashed to use. Several scripts are available
|
||||
to flash the new firmware, depending on how it is going to be written.
|
||||
|
||||
- `scripts/qemu.sh`: [Run the firmware in QEMU](./debugging.md#using-qemu) (specific to the QEMU model)
|
||||
- `scripts/flash.sh`: Flash using firmware-update
|
||||
- `scripts/ch341a-flash.sh`: Flash using a CH341A programmer
|
||||
- `scripts/spipi-flash.sh`: Flash using a Raspberry Pi
|
||||
|
||||
See [Flashing firmware](./flashing.md) for more details.
|
||||
@ -1,97 +0,0 @@
|
||||
# Debugging
|
||||
|
||||
## Component
|
||||
|
||||
### coreboot
|
||||
|
||||
coreboot debug logging is enabled by default at the level of `Debug`. This can
|
||||
be changed using `nvramtool` to set the CMOS option `debug_level`.
|
||||
|
||||
```
|
||||
sudo nvramtool -w debug_level=<level>
|
||||
```
|
||||
|
||||
Available log levels are:
|
||||
|
||||
- Emergency
|
||||
- Alert
|
||||
- Critical
|
||||
- Error
|
||||
- Warning
|
||||
- Notice
|
||||
- Info
|
||||
- Debug
|
||||
- Spew
|
||||
|
||||
### edk2
|
||||
|
||||
Modify `./scripts/_build/edk2.sh` so `BUILD_TYPE` is set to `DEBUG` instead of
|
||||
`RELEASE`.
|
||||
|
||||
```sh
|
||||
#BUILD_TYPE=RELEASE
|
||||
BUILD_TYPE=DEBUG
|
||||
```
|
||||
|
||||
The default PCD values are used, so a lot of ouput will be generated. This can
|
||||
have a significant impact on the boot time.
|
||||
|
||||
This also unconditionally enables asserts, so any failures will result in edk2
|
||||
hanging and require a reflash to fix.
|
||||
|
||||
### Rust UEFI apps
|
||||
|
||||
Debug logging can be enabled in the Rust UEFI apps (e.g., `firmware-setup`) by
|
||||
selecting the `debug` feature in `Cargo.toml`.
|
||||
|
||||
## Method
|
||||
|
||||
A couple of methods can be used to get debug logging.
|
||||
|
||||
### Parallel port
|
||||
|
||||
This method requires no soldering of board components.
|
||||
|
||||
See [Debugging the EC firmware](https://github.com/system76/ec/blob/master/docs/debugging.md)
|
||||
for details on setting up EC debugging over the parallel port.
|
||||
|
||||
cbmem output can be passed through the EC by enabling the driver in coreboot.
|
||||
Uncomment the config in `models/<model>/coreboot.config` to enable logging the
|
||||
cbmem console through the EC.
|
||||
|
||||
```
|
||||
CONFIG_CONSOLE_SYSTEM76_EC=y
|
||||
```
|
||||
|
||||
edk2 output can be passed through as well by enabling the driver in edk2.
|
||||
This causes boot to be *very* slow, as edk2 generates a lot of output.
|
||||
Uncomment the config in `models/<model>/edk2.config` to enable the driver.
|
||||
|
||||
```
|
||||
SYSTEM76_EC_LOGGING=TRUE
|
||||
```
|
||||
|
||||
### Using QEMU
|
||||
|
||||
A `qemu` target is provided to allow development and debugging in a VM.
|
||||
|
||||
```
|
||||
./scripts/build.sh qemu
|
||||
```
|
||||
|
||||
Install QEMU:
|
||||
|
||||
```sh
|
||||
# Arch
|
||||
sudo pacman -S qemu
|
||||
# Fedora
|
||||
sudo dnf install qemu-system-x86
|
||||
# Ubuntu
|
||||
sudo apt install qemu-system-x86
|
||||
```
|
||||
|
||||
And run the image in a VM:
|
||||
|
||||
```
|
||||
./scripts/qemu.sh
|
||||
```
|
||||
190
docs/features.md
190
docs/features.md
@ -1,190 +0,0 @@
|
||||
# System76 Open Firmware Feature Matrix
|
||||
|
||||
This lists important features provided by System76 Open Firmware. Your system
|
||||
must be updated to at least the firmware version specified in the following
|
||||
[platform tables](#platforms) to include all specified [features](#features).
|
||||
To see the changes in specific firmware versions, see the
|
||||
[changelog](./../CHANGELOG.md).
|
||||
|
||||
## Platforms
|
||||
|
||||
- [Intel 13th Gen (Raptor Lake)](#intel-13th-gen-raptor-lake)
|
||||
- [Intel 12th Gen (Alder Lake)](#intel-12th-gen-alder-lake)
|
||||
- [Intel 11th Gen (Tiger Lake)](#intel-11th-gen-tiger-lake)
|
||||
- [Intel 10th Gen (Comet Lake)](#intel-10th-gen-comet-lake)
|
||||
|
||||
### Intel 13th Gen (Raptor Lake)
|
||||
|
||||
This generation universally supports these features with up-to-date firmware:
|
||||
|
||||
- [Intel VT-x](#intel-vt-x)
|
||||
- [Intel VT-d](#intel-vt-d)
|
||||
- [Disabled Management Engine](#disabled-management-engine)
|
||||
- [TPM 2.0 Support](#tpm-20-support)
|
||||
- [Battery Charging Thresholds](#battery-charging-thresholds)
|
||||
- [Keyboard Customization](#keyboard-customization)
|
||||
- [Measured Boot](#measured-boot)
|
||||
- [Firmware Security System](#firmware-security-system)
|
||||
- [Secure Boot Support](#secure-boot-support)
|
||||
|
||||
| System76 Model (Version) | Firmware Version | SoC | [Windows 11 Support](#windows-11-support) | [NVIDIA Dynamic Boost](#nvidia-dynamic-boost) |
|
||||
|--------------------------|---------------------|--------|-----|-----|
|
||||
| Adder WS (addw3) | 2023-05-17\_9560b2e | RPL-HX | ✔ | ✔ |
|
||||
| Bonobo WS (bonw15) | 2023-07-10\_0e4a64a | RPL-HX | ✔ | ✔ |
|
||||
| Darter Pro (darp9) | 2023-06-08\_a8590a5 | RPL-P | ✔ | N/A |
|
||||
| Galago Pro (galp7) | 2023-05-25\_5608a8d | RPL-H | ✔ | N/A |
|
||||
| Gazelle (gaze18) | 2023-03-22\_799ed79 | RPL-H | ✔ | ✔ |
|
||||
| Lemur Pro (lemp12) | 2023-05-16\_e9b9ea8 | RPL-U | ✔ | N/A |
|
||||
| Oryx Pro (oryp11) | 2023-06-22\_e5c3632 | RPL-H | ✔ | ✔ |
|
||||
| Serval WS (serw13) | 2023-05-17\_9560b2e | RPL-HX | ✔ | ✔ |
|
||||
|
||||
### Intel 12th Gen (Alder Lake)
|
||||
|
||||
This generation universally supports these features with up-to-date firmware:
|
||||
|
||||
- [Intel VT-x](#intel-vt-x)
|
||||
- [Intel VT-d](#intel-vt-d)
|
||||
- [TPM 2.0 Support](#tpm-20-support)
|
||||
- [Battery Charging Thresholds](#battery-charging-thresholds)
|
||||
- [Keyboard Customization](#keyboard-customization)
|
||||
- [Measured Boot](#measured-boot)
|
||||
|
||||
| System76 Model (Version) | Firmware Version | SoC |
|
||||
|--------------------------|---------------------|--------|
|
||||
| Darter Pro (darp8) | 2022-11-21\_b337ac6 | ADL-P |
|
||||
| Galago Pro (galp6) | 2022-11-21\_b337ac6 | ADL-P |
|
||||
| Gazelle (gaze17-3050) | 2022-11-21\_b337ac6 | ADL-H |
|
||||
| Gazelle (gaze17-3060-b) | 2022-06-07\_090f9e0 | ADL-H |
|
||||
| Lemur Pro (lemp11) | 2022-11-21\_b337ac6 | ADL-U |
|
||||
| Oryx Pro (oryp9) | 2022-07-20\_ae6aa72 | ADL-H |
|
||||
| Oryx Pro (oryp10) | 2022-09-26\_aa797d2 | ADL-H |
|
||||
|
||||
### Intel 11th Gen (Tiger Lake)
|
||||
|
||||
This generation universally supports these features with up-to-date firmware:
|
||||
|
||||
- [Intel VT-x](#intel-vt-x)
|
||||
- [Intel VT-d](#intel-vt-d)
|
||||
- [TPM 2.0 Support](#tpm-20-support)
|
||||
- [Battery Charging Thresholds](#battery-charging-thresholds)
|
||||
- [Keyboard Customization](#keyboard-customization)
|
||||
|
||||
| System76 Model (Version) | Firmware Version | SoC | [Measured Boot](#measured-boot) |
|
||||
|--------------------------|---------------------|--------|----|
|
||||
| Darter Pro (darp7) | 2022-11-21\_b337ac6 | TGL-U | ✔️ |
|
||||
| Galago Pro (galp5) | 2022-11-21\_b337ac6 | TGL-U | ✔️ |
|
||||
| Gazelle (gaze16-3050) | 2022-11-21\_b337ac6 | TGL-H | ✔️ |
|
||||
| Gazelle (gaze16-3060) | 2021-09-30\_14b8a6e | TGL-H | ❌ |
|
||||
| Gazelle (gaze16-3060-b) | 2021-11-01\_fb9d759 | TGL-H | ❌ |
|
||||
| Lemur Pro (lemp10) | 2022-11-21\_b337ac6 | TGL-U | ✔️ |
|
||||
| Oryx Pro (oryp8) | 2022-10-14\_4136ef8 | TGL-H | ✔️ |
|
||||
|
||||
### Intel 10th Gen (Comet Lake)
|
||||
|
||||
This generation universally supports these features with up-to-date firmware:
|
||||
|
||||
- [Intel VT-x](#intel-vt-x)
|
||||
- [Intel VT-d](#intel-vt-d)
|
||||
- [Disabled Management Engine](#disabled-management-engine)
|
||||
- [TPM 2.0 Support](#tpm-20-support)
|
||||
- [Battery Charging Thresholds](#battery-charging-thresholds)
|
||||
- [Keyboard Customization](#keyboard-customization)
|
||||
|
||||
| System76 Model (Version) | Firmware Version | SoC | [Measured Boot](#measured-boot) |
|
||||
|--------------------------|---------------------|--------|----|
|
||||
| Adder WS (addw2) | 2022-11-21\_b337ac6 | CML-H | ✔️ |
|
||||
| Bonobo WS (bonw14) | 2021-07-20\_93c2809 | CML-S | ❌ |
|
||||
| Darter Pro (darp6) | 2021-07-20\_93c2809 | CML-U | ❌ |
|
||||
| Gazelle (gaze15) | 2022-11-21\_b337ac6 | CML-H | ✔️ |
|
||||
| Lemur Pro (lemp9) | 2021-07-20\_93c2809 | CML-U | ❌ |
|
||||
| Oryx Pro (oryp6) | 2021-07-20\_93c2809 | CML-H | ❌ |
|
||||
| Oryx Pro (oryp7) | 2022-11-21\_b337ac6 | CML-H | ✔️ |
|
||||
|
||||
## Features
|
||||
|
||||
### Intel VT-x
|
||||
|
||||
Intel Virtualization Technology is enabled, which provides support for high
|
||||
performance virtual machines.
|
||||
|
||||
### Intel VT-d
|
||||
|
||||
Intel Virtualization Technology for Directed I/O is enabled, which provides
|
||||
support for passing PCIe devices to virtual machines, and for protecting against
|
||||
PCIe device craches and DMA attacks.
|
||||
|
||||
### Disabled Management Engine
|
||||
|
||||
The Intel Management Engine is disabled at runtime to improve security.
|
||||
|
||||
### TPM 2.0 Support
|
||||
|
||||
**Introduced in firmware version 2020-08-13.**
|
||||
|
||||
A discrete TPM 2.0 is available for use.
|
||||
|
||||
### Battery Charging Thresholds
|
||||
|
||||
**Introduced in firmware version 2020-10-19.**
|
||||
|
||||
Battery charging thresholds extend the life of the battery by reducing the
|
||||
maximum charge that the battery is charged to, as well as the minimum charge
|
||||
when charging the battery begins.
|
||||
|
||||
### Keyboard Customization
|
||||
|
||||
**Introduced in firmware version 2020-10-19.**
|
||||
|
||||
Keyboard customization allows the keyboard layout to be modified at runtime
|
||||
using the
|
||||
[System76 Keyboard Configurator](https://github.com/pop-os/keyboard-configurator/).
|
||||
|
||||
### Measured Boot
|
||||
|
||||
**Introduced in firmware version 2022-01-06.**
|
||||
|
||||
Measured boot uses the TPM to maintain hashes of all binaries used in the boot
|
||||
process. This allows for detecting changes to the firmware, which can be used
|
||||
by a system such as TPM2-TOTP or BitLocker to improve security.
|
||||
|
||||
### Firmware Security System
|
||||
|
||||
**Introduced in firmware version 2023-04-03.**
|
||||
|
||||
The firmware security system ensures both SoC and EC firmware is read-only at
|
||||
runtime. Unlocking the firmware requires the system to reboot and physical
|
||||
presence is required. The user must enter in a secure, randomly generated number
|
||||
before the system can boot any third-party code while unlocked. Both EC firmware
|
||||
and system firmware are locked on any boots where the prompt is not shown. For
|
||||
screenshots showing this prompt, see the pull request here:
|
||||
https://github.com/system76/firmware-setup/pull/18
|
||||
|
||||
### Secure Boot Support
|
||||
|
||||
**Introduced in firmware version 2023-04-03.**
|
||||
|
||||
A new firmware setup menu allows enabling and disabling Secure Boot and also
|
||||
allows for entering setup mode for custom key enrollment. Work is being done in
|
||||
Pop!\_OS to enable the use of custom secure boot keys, in addition to adding
|
||||
TPM2-TOTP authentication of the firmware boot path. For screenshots showing the
|
||||
new menus, see the pull request here:
|
||||
https://github.com/system76/edk2/pull/38
|
||||
|
||||
### Windows 11 Support
|
||||
|
||||
**Introduced in firmware version 2023-04-03.**
|
||||
|
||||
Windows 11 requires [TPM 2.0 Support](#tpm-20-support) and
|
||||
[Secure Boot Support](#secure-boot-support). For users wanting to use Windows, the use of Windows 11 is
|
||||
recommended for Intel 12th Generation (Alder Lake) and newer systems, as it
|
||||
includes a new scheduler that supports the efficiency cores.
|
||||
|
||||
### NVIDIA Dynamic Boost
|
||||
|
||||
**Introduced in firmware version 2023-04-03.**
|
||||
|
||||
On new systems with the NVIDIA 4000 series GPUs, NVIDIA Dynamic Boost has been
|
||||
enabled with new code in coreboot. This allows power to be shared between the
|
||||
CPU and GPU, diverting power to the subsystem that needs it most. This can
|
||||
provide an additional 25W boost split between the CPU and GPU depending on the
|
||||
task, significantly improving throughput and framerates.
|
||||
@ -13,44 +13,16 @@ coreboot's `cbmem` tool can be used to verify this. The call to
|
||||
`FspMemoryInit()` can report 20+ seconds on the first boot, and a few hundred
|
||||
milliseconds on subsequent boots.
|
||||
|
||||
## UEFI application
|
||||
|
||||
This is the default method for flashing firmware (using firmware-update). When
|
||||
used from this repo, it only works with systems running System76 open firmware.
|
||||
|
||||
```
|
||||
./scripts/flash.sh <model>
|
||||
```
|
||||
|
||||
By default the script will attempt to flash both the BIOS and the EC. Their
|
||||
respective file can be deleted to skip flashing them.
|
||||
|
||||
If the EC is flashed, the system will immediately power off.
|
||||
|
||||
## Internal programmer
|
||||
|
||||
### Availability
|
||||
|
||||
This method is only possible when firmware is unlocked. Firmware is unlocked by
|
||||
one of two methods:
|
||||
|
||||
- The EC feature `CONFIG_SECURITY` is unset/disabled
|
||||
- The EC is unlock for a single boot (via firmware-update or ectool)
|
||||
|
||||
The current state can be determined using ectool:
|
||||
Use this method for flashing a system already running System76 Open Firmware.
|
||||
|
||||
```
|
||||
./ec/scripts/ectool.sh security
|
||||
./scripts/flash.sh <model> [--without-ec]
|
||||
```
|
||||
|
||||
- `Lock`: This method can't be used
|
||||
- `Unlock`: This method can be used
|
||||
|
||||
### flashrom
|
||||
|
||||
```
|
||||
sudo flashrom -p internal -w build/<model>/firmware.rom
|
||||
```
|
||||
By default the script will attempt to flash the EC. If the EC is flashed, the
|
||||
system will immediately power off.
|
||||
|
||||
## External programmer
|
||||
|
||||
@ -59,14 +31,13 @@ Use one of these methods for first-time flashing or flashing a bricked system.
|
||||
### Identifying the BIOS chip
|
||||
|
||||
The packaging and protocol can be determined by `board_info.txt` in coreboot.
|
||||
Pin 1 is sometimes marked by a small dot indent and a white paint mark. The
|
||||
silkscreen may also indicate pin 1.
|
||||
Laptops use a SOIC-8 package for the SPI flash ROM. Pin 1 is marked by a small
|
||||
dot indent and a white paint mark. The silkscreen may also indicate pin 1.
|
||||
|
||||
### CH341A USB programmer - slower, but easier to set up
|
||||
|
||||
These can be purchased from many places for around 15 USD. Make sure that the
|
||||
one you get has a ROM clip. Here are some examples:
|
||||
|
||||
- [Amazon.com, Organizer.](https://www.amazon.com/Organizer-Socket-Adpter-Programmer-CH341A/dp/B07R5LPTYM)
|
||||
- [Amazon.com, KeeYees.](https://www.amazon.com/KeeYees-SOIC8-EEPROM-CH341A-Programmer/dp/B07SHSL9X9)
|
||||
- [AliExpress.com, TZT.](https://aliexpress.com/item/32725360255.html)
|
||||
|
||||
@ -1,9 +0,0 @@
|
||||
# Documentation
|
||||
|
||||
This is the documentation for System76 Open Firmware. It is set up to be used
|
||||
with [mdBook](https://github.com/rust-lang/mdBook), which can generate HTML
|
||||
output for easy navigation.
|
||||
|
||||
```
|
||||
mdbook build --open docs/
|
||||
```
|
||||
@ -27,46 +27,15 @@ A restart is required for the change to take effect. On the boot after changing
|
||||
the value, the system will perform a global reset (power off again) to complete
|
||||
the change and ensure the IME is operating in a valid state.
|
||||
|
||||
### Checking the state
|
||||
## Tiger Lake-U
|
||||
|
||||
coreboot will log some IME data to cbmem during startup. This can be used to
|
||||
check if it is in the correct state.
|
||||
|
||||
```
|
||||
make -C coreboot/util/cbmem
|
||||
sudo ./coreboot/util/cbmem/cbmem -c
|
||||
```
|
||||
|
||||
When disabled it will report:
|
||||
|
||||
```
|
||||
ME: Current Working State : 4
|
||||
ME: Current Operation State : 1
|
||||
ME: Current Operation Mode : 3
|
||||
ME: Error Code : 2
|
||||
```
|
||||
|
||||
When enabled it will report:
|
||||
|
||||
```
|
||||
ME: Current Working State : 5
|
||||
ME: Current Operation State : 1
|
||||
ME: Current Operation Mode : 0
|
||||
ME: Error Code : 0
|
||||
```
|
||||
|
||||
## S0ix
|
||||
|
||||
S0ix (Modern Standby, s2idle) requires all CPU, PCH, and PCIe devices to have
|
||||
ACPI defined low power states. The CPU has numerous states for low power, with
|
||||
the lowest being C10. In order to reach this C10 state, the CSME must report
|
||||
that it is in a low power state.
|
||||
|
||||
Disabling the CSME with the HAP bit or HECI command keeps the CPU in the C8
|
||||
state. This nearly triples the power usage in S0ix suspend, from around 1 watt
|
||||
to around 3 watts.
|
||||
|
||||
TGL-U removed support for S3 and requires S0ix.
|
||||
Models using TGL-U processors default to having the IME enabled. TGL-U removes
|
||||
support for S3 and requires S0ix. This requires all CPU, PCH, and PCIe devices
|
||||
to have ACPI defined low power states. With S0ix, the CPU has numerous states
|
||||
for low power, with the lowest being C10. In order to reach this C10 state, the
|
||||
IME must report that it is in a low power state. Disabling the ME with the HAP
|
||||
bit keeps the CPU in the C8 state. This nearly triples the power usage in S0ix
|
||||
suspend, from around 1 watt to around 3 watts.
|
||||
|
||||
|
||||
[wiki]: https://en.wikipedia.org/wiki/Intel_Management_Engine
|
||||
|
||||
@ -1,18 +0,0 @@
|
||||
# Schematics
|
||||
|
||||
## Systems using System76 Open Firmware
|
||||
|
||||
System76 customers may request board schematics for their system by sending an
|
||||
email to `firmware@system76.com` with the subject line:
|
||||
|
||||
> Schematics for <model>
|
||||
|
||||
where `<model>` is a model that uses firmware-open. Include the serial number
|
||||
of your system for verification.
|
||||
|
||||
You may not share these without explicit permission from System76.
|
||||
|
||||
## Other models and components
|
||||
|
||||
System76 cannot provide schematics for models not using firmware-open, nor
|
||||
datasheets for any components that are not already publicly available.
|
||||
11
docs/uefi.md
11
docs/uefi.md
@ -14,15 +14,12 @@ Network functionality is disabled. Native PXE booting is not supported.
|
||||
|
||||
### Secure Boot
|
||||
|
||||
Secure Boot support is enabled since system76/firmware-open@105e74b14613
|
||||
(2023-04-03).
|
||||
Secure Boot support is currently disabled.
|
||||
|
||||
A minimal firmware UI is available to delete all keys and enroll the default
|
||||
keys. It is intended that most management is done from the OS.
|
||||
The implementation from 9elements is in development. If building a custom
|
||||
image, the edk2 config `SECURE_BOOT_ENABLE` can be set to enable support.
|
||||
|
||||
Note that the Secure Boot support present is only intended for allowing
|
||||
Microsoft Windows installation checks to pass. It should not be relied on for
|
||||
system security due to limitations of the implementation.
|
||||
There is currently no firmware UI to view or configure Secure Boot.
|
||||
|
||||
## Shell
|
||||
|
||||
|
||||
2
ec
2
ec
Submodule ec updated: e41716575c...55a617f2e0
2
edk2
2
edk2
Submodule edk2 updated: 9ca522ba15...a2abc5e15f
1
edk2-non-osi
Submodule
1
edk2-non-osi
Submodule
Submodule edk2-non-osi added at 88ec4bf04c
1
edk2-platforms
Submodule
1
edk2-platforms
Submodule
Submodule edk2-platforms added at 3176197844
File diff suppressed because it is too large
Load Diff
BIN
fsp/mtl/4122.12/MeteorLakeFspBinPkg/Fsp.fd
(Stored with Git LFS)
BIN
fsp/mtl/4122.12/MeteorLakeFspBinPkg/Fsp.fd
(Stored with Git LFS)
Binary file not shown.
@ -1,114 +0,0 @@
|
||||
## @file
|
||||
# Platform description for DynamicEx PCDs, defined in FSP Package
|
||||
# and shared with Board Package.
|
||||
#
|
||||
# @copyright
|
||||
# INTEL CONFIDENTIAL
|
||||
# Copyright 2018 - 2021 Intel Corporation.
|
||||
#
|
||||
# The source code contained or described herein and all documents related to the
|
||||
# source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
# licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
# and licensors. The Material may contain trade secrets and proprietary and
|
||||
# confidential information of Intel Corporation and its suppliers and licensors,
|
||||
# and is protected by worldwide copyright and trade secret laws and treaty
|
||||
# provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
# without Intel's prior express written permission.
|
||||
#
|
||||
# No license under any patent, copyright, trade secret or other intellectual
|
||||
# property right is granted to or conferred upon you by disclosure or delivery
|
||||
# of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
# otherwise. Any license under such intellectual property rights must be
|
||||
# express and approved by Intel in writing.
|
||||
#
|
||||
# Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
# this notice or any other notice embedded in Materials by Intel or
|
||||
# Intel's suppliers or licensors in any way.
|
||||
#
|
||||
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
# the terms of your license agreement with Intel or your vendor. This file may
|
||||
# be modified by the user, subject to additional terms of the license agreement.
|
||||
#
|
||||
# @par Specification
|
||||
##
|
||||
|
||||
[PcdsDynamicExDefault]
|
||||
|
||||
## Specifies max supported number of Logical Processors.
|
||||
# @Prompt Configure max supported number of Logical Processorss
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
|
||||
|
||||
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xC0000000
|
||||
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
|
||||
|
||||
## Specifies the base address of the first microcode Patch in the microcode Region.
|
||||
# @Prompt Microcode Region base address.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0
|
||||
|
||||
## Specifies the size of the microcode Region.
|
||||
# @Prompt Microcode Region size.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0
|
||||
|
||||
## Specifies the AP wait loop state during POST phase.
|
||||
# The value is defined as below.
|
||||
# 1: Place AP in the Hlt-Loop state.
|
||||
# 2: Place AP in the Mwait-Loop state.
|
||||
# 3: Place AP in the Run-Loop state.
|
||||
# @Prompt The AP wait loop state.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
|
||||
|
||||
## Specifies the AP target C-state for Mwait during POST phase.
|
||||
# The default value 0 means C1 state.
|
||||
# The value is defined as below.<BR><BR>
|
||||
# @Prompt The specified AP target C-state for Mwait.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
|
||||
|
||||
#
|
||||
# Enable ACPI S3 support in FSP by default
|
||||
#
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1
|
||||
|
||||
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
|
||||
# @Prompt The pointer to a CPU S3 data buffer.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00
|
||||
|
||||
## As input, specifies user's desired settings for enabling/disabling processor features.
|
||||
## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
|
||||
# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
||||
|
||||
## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
|
||||
# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
|
||||
# @Prompt The memory size used for processor trace if processor trace is enabled.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0
|
||||
|
||||
## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
|
||||
# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
|
||||
# @Prompt The processor trace output scheme used when processor trace is enabled.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0
|
||||
|
||||
## Indicates processor feature capabilities, each bit corresponding to a specific feature.
|
||||
# @Prompt Processor feature capabilities.
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
||||
|
||||
# Set SEV-ES defaults
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0
|
||||
|
||||
## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library
|
||||
# instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
|
||||
# only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
|
||||
# default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
|
||||
# @Prompt S3 Boot Script Table Private Data pointer.
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
|
||||
|
||||
## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library
|
||||
# instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
|
||||
# only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
|
||||
# default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
|
||||
# @Prompt S3 Boot Script Table Private Smm Data pointer.
|
||||
# @ValidList 0x80000001 | 0x0
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0
|
||||
@ -1,55 +0,0 @@
|
||||
/** @file
|
||||
Intel Firmware Version Info (FVI) related definitions.
|
||||
|
||||
@todo update document/spec reference
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
@par Specification Reference:
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FIRMWARE_VERSION_INFO_H__
|
||||
#define __FIRMWARE_VERSION_INFO_H__
|
||||
|
||||
#include <IndustryStandard/SmBios.h>
|
||||
|
||||
#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info"
|
||||
#define INTEL_FVI_SMBIOS_TYPE 0xDD
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
///
|
||||
/// Firmware Version Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 MajorVersion;
|
||||
UINT8 MinorVersion;
|
||||
UINT8 Revision;
|
||||
UINT16 BuildNumber;
|
||||
} INTEL_FIRMWARE_VERSION;
|
||||
|
||||
///
|
||||
/// Firmware Version Info (FVI) Structure
|
||||
///
|
||||
typedef struct {
|
||||
SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name
|
||||
SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String
|
||||
INTEL_FIRMWARE_VERSION Version; ///< Firmware version
|
||||
} INTEL_FIRMWARE_VERSION_INFO;
|
||||
|
||||
///
|
||||
/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
|
||||
///
|
||||
typedef struct {
|
||||
SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
|
||||
UINT8 Count; ///< Number of FVI entries in this structure
|
||||
INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
|
||||
} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@ -1,80 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
**/
|
||||
#ifndef _FSP_PRODUCER_DATA_HEADER_H_
|
||||
#define _FSP_PRODUCER_DATA_HEADER_H_
|
||||
|
||||
#include <Guid/FspHeaderFile.h>
|
||||
|
||||
#define BUILD_TIME_STAMP_SIZE 12
|
||||
|
||||
//
|
||||
// FSP Header Data structure from FspHeader driver.
|
||||
//
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// FSP Producer Data Subtype - 1
|
||||
///
|
||||
typedef struct {
|
||||
///
|
||||
/// Byte 0x00: Length of this FSP producer data type record.
|
||||
///
|
||||
UINT16 Length;
|
||||
///
|
||||
/// Byte 0x02: FSP producer data type.
|
||||
///
|
||||
UINT8 Type;
|
||||
///
|
||||
/// Byte 0x03: Revision of this FSP producer data type.
|
||||
///
|
||||
UINT8 Revision;
|
||||
///
|
||||
/// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
|
||||
///
|
||||
UINT32 RcVersion;
|
||||
///
|
||||
/// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
|
||||
///
|
||||
UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
|
||||
} FSP_PRODUCER_DATA_TYPE1;
|
||||
|
||||
///
|
||||
/// FSP Producer Data Subtype - 2
|
||||
///
|
||||
typedef struct {
|
||||
///
|
||||
/// Byte 0x00: Length of this FSP producer data type record.
|
||||
///
|
||||
UINT16 Length;
|
||||
///
|
||||
/// Byte 0x02: FSP producer data type.
|
||||
///
|
||||
UINT8 Type;
|
||||
///
|
||||
/// Byte 0x03: Revision of this FSP producer data type.
|
||||
///
|
||||
UINT8 Revision;
|
||||
///
|
||||
/// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
|
||||
///
|
||||
UINT8 MrcVersion [4];
|
||||
} FSP_PRODUCER_DATA_TYPE2;
|
||||
|
||||
typedef struct {
|
||||
FSP_INFO_HEADER FspInfoHeader;
|
||||
FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
|
||||
FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1;
|
||||
FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2;
|
||||
FSP_PATCH_TABLE FspPatchTable;
|
||||
} FSP_PRODUCER_DATA_TABLES;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _FSP_PRODUCER_DATA_HEADER_H
|
||||
@ -1,48 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPUPD_H__
|
||||
#define __FSPUPD_H__
|
||||
|
||||
#include <FspEas.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define FSPT_UPD_SIGNATURE 0x545F4450554C544D /* 'MTLUPD_T' */
|
||||
|
||||
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C544D /* 'MTLUPD_M' */
|
||||
|
||||
#define FSPS_UPD_SIGNATURE 0x535F4450554C544D /* 'MTLUPD_S' */
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,420 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPTUPD_H__
|
||||
#define __FSPTUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
|
||||
/** Fsp T Core UPD
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
UINT32 MicrocodeRegionBase;
|
||||
|
||||
/** Offset 0x0044
|
||||
**/
|
||||
UINT32 MicrocodeRegionSize;
|
||||
|
||||
/** Offset 0x0048
|
||||
**/
|
||||
UINT32 CodeRegionBase;
|
||||
|
||||
/** Offset 0x004C
|
||||
**/
|
||||
UINT32 CodeRegionSize;
|
||||
|
||||
/** Offset 0x0050
|
||||
**/
|
||||
UINT8 Reserved[16];
|
||||
} FSPT_CORE_UPD;
|
||||
|
||||
/** Fsp T Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0060 - PcdSerialIoUartDebugEnable
|
||||
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
|
||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDebugEnable;
|
||||
|
||||
/** Offset 0x0061 - PcdSerialIoUartNumber
|
||||
Select SerialIo Uart Controller for debug.
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIoUartNumber;
|
||||
|
||||
/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
|
||||
Select SerialIo Uart Controller mode
|
||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 PcdSerialIoUartMode;
|
||||
|
||||
/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT
|
||||
Select SerialIo Uart Controller Powergating mode
|
||||
0:Disabled, 1:Enabled, 2:Auto
|
||||
**/
|
||||
UINT8 PcdSerialIoUartPowerGating;
|
||||
|
||||
/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
**/
|
||||
UINT32 PcdSerialIoUartBaudRate;
|
||||
|
||||
/** Offset 0x0068 - Pci Express Base Address
|
||||
Base address to be programmed for Pci Express
|
||||
**/
|
||||
UINT64 PcdPciExpressBaseAddress;
|
||||
|
||||
/** Offset 0x0070 - Pci Express Region Length
|
||||
Region Length to be programmed for Pci Express
|
||||
**/
|
||||
UINT32 PcdPciExpressRegionLength;
|
||||
|
||||
/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
|
||||
Set default Parity.
|
||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||
**/
|
||||
UINT8 PcdSerialIoUartParity;
|
||||
|
||||
/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
|
||||
Set default word length. 0: Default, 5,6,7,8
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDataBits;
|
||||
|
||||
/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
|
||||
Set default stop bits.
|
||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||
**/
|
||||
UINT8 PcdSerialIoUartStopBits;
|
||||
|
||||
/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
|
||||
Enables UART hardware flow control, CTS and RTS lines.
|
||||
0: Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdSerialIoUartAutoFlow;
|
||||
|
||||
/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
|
||||
Select RX pin muxing for SerialIo UART used for debug
|
||||
**/
|
||||
UINT32 PcdSerialIoUartRxPinMux;
|
||||
|
||||
/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
|
||||
Select TX pin muxing for SerialIo UART used for debug
|
||||
**/
|
||||
UINT32 PcdSerialIoUartTxPinMux;
|
||||
|
||||
/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
|
||||
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartRtsPinMux;
|
||||
|
||||
/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
|
||||
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartCtsPinMux;
|
||||
|
||||
/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
||||
= SerialIoUartPci.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartDebugMmioBase;
|
||||
|
||||
/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT
|
||||
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
|
||||
**/
|
||||
UINT32 PcdSerialIoUartDebugPciCfgBase;
|
||||
|
||||
/** Offset 0x0090 - PcdLpcUartDebugEnable
|
||||
Enable to initialize LPC Uart device in FSP.
|
||||
0:Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdLpcUartDebugEnable;
|
||||
|
||||
/** Offset 0x0091 - Debug Interfaces
|
||||
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
|
||||
BIT2 - Not used.
|
||||
**/
|
||||
UINT8 PcdDebugInterfaceFlags;
|
||||
|
||||
/** Offset 0x0092 - PcdSerialDebugLevel
|
||||
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
|
||||
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
|
||||
Info & Verbose.
|
||||
0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
|
||||
Error Warnings and Info, 5:Load Error Warnings Info and Verbose
|
||||
**/
|
||||
UINT8 PcdSerialDebugLevel;
|
||||
|
||||
/** Offset 0x0093 - ISA Serial Base selection
|
||||
Select ISA Serial Base address. Default is 0x3F8.
|
||||
0:0x3F8, 1:0x2F8
|
||||
**/
|
||||
UINT8 PcdIsaSerialUartBase;
|
||||
|
||||
/** Offset 0x0094 - PcdSerialIo2ndUartEnable
|
||||
Enable Additional SerialIo Uart device in FSP.
|
||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartEnable;
|
||||
|
||||
/** Offset 0x0095 - PcdSerialIo2ndUartNumber
|
||||
Select SerialIo Uart Controller Number
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartNumber;
|
||||
|
||||
/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT
|
||||
Select SerialIo Uart Controller mode
|
||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartMode;
|
||||
|
||||
/** Offset 0x0097
|
||||
**/
|
||||
UINT8 Rsvd020[1];
|
||||
|
||||
/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartBaudRate;
|
||||
|
||||
/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT
|
||||
Set default Parity.
|
||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartParity;
|
||||
|
||||
/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT
|
||||
Set default word length. 0: Default, 5,6,7,8
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartDataBits;
|
||||
|
||||
/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT
|
||||
Set default stop bits.
|
||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartStopBits;
|
||||
|
||||
/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT
|
||||
Enables UART hardware flow control, CTS and RTS lines.
|
||||
0: Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartAutoFlow;
|
||||
|
||||
/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT
|
||||
Select RX pin muxing for SerialIo UART
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartRxPinMux;
|
||||
|
||||
/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT
|
||||
Select TX pin muxing for SerialIo UART
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartTxPinMux;
|
||||
|
||||
/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT
|
||||
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartRtsPinMux;
|
||||
|
||||
/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT
|
||||
Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartCtsPinMux;
|
||||
|
||||
/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
|
||||
= SerialIoUartPci.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartMmioBase;
|
||||
|
||||
/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT
|
||||
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartPciCfgBase;
|
||||
|
||||
/** Offset 0x00B8
|
||||
**/
|
||||
UINT32 TopMemoryCacheSize;
|
||||
|
||||
/** Offset 0x00BC - FspDebugHandler
|
||||
<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
|
||||
**/
|
||||
UINT32 FspDebugHandler;
|
||||
|
||||
/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity
|
||||
Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
|
||||
1:SerialIoSpiCsActiveHigh
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsPolarity[2];
|
||||
|
||||
/** Offset 0x00C2 - Serial Io SPI Chip Select Enable
|
||||
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsEnable[2];
|
||||
|
||||
/** Offset 0x00C4 - Serial Io SPI Device Mode
|
||||
When mode is set to Pci, controller is initalized in early stage. Available modes:
|
||||
0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiMode;
|
||||
|
||||
/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output
|
||||
Sets Default CS as Output. Available options: 0:CS0, 1:CS1
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiDefaultCsOutput;
|
||||
|
||||
/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW
|
||||
Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsMode;
|
||||
|
||||
/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High
|
||||
Sets Default CS State Low or High. Available options: 0:Low, 1:High
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsState;
|
||||
|
||||
/** Offset 0x00C8 - Serial Io SPI Device Number
|
||||
Select which Serial Io SPI controller is initalized in early stage.
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiNumber;
|
||||
|
||||
/** Offset 0x00C9
|
||||
**/
|
||||
UINT8 Rsvd030[3];
|
||||
|
||||
/** Offset 0x00CC - Serial Io SPI Device MMIO Base
|
||||
Assigns MMIO for Serial Io SPI controller usage in early stage.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMmioBase;
|
||||
|
||||
/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing
|
||||
Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
|
||||
possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiCsPinMux[2];
|
||||
|
||||
/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing
|
||||
Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
|
||||
possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiClkPinMux;
|
||||
|
||||
/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing
|
||||
Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMisoPinMux;
|
||||
|
||||
/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing
|
||||
Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMosiPinMux;
|
||||
|
||||
/** Offset 0x00E4 - Serial Io I2C Device MMIO Base
|
||||
Assigns MMIO for Serial Io I2C controller usage in early stage.
|
||||
**/
|
||||
UINT32 PcdSerialIoI2cMmioBase;
|
||||
|
||||
/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin
|
||||
Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoI2cSdaPin;
|
||||
|
||||
/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin
|
||||
Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoI2cSclPin;
|
||||
|
||||
/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination
|
||||
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
|
||||
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
|
||||
respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
|
||||
**/
|
||||
UINT8 PcdSerialIoI2cPadsTerm;
|
||||
|
||||
/** Offset 0x00F1 - Serial Io I2c Controller Number
|
||||
Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF
|
||||
0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable
|
||||
**/
|
||||
UINT8 PcdSerialIoI2cNumber;
|
||||
|
||||
/** Offset 0x00F2
|
||||
**/
|
||||
UINT8 ReservedFsptUpd1[6];
|
||||
} FSP_T_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_ARCH_UPD FsptArchUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0060
|
||||
**/
|
||||
FSP_T_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x00F8
|
||||
**/
|
||||
UINT8 Rsvd3[6];
|
||||
|
||||
/** Offset 0x00FE
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@ -1,349 +0,0 @@
|
||||
/** @file
|
||||
Header file for GpioConfig structure used by GPIO library.
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 2014 - 2017 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _GPIO_CONFIG_H_
|
||||
#define _GPIO_CONFIG_H_
|
||||
|
||||
#pragma pack(push, 1)
|
||||
|
||||
///
|
||||
/// For any GpioPad usage in code use GPIO_PAD type
|
||||
///
|
||||
typedef UINT32 GPIO_PAD;
|
||||
|
||||
|
||||
///
|
||||
/// For any GpioGroup usage in code use GPIO_GROUP type
|
||||
///
|
||||
typedef UINT32 GPIO_GROUP;
|
||||
|
||||
/**
|
||||
GPIO configuration structure used for pin programming.
|
||||
Structure contains fields that can be used to configure pad.
|
||||
**/
|
||||
typedef struct {
|
||||
/**
|
||||
Pad Mode
|
||||
Pad can be set as GPIO or one of its native functions.
|
||||
When in native mode setting Direction (except Inversion), OutputState,
|
||||
InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
|
||||
Refer to definition of GPIO_PAD_MODE.
|
||||
Refer to EDS for each native mode according to the pad.
|
||||
**/
|
||||
UINT32 PadMode : 5;
|
||||
/**
|
||||
Host Software Pad Ownership
|
||||
Set pad to ACPI mode or GPIO Driver Mode.
|
||||
Refer to definition of GPIO_HOSTSW_OWN.
|
||||
**/
|
||||
UINT32 HostSoftPadOwn : 2;
|
||||
/**
|
||||
GPIO Direction
|
||||
Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
|
||||
Refer to definition of GPIO_DIRECTION for supported settings.
|
||||
**/
|
||||
UINT32 Direction : 6;
|
||||
/**
|
||||
Output State
|
||||
Set Pad output value.
|
||||
Refer to definition of GPIO_OUTPUT_STATE for supported settings.
|
||||
This setting takes place when output is enabled.
|
||||
**/
|
||||
UINT32 OutputState : 2;
|
||||
/**
|
||||
GPIO Interrupt Configuration
|
||||
Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
|
||||
This setting is applicable only if GPIO is in GpioMode with input enabled.
|
||||
Refer to definition of GPIO_INT_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 InterruptConfig : 9;
|
||||
/**
|
||||
GPIO Power Configuration.
|
||||
This setting controls Pad Reset Configuration.
|
||||
Refer to definition of GPIO_RESET_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 PowerConfig : 8;
|
||||
/**
|
||||
GPIO Electrical Configuration
|
||||
This setting controls pads termination and voltage tolerance.
|
||||
Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 ElectricalConfig : 9;
|
||||
/**
|
||||
GPIO Lock Configuration
|
||||
This setting controls pads lock.
|
||||
Refer to definition of GPIO_LOCK_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 LockConfig : 4;
|
||||
/**
|
||||
Additional GPIO configuration
|
||||
Refer to definition of GPIO_OTHER_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 OtherSettings : 2;
|
||||
UINT32 RsvdBits : 17; ///< Reserved bits for future extension
|
||||
} GPIO_CONFIG;
|
||||
|
||||
|
||||
typedef enum {
|
||||
GpioHardwareDefault = 0x0 ///< Leave setting unmodified
|
||||
} GPIO_HARDWARE_DEFAULT;
|
||||
|
||||
/**
|
||||
GPIO Pad Mode
|
||||
Refer to GPIO documentation on native functions available for certain pad.
|
||||
If GPIO is set to one of NativeX modes then following settings are not applicable
|
||||
and can be skipped:
|
||||
- Interrupt related settings
|
||||
- Host Software Ownership
|
||||
- Output/Input enabling/disabling
|
||||
- Output lock
|
||||
**/
|
||||
typedef enum {
|
||||
GpioPadModeGpio = 0x1,
|
||||
GpioPadModeNative1 = 0x3,
|
||||
GpioPadModeNative2 = 0x5,
|
||||
GpioPadModeNative3 = 0x7,
|
||||
GpioPadModeNative4 = 0x9
|
||||
} GPIO_PAD_MODE;
|
||||
|
||||
/**
|
||||
Host Software Pad Ownership modes
|
||||
This setting affects GPIO interrupt status registers. Depending on chosen ownership
|
||||
some GPIO Interrupt status register get updated and other masked.
|
||||
Please refer to EDS for HOSTSW_OWN register description.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
|
||||
/**
|
||||
Set HOST ownership to ACPI.
|
||||
Use this setting if pad is not going to be used by GPIO OS driver.
|
||||
If GPIO is configured to generate SCI/SMI/NMI then this setting must be
|
||||
used for interrupts to work
|
||||
**/
|
||||
GpioHostOwnAcpi = 0x1,
|
||||
/**
|
||||
Set HOST ownership to GPIO Driver mode.
|
||||
Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
|
||||
GPIO OS Driver will be able to control the pad if appropriate entry in
|
||||
ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
|
||||
**/
|
||||
GpioHostOwnGpio = 0x3
|
||||
} GPIO_HOSTSW_OWN;
|
||||
|
||||
///
|
||||
/// GPIO Direction
|
||||
///
|
||||
typedef enum {
|
||||
GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
|
||||
GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
|
||||
GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
|
||||
GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
|
||||
GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
|
||||
GpioDirOut = 0x5, ///< Set pad for output only
|
||||
GpioDirNone = 0x7 ///< Disable both output and input
|
||||
} GPIO_DIRECTION;
|
||||
|
||||
/**
|
||||
GPIO Output State
|
||||
This field is relevant only if output is enabled
|
||||
**/
|
||||
typedef enum {
|
||||
GpioOutDefault = 0x0, ///< Leave output value unmodified
|
||||
GpioOutLow = 0x1, ///< Set output to low
|
||||
GpioOutHigh = 0x3 ///< Set output to high
|
||||
} GPIO_OUTPUT_STATE;
|
||||
|
||||
/**
|
||||
GPIO interrupt configuration
|
||||
This setting is applicable only if pad is in GPIO mode and has input enabled.
|
||||
GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
|
||||
and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
|
||||
EDS for details on this settings.
|
||||
Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
|
||||
to describe an interrupt e.g. GpioIntApic | GpioIntLevel
|
||||
If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
|
||||
If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
|
||||
Not all GPIO are capable of generating an SMI or NMI interrupt.
|
||||
When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
|
||||
interrupt cannot be shared and its IRQn number is not configurable.
|
||||
Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
|
||||
If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
|
||||
exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
|
||||
This type of GPIO Driver interrupt doesn't have any additional routing setting
|
||||
required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
|
||||
**/
|
||||
|
||||
typedef enum {
|
||||
GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
|
||||
GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
|
||||
GpioIntNmi = 0x3, ///< Enable NMI interrupt only
|
||||
GpioIntSmi = 0x5, ///< Enable SMI interrupt only
|
||||
GpioIntSci = 0x9, ///< Enable SCI interrupt only
|
||||
GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
|
||||
GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
|
||||
GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
|
||||
GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
|
||||
GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
|
||||
} GPIO_INT_CONFIG;
|
||||
|
||||
#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
|
||||
#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
|
||||
|
||||
/**
|
||||
GPIO Power Configuration
|
||||
GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
|
||||
be used to reset certain GPIO settings.
|
||||
Refer to EDS for settings that are controllable by PadRstCfg.
|
||||
**/
|
||||
typedef enum {
|
||||
|
||||
|
||||
GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
|
||||
|
||||
///
|
||||
/// New GPIO reset configuration options
|
||||
///
|
||||
/**
|
||||
Resume Reset (RSMRST)
|
||||
GPP: PadRstCfg = 00b = "Powergood"
|
||||
GPD: PadRstCfg = 11b = "Resume Reset"
|
||||
Pad setting will reset on:
|
||||
- DeepSx transition
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
**/
|
||||
GpioResumeReset = 0x01,
|
||||
/**
|
||||
Host Deep Reset
|
||||
PadRstCfg = 01b = "Deep GPIO Reset"
|
||||
Pad settings will reset on:
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
**/
|
||||
GpioHostDeepReset = 0x03,
|
||||
/**
|
||||
Platform Reset (PLTRST)
|
||||
PadRstCfg = 10b = "GPIO Reset"
|
||||
Pad settings will reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
- G3
|
||||
**/
|
||||
GpioPlatformReset = 0x05,
|
||||
/**
|
||||
Deep Sleep Well Reset (DSW_PWROK)
|
||||
GPP: not applicable
|
||||
GPD: PadRstCfg = 00b = "Powergood"
|
||||
Pad settings will reset on:
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
**/
|
||||
GpioDswReset = 0x07
|
||||
} GPIO_RESET_CONFIG;
|
||||
|
||||
/**
|
||||
GPIO Electrical Configuration
|
||||
Set GPIO termination and Pad Tolerance (applicable only for some pads)
|
||||
Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioTermDefault = 0x0, ///< Leave termination setting unmodified
|
||||
GpioTermNone = 0x1, ///< none
|
||||
GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
|
||||
GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
|
||||
GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
|
||||
GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
|
||||
GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
|
||||
GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
|
||||
GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
|
||||
/**
|
||||
Native function controls pads termination
|
||||
This setting is applicable only to some native modes.
|
||||
Please check EDS to determine which native functionality
|
||||
can control pads termination
|
||||
**/
|
||||
GpioTermNative = 0x1F,
|
||||
GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
|
||||
GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
|
||||
} GPIO_ELECTRICAL_CONFIG;
|
||||
|
||||
#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
|
||||
#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
|
||||
|
||||
/**
|
||||
GPIO LockConfiguration
|
||||
Set GPIO configuration lock and output state lock.
|
||||
GpioLockPadConfig and GpioLockOutputState can be OR'ed.
|
||||
Lock settings reset is in Powergood domain. Care must be taken when using this setting
|
||||
as fields it locks may be reset by a different signal and can be controllable
|
||||
by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
|
||||
functions which allow to unlock a GPIO pad.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioLockDefault = 0x0, ///< Leave lock setting unmodified
|
||||
GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
|
||||
GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
|
||||
} GPIO_LOCK_CONFIG;
|
||||
|
||||
#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
|
||||
#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
|
||||
|
||||
/**
|
||||
Other GPIO Configuration
|
||||
GPIO_OTHER_CONFIG is used for less often settings and for future extensions
|
||||
Supported settings:
|
||||
- RX raw override to '1' - allows to override input value to '1'
|
||||
This setting is applicable only if in input mode (both in GPIO and native usage).
|
||||
The override takes place at the internal pad state directly from buffer and before the RXINV.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioRxRaw1Default = 0x0, ///< Use default input override value
|
||||
GpioRxRaw1Dis = 0x1, ///< Don't override input
|
||||
GpioRxRaw1En = 0x3 ///< Override input to '1'
|
||||
} GPIO_OTHER_CONFIG;
|
||||
|
||||
#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif //_GPIO_CONFIG_H_
|
||||
@ -1,382 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __GPIOCONFIG_H__
|
||||
#define __GPIOCONFIG_H__
|
||||
#include <FsptUpd.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <FspsUpd.h>
|
||||
|
||||
/*
|
||||
SKL LP GPIO pins
|
||||
Use below for functions from PCH GPIO Lib which
|
||||
require GpioPad as argument. Encoding used here
|
||||
has all information required by library functions
|
||||
*/
|
||||
#define GPIO_SKL_LP_GPP_A0 0x02000000
|
||||
#define GPIO_SKL_LP_GPP_A1 0x02000001
|
||||
#define GPIO_SKL_LP_GPP_A2 0x02000002
|
||||
#define GPIO_SKL_LP_GPP_A3 0x02000003
|
||||
#define GPIO_SKL_LP_GPP_A4 0x02000004
|
||||
#define GPIO_SKL_LP_GPP_A5 0x02000005
|
||||
#define GPIO_SKL_LP_GPP_A6 0x02000006
|
||||
#define GPIO_SKL_LP_GPP_A7 0x02000007
|
||||
#define GPIO_SKL_LP_GPP_A8 0x02000008
|
||||
#define GPIO_SKL_LP_GPP_A9 0x02000009
|
||||
#define GPIO_SKL_LP_GPP_A10 0x0200000A
|
||||
#define GPIO_SKL_LP_GPP_A11 0x0200000B
|
||||
#define GPIO_SKL_LP_GPP_A12 0x0200000C
|
||||
#define GPIO_SKL_LP_GPP_A13 0x0200000D
|
||||
#define GPIO_SKL_LP_GPP_A14 0x0200000E
|
||||
#define GPIO_SKL_LP_GPP_A15 0x0200000F
|
||||
#define GPIO_SKL_LP_GPP_A16 0x02000010
|
||||
#define GPIO_SKL_LP_GPP_A17 0x02000011
|
||||
#define GPIO_SKL_LP_GPP_A18 0x02000012
|
||||
#define GPIO_SKL_LP_GPP_A19 0x02000013
|
||||
#define GPIO_SKL_LP_GPP_A20 0x02000014
|
||||
#define GPIO_SKL_LP_GPP_A21 0x02000015
|
||||
#define GPIO_SKL_LP_GPP_A22 0x02000016
|
||||
#define GPIO_SKL_LP_GPP_A23 0x02000017
|
||||
#define GPIO_SKL_LP_GPP_B0 0x02010000
|
||||
#define GPIO_SKL_LP_GPP_B1 0x02010001
|
||||
#define GPIO_SKL_LP_GPP_B2 0x02010002
|
||||
#define GPIO_SKL_LP_GPP_B3 0x02010003
|
||||
#define GPIO_SKL_LP_GPP_B4 0x02010004
|
||||
#define GPIO_SKL_LP_GPP_B5 0x02010005
|
||||
#define GPIO_SKL_LP_GPP_B6 0x02010006
|
||||
#define GPIO_SKL_LP_GPP_B7 0x02010007
|
||||
#define GPIO_SKL_LP_GPP_B8 0x02010008
|
||||
#define GPIO_SKL_LP_GPP_B9 0x02010009
|
||||
#define GPIO_SKL_LP_GPP_B10 0x0201000A
|
||||
#define GPIO_SKL_LP_GPP_B11 0x0201000B
|
||||
#define GPIO_SKL_LP_GPP_B12 0x0201000C
|
||||
#define GPIO_SKL_LP_GPP_B13 0x0201000D
|
||||
#define GPIO_SKL_LP_GPP_B14 0x0201000E
|
||||
#define GPIO_SKL_LP_GPP_B15 0x0201000F
|
||||
#define GPIO_SKL_LP_GPP_B16 0x02010010
|
||||
#define GPIO_SKL_LP_GPP_B17 0x02010011
|
||||
#define GPIO_SKL_LP_GPP_B18 0x02010012
|
||||
#define GPIO_SKL_LP_GPP_B19 0x02010013
|
||||
#define GPIO_SKL_LP_GPP_B20 0x02010014
|
||||
#define GPIO_SKL_LP_GPP_B21 0x02010015
|
||||
#define GPIO_SKL_LP_GPP_B22 0x02010016
|
||||
#define GPIO_SKL_LP_GPP_B23 0x02010017
|
||||
#define GPIO_SKL_LP_GPP_C0 0x02020000
|
||||
#define GPIO_SKL_LP_GPP_C1 0x02020001
|
||||
#define GPIO_SKL_LP_GPP_C2 0x02020002
|
||||
#define GPIO_SKL_LP_GPP_C3 0x02020003
|
||||
#define GPIO_SKL_LP_GPP_C4 0x02020004
|
||||
#define GPIO_SKL_LP_GPP_C5 0x02020005
|
||||
#define GPIO_SKL_LP_GPP_C6 0x02020006
|
||||
#define GPIO_SKL_LP_GPP_C7 0x02020007
|
||||
#define GPIO_SKL_LP_GPP_C8 0x02020008
|
||||
#define GPIO_SKL_LP_GPP_C9 0x02020009
|
||||
#define GPIO_SKL_LP_GPP_C10 0x0202000A
|
||||
#define GPIO_SKL_LP_GPP_C11 0x0202000B
|
||||
#define GPIO_SKL_LP_GPP_C12 0x0202000C
|
||||
#define GPIO_SKL_LP_GPP_C13 0x0202000D
|
||||
#define GPIO_SKL_LP_GPP_C14 0x0202000E
|
||||
#define GPIO_SKL_LP_GPP_C15 0x0202000F
|
||||
#define GPIO_SKL_LP_GPP_C16 0x02020010
|
||||
#define GPIO_SKL_LP_GPP_C17 0x02020011
|
||||
#define GPIO_SKL_LP_GPP_C18 0x02020012
|
||||
#define GPIO_SKL_LP_GPP_C19 0x02020013
|
||||
#define GPIO_SKL_LP_GPP_C20 0x02020014
|
||||
#define GPIO_SKL_LP_GPP_C21 0x02020015
|
||||
#define GPIO_SKL_LP_GPP_C22 0x02020016
|
||||
#define GPIO_SKL_LP_GPP_C23 0x02020017
|
||||
#define GPIO_SKL_LP_GPP_D0 0x02030000
|
||||
#define GPIO_SKL_LP_GPP_D1 0x02030001
|
||||
#define GPIO_SKL_LP_GPP_D2 0x02030002
|
||||
#define GPIO_SKL_LP_GPP_D3 0x02030003
|
||||
#define GPIO_SKL_LP_GPP_D4 0x02030004
|
||||
#define GPIO_SKL_LP_GPP_D5 0x02030005
|
||||
#define GPIO_SKL_LP_GPP_D6 0x02030006
|
||||
#define GPIO_SKL_LP_GPP_D7 0x02030007
|
||||
#define GPIO_SKL_LP_GPP_D8 0x02030008
|
||||
#define GPIO_SKL_LP_GPP_D9 0x02030009
|
||||
#define GPIO_SKL_LP_GPP_D10 0x0203000A
|
||||
#define GPIO_SKL_LP_GPP_D11 0x0203000B
|
||||
#define GPIO_SKL_LP_GPP_D12 0x0203000C
|
||||
#define GPIO_SKL_LP_GPP_D13 0x0203000D
|
||||
#define GPIO_SKL_LP_GPP_D14 0x0203000E
|
||||
#define GPIO_SKL_LP_GPP_D15 0x0203000F
|
||||
#define GPIO_SKL_LP_GPP_D16 0x02030010
|
||||
#define GPIO_SKL_LP_GPP_D17 0x02030011
|
||||
#define GPIO_SKL_LP_GPP_D18 0x02030012
|
||||
#define GPIO_SKL_LP_GPP_D19 0x02030013
|
||||
#define GPIO_SKL_LP_GPP_D20 0x02030014
|
||||
#define GPIO_SKL_LP_GPP_D21 0x02030015
|
||||
#define GPIO_SKL_LP_GPP_D22 0x02030016
|
||||
#define GPIO_SKL_LP_GPP_D23 0x02030017
|
||||
#define GPIO_SKL_LP_GPP_E0 0x02040000
|
||||
#define GPIO_SKL_LP_GPP_E1 0x02040001
|
||||
#define GPIO_SKL_LP_GPP_E2 0x02040002
|
||||
#define GPIO_SKL_LP_GPP_E3 0x02040003
|
||||
#define GPIO_SKL_LP_GPP_E4 0x02040004
|
||||
#define GPIO_SKL_LP_GPP_E5 0x02040005
|
||||
#define GPIO_SKL_LP_GPP_E6 0x02040006
|
||||
#define GPIO_SKL_LP_GPP_E7 0x02040007
|
||||
#define GPIO_SKL_LP_GPP_E8 0x02040008
|
||||
#define GPIO_SKL_LP_GPP_E9 0x02040009
|
||||
#define GPIO_SKL_LP_GPP_E10 0x0204000A
|
||||
#define GPIO_SKL_LP_GPP_E11 0x0204000B
|
||||
#define GPIO_SKL_LP_GPP_E12 0x0204000C
|
||||
#define GPIO_SKL_LP_GPP_E13 0x0204000D
|
||||
#define GPIO_SKL_LP_GPP_E14 0x0204000E
|
||||
#define GPIO_SKL_LP_GPP_E15 0x0204000F
|
||||
#define GPIO_SKL_LP_GPP_E16 0x02040010
|
||||
#define GPIO_SKL_LP_GPP_E17 0x02040011
|
||||
#define GPIO_SKL_LP_GPP_E18 0x02040012
|
||||
#define GPIO_SKL_LP_GPP_E19 0x02040013
|
||||
#define GPIO_SKL_LP_GPP_E20 0x02040014
|
||||
#define GPIO_SKL_LP_GPP_E21 0x02040015
|
||||
#define GPIO_SKL_LP_GPP_E22 0x02040016
|
||||
#define GPIO_SKL_LP_GPP_E23 0x02040017
|
||||
#define GPIO_SKL_LP_GPP_F0 0x02050000
|
||||
#define GPIO_SKL_LP_GPP_F1 0x02050001
|
||||
#define GPIO_SKL_LP_GPP_F2 0x02050002
|
||||
#define GPIO_SKL_LP_GPP_F3 0x02050003
|
||||
#define GPIO_SKL_LP_GPP_F4 0x02050004
|
||||
#define GPIO_SKL_LP_GPP_F5 0x02050005
|
||||
#define GPIO_SKL_LP_GPP_F6 0x02050006
|
||||
#define GPIO_SKL_LP_GPP_F7 0x02050007
|
||||
#define GPIO_SKL_LP_GPP_F8 0x02050008
|
||||
#define GPIO_SKL_LP_GPP_F9 0x02050009
|
||||
#define GPIO_SKL_LP_GPP_F10 0x0205000A
|
||||
#define GPIO_SKL_LP_GPP_F11 0x0205000B
|
||||
#define GPIO_SKL_LP_GPP_F12 0x0205000C
|
||||
#define GPIO_SKL_LP_GPP_F13 0x0205000D
|
||||
#define GPIO_SKL_LP_GPP_F14 0x0205000E
|
||||
#define GPIO_SKL_LP_GPP_F15 0x0205000F
|
||||
#define GPIO_SKL_LP_GPP_F16 0x02050010
|
||||
#define GPIO_SKL_LP_GPP_F17 0x02050011
|
||||
#define GPIO_SKL_LP_GPP_F18 0x02050012
|
||||
#define GPIO_SKL_LP_GPP_F19 0x02050013
|
||||
#define GPIO_SKL_LP_GPP_F20 0x02050014
|
||||
#define GPIO_SKL_LP_GPP_F21 0x02050015
|
||||
#define GPIO_SKL_LP_GPP_F22 0x02050016
|
||||
#define GPIO_SKL_LP_GPP_F23 0x02050017
|
||||
#define GPIO_SKL_LP_GPP_G0 0x02060000
|
||||
#define GPIO_SKL_LP_GPP_G1 0x02060001
|
||||
#define GPIO_SKL_LP_GPP_G2 0x02060002
|
||||
#define GPIO_SKL_LP_GPP_G3 0x02060003
|
||||
#define GPIO_SKL_LP_GPP_G4 0x02060004
|
||||
#define GPIO_SKL_LP_GPP_G5 0x02060005
|
||||
#define GPIO_SKL_LP_GPP_G6 0x02060006
|
||||
#define GPIO_SKL_LP_GPP_G7 0x02060007
|
||||
#define GPIO_SKL_LP_GPD0 0x02070000
|
||||
#define GPIO_SKL_LP_GPD1 0x02070001
|
||||
#define GPIO_SKL_LP_GPD2 0x02070002
|
||||
#define GPIO_SKL_LP_GPD3 0x02070003
|
||||
#define GPIO_SKL_LP_GPD4 0x02070004
|
||||
#define GPIO_SKL_LP_GPD5 0x02070005
|
||||
#define GPIO_SKL_LP_GPD6 0x02070006
|
||||
#define GPIO_SKL_LP_GPD7 0x02070007
|
||||
#define GPIO_SKL_LP_GPD8 0x02070008
|
||||
#define GPIO_SKL_LP_GPD9 0x02070009
|
||||
#define GPIO_SKL_LP_GPD10 0x0207000A
|
||||
#define GPIO_SKL_LP_GPD11 0x0207000B
|
||||
|
||||
#define END_OF_GPIO_TABLE 0xFFFFFFFF
|
||||
|
||||
//Sample GPIO Table
|
||||
|
||||
static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
|
||||
{
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
|
||||
{GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
|
||||
{GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
|
||||
{GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
|
||||
{GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
|
||||
{GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
|
||||
{GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
|
||||
{GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
|
||||
{GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
|
||||
{GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
|
||||
{GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
|
||||
{GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
|
||||
{GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
|
||||
{GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
|
||||
{GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
|
||||
{GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
|
||||
{GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
|
||||
{GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
|
||||
// {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
|
||||
// {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
|
||||
// {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
|
||||
// {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
|
||||
// {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
|
||||
{GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
|
||||
{GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
|
||||
{GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
|
||||
{GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
|
||||
{GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
|
||||
{GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
|
||||
{GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
|
||||
{GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
|
||||
{GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
|
||||
{GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
|
||||
{GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
|
||||
{GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
|
||||
{GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
|
||||
{GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
|
||||
{GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
|
||||
{GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
|
||||
{GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
|
||||
{GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
|
||||
{GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
|
||||
{GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
|
||||
{GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
|
||||
{GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
|
||||
{GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
|
||||
{GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
|
||||
{GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
|
||||
{GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
|
||||
{GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
|
||||
{GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
|
||||
{GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
|
||||
{GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
|
||||
{GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
|
||||
{GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
|
||||
{GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
|
||||
{GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
|
||||
{GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
|
||||
{GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
|
||||
{GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
|
||||
{GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
|
||||
{GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
|
||||
{GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
|
||||
{GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
|
||||
{GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
|
||||
{GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
|
||||
{GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
|
||||
{GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
|
||||
{GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
|
||||
{GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
|
||||
{GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
|
||||
{GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
|
||||
{GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
|
||||
{GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
|
||||
{GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
|
||||
{GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
|
||||
{GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
|
||||
{GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
|
||||
{GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
|
||||
{GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
|
||||
{GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
|
||||
{GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
|
||||
{GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
|
||||
{GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
|
||||
{GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
|
||||
{GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
|
||||
{GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
|
||||
{GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
|
||||
{GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
|
||||
{GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
|
||||
{GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
|
||||
{GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
|
||||
{GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
|
||||
{GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
|
||||
{GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
|
||||
{GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
|
||||
{GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
|
||||
{GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
|
||||
{GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
|
||||
{GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
|
||||
{GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
|
||||
{GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
|
||||
{GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
|
||||
{GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
|
||||
{GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
|
||||
{GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
|
||||
{GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
|
||||
{GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
|
||||
{GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
|
||||
{GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
|
||||
{GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
|
||||
{GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
|
||||
{GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
|
||||
{GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
|
||||
{GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
|
||||
{GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
|
||||
{GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
|
||||
{GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
|
||||
{GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
|
||||
{GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
|
||||
{GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
|
||||
{GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
|
||||
{GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
|
||||
{GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
|
||||
{GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
|
||||
{GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
|
||||
{GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
|
||||
{GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
|
||||
{GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
|
||||
{GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
|
||||
{GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
|
||||
{GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
|
||||
{GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
|
||||
{GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
|
||||
{GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
|
||||
{GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
|
||||
{GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
|
||||
{GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
|
||||
{GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
|
||||
{GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
|
||||
{GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
|
||||
{GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
|
||||
{GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
|
||||
{GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
|
||||
{GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
|
||||
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
|
||||
};
|
||||
|
||||
#endif //_GPIO_CONFIG_H_
|
||||
@ -1,59 +0,0 @@
|
||||
/** @file
|
||||
Definitions for Hob Usage data HOB
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 2017 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
|
||||
#ifndef _HOB_USAGE_DATA_HOB_H_
|
||||
#define _HOB_USAGE_DATA_HOB_H_
|
||||
|
||||
extern EFI_GUID gHobUsageDataGuid;
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
/**
|
||||
Hob Usage Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
**/
|
||||
typedef struct {
|
||||
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
|
||||
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
|
||||
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
|
||||
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
|
||||
UINTN FreeMemory;
|
||||
} HOB_USAGE_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _HOB_USAGE_DATA_HOB_H_
|
||||
@ -1,345 +0,0 @@
|
||||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 1999 - 2022 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryS3Data2Guid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 2
|
||||
#define MAX_CH 4
|
||||
#define MAX_DDR5_CH 2
|
||||
#define MAX_DIMM 2
|
||||
// Must match definitions in
|
||||
// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
|
||||
#define HOB_MAX_SAGV_POINTS 4
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
// @todo remove and use the MdePkg\Include\Pi\PiHob.h
|
||||
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
|
||||
#ifndef __HOB__H__
|
||||
typedef struct _EFI_HOB_GENERIC_HEADER {
|
||||
UINT16 HobType;
|
||||
UINT16 HobLength;
|
||||
UINT32 Reserved;
|
||||
} EFI_HOB_GENERIC_HEADER;
|
||||
|
||||
typedef struct _EFI_HOB_GUID_TYPE {
|
||||
EFI_HOB_GENERIC_HEADER Header;
|
||||
EFI_GUID Name;
|
||||
///
|
||||
/// Guid specific data goes here
|
||||
///
|
||||
} EFI_HOB_GUID_TYPE;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef __MRC_BOOT_MODE__
|
||||
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||
#ifndef INT32_MAX
|
||||
#define INT32_MAX (0x7FFFFFFF)
|
||||
#endif //INT32_MAX
|
||||
typedef enum {
|
||||
bmCold, ///< Cold boot
|
||||
bmWarm, ///< Warm boot
|
||||
bmS3, ///< S3 resume
|
||||
bmFast, ///< Fast boot
|
||||
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||
} MRC_BOOT_MODE;
|
||||
#endif //__MRC_BOOT_MODE__
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR5
|
||||
#define MRC_DDR_TYPE_DDR5 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR5
|
||||
#define MRC_DDR_TYPE_LPDDR5 2
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 4
|
||||
#endif
|
||||
|
||||
#define MAX_PROFILE_NUM 7 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
|
||||
|
||||
#ifndef MAX_RCOMP_TARGETS
|
||||
#define MAX_RCOMP_TARGETS 5
|
||||
#endif
|
||||
|
||||
#ifndef MAX_ODT_ENTRIES
|
||||
#define MAX_ODT_ENTRIES 11
|
||||
#endif
|
||||
|
||||
#define MAX_TRACE_REGION 5
|
||||
#define MAX_TRACE_CACHE_TYPE 2
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
|
||||
UINT8 Resv[2]; ///< Resv
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
typedef struct {
|
||||
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
|
||||
} MRC_IP_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT64 BaseAddress; ///< Trace Base Address
|
||||
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
||||
UINT8 CacheType; ///< Trace Cache Type
|
||||
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
||||
UINT8 Rsvd[2];
|
||||
} PSMI_MEM_INFO;
|
||||
|
||||
/// This data structure contains per-SaGv timing values that are considered output by the MRC.
|
||||
typedef struct {
|
||||
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
|
||||
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
|
||||
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
|
||||
} HOB_SAGV_TIMING_OUT;
|
||||
|
||||
/// This data structure contains SAGV config values that are considered output by the MRC.
|
||||
typedef struct {
|
||||
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
|
||||
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
|
||||
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
|
||||
} HOB_SAGV_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
|
||||
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
|
||||
UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VddqVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VppVoltage[MAX_PROFILE_NUM];
|
||||
UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
|
||||
UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
|
||||
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
|
||||
BOOLEAN IsIbeccEnabled;
|
||||
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
|
||||
UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows
|
||||
UINT16 PprRepairFails; ///< PPR: Counts of repair failure
|
||||
UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT64 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
||||
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
|
||||
BOOLEAN MrcBasicMemoryTestPass;
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
@ -1,56 +0,0 @@
|
||||
/** @file
|
||||
Header file for SMBIOS Cache Info HOB
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License which accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.1.0
|
||||
dated 2016-Nov-16 (DSP0134)
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
|
||||
**/
|
||||
|
||||
#ifndef _SMBIOS_CACHE_INFO_HOB_H_
|
||||
#define _SMBIOS_CACHE_INFO_HOB_H_
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// SMBIOS Cache Info HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 ProcessorSocketNumber;
|
||||
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
|
||||
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
|
||||
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
|
||||
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
|
||||
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
|
||||
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
|
||||
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
|
||||
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
|
||||
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
|
||||
//
|
||||
// Add for smbios 3.1.0
|
||||
//
|
||||
UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
/**
|
||||
String Buffer - each string terminated by NULL "0x00"
|
||||
String buffer terminated by double NULL "0x0000"
|
||||
**/
|
||||
} SMBIOS_CACHE_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _SMBIOS_CACHE_INFO_HOB_H_
|
||||
@ -1,67 +0,0 @@
|
||||
/** @file
|
||||
Header file for SMBIOS Processor Info HOB
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.1.0
|
||||
dated 2016-Nov-16 (DSP0134)
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
|
||||
**/
|
||||
|
||||
#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
#define _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// SMBIOS Processor Info HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 TotalNumberOfSockets;
|
||||
UINT16 CurrentSocketNumber;
|
||||
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
|
||||
/** This info is used for both ProcessorFamily and ProcessorFamily2 fields
|
||||
See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
|
||||
**/
|
||||
UINT16 ProcessorFamily;
|
||||
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
|
||||
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
|
||||
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
|
||||
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
|
||||
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
|
||||
UINT16 MaxSpeedInMHz; ///< Snapshot of Max processor speed during boot
|
||||
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
|
||||
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21
|
||||
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
|
||||
/** This info is used for both CoreCount & CoreCount2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.6
|
||||
**/
|
||||
UINT16 CoreCount;
|
||||
/** This info is used for both CoreEnabled & CoreEnabled2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.7
|
||||
**/
|
||||
UINT16 EnabledCoreCount;
|
||||
/** This info is used for both ThreadCount & ThreadCount2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.8
|
||||
**/
|
||||
UINT16 ThreadCount;
|
||||
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
|
||||
/**
|
||||
String Buffer - each string terminated by NULL "0x00"
|
||||
String buffer terminated by double NULL "0x0000"
|
||||
**/
|
||||
} SMBIOS_PROCESSOR_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
@ -1,49 +0,0 @@
|
||||
/** @file
|
||||
Library instance to list all DynamicEx PCD FSP consumes.
|
||||
No real functionality.
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 2019 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
/**
|
||||
Do nothing function.
|
||||
|
||||
**/
|
||||
VOID
|
||||
FspPcdListLibNull (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
@ -1,86 +0,0 @@
|
||||
## @file
|
||||
# Library instance to list all DynamicEx PCD FSP consumes.
|
||||
#
|
||||
# @copyright
|
||||
# INTEL CONFIDENTIAL
|
||||
# Copyright 2019 - 2021 Intel Corporation.
|
||||
#
|
||||
# The source code contained or described herein and all documents related to the
|
||||
# source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
# licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
# and licensors. The Material may contain trade secrets and proprietary and
|
||||
# confidential information of Intel Corporation and its suppliers and licensors,
|
||||
# and is protected by worldwide copyright and trade secret laws and treaty
|
||||
# provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
# without Intel's prior express written permission.
|
||||
#
|
||||
# No license under any patent, copyright, trade secret or other intellectual
|
||||
# property right is granted to or conferred upon you by disclosure or delivery
|
||||
# of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
# otherwise. Any license under such intellectual property rights must be
|
||||
# express and approved by Intel in writing.
|
||||
#
|
||||
# Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
# this notice or any other notice embedded in Materials by Intel or
|
||||
# Intel's suppliers or licensors in any way.
|
||||
#
|
||||
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
# the terms of your license agreement with Intel or your vendor. This file may
|
||||
# be modified by the user, subject to additional terms of the license agreement.
|
||||
#
|
||||
# @par Specification Reference:
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010017
|
||||
BASE_NAME = FspPcdListLibNull
|
||||
FILE_GUID = C5D4D79E-3D5C-4EB6-899E-6F1563CB0B32
|
||||
VERSION_STRING = 1.0
|
||||
MODULE_TYPE = BASE
|
||||
LIBRARY_CLASS = NULL
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
|
||||
#
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
UefiCpuPkg/UefiCpuPkg.dec
|
||||
ClientOneSiliconPkg/SiPkg.dec
|
||||
|
||||
[Sources]
|
||||
FspPcdListLibNull.c
|
||||
|
||||
[Pcd]
|
||||
#
|
||||
# List all the DynamicEx PCDs that FSP will consume.
|
||||
# FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are
|
||||
# built into PCD database.
|
||||
#
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
|
||||
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress ## CONSUMES
|
||||
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONSUMES
|
||||
|
||||
@ -1,43 +0,0 @@
|
||||
## @file
|
||||
# Component description file for MeteorLake Fsp Bin package.
|
||||
#
|
||||
# @copyright
|
||||
# INTEL CONFIDENTIAL
|
||||
# Copyright 2016 - 2019 Intel Corporation.
|
||||
#
|
||||
# The source code contained or described herein and all documents related to the
|
||||
# source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
# licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
# and licensors. The Material may contain trade secrets and proprietary and
|
||||
# confidential information of Intel Corporation and its suppliers and licensors,
|
||||
# and is protected by worldwide copyright and trade secret laws and treaty
|
||||
# provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
# without Intel's prior express written permission.
|
||||
#
|
||||
# No license under any patent, copyright, trade secret or other intellectual
|
||||
# property right is granted to or conferred upon you by disclosure or delivery
|
||||
# of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
# otherwise. Any license under such intellectual property rights must be
|
||||
# express and approved by Intel in writing.
|
||||
#
|
||||
# Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
# this notice or any other notice embedded in Materials by Intel or
|
||||
# Intel's suppliers or licensors in any way.
|
||||
#
|
||||
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
# the terms of your license agreement with Intel or your vendor. This file may
|
||||
# be modified by the user, subject to additional terms of the license agreement.
|
||||
#
|
||||
# @par Specification
|
||||
##
|
||||
|
||||
[Defines]
|
||||
DEC_SPECIFICATION = 0x00010005
|
||||
PACKAGE_NAME = MeteorLakeFspBinPkg
|
||||
PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06
|
||||
PACKAGE_VERSION = 1.02
|
||||
|
||||
[Includes]
|
||||
Include
|
||||
13
libs/README.md
Normal file
13
libs/README.md
Normal file
@ -0,0 +1,13 @@
|
||||
# Libraries
|
||||
|
||||
## Contents
|
||||
|
||||
- [coreboot-fs](https://gitlab.redox-os.org/redox-os/coreboot-fs.git) - coreboot-fs
|
||||
- [coreboot-table](https://gitlab.redox-os.org/redox-os/coreboot-table.git) - coreboot-table
|
||||
- [ecflash](https://github.com/system76/ecflash.git) - ecflash
|
||||
- [intelflash](https://gitlab.redox-os.org/redox-os/intelflash.git) - intelflash
|
||||
- [intel-spi](https://github.com/system76/intel-spi.git) - intel-spi
|
||||
- [smmstore](https://github.com/system76/smmstore.git) - smmstore
|
||||
- [uefi](https://gitlab.redox-os.org/redox-os/uefi.git)
|
||||
- [uefi_alloc](https://gitlab.redox-os.org/redox-os/uefi_alloc.git)
|
||||
- [uefi_std](https://gitlab.redox-os.org/redox-os/uefi_std.git) - uefi_std
|
||||
1
libs/README.md.in
Normal file
1
libs/README.md.in
Normal file
@ -0,0 +1 @@
|
||||
# Libraries
|
||||
1
libs/coreboot-fs
Submodule
1
libs/coreboot-fs
Submodule
Submodule libs/coreboot-fs added at 514f88c960
1
libs/coreboot-table
Submodule
1
libs/coreboot-table
Submodule
Submodule libs/coreboot-table added at df19cf3dc7
1
libs/ecflash
Submodule
1
libs/ecflash
Submodule
Submodule libs/ecflash added at b08db29313
1
libs/intel-spi
Submodule
1
libs/intel-spi
Submodule
Submodule libs/intel-spi added at b918b2b1fe
1
libs/intelflash
Submodule
1
libs/intelflash
Submodule
Submodule libs/intelflash added at 443adc01d3
1
libs/uefi
Submodule
1
libs/uefi
Submodule
Submodule libs/uefi added at 81e60876b3
1
libs/uefi_alloc
Submodule
1
libs/uefi_alloc
Submodule
Submodule libs/uefi_alloc added at 7a74e171cd
1
libs/uefi_std
Submodule
1
libs/uefi_std
Submodule
Submodule libs/uefi_std added at a069826ad5
@ -4,48 +4,27 @@
|
||||
|
||||
- [addw1](./addw1) - System76 Adder Workstation (addw1)
|
||||
- [addw2](./addw2) - System76 Adder WS (addw2)
|
||||
- [addw3](./addw3) - System76 Adder WS (addw3)
|
||||
- [addw4](./addw4) - System76 Adder WS (addw4)
|
||||
- [bonw14](./bonw14) - System76 Bonobo WS (bonw14)
|
||||
- [bonw15](./bonw15) - System76 Bonobo WS (bonw15)
|
||||
- [bonw15-b](./bonw15-b) - System76 Bonobo WS (bonw15-b)
|
||||
- [darp10](./darp10) - System76 Darter Pro (darp10)
|
||||
- [darp10-b](./darp10-b) - System76 Darter Pro (darp10-b)
|
||||
- [darp5](./darp5) - System76 Darter Pro (darp5)
|
||||
- [darp6](./darp6) - System76 Darter Pro (darp6)
|
||||
- [darp7](./darp7) - System76 Darter Pro (darp7)
|
||||
- [darp8](./darp8) - System76 Darter Pro (darp8)
|
||||
- [darp9](./darp9) - System76 Darter Pro (darp9)
|
||||
- [galp2](./galp2) - System76 Galago Pro (galp2)
|
||||
- [galp3](./galp3) - System76 Galago Pro (galp3)
|
||||
- [galp3-b](./galp3-b) - System76 Galago Pro (galp3-b)
|
||||
- [galp3-c](./galp3-c) - System76 Galago Pro (galp3-c)
|
||||
- [galp4](./galp4) - System76 Galago Pro (galp4)
|
||||
- [galp5](./galp5) - System76 Galago Pro (galp5)
|
||||
- [galp6](./galp6) - System76 Galago Pro (galp6)
|
||||
- [galp7](./galp7) - System76 Galago Pro (galp7)
|
||||
- [gaze14_1650](./gaze14_1650) - System76 Gazelle (gaze14)
|
||||
- [gaze14_1660ti](./gaze14_1660ti) - System76 Gazelle (gaze14)
|
||||
- [gaze15](./gaze15) - System76 Gazelle (gaze15)
|
||||
- [gaze16-3050](./gaze16-3050) - System76 Gazelle (gaze16)
|
||||
- [gaze16-3060](./gaze16-3060) - System76 Gazelle (gaze16)
|
||||
- [gaze16-3060-b](./gaze16-3060-b) - System76 Gazelle (gaze16)
|
||||
- [gaze17-3050](./gaze17-3050) - System76 Gazelle (gaze17)
|
||||
- [gaze17-3060-b](./gaze17-3060-b) - System76 Gazelle (gaze17-3060-b)
|
||||
- [gaze18](./gaze18) - System76 Gazelle (gaze18)
|
||||
- [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
|
||||
- [lemp11](./lemp11) - System76 Lemur Pro (lemp11)
|
||||
- [lemp12](./lemp12) - System76 Lemur Pro (lemp12)
|
||||
- [lemp13](./lemp13) - System76 Lemur Pro (lemp13)
|
||||
- [lemp13-b](./lemp13-b) - System76 Lemur Pro (lemp13-b)
|
||||
- [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
|
||||
- [oryp10](./oryp10) - System76 Oryx Pro (oryp10)
|
||||
- [oryp11](./oryp11) - System76 Oryx Pro (oryp11)
|
||||
- [oryp12](./oryp12) - System76 Oryx Pro (oryp12)
|
||||
- [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
|
||||
- [oryp6](./oryp6) - System76 Oryx Pro (oryp6)
|
||||
- [oryp7](./oryp7) - System76 Oryx Pro (oryp7)
|
||||
- [oryp8](./oryp8) - System76 Oryx Pro (oryp8)
|
||||
- [oryp9](./oryp9) - System76 Oryx Pro (oryp9)
|
||||
- [qemu](./qemu) - QEMU (Virtualization)
|
||||
- [serw13](./serw13) - System76 Serval WS (serw13)
|
||||
- [thelio-b1](./thelio-b1) - System76 Thelio (thelio-b1)
|
||||
|
||||
@ -11,4 +11,4 @@ https://system76.com/guides/addw1
|
||||
- HAP: false
|
||||
- [ME](./me.rom)
|
||||
- Size: 6140 KB
|
||||
- Version: 12.0.94.2428
|
||||
- Version: 12.0.85.1919
|
||||
|
||||
@ -12,8 +12,10 @@ CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
|
||||
CONFIG_POST_IO=n
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
CONFIG_SMMSTORE=y
|
||||
CONFIG_SMMSTORE_V2=y
|
||||
CONFIG_TPM_MEASURED_BOOT=y
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
|
||||
#CONFIG_CONSOLE_SYSTEM76_EC=y
|
||||
|
||||
@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
|
||||
DISABLE_SERIAL_TERMINAL=TRUE
|
||||
PLATFORM_BOOT_TIMEOUT=2
|
||||
PS2_KEYBOARD_ENABLE=TRUE
|
||||
SECURE_BOOT_ENABLE=TRUE
|
||||
#SECURE_BOOT_ENABLE=TRUE
|
||||
SERIAL_DRIVER_ENABLE=FALSE
|
||||
SHELL_TYPE=NONE
|
||||
TPM_ENABLE=TRUE
|
||||
|
||||
245
models/addw1/gpio.h
Normal file
245
models/addw1/gpio.h
Normal file
@ -0,0 +1,245 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_H18, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
43
models/addw1/hda_verb.c
Normal file
43
models/addw1/hda_verb.c
Normal file
@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865d1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865d1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU93HDMI/DP */
|
||||
0x10de0093, /* Vendor ID */
|
||||
0x155865d1, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865d1),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
BIN
models/addw1/me.rom
(Stored with Git LFS)
BIN
models/addw1/me.rom
(Stored with Git LFS)
Binary file not shown.
@ -11,4 +11,4 @@ https://system76.com/guides/addw2
|
||||
- HAP: false
|
||||
- [ME](./me.rom)
|
||||
- Size: 4092 KB
|
||||
- Version: 14.1.72.2287
|
||||
- Version: 14.0.60.1807
|
||||
|
||||
@ -12,8 +12,10 @@ CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
|
||||
CONFIG_POST_IO=n
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
CONFIG_SMMSTORE=y
|
||||
CONFIG_SMMSTORE_V2=y
|
||||
CONFIG_TPM_MEASURED_BOOT=y
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
|
||||
#CONFIG_CONSOLE_SYSTEM76_EC=y
|
||||
|
||||
@ -2,7 +2,7 @@ BOOTLOADER=COREBOOT
|
||||
DISABLE_SERIAL_TERMINAL=TRUE
|
||||
PLATFORM_BOOT_TIMEOUT=2
|
||||
PS2_KEYBOARD_ENABLE=TRUE
|
||||
SECURE_BOOT_ENABLE=TRUE
|
||||
#SECURE_BOOT_ENABLE=TRUE
|
||||
SERIAL_DRIVER_ENABLE=FALSE
|
||||
SHELL_TYPE=NONE
|
||||
TPM_ENABLE=TRUE
|
||||
|
||||
258
models/addw2/gpio.h
Normal file
258
models/addw2/gpio.h
Normal file
@ -0,0 +1,258 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A14, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
43
models/addw2/hda_verb.c
Normal file
43
models/addw2/hda_verb.c
Normal file
@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865e1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU92HDMI/DP */
|
||||
0x10de0092, /* Vendor ID */
|
||||
0x155865e1, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e1),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
BIN
models/addw2/me.rom
(Stored with Git LFS)
BIN
models/addw2/me.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw3/IntelGopDriver.efi
(Stored with Git LFS)
BIN
models/addw3/IntelGopDriver.efi
(Stored with Git LFS)
Binary file not shown.
@ -1,12 +0,0 @@
|
||||
# System76 Adder WS (addw3)
|
||||
|
||||
## Contents
|
||||
|
||||
- [EC](./ec.rom)
|
||||
- *Read Error: No such file or directory (os error 2)*
|
||||
- [FD](./fd.rom)
|
||||
- Size: 4 KB
|
||||
- HAP: false
|
||||
- [ME](./me.rom)
|
||||
- Size: 3944 KB
|
||||
- Version: 16.1.25.2091
|
||||
@ -1 +0,0 @@
|
||||
# System76 Adder WS (addw3)
|
||||
@ -1 +0,0 @@
|
||||
GD25Q256D
|
||||
@ -1,333 +0,0 @@
|
||||
## PCI ##
|
||||
PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
|
||||
PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
|
||||
PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
|
||||
PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
|
||||
PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
|
||||
PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
|
||||
PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
|
||||
PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
|
||||
PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
|
||||
PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
|
||||
PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
|
||||
PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
|
||||
PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
|
||||
PCI Device: 0000:00:1b.0: Class 0x00060400, Vendor 0x8086, Device 0x7A44, Revision 0x11
|
||||
PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3C, Revision 0x11
|
||||
PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
|
||||
PCI Device: 0000:00:1f.3: Class 0x00040100, Vendor 0x8086, Device 0x7A50, Revision 0x11
|
||||
PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
|
||||
PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
|
||||
PCI Device: 0000:00:1f.6: Class 0x00020000, Vendor 0x8086, Device 0x0DC8, Revision 0x11
|
||||
PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2820, Revision 0xA1
|
||||
PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BD, Revision 0xA1
|
||||
PCI Device: 0000:02:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
|
||||
PCI Device: 0000:03:00.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
|
||||
PCI Device: 0000:03:01.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
|
||||
PCI Device: 0000:03:02.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
|
||||
PCI Device: 0000:03:03.0: Class 0x00060400, Vendor 0x8086, Device 0x1133, Revision 0x02
|
||||
PCI Device: 0000:04:00.0: Class 0x000C0340, Vendor 0x8086, Device 0x1134, Revision 0x00
|
||||
PCI Device: 0000:39:00.0: Class 0x000C0330, Vendor 0x8086, Device 0x1135, Revision 0x00
|
||||
PCI Device: 0000:6c:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
|
||||
PCI Device: 10000:e0:1d.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
|
||||
PCI Device: 10000:e0:1d.4: Class 0x00060400, Vendor 0x8086, Device 0x7A34, Revision 0x11
|
||||
PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
|
||||
## GPIO ##
|
||||
600 Series PCH
|
||||
GPP_I0 (0x6E,0x00) 0x44000100 0x00000018 0x00000000 0x00000000
|
||||
GPP_I1 (0x6E,0x02) 0x44000500 0x00000019 0x00000000 0x00000000
|
||||
GPP_I2 (0x6E,0x04) 0x86800100 0x0000001a 0x00000000 0x00000000
|
||||
GPP_I3 (0x6E,0x06) 0x44000500 0x0000001b 0x00000000 0x00000000
|
||||
GPP_I4 (0x6E,0x08) 0x86800100 0x0000001c 0x00000000 0x00000000
|
||||
GPP_I5 (0x6E,0x0A) 0x84000201 0x0000001d 0x00000000 0x00000000
|
||||
GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
|
||||
GPP_I7 (0x6E,0x0E) 0x44000300 0x00000020 0x00000000 0x00000000
|
||||
GPP_I8 (0x6E,0x10) 0x44000200 0x00000021 0x00000000 0x00000000
|
||||
GPP_I9 (0x6E,0x12) 0x44000300 0x00000022 0x00000000 0x00000000
|
||||
GPP_I10 (0x6E,0x14) 0x44000300 0x00000023 0x00000000 0x00000000
|
||||
GPP_I11 (0x6E,0x16) 0x84000402 0x00000024 0x00000000 0x00000000
|
||||
GPP_I12 (0x6E,0x18) 0x84000402 0x00000025 0x00000000 0x00000000
|
||||
GPP_I13 (0x6E,0x1A) 0x84000402 0x00000026 0x00000000 0x00000000
|
||||
GPP_I14 (0x6E,0x1C) 0x84000402 0x00000027 0x00000000 0x00000000
|
||||
GPP_I15 (0x6E,0x1E) 0x44000300 0x00000028 0x00000000 0x00000000
|
||||
GPP_I16 (0x6E,0x20) 0x44000300 0x00000029 0x00000000 0x00000000
|
||||
GPP_I17 (0x6E,0x22) 0x44000300 0x0000002a 0x00000000 0x00000000
|
||||
GPP_I18 (0x6E,0x24) 0x44000200 0x0000002b 0x00000000 0x00000000
|
||||
GPP_I19 (0x6E,0x26) 0x44000300 0x0000002c 0x00000000 0x00000000
|
||||
GPP_I20 (0x6E,0x28) 0x44000300 0x0000002d 0x00000000 0x00000000
|
||||
GPP_I21 (0x6E,0x2A) 0x44000300 0x0000002e 0x00000000 0x00000000
|
||||
GPP_I22 (0x6E,0x2C) 0x44000200 0x00000030 0x00000000 0x00000000
|
||||
GPP_R0 (0x6E,0x32) 0x44000600 0x00000031 0x00000000 0x00000000
|
||||
GPP_R1 (0x6E,0x34) 0x44000600 0x00003c32 0x00000000 0x00000000
|
||||
GPP_R2 (0x6E,0x36) 0x44000600 0x00003c33 0x00000000 0x00000000
|
||||
GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
|
||||
GPP_R4 (0x6E,0x3A) 0x44000600 0x00000035 0x00000000 0x00000000
|
||||
GPP_R5 (0x6E,0x3C) 0x44000300 0x00000036 0x00000000 0x00000000
|
||||
GPP_R6 (0x6E,0x3E) 0x44000300 0x00000037 0x00000000 0x00000000
|
||||
GPP_R7 (0x6E,0x40) 0x44000300 0x00000038 0x00000000 0x00000000
|
||||
GPP_R8 (0x6E,0x42) 0x84000102 0x00000039 0x00000000 0x00000000
|
||||
GPP_R9 (0x6E,0x44) 0x44000502 0x0000003a 0x00000000 0x00000000
|
||||
GPP_R10 (0x6E,0x46) 0x44000300 0x0000003b 0x00000000 0x00000000
|
||||
GPP_R11 (0x6E,0x48) 0x44000300 0x0000003c 0x00000000 0x00000000
|
||||
GPP_R12 (0x6E,0x4A) 0x44000300 0x0000003d 0x00000000 0x00000000
|
||||
GPP_R13 (0x6E,0x4C) 0x44000300 0x0000003e 0x00000000 0x00000000
|
||||
GPP_R14 (0x6E,0x4E) 0x44000300 0x0000003f 0x00000000 0x00000000
|
||||
GPP_R15 (0x6E,0x50) 0x44000300 0x00000040 0x00000000 0x00000000
|
||||
GPP_R16 (0x6E,0x52) 0x44000201 0x00000041 0x00000000 0x00000000
|
||||
GPP_R17 (0x6E,0x54) 0x44000300 0x00000042 0x00000000 0x00000000
|
||||
GPP_R18 (0x6E,0x56) 0x44000300 0x00000043 0x00000000 0x00000000
|
||||
GPP_R19 (0x6E,0x58) 0x44000300 0x00000044 0x00000000 0x00000000
|
||||
GPP_R20 (0x6E,0x5A) 0x44000300 0x00000045 0x00000000 0x00000000
|
||||
GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
|
||||
GPP_J0 (0x6E,0x60) 0x44000502 0x00000047 0x00000000 0x00000000
|
||||
GPP_J1 (0x6E,0x62) 0x84000600 0x00000048 0x00000000 0x00000000
|
||||
GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
|
||||
GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
|
||||
GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
|
||||
GPP_J5 (0x6E,0x6A) 0x44000502 0x0000304c 0x00000000 0x00000000
|
||||
GPP_J6 (0x6E,0x6C) 0x44000502 0x0000004d 0x00000000 0x00000000
|
||||
GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
|
||||
GPP_J8 (0x6E,0x70) 0x44000300 0x00000050 0x00000000 0x00000000
|
||||
GPP_J9 (0x6E,0x72) 0x44000300 0x00000051 0x00000000 0x00000000
|
||||
GPP_J10 (0x6E,0x74) 0x44000700 0x00001052 0x00000000 0x00000000
|
||||
GPP_J11 (0x6E,0x76) 0x44000700 0x00001053 0x00000000 0x00000000
|
||||
GPP_B0 (0x6D,0x00) 0x40100102 0x00000050 0x00000000 0x00000000
|
||||
GPP_B1 (0x6D,0x02) 0x44000300 0x00000051 0x00000000 0x00000000
|
||||
GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
|
||||
GPP_B3 (0x6D,0x06) 0x44000201 0x00000053 0x00000000 0x00000000
|
||||
GPP_B4 (0x6D,0x08) 0x44000300 0x00000054 0x00000000 0x00000000
|
||||
GPP_B5 (0x6D,0x0A) 0x44000300 0x00000055 0x00000000 0x00000000
|
||||
GPP_B6 (0x6D,0x0C) 0x44000300 0x00000056 0x00000000 0x00000000
|
||||
GPP_B7 (0x6D,0x0E) 0x44000300 0x00000057 0x00000000 0x00000000
|
||||
GPP_B8 (0x6D,0x10) 0x44000300 0x00000058 0x00000000 0x00000000
|
||||
GPP_B9 (0x6D,0x12) 0x44000300 0x00000059 0x00000000 0x00000000
|
||||
GPP_B10 (0x6D,0x14) 0x44000300 0x0000005a 0x00000000 0x00000000
|
||||
GPP_B11 (0x6D,0x16) 0x44000300 0x0000005b 0x00000000 0x00000000
|
||||
GPP_B12 (0x6D,0x18) 0x44000600 0x0000005c 0x00000000 0x00000000
|
||||
GPP_B13 (0x6D,0x1A) 0x44000600 0x0000005d 0x00000000 0x00000000
|
||||
GPP_B14 (0x6D,0x1C) 0x44000200 0x0000005e 0x00000000 0x00000000
|
||||
GPP_B15 (0x6D,0x1E) 0x44000102 0x0000005f 0x00000000 0x00000000
|
||||
GPP_B16 (0x6D,0x20) 0x44000300 0x00000060 0x00000000 0x00000000
|
||||
GPP_B17 (0x6D,0x22) 0x44000300 0x00000061 0x00000000 0x00000000
|
||||
GPP_B18 (0x6D,0x24) 0x04000602 0x00000062 0x00000000 0x00000000
|
||||
GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
|
||||
GPP_B20 (0x6D,0x28) 0x44000700 0x00001064 0x00000000 0x00000000
|
||||
GPP_B21 (0x6D,0x2A) 0x42880102 0x00000065 0x00000000 0x00000000
|
||||
GPP_B22 (0x6D,0x2C) 0x44000201 0x00000066 0x00000000 0x00000000
|
||||
GPP_B23 (0x6D,0x2E) 0x44000200 0x00000067 0x00000800 0x00000000
|
||||
GPP_G0 (0x6D,0x30) 0x44000100 0x00000068 0x00000000 0x00000000
|
||||
GPP_G1 (0x6D,0x32) 0x44000102 0x00000069 0x00000000 0x00000000
|
||||
GPP_G2 (0x6D,0x34) 0x44000700 0x0000106a 0x00000000 0x00000000
|
||||
GPP_G3 (0x6D,0x36) 0x44000100 0x0000006b 0x00000000 0x00000000
|
||||
GPP_G4 (0x6D,0x38) 0x44000102 0x0000006c 0x00000000 0x00000000
|
||||
GPP_G5 (0x6D,0x3A) 0x44000600 0x0000006d 0x00000000 0x00000000
|
||||
GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
|
||||
GPP_G7 (0x6D,0x3E) 0x44000100 0x0000006f 0x00000000 0x00000000
|
||||
GPP_H0 (0x6D,0x40) 0x44000300 0x00000070 0x00000000 0x00000000
|
||||
GPP_H1 (0x6D,0x42) 0x44000102 0x00000071 0x00000000 0x00000000
|
||||
GPP_H2 (0x6D,0x44) 0x44000702 0x00000072 0x00000000 0x00000000
|
||||
GPP_H3 (0x6D,0x46) 0x44000300 0x00000073 0x00000000 0x00000000
|
||||
GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
|
||||
GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
|
||||
GPP_H6 (0x6D,0x4C) 0x44000702 0x00000076 0x00000000 0x00000000
|
||||
GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
|
||||
GPP_H8 (0x6D,0x50) 0x44000700 0x00000018 0x00000000 0x00000000
|
||||
GPP_H9 (0x6D,0x52) 0x44000700 0x00000019 0x00000000 0x00000000
|
||||
GPP_H10 (0x6D,0x54) 0x84000402 0x00000020 0x00000000 0x00000000
|
||||
GPP_H11 (0x6D,0x56) 0x84000402 0x00000021 0x00000000 0x00000000
|
||||
GPP_H12 (0x6D,0x58) 0x44000200 0x00000022 0x00000000 0x00000000
|
||||
GPP_H13 (0x6D,0x5A) 0x84000402 0x00000023 0x00000000 0x00000000
|
||||
GPP_H14 (0x6D,0x5C) 0x84000402 0x00000024 0x00000000 0x00000000
|
||||
GPP_H15 (0x6D,0x5E) 0x84000402 0x00000025 0x00000800 0x00000000
|
||||
GPP_H16 (0x6D,0x60) 0x84000402 0x00000026 0x00000000 0x00000000
|
||||
GPP_H17 (0x6D,0x62) 0x84000201 0x00000027 0x00000000 0x00000000
|
||||
GPP_H18 (0x6D,0x64) 0x44000200 0x00000028 0x00000000 0x00000000
|
||||
GPP_H19 (0x6D,0x66) 0x44000300 0x00000029 0x00000000 0x00000000
|
||||
GPP_H20 (0x6D,0x68) 0x44000300 0x0000002a 0x00000000 0x00000000
|
||||
GPP_H21 (0x6D,0x6A) 0x44000200 0x0000002b 0x00000000 0x00000000
|
||||
GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
|
||||
GPP_H23 (0x6D,0x6E) 0x44000300 0x0000002d 0x00000000 0x00000000
|
||||
GPD0 (0x6C,0x00) 0x04000502 0x00003060 0x00000000 0x00000000
|
||||
GPD1 (0x6C,0x02) 0x04000502 0x00003c61 0x00000000 0x00000000
|
||||
GPD2 (0x6C,0x04) 0x04000702 0x00000062 0x00000000 0x00000000
|
||||
GPD3 (0x6C,0x06) 0x04000502 0x00003063 0x00000010 0x00000000
|
||||
GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
|
||||
GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
|
||||
GPD6 (0x6C,0x0C) 0x04000600 0x00000066 0x00000000 0x00000000
|
||||
GPD7 (0x6C,0x0E) 0x04000200 0x00000067 0x00000000 0x00000000
|
||||
GPD8 (0x6C,0x10) 0x04000600 0x00000068 0x00000000 0x00000000
|
||||
GPD9 (0x6C,0x12) 0x04000600 0x00000069 0x00000000 0x00000000
|
||||
GPD10 (0x6C,0x14) 0x04000600 0x0000006a 0x00000000 0x00000000
|
||||
GPD11 (0x6C,0x16) 0x04000600 0x0000006b 0x00000000 0x00000000
|
||||
GPD12 (0x6C,0x18) 0x04000300 0x0000006c 0x00000000 0x00000000
|
||||
GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
|
||||
GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
|
||||
GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
|
||||
GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
|
||||
GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
|
||||
GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
|
||||
GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
|
||||
GPP_A7 (0x6B,0x20) 0x44000700 0x00003025 0x00000000 0x00000000
|
||||
GPP_A8 (0x6B,0x22) 0x44000700 0x00003026 0x00000000 0x00000000
|
||||
GPP_A9 (0x6B,0x24) 0x44000700 0x00003027 0x00000000 0x00000000
|
||||
GPP_A10 (0x6B,0x26) 0x44000702 0x00003028 0x00000000 0x00000000
|
||||
GPP_A11 (0x6B,0x28) 0x44000702 0x00003029 0x00000000 0x00000000
|
||||
GPP_A12 (0x6B,0x2A) 0x44000702 0x0000302a 0x00000000 0x00000000
|
||||
GPP_A13 (0x6B,0x2C) 0x44000702 0x0000302b 0x00000000 0x00000000
|
||||
GPP_A14 (0x6B,0x2E) 0x44000300 0x0000002c 0x00000000 0x00000000
|
||||
GPP_C0 (0x6B,0x32) 0x44000402 0x0000002d 0x00000000 0x00000000
|
||||
GPP_C1 (0x6B,0x34) 0x44000402 0x0000002e 0x00000000 0x00000000
|
||||
GPP_C2 (0x6B,0x36) 0x44000200 0x0000002f 0x00000800 0x00000000
|
||||
GPP_C3 (0x6B,0x38) 0x44000c02 0x00000030 0x00000000 0x00000000
|
||||
GPP_C4 (0x6B,0x3A) 0x44000c02 0x00000031 0x00000000 0x00000000
|
||||
GPP_C5 (0x6B,0x3C) 0x44000200 0x00000032 0x00000000 0x00000000
|
||||
GPP_C6 (0x6B,0x3E) 0x44000802 0x00000033 0x00000000 0x00000000
|
||||
GPP_C7 (0x6B,0x40) 0x44000802 0x00000034 0x00000000 0x00000000
|
||||
GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
|
||||
GPP_C9 (0x6B,0x44) 0x44000300 0x00000036 0x00000000 0x00000000
|
||||
GPP_C10 (0x6B,0x46) 0x44000201 0x00000037 0x00000000 0x00000000
|
||||
GPP_C11 (0x6B,0x48) 0x44000201 0x00000038 0x00000000 0x00000000
|
||||
GPP_C12 (0x6B,0x4A) 0x44000300 0x00000039 0x00000000 0x00000000
|
||||
GPP_C13 (0x6B,0x4C) 0x44000300 0x0000003a 0x00000000 0x00000000
|
||||
GPP_C14 (0x6B,0x4E) 0x44000300 0x0000003b 0x00000000 0x00000000
|
||||
GPP_C15 (0x6B,0x50) 0x44000300 0x0000003c 0x00000000 0x00000000
|
||||
GPP_C16 (0x6B,0x52) 0x44000402 0x0000003d 0x00000000 0x00000000
|
||||
GPP_C17 (0x6B,0x54) 0x44000402 0x0000003e 0x00000000 0x00000000
|
||||
GPP_C18 (0x6B,0x56) 0x44000402 0x0000003f 0x00000000 0x00000000
|
||||
GPP_C19 (0x6B,0x58) 0x44000402 0x00000040 0x00000000 0x00000000
|
||||
GPP_C20 (0x6B,0x5A) 0x44000300 0x00000041 0x00000000 0x00000000
|
||||
GPP_C21 (0x6B,0x5C) 0x44000300 0x00000042 0x00000000 0x00000000
|
||||
GPP_C22 (0x6B,0x5E) 0x44000300 0x00000043 0x00000000 0x00000000
|
||||
GPP_C23 (0x6B,0x60) 0x44000300 0x00000044 0x00000000 0x00000000
|
||||
GPP_S0 (0x6A,0x00) 0x44000300 0x01800030 0x00000000 0x00000000
|
||||
GPP_S1 (0x6A,0x02) 0x44000300 0x01800031 0x00000000 0x00000000
|
||||
GPP_S2 (0x6A,0x04) 0x44000300 0x01800032 0x00000000 0x00000000
|
||||
GPP_S3 (0x6A,0x06) 0x44000300 0x01800033 0x00000000 0x00000000
|
||||
GPP_S4 (0x6A,0x08) 0x44000300 0x01800034 0x00000000 0x00000000
|
||||
GPP_S5 (0x6A,0x0A) 0x44000300 0x01800035 0x00000000 0x00000000
|
||||
GPP_S6 (0x6A,0x0C) 0x44000a00 0x01800036 0x00000000 0x00000000
|
||||
GPP_S7 (0x6A,0x0E) 0x44000900 0x01800037 0x00000000 0x00000000
|
||||
GPP_E0 (0x6A,0x10) 0x44000300 0x00000038 0x00000000 0x00000000
|
||||
GPP_E1 (0x6A,0x12) 0x44000300 0x00000039 0x00000000 0x00000000
|
||||
GPP_E2 (0x6A,0x14) 0x44000300 0x0000003a 0x00000000 0x00000000
|
||||
GPP_E3 (0x6A,0x16) 0x42840103 0x0000003b 0x00000000 0x00000000
|
||||
GPP_E4 (0x6A,0x18) 0x44000300 0x0000003c 0x00000000 0x00000000
|
||||
GPP_E5 (0x6A,0x1A) 0x44000300 0x0000003d 0x00000000 0x00000000
|
||||
GPP_E6 (0x6A,0x1C) 0x44000300 0x0000003e 0x00000000 0x00000000
|
||||
GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
|
||||
GPP_E8 (0x6A,0x20) 0x44000600 0x00000040 0x00000000 0x00000000
|
||||
GPP_E9 (0x6A,0x22) 0x44000602 0x00000041 0x00000800 0x00000000
|
||||
GPP_E10 (0x6A,0x24) 0x44000602 0x00000042 0x00000800 0x00000000
|
||||
GPP_E11 (0x6A,0x26) 0x44000602 0x00000043 0x00000800 0x00000000
|
||||
GPP_E12 (0x6A,0x28) 0x44000602 0x00000044 0x00000000 0x00000000
|
||||
GPP_E13 (0x6A,0x2A) 0x44000300 0x00000045 0x00000000 0x00000000
|
||||
GPP_E14 (0x6A,0x2C) 0x44000300 0x00000046 0x00000000 0x00000000
|
||||
GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
|
||||
GPP_E16 (0x6A,0x30) 0x44000300 0x00000048 0x00000000 0x00000000
|
||||
GPP_E17 (0x6A,0x32) 0x44000102 0x00001049 0x00000000 0x00000000
|
||||
GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
|
||||
GPP_E19 (0x6A,0x36) 0x44000300 0x0000004b 0x00000000 0x00000000
|
||||
GPP_E20 (0x6A,0x38) 0x44000300 0x0000004c 0x00000000 0x00000000
|
||||
GPP_E21 (0x6A,0x3A) 0x44000300 0x0000004d 0x00000000 0x00000000
|
||||
GPP_K0 (0x6A,0x3E) 0x42800102 0x0000004e 0x00000000 0x00000000
|
||||
GPP_K1 (0x6A,0x40) 0x44000300 0x00000050 0x00000000 0x00000000
|
||||
GPP_K2 (0x6A,0x42) 0x44000300 0x00000051 0x00000000 0x00000000
|
||||
GPP_K3 (0x6A,0x44) 0x84000201 0x00000052 0x00000000 0x00000000
|
||||
GPP_K4 (0x6A,0x46) 0x04000200 0x00000053 0x00000000 0x00000000
|
||||
GPP_K5 (0x6A,0x48) 0x44000300 0x00000054 0x00000000 0x00000000
|
||||
GPP_K6 (0x6A,0x4A) 0x44000b02 0x00003055 0x00000000 0x00000000
|
||||
GPP_K7 (0x6A,0x4C) 0x44000b00 0x00001056 0x00000000 0x00000000
|
||||
GPP_K8 (0x6A,0x4E) 0x44000600 0x00000057 0x00000000 0x00000000
|
||||
GPP_K9 (0x6A,0x50) 0x44000600 0x00000058 0x00000000 0x00000000
|
||||
GPP_K10 (0x6A,0x52) 0x44000b02 0x00003059 0x00000000 0x00000000
|
||||
GPP_K11 (0x6A,0x54) 0x44000300 0x0000005a 0x00000000 0x00000000
|
||||
GPP_F0 (0x6A,0x5C) 0x44000a02 0x0000005b 0x00000000 0x00000000
|
||||
GPP_F1 (0x6A,0x5E) 0x44000300 0x0000005c 0x00000000 0x00000000
|
||||
GPP_F2 (0x6A,0x60) 0x84000201 0x0000005d 0x00000000 0x00000000
|
||||
GPP_F3 (0x6A,0x62) 0x84000201 0x0000005e 0x00000000 0x00000000
|
||||
GPP_F4 (0x6A,0x64) 0x84000201 0x00000060 0x00000000 0x00000000
|
||||
GPP_F5 (0x6A,0x66) 0x44000600 0x00000061 0x00000000 0x00000000
|
||||
GPP_F6 (0x6A,0x68) 0x44000300 0x00000062 0x00000000 0x00000000
|
||||
GPP_F7 (0x6A,0x6A) 0x84000102 0x00000063 0x00000000 0x00000000
|
||||
GPP_F8 (0x6A,0x6C) 0x44000100 0x00000064 0x00000000 0x00000000
|
||||
GPP_F9 (0x6A,0x6E) 0x44000201 0x00000065 0x00000000 0x00000000
|
||||
GPP_F10 (0x6A,0x70) 0x44000300 0x00000066 0x00000000 0x00000000
|
||||
GPP_F11 (0x6A,0x72) 0x44000300 0x00000067 0x00000000 0x00000000
|
||||
GPP_F12 (0x6A,0x74) 0x44000300 0x00000068 0x00000000 0x00000000
|
||||
GPP_F13 (0x6A,0x76) 0x44000300 0x00000069 0x00000000 0x00000000
|
||||
GPP_F14 (0x6A,0x78) 0x44000700 0x0000006a 0x00000000 0x00000000
|
||||
GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
|
||||
GPP_F16 (0x6A,0x7C) 0x44000300 0x0000006c 0x00000000 0x00000000
|
||||
GPP_F17 (0x6A,0x7E) 0x44000102 0x0000006d 0x00000000 0x00000000
|
||||
GPP_F18 (0x6A,0x80) 0x84000200 0x0000006e 0x00000000 0x00000000
|
||||
GPP_F19 (0x6A,0x82) 0x44000600 0x0000006f 0x00000000 0x00000000
|
||||
GPP_F20 (0x6A,0x84) 0x44000600 0x00000070 0x00000000 0x00000000
|
||||
GPP_F21 (0x6A,0x86) 0x44000600 0x00000071 0x00000000 0x00000000
|
||||
GPP_F22 (0x6A,0x88) 0x44000300 0x00000072 0x00000000 0x00000000
|
||||
GPP_F23 (0x6A,0x8A) 0x44000300 0x00000073 0x00000000 0x00000000
|
||||
GPP_D0 (0x69,0x20) 0x44000300 0x00000026 0x00000000 0x00000000
|
||||
GPP_D1 (0x69,0x22) 0x44000300 0x00000027 0x00000000 0x00000000
|
||||
GPP_D2 (0x69,0x24) 0x44000300 0x00000028 0x00000000 0x00000000
|
||||
GPP_D3 (0x69,0x26) 0x44000300 0x00000029 0x00000000 0x00000000
|
||||
GPP_D4 (0x69,0x28) 0x44000300 0x0000002a 0x00000000 0x00000000
|
||||
GPP_D5 (0x69,0x2A) 0x44000300 0x0000002b 0x00000000 0x00000000
|
||||
GPP_D6 (0x69,0x2C) 0x44000300 0x0000002c 0x00000000 0x00000000
|
||||
GPP_D7 (0x69,0x2E) 0x44000300 0x0000002d 0x00000000 0x00000000
|
||||
GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
|
||||
GPP_D9 (0x69,0x32) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D10 (0x69,0x34) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D13 (0x69,0x3A) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D14 (0x69,0x3C) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
|
||||
GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
GPP_D22 (0x69,0x4C) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
## HDAUDIO ##
|
||||
hdaudioC0D0
|
||||
vendor_name: Realtek
|
||||
chip_name: ALC256
|
||||
vendor_id: 0x10ec0256
|
||||
subsystem_id: 0x1558a671
|
||||
revision_id: 0x100002
|
||||
0x12: 0x90a60130
|
||||
0x13: 0x40000000
|
||||
0x14: 0x90170110
|
||||
0x18: 0x411111f0
|
||||
0x19: 0x411111f0
|
||||
0x1a: 0x411111f0
|
||||
0x1b: 0x02a11040
|
||||
0x1d: 0x41700001
|
||||
0x1e: 0x411111f0
|
||||
0x21: 0x02211020
|
||||
hdaudioC0D2
|
||||
vendor_name: Intel
|
||||
chip_name: Raptorlake HDMI
|
||||
vendor_id: 0x80862818
|
||||
subsystem_id: 0x80860101
|
||||
revision_id: 0x100000
|
||||
0x04: 0x18560010
|
||||
0x06: 0x18560010
|
||||
0x08: 0x18560010
|
||||
0x0a: 0x18560010
|
||||
0x0b: 0x18560010
|
||||
0x0c: 0x18560010
|
||||
0x0d: 0x18560010
|
||||
0x0e: 0x18560010
|
||||
0x0f: 0x18560010
|
||||
hdaudioC1D0
|
||||
vendor_name: Nvidia
|
||||
chip_name: Generic HDMI
|
||||
vendor_id: 0x10de00a6
|
||||
subsystem_id: 0x10de0000
|
||||
revision_id: 0x100100
|
||||
0x04: 0x185600f0
|
||||
0x05: 0x585600f0
|
||||
0x06: 0x185600f0
|
||||
0x07: 0x585600f0
|
||||
@ -1,21 +0,0 @@
|
||||
CONFIG_VENDOR_SYSTEM76=y
|
||||
CONFIG_BOARD_SYSTEM76_ADDW3=y
|
||||
CONFIG_CCACHE=y
|
||||
CONFIG_CONSOLE_SERIAL=n
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
CONFIG_GBE_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/gbe.rom"
|
||||
CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
|
||||
CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
|
||||
CONFIG_PAYLOAD_ELF=y
|
||||
CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
|
||||
CONFIG_POST_IO=n
|
||||
CONFIG_SMMSTORE=y
|
||||
CONFIG_SMMSTORE_V2=y
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
|
||||
#CONFIG_CONSOLE_SYSTEM76_EC=y
|
||||
@ -1 +0,0 @@
|
||||
BOARD=system76/addw3
|
||||
@ -1,89 +0,0 @@
|
||||
id 5570 rev 6
|
||||
A0: data 1 mirror 1 pot 0 control 00
|
||||
A1: data 0 mirror 0 pot 0 control 00
|
||||
A2: data 0 mirror 1 pot 0 control 00
|
||||
A3: data 1 mirror 1 pot 0 control 80
|
||||
A4: data 0 mirror 0 pot 0 control 00
|
||||
A5: data 0 mirror 0 pot 0 control 00
|
||||
A6: data 0 mirror 0 pot 0 control 00
|
||||
A7: data 0 mirror 1 pot 0 control 00
|
||||
B0: data 0 mirror 0 pot 0 control 84
|
||||
B1: data 1 mirror 1 pot 0 control 84
|
||||
B2: data 1 mirror 1 pot 0 control 80
|
||||
B3: data 1 mirror 1 pot 0 control 80
|
||||
B4: data 1 mirror 1 pot 0 control 40
|
||||
B5: data 1 mirror 1 pot 0 control 40
|
||||
B6: data 1 mirror 1 pot 0 control 44
|
||||
B7: data 1 mirror 1 pot 0 control 80
|
||||
C0: data 1 mirror 1 pot 0 control 80
|
||||
C1: data 1 mirror 1 pot 0 control 04
|
||||
C2: data 1 mirror 1 pot 0 control 04
|
||||
C3: data 0 mirror 0 pot 0 control 04
|
||||
C4: data 0 mirror 0 pot 0 control 84
|
||||
C5: data 0 mirror 0 pot 0 control 04
|
||||
C6: data 1 mirror 1 pot 0 control 40
|
||||
C7: data 1 mirror 1 pot 0 control 44
|
||||
D0: data 1 mirror 1 pot 0 control 44
|
||||
D1: data 1 mirror 1 pot 0 control 44
|
||||
D2: data 1 mirror 1 pot 0 control 00
|
||||
D3: data 1 mirror 1 pot 0 control 44
|
||||
D4: data 1 mirror 1 pot 0 control 40
|
||||
D5: data 1 mirror 1 pot 0 control 44
|
||||
D6: data 1 mirror 1 pot 0 control 02
|
||||
D7: data 0 mirror 0 pot 0 control 02
|
||||
E0: data 1 mirror 1 pot 0 control 04
|
||||
E1: data 1 mirror 1 pot 0 control 44
|
||||
E2: data 0 mirror 0 pot 0 control 84
|
||||
E3: data 1 mirror 1 pot 0 control 40
|
||||
E4: data 1 mirror 1 pot 0 control 42
|
||||
E5: data 1 mirror 1 pot 0 control 40
|
||||
E6: data 1 mirror 1 pot 0 control 80
|
||||
E7: data 1 mirror 1 pot 0 control 04
|
||||
F0: data 0 mirror 0 pot 0 control 44
|
||||
F1: data 1 mirror 1 pot 0 control 44
|
||||
F2: data 1 mirror 1 pot 0 control 44
|
||||
F3: data 1 mirror 1 pot 0 control 40
|
||||
F4: data 1 mirror 1 pot 0 control 04
|
||||
F5: data 1 mirror 1 pot 0 control 04
|
||||
F6: data 0 mirror 0 pot 0 control 00
|
||||
F7: data 0 mirror 0 pot 0 control 80
|
||||
G0: data 0 mirror 0 pot 0 control 80
|
||||
G1: data 1 mirror 1 pot 0 control 80
|
||||
G2: data 1 mirror 1 pot 0 control 80
|
||||
G3: data 0 mirror 0 pot 0 control 00
|
||||
G4: data 0 mirror 0 pot 0 control 00
|
||||
G5: data 0 mirror 0 pot 0 control 00
|
||||
G6: data 0 mirror 0 pot 0 control 44
|
||||
G7: data 0 mirror 0 pot 0 control 00
|
||||
H0: data 0 mirror 0 pot 0 control 80
|
||||
H1: data 1 mirror 1 pot 0 control 80
|
||||
H2: data 0 mirror 0 pot 0 control 44
|
||||
H3: data 0 mirror 0 pot 0 control 40
|
||||
H4: data 1 mirror 1 pot 0 control 80
|
||||
H5: data 0 mirror 0 pot 0 control 44
|
||||
H6: data 1 mirror 1 pot 0 control 80
|
||||
H7: data 1 mirror 1 pot 0 control 80
|
||||
I0: data 0 mirror 0 pot 0 control 00
|
||||
I1: data 0 mirror 0 pot 0 control 00
|
||||
I2: data 0 mirror 0 pot 0 control 00
|
||||
I3: data 0 mirror 0 pot 0 control 00
|
||||
I4: data 0 mirror 0 pot 0 control 00
|
||||
I5: data 1 mirror 1 pot 0 control 80
|
||||
I6: data 1 mirror 1 pot 0 control 80
|
||||
I7: data 0 mirror 0 pot 0 control 00
|
||||
J0: data 1 mirror 1 pot 0 control 44
|
||||
J1: data 1 mirror 1 pot 0 control 40
|
||||
J2: data 1 mirror 1 pot 0 control 80
|
||||
J3: data 0 mirror 0 pot 0 control 80
|
||||
J4: data 1 mirror 1 pot 0 control 40
|
||||
J5: data 0 mirror 0 pot 0 control 40
|
||||
J6: data 0 mirror 0 pot 0 control 44
|
||||
J7: data 1 mirror 1 pot 0 control 80
|
||||
M0: data 0 mirror 0 control 06
|
||||
M1: data 1 mirror 0 control 06
|
||||
M2: data 1 mirror 1 control 06
|
||||
M3: data 1 mirror 1 control 06
|
||||
M4: data 0 mirror 1 control 06
|
||||
M5: data 0 mirror 0 control 00
|
||||
M6: data 1 mirror 1 control 86
|
||||
M7: data 0 mirror 0 control 00
|
||||
@ -1,9 +0,0 @@
|
||||
BOOTLOADER=COREBOOT
|
||||
DISABLE_SERIAL_TERMINAL=TRUE
|
||||
PLATFORM_BOOT_TIMEOUT=2
|
||||
PS2_KEYBOARD_ENABLE=TRUE
|
||||
SECURE_BOOT_ENABLE=TRUE
|
||||
SERIAL_DRIVER_ENABLE=FALSE
|
||||
SHELL_TYPE=NONE
|
||||
TPM_ENABLE=TRUE
|
||||
#SYSTEM76_EC_LOGGING=TRUE
|
||||
BIN
models/addw3/fd.rom
(Stored with Git LFS)
BIN
models/addw3/fd.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw3/gbe.rom
(Stored with Git LFS)
BIN
models/addw3/gbe.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw3/me.rom
(Stored with Git LFS)
BIN
models/addw3/me.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw3/vbt.rom
(Stored with Git LFS)
BIN
models/addw3/vbt.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw4/IntelGopDriver.efi
(Stored with Git LFS)
BIN
models/addw4/IntelGopDriver.efi
(Stored with Git LFS)
Binary file not shown.
@ -1,9 +0,0 @@
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = IntelGopDriver
|
||||
FILE_GUID = 767222f4-a9f4-41ba-9faa-edaa1405a486
|
||||
MODULE_TYPE = UEFI_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
[Binaries.X64]
|
||||
PE32|IntelGopDriver.efi|*
|
||||
@ -1 +0,0 @@
|
||||
# System76 Adder WS (addw4)
|
||||
@ -1 +0,0 @@
|
||||
GD25Q256D
|
||||
@ -1,326 +0,0 @@
|
||||
## PCI ##
|
||||
PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0xA702, Revision 0x01
|
||||
PCI Device: 0000:00:01.0: Class 0x00060400, Vendor 0x8086, Device 0xA70D, Revision 0x01
|
||||
PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0xA788, Revision 0x04
|
||||
PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0xA71D, Revision 0x01
|
||||
PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0xA74F, Revision 0x01
|
||||
PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0xA77D, Revision 0x01
|
||||
PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0xA77F, Revision 0x00
|
||||
PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7A60, Revision 0x11
|
||||
PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7A27, Revision 0x11
|
||||
PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7A70, Revision 0x11
|
||||
PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7A4C, Revision 0x11
|
||||
PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7A4D, Revision 0x11
|
||||
PCI Device: 0000:00:15.3: Class 0x000C8000, Vendor 0x8086, Device 0x7A4F, Revision 0x11
|
||||
PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7A68, Revision 0x11
|
||||
PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7A3A, Revision 0x11
|
||||
PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7A0C, Revision 0x11
|
||||
PCI Device: 0000:00:1f.3: Class 0x00040380, Vendor 0x8086, Device 0x7A50, Revision 0x11
|
||||
PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7A23, Revision 0x11
|
||||
PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7A24, Revision 0x11
|
||||
PCI Device: 0000:01:00.0: Class 0x00030000, Vendor 0x10DE, Device 0x2820, Revision 0xA1
|
||||
PCI Device: 0000:01:00.1: Class 0x00040300, Vendor 0x10DE, Device 0x22BD, Revision 0xA1
|
||||
PCI Device: 0000:02:00.0: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x15
|
||||
PCI Device: 10000:e0:1d.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
|
||||
PCI Device: 10000:e0:1d.4: Class 0x00060400, Vendor 0x8086, Device 0x7A34, Revision 0x11
|
||||
PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
|
||||
## GPIO ##
|
||||
600 Series PCH
|
||||
GPP_I0 (0x6E,0x00) 0x84000200 0x00000018 0x00000000 0x00000000
|
||||
GPP_I1 (0x6E,0x02) 0x82000500 0x00000019 0x00000000 0x00000000
|
||||
GPP_I2 (0x6E,0x04) 0x86880100 0x0000001a 0x00000000 0x00000000
|
||||
GPP_I3 (0x6E,0x06) 0x82000502 0x0000001b 0x00000000 0x00000000
|
||||
GPP_I4 (0x6E,0x08) 0x84000200 0x0000001c 0x00000000 0x00000000
|
||||
GPP_I5 (0x6E,0x0A) 0x44000200 0x0000001d 0x00000000 0x00000000
|
||||
GPP_I6 (0x6E,0x0C) 0x44000200 0x0000001e 0x00000000 0x00000000
|
||||
GPP_I7 (0x6E,0x0E) 0x44000200 0x00000020 0x00000000 0x00000000
|
||||
GPP_I8 (0x6E,0x10) 0x44000102 0x00000021 0x00000000 0x00000000
|
||||
GPP_I9 (0x6E,0x12) 0x44000200 0x00000022 0x00000000 0x00000000
|
||||
GPP_I10 (0x6E,0x14) 0x44000200 0x00000023 0x00000000 0x00000000
|
||||
GPP_I11 (0x6E,0x16) 0x44000102 0x00000024 0x00000000 0x00000000
|
||||
GPP_I12 (0x6E,0x18) 0x44000102 0x00000025 0x00000000 0x00000000
|
||||
GPP_I13 (0x6E,0x1A) 0x44000902 0x00000026 0x00000000 0x00000000
|
||||
GPP_I14 (0x6E,0x1C) 0x44000902 0x00000027 0x00000000 0x00000000
|
||||
GPP_I15 (0x6E,0x1E) 0x44000200 0x00000028 0x00000000 0x00000000
|
||||
GPP_I16 (0x6E,0x20) 0x44000200 0x00000029 0x00000000 0x00000000
|
||||
GPP_I17 (0x6E,0x22) 0x44000200 0x0000002a 0x00000000 0x00000000
|
||||
GPP_I18 (0x6E,0x24) 0x44000200 0x0000002b 0x00000000 0x00000000
|
||||
GPP_I19 (0x6E,0x26) 0x44000200 0x0000002c 0x00000000 0x00000000
|
||||
GPP_I20 (0x6E,0x28) 0x44000200 0x0000002d 0x00000000 0x00000000
|
||||
GPP_I21 (0x6E,0x2A) 0x44000200 0x0000002e 0x00000000 0x00000000
|
||||
GPP_I22 (0x6E,0x2C) 0x44000200 0x00000030 0x00000000 0x00000000
|
||||
GPP_R0 (0x6E,0x32) 0x44000600 0x00000031 0x00000000 0x00000000
|
||||
GPP_R1 (0x6E,0x34) 0x44000600 0x00003c32 0x00000000 0x00000000
|
||||
GPP_R2 (0x6E,0x36) 0x44000600 0x00003c33 0x00000000 0x00000000
|
||||
GPP_R3 (0x6E,0x38) 0x44000500 0x00003c34 0x00000000 0x00000000
|
||||
GPP_R4 (0x6E,0x3A) 0x44000600 0x00000035 0x00000000 0x00000000
|
||||
GPP_R5 (0x6E,0x3C) 0x44000200 0x00000036 0x00000000 0x00000000
|
||||
GPP_R6 (0x6E,0x3E) 0x44000200 0x00000037 0x00000000 0x00000000
|
||||
GPP_R7 (0x6E,0x40) 0x44000200 0x00000038 0x00000000 0x00000000
|
||||
GPP_R8 (0x6E,0x42) 0x44000100 0x00000039 0x00000000 0x00000000
|
||||
GPP_R9 (0x6E,0x44) 0x44000702 0x0000003a 0x00000000 0x00000000
|
||||
GPP_R10 (0x6E,0x46) 0x44000200 0x0000003b 0x00000000 0x00000000
|
||||
GPP_R11 (0x6E,0x48) 0x44000200 0x0000003c 0x00000000 0x00000000
|
||||
GPP_R12 (0x6E,0x4A) 0x44000200 0x0000003d 0x00000000 0x00000000
|
||||
GPP_R13 (0x6E,0x4C) 0x44000200 0x0000003e 0x00000000 0x00000000
|
||||
GPP_R14 (0x6E,0x4E) 0x44000200 0x0000003f 0x00000000 0x00000000
|
||||
GPP_R15 (0x6E,0x50) 0x44000200 0x00000040 0x00000000 0x00000000
|
||||
GPP_R16 (0x6E,0x52) 0x44000200 0x00000041 0x00000000 0x00000000
|
||||
GPP_R17 (0x6E,0x54) 0x44000200 0x00000042 0x00000000 0x00000000
|
||||
GPP_R18 (0x6E,0x56) 0x44000200 0x00000043 0x00000000 0x00000000
|
||||
GPP_R19 (0x6E,0x58) 0x44000102 0x00000044 0x00000000 0x00000000
|
||||
GPP_R20 (0x6E,0x5A) 0x44000200 0x00000045 0x00000000 0x00000000
|
||||
GPP_R21 (0x6E,0x5C) 0x44000200 0x00000046 0x00000000 0x00000000
|
||||
GPP_J0 (0x6E,0x60) 0x44000500 0x00000047 0x00000000 0x00000000
|
||||
GPP_J1 (0x6E,0x62) 0x44000700 0x00000048 0x00000000 0x00000000
|
||||
GPP_J2 (0x6E,0x64) 0x44000500 0x00000049 0x00000000 0x00000000
|
||||
GPP_J3 (0x6E,0x66) 0x44000502 0x0000304a 0x00000000 0x00000000
|
||||
GPP_J4 (0x6E,0x68) 0x44000500 0x0000004b 0x00000000 0x00000000
|
||||
GPP_J5 (0x6E,0x6A) 0x44000500 0x0000304c 0x00000000 0x00000000
|
||||
GPP_J6 (0x6E,0x6C) 0x44000500 0x0000004d 0x00000000 0x00000000
|
||||
GPP_J7 (0x6E,0x6E) 0x44000500 0x0000004e 0x00000000 0x00000000
|
||||
GPP_J8 (0x6E,0x70) 0x44000102 0x00000050 0x00000000 0x00000000
|
||||
GPP_J9 (0x6E,0x72) 0x44000200 0x00000051 0x00000000 0x00000000
|
||||
GPP_J10 (0x6E,0x74) 0x44000200 0x00000052 0x00000000 0x00000000
|
||||
GPP_J11 (0x6E,0x76) 0x44000200 0x00000053 0x00000000 0x00000000
|
||||
GPP_B0 (0x6D,0x00) 0x40100102 0x00003050 0x00000000 0x00000000
|
||||
GPP_B1 (0x6D,0x02) 0x44000102 0x00000051 0x00000000 0x00000000
|
||||
GPP_B2 (0x6D,0x04) 0x44000102 0x00000052 0x00000000 0x00000000
|
||||
GPP_B3 (0x6D,0x06) 0x84000201 0x00000053 0x00000000 0x00000000
|
||||
GPP_B4 (0x6D,0x08) 0x44000200 0x00000054 0x00000000 0x00000000
|
||||
GPP_B5 (0x6D,0x0A) 0x44000200 0x00000055 0x00000000 0x00000000
|
||||
GPP_B6 (0x6D,0x0C) 0x44000200 0x00000056 0x00000000 0x00000000
|
||||
GPP_B7 (0x6D,0x0E) 0x44000200 0x00000057 0x00000000 0x00000000
|
||||
GPP_B8 (0x6D,0x10) 0x44000200 0x00000058 0x00000000 0x00000000
|
||||
GPP_B9 (0x6D,0x12) 0x44000200 0x00000059 0x00000000 0x00000000
|
||||
GPP_B10 (0x6D,0x14) 0x44000200 0x0000005a 0x00000000 0x00000000
|
||||
GPP_B11 (0x6D,0x16) 0x44000200 0x0000005b 0x00000000 0x00000000
|
||||
GPP_B12 (0x6D,0x18) 0x44000200 0x0000005c 0x00000000 0x00000000
|
||||
GPP_B13 (0x6D,0x1A) 0x44000700 0x0000005d 0x00000000 0x00000000
|
||||
GPP_B14 (0x6D,0x1C) 0x44000500 0x0000005e 0x00000000 0x00000000
|
||||
GPP_B15 (0x6D,0x1E) 0x44000200 0x0000005f 0x00000000 0x00000000
|
||||
GPP_B16 (0x6D,0x20) 0x44000200 0x00000060 0x00000000 0x00000000
|
||||
GPP_B17 (0x6D,0x22) 0x44000200 0x00000061 0x00000000 0x00000000
|
||||
GPP_B18 (0x6D,0x24) 0x04000702 0x00000062 0x00000000 0x00000000
|
||||
GPP_B19 (0x6D,0x26) 0x44000201 0x00000063 0x00000000 0x00000000
|
||||
GPP_B20 (0x6D,0x28) 0x44000200 0x00000064 0x00000000 0x00000000
|
||||
GPP_B21 (0x6D,0x2A) 0x44000200 0x00000065 0x00000000 0x00000000
|
||||
GPP_B22 (0x6D,0x2C) 0x44000200 0x00000066 0x00000000 0x00000000
|
||||
GPP_B23 (0x6D,0x2E) 0x44000102 0x00000067 0x00000800 0x00000000
|
||||
GPP_G0 (0x6D,0x30) 0x44000200 0x00000068 0x00000000 0x00000000
|
||||
GPP_G1 (0x6D,0x32) 0x44000200 0x00000069 0x00000000 0x00000000
|
||||
GPP_G2 (0x6D,0x34) 0x44000200 0x0000006a 0x00000000 0x00000000
|
||||
GPP_G3 (0x6D,0x36) 0x44000102 0x0000006b 0x00000000 0x00000000
|
||||
GPP_G4 (0x6D,0x38) 0x44000102 0x0000006c 0x00000000 0x00000000
|
||||
GPP_G5 (0x6D,0x3A) 0x44000600 0x0000006d 0x00000000 0x00000000
|
||||
GPP_G6 (0x6D,0x3C) 0x44000100 0x0000006e 0x00000000 0x00000000
|
||||
GPP_G7 (0x6D,0x3E) 0x44000100 0x0000006f 0x00000000 0x00000000
|
||||
GPP_H0 (0x6D,0x40) 0x44000102 0x00000070 0x00000000 0x00000000
|
||||
GPP_H1 (0x6D,0x42) 0x44000200 0x00000071 0x00000000 0x00000000
|
||||
GPP_H2 (0x6D,0x44) 0x44000102 0x00000072 0x00000000 0x00000000
|
||||
GPP_H3 (0x6D,0x46) 0x44000300 0x00000073 0x00000000 0x00000000
|
||||
GPP_H4 (0x6D,0x48) 0x44000700 0x00000074 0x00000000 0x00000000
|
||||
GPP_H5 (0x6D,0x4A) 0x44000702 0x00000075 0x00000000 0x00000000
|
||||
GPP_H6 (0x6D,0x4C) 0x44000702 0x00000076 0x00000000 0x00000000
|
||||
GPP_H7 (0x6D,0x4E) 0x44000700 0x00000077 0x00000000 0x00000000
|
||||
GPP_H8 (0x6D,0x50) 0x44000702 0x00000018 0x00000000 0x00000000
|
||||
GPP_H9 (0x6D,0x52) 0x44000700 0x00000019 0x00000000 0x00000000
|
||||
GPP_H10 (0x6D,0x54) 0x44000200 0x00000020 0x00000000 0x00000000
|
||||
GPP_H11 (0x6D,0x56) 0x44000200 0x00000021 0x00000000 0x00000000
|
||||
GPP_H12 (0x6D,0x58) 0x44000200 0x00000022 0x00000000 0x00000000
|
||||
GPP_H13 (0x6D,0x5A) 0x44000200 0x00000023 0x00000000 0x00000000
|
||||
GPP_H14 (0x6D,0x5C) 0x44000200 0x00000024 0x00000000 0x00000000
|
||||
GPP_H15 (0x6D,0x5E) 0x44000200 0x00000025 0x00000000 0x00000000
|
||||
GPP_H16 (0x6D,0x60) 0x44000200 0x00000026 0x00000000 0x00000000
|
||||
GPP_H17 (0x6D,0x62) 0x44000200 0x00000027 0x00000000 0x00000000
|
||||
GPP_H18 (0x6D,0x64) 0x44000200 0x00000028 0x00000000 0x00000000
|
||||
GPP_H19 (0x6D,0x66) 0x44000200 0x00000029 0x00000000 0x00000000
|
||||
GPP_H20 (0x6D,0x68) 0x44000200 0x0000002a 0x00000000 0x00000000
|
||||
GPP_H21 (0x6D,0x6A) 0x44000200 0x0000002b 0x00000000 0x00000000
|
||||
GPP_H22 (0x6D,0x6C) 0x44000200 0x0000002c 0x00000000 0x00000000
|
||||
GPP_H23 (0x6D,0x6E) 0x44000200 0x0000002d 0x00000000 0x00000000
|
||||
GPD0 (0x6C,0x00) 0x04000702 0x00003060 0x00000000 0x00000000
|
||||
GPD1 (0x6C,0x02) 0x04000702 0x00003c61 0x00000000 0x00000000
|
||||
GPD2 (0x6C,0x04) 0x44000200 0x00000062 0x00000000 0x00000000
|
||||
GPD3 (0x6C,0x06) 0x04000702 0x00003063 0x00000010 0x00000000
|
||||
GPD4 (0x6C,0x08) 0x04000600 0x00000064 0x00000000 0x00000000
|
||||
GPD5 (0x6C,0x0A) 0x04000600 0x00000065 0x00000000 0x00000000
|
||||
GPD6 (0x6C,0x0C) 0x44000600 0x00000066 0x00000000 0x00000000
|
||||
GPD7 (0x6C,0x0E) 0x44000200 0x00000067 0x00000800 0x00000000
|
||||
GPD8 (0x6C,0x10) 0x04000700 0x00000068 0x00000000 0x00000000
|
||||
GPD9 (0x6C,0x12) 0x04000200 0x00000069 0x00000000 0x00000000
|
||||
GPD10 (0x6C,0x14) 0x44000600 0x0000006a 0x00000000 0x00000000
|
||||
GPD11 (0x6C,0x16) 0x44000200 0x0000006b 0x00000000 0x00000000
|
||||
GPD12 (0x6C,0x18) 0x44000200 0x0000006c 0x00000000 0x00000000
|
||||
GPP_A0 (0x6B,0x12) 0x44000700 0x00003018 0x00000000 0x00000000
|
||||
GPP_A1 (0x6B,0x14) 0x44000702 0x00003019 0x00000000 0x00000000
|
||||
GPP_A2 (0x6B,0x16) 0x44000700 0x00003020 0x00000000 0x00000000
|
||||
GPP_A3 (0x6B,0x18) 0x44000700 0x00003021 0x00000000 0x00000000
|
||||
GPP_A4 (0x6B,0x1A) 0x44000700 0x00003022 0x00000000 0x00000000
|
||||
GPP_A5 (0x6B,0x1C) 0x44000700 0x00001023 0x00000000 0x00000000
|
||||
GPP_A6 (0x6B,0x1E) 0x44000700 0x00000024 0x00000000 0x00000000
|
||||
GPP_A7 (0x6B,0x20) 0x44000200 0x00000025 0x00000000 0x00000000
|
||||
GPP_A8 (0x6B,0x22) 0x44000200 0x00000026 0x00000000 0x00000000
|
||||
GPP_A9 (0x6B,0x24) 0x44000200 0x00000027 0x00000000 0x00000000
|
||||
GPP_A10 (0x6B,0x26) 0x44000702 0x00003028 0x00000000 0x00000000
|
||||
GPP_A11 (0x6B,0x28) 0x44000102 0x00003029 0x00000000 0x00000000
|
||||
GPP_A12 (0x6B,0x2A) 0x44000200 0x0000002a 0x00000000 0x00000000
|
||||
GPP_A13 (0x6B,0x2C) 0x44000200 0x0000002b 0x00000000 0x00000000
|
||||
GPP_A14 (0x6B,0x2E) 0x44000200 0x0000002c 0x00000000 0x00000000
|
||||
GPP_C0 (0x6B,0x32) 0x44000502 0x0000002d 0x00000000 0x00000000
|
||||
GPP_C1 (0x6B,0x34) 0x44000502 0x0000002e 0x00000000 0x00000000
|
||||
GPP_C2 (0x6B,0x36) 0x44000102 0x0000002f 0x00000800 0x00000000
|
||||
GPP_C3 (0x6B,0x38) 0x44000d02 0x00000030 0x00000000 0x00000000
|
||||
GPP_C4 (0x6B,0x3A) 0x44000d02 0x00000031 0x00000000 0x00000000
|
||||
GPP_C5 (0x6B,0x3C) 0x44000200 0x00000032 0x00000000 0x00000000
|
||||
GPP_C6 (0x6B,0x3E) 0x44000902 0x00000033 0x00000000 0x00000000
|
||||
GPP_C7 (0x6B,0x40) 0x44000902 0x00000034 0x00000000 0x00000000
|
||||
GPP_C8 (0x6B,0x42) 0x44000102 0x00000035 0x00000000 0x00000000
|
||||
GPP_C9 (0x6B,0x44) 0x44000200 0x00000036 0x00000000 0x00000000
|
||||
GPP_C10 (0x6B,0x46) 0x44000200 0x00000037 0x00000000 0x00000000
|
||||
GPP_C11 (0x6B,0x48) 0x44000200 0x00000038 0x00000000 0x00000000
|
||||
GPP_C12 (0x6B,0x4A) 0x44000200 0x00000039 0x00000000 0x00000000
|
||||
GPP_C13 (0x6B,0x4C) 0x44000200 0x0000003a 0x00000000 0x00000000
|
||||
GPP_C14 (0x6B,0x4E) 0x44000200 0x0000003b 0x00000000 0x00000000
|
||||
GPP_C15 (0x6B,0x50) 0x44000200 0x0000003c 0x00000000 0x00000000
|
||||
GPP_C16 (0x6B,0x52) 0x44000502 0x0000003d 0x00000000 0x00000000
|
||||
GPP_C17 (0x6B,0x54) 0x44000502 0x0000003e 0x00000000 0x00000000
|
||||
GPP_C18 (0x6B,0x56) 0x44000502 0x0000003f 0x00000000 0x00000000
|
||||
GPP_C19 (0x6B,0x58) 0x44000502 0x00000040 0x00000000 0x00000000
|
||||
GPP_C20 (0x6B,0x5A) 0x44000200 0x00000041 0x00000000 0x00000000
|
||||
GPP_C21 (0x6B,0x5C) 0x44000200 0x00000042 0x00000000 0x00000000
|
||||
GPP_C22 (0x6B,0x5E) 0x44000200 0x00000043 0x00000000 0x00000000
|
||||
GPP_C23 (0x6B,0x60) 0x44000200 0x00000044 0x00000000 0x00000000
|
||||
GPP_S0 (0x6A,0x00) 0x44000200 0x01800030 0x00000000 0x00000000
|
||||
GPP_S1 (0x6A,0x02) 0x44000200 0x01800031 0x00000000 0x00000000
|
||||
GPP_S2 (0x6A,0x04) 0x44000200 0x01800032 0x00000000 0x00000000
|
||||
GPP_S3 (0x6A,0x06) 0x44000200 0x01800033 0x00000000 0x00000000
|
||||
GPP_S4 (0x6A,0x08) 0x44000a00 0x01800034 0x00000000 0x00000000
|
||||
GPP_S5 (0x6A,0x0A) 0x44000900 0x01800035 0x00000000 0x00000000
|
||||
GPP_S6 (0x6A,0x0C) 0x44000200 0x01800036 0x00000000 0x00000000
|
||||
GPP_S7 (0x6A,0x0E) 0x44000200 0x01800037 0x00000000 0x00000000
|
||||
GPP_E0 (0x6A,0x10) 0x44000200 0x00000038 0x00000000 0x00000000
|
||||
GPP_E1 (0x6A,0x12) 0x44000200 0x00000039 0x00000000 0x00000000
|
||||
GPP_E2 (0x6A,0x14) 0x44000102 0x0000003a 0x00000000 0x00000000
|
||||
GPP_E3 (0x6A,0x16) 0x44000102 0x0000003b 0x00000000 0x00000000
|
||||
GPP_E4 (0x6A,0x18) 0x44000200 0x0000003c 0x00000000 0x00000000
|
||||
GPP_E5 (0x6A,0x1A) 0x44000200 0x0000003d 0x00000000 0x00000000
|
||||
GPP_E6 (0x6A,0x1C) 0x44000200 0x0000003e 0x00000000 0x00000000
|
||||
GPP_E7 (0x6A,0x1E) 0x80100102 0x0000003f 0x00000000 0x00000000
|
||||
GPP_E8 (0x6A,0x20) 0x44000600 0x00000040 0x00000000 0x00000000
|
||||
GPP_E9 (0x6A,0x22) 0x44000102 0x00000041 0x00000800 0x00000000
|
||||
GPP_E10 (0x6A,0x24) 0x44000102 0x00000042 0x00000800 0x00000000
|
||||
GPP_E11 (0x6A,0x26) 0x44000102 0x00000043 0x00000800 0x00000000
|
||||
GPP_E12 (0x6A,0x28) 0x44000102 0x00000044 0x00000000 0x00000000
|
||||
GPP_E13 (0x6A,0x2A) 0x44000200 0x00000045 0x00000000 0x00000000
|
||||
GPP_E14 (0x6A,0x2C) 0x44000200 0x00000046 0x00000000 0x00000000
|
||||
GPP_E15 (0x6A,0x2E) 0x44000200 0x00000047 0x00000000 0x00000000
|
||||
GPP_E16 (0x6A,0x30) 0x44000200 0x00000048 0x00000000 0x00000000
|
||||
GPP_E17 (0x6A,0x32) 0x44000102 0x00000049 0x00000000 0x00000000
|
||||
GPP_E18 (0x6A,0x34) 0x44000201 0x0000004a 0x00000000 0x00000000
|
||||
GPP_E19 (0x6A,0x36) 0x44000200 0x0000004b 0x00000000 0x00000000
|
||||
GPP_E20 (0x6A,0x38) 0x44000200 0x0000004c 0x00000000 0x00000000
|
||||
GPP_E21 (0x6A,0x3A) 0x44000200 0x0000004d 0x00000000 0x00000000
|
||||
GPP_K0 (0x6A,0x3E) 0x42800102 0x0000004e 0x00000000 0x00000000
|
||||
GPP_K1 (0x6A,0x40) 0x44000200 0x00000050 0x00000000 0x00000000
|
||||
GPP_K2 (0x6A,0x42) 0x44000200 0x00000051 0x00000000 0x00000000
|
||||
GPP_K3 (0x6A,0x44) 0x84000201 0x00000052 0x00000000 0x00000000
|
||||
GPP_K4 (0x6A,0x46) 0x44000200 0x00003053 0x00000000 0x00000000
|
||||
GPP_K5 (0x6A,0x48) 0x44000200 0x00000054 0x00000000 0x00000000
|
||||
GPP_K6 (0x6A,0x4A) 0x44000a02 0x00000055 0x00000000 0x00000000
|
||||
GPP_K7 (0x6A,0x4C) 0x44000a02 0x00000056 0x00000000 0x00000000
|
||||
GPP_K8 (0x6A,0x4E) 0x44000700 0x00000057 0x00000000 0x00000000
|
||||
GPP_K9 (0x6A,0x50) 0x44000700 0x00000058 0x00000000 0x00000000
|
||||
GPP_K10 (0x6A,0x52) 0x44000a02 0x00000059 0x00000000 0x00000000
|
||||
GPP_K11 (0x6A,0x54) 0x44000200 0x0000005a 0x00000000 0x00000000
|
||||
GPP_F0 (0x6A,0x5C) 0x44000300 0x0000005b 0x00000000 0x00000000
|
||||
GPP_F1 (0x6A,0x5E) 0x44000200 0x0000005c 0x00000000 0x00000000
|
||||
GPP_F2 (0x6A,0x60) 0x44000200 0x0000005d 0x00000000 0x00000000
|
||||
GPP_F3 (0x6A,0x62) 0x44000200 0x0000005e 0x00000000 0x00000000
|
||||
GPP_F4 (0x6A,0x64) 0x44000200 0x00000060 0x00000000 0x00000000
|
||||
GPP_F5 (0x6A,0x66) 0x44000300 0x00000061 0x00000000 0x00000000
|
||||
GPP_F6 (0x6A,0x68) 0x44000200 0x00000062 0x00000000 0x00000000
|
||||
GPP_F7 (0x6A,0x6A) 0x80100100 0x00000063 0x00000000 0x00000000
|
||||
GPP_F8 (0x6A,0x6C) 0x84000100 0x00000064 0x00000000 0x00000000
|
||||
GPP_F9 (0x6A,0x6E) 0x44000200 0x00000065 0x00000000 0x00000000
|
||||
GPP_F10 (0x6A,0x70) 0x44000102 0x00000066 0x00000000 0x00000000
|
||||
GPP_F11 (0x6A,0x72) 0x44000200 0x00000067 0x00000000 0x00000000
|
||||
GPP_F12 (0x6A,0x74) 0x44000200 0x00000068 0x00000000 0x00000000
|
||||
GPP_F13 (0x6A,0x76) 0x44000200 0x00000069 0x00000000 0x00000000
|
||||
GPP_F14 (0x6A,0x78) 0x44000200 0x0000006a 0x00000000 0x00000000
|
||||
GPP_F15 (0x6A,0x7A) 0x44000100 0x0000006b 0x00000000 0x00000000
|
||||
GPP_F16 (0x6A,0x7C) 0x80100100 0x0000006c 0x00000000 0x00000000
|
||||
GPP_F17 (0x6A,0x7E) 0x44000102 0x0000006d 0x00000000 0x00000000
|
||||
GPP_F18 (0x6A,0x80) 0x44000200 0x0000006e 0x00000000 0x00000000
|
||||
GPP_F19 (0x6A,0x82) 0x44000700 0x0000006f 0x00000000 0x00000000
|
||||
GPP_F20 (0x6A,0x84) 0x44000700 0x00000070 0x00000000 0x00000000
|
||||
GPP_F21 (0x6A,0x86) 0x44000700 0x00000071 0x00000000 0x00000000
|
||||
GPP_F22 (0x6A,0x88) 0x44000200 0x00000072 0x00000000 0x00000000
|
||||
GPP_F23 (0x6A,0x8A) 0x44000200 0x00000073 0x00000000 0x00000000
|
||||
GPP_D0 (0x69,0x20) 0x44000200 0x00000026 0x00000000 0x00000000
|
||||
GPP_D1 (0x69,0x22) 0x44000200 0x00000027 0x00000000 0x00000000
|
||||
GPP_D2 (0x69,0x24) 0x44000200 0x00000028 0x00000000 0x00000000
|
||||
GPP_D3 (0x69,0x26) 0x44000200 0x00000029 0x00000000 0x00000000
|
||||
GPP_D4 (0x69,0x28) 0x44000200 0x0000002a 0x00000000 0x00000000
|
||||
GPP_D5 (0x69,0x2A) 0x44000200 0x0000002b 0x00000000 0x00000000
|
||||
GPP_D6 (0x69,0x2C) 0x44000200 0x0000002c 0x00000000 0x00000000
|
||||
GPP_D7 (0x69,0x2E) 0x44000200 0x0000002d 0x00000000 0x00000000
|
||||
GPP_D8 (0x69,0x30) 0x40000300 0x00000000 0x00000000 0x00000000
|
||||
GPP_D9 (0x69,0x32) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D10 (0x69,0x34) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D11 (0x69,0x36) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D12 (0x69,0x38) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D13 (0x69,0x3A) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D14 (0x69,0x3C) 0x40000702 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D15 (0x69,0x3E) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D16 (0x69,0x40) 0x40000700 0x00003c00 0x00000800 0x00000000
|
||||
GPP_D17 (0x69,0x42) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D18 (0x69,0x44) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D19 (0x69,0x46) 0x40000700 0x00003c00 0x00000000 0x00000000
|
||||
GPP_D20 (0x69,0x48) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
GPP_D21 (0x69,0x4A) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
GPP_D22 (0x69,0x4C) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
GPP_D23 (0x69,0x4E) 0x40000700 0x00000000 0x00000000 0x00000000
|
||||
## HDAUDIO ##
|
||||
hdaudioC0D0
|
||||
vendor_name: Realtek
|
||||
chip_name: ALC245
|
||||
vendor_id: 0x10ec0245
|
||||
subsystem_id: 0x15580353
|
||||
revision_id: 0x100001
|
||||
0x12: 0x90a60130
|
||||
0x13: 0x40000000
|
||||
0x14: 0x90170110
|
||||
0x17: 0x411111f0
|
||||
0x18: 0x411111f0
|
||||
0x19: 0x411111f0
|
||||
0x1a: 0x411111f0
|
||||
0x1b: 0x411111f0
|
||||
0x1d: 0x40689b2d
|
||||
0x1e: 0x411111f0
|
||||
0x21: 0x04211020
|
||||
hdaudioC0D2
|
||||
vendor_name: Intel
|
||||
chip_name: Raptorlake HDMI
|
||||
vendor_id: 0x80862818
|
||||
subsystem_id: 0x80860101
|
||||
revision_id: 0x100000
|
||||
0x04: 0x18560010
|
||||
0x06: 0x18560010
|
||||
0x08: 0x18560010
|
||||
0x0a: 0x18560010
|
||||
0x0b: 0x18560010
|
||||
0x0c: 0x18560010
|
||||
0x0d: 0x18560010
|
||||
0x0e: 0x18560010
|
||||
0x0f: 0x18560010
|
||||
hdaudioC1D0
|
||||
vendor_name: Nvidia
|
||||
chip_name: GPU a6 HDMI/DP
|
||||
vendor_id: 0x10de00a6
|
||||
subsystem_id: 0x10de0000
|
||||
revision_id: 0x100100
|
||||
0x04: 0x185600f0
|
||||
0x05: 0x585600f0
|
||||
0x06: 0x585600f0
|
||||
0x07: 0x585600f0
|
||||
@ -1,19 +0,0 @@
|
||||
CONFIG_VENDOR_SYSTEM76=y
|
||||
CONFIG_BOARD_SYSTEM76_ADDW4=y
|
||||
CONFIG_CCACHE=y
|
||||
CONFIG_CONSOLE_SERIAL=n
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
|
||||
CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
|
||||
CONFIG_PAYLOAD_ELF=y
|
||||
CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
|
||||
CONFIG_POST_IO=n
|
||||
CONFIG_SMMSTORE=y
|
||||
CONFIG_SMMSTORE_V2=y
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
|
||||
#CONFIG_CONSOLE_SYSTEM76_EC=y
|
||||
@ -1 +0,0 @@
|
||||
BOARD=system76/addw4
|
||||
@ -1,89 +0,0 @@
|
||||
id 5570 rev 7
|
||||
A0: data 1 mirror 1 pot 0 control 00
|
||||
A1: data 0 mirror 0 pot 0 control 80
|
||||
A2: data 0 mirror 0 pot 0 control 00
|
||||
A3: data 1 mirror 1 pot 0 control 80
|
||||
A4: data 0 mirror 0 pot 0 control 00
|
||||
A5: data 0 mirror 0 pot 0 control 00
|
||||
A6: data 0 mirror 0 pot 0 control 00
|
||||
A7: data 1 mirror 0 pot 0 control 00
|
||||
B0: data 0 mirror 0 pot 0 control 84
|
||||
B1: data 1 mirror 1 pot 0 control 84
|
||||
B2: data 1 mirror 1 pot 0 control 80
|
||||
B3: data 1 mirror 1 pot 0 control 80
|
||||
B4: data 1 mirror 1 pot 0 control 40
|
||||
B5: data 0 mirror 0 pot 0 control 80
|
||||
B6: data 1 mirror 1 pot 0 control 44
|
||||
B7: data 1 mirror 1 pot 0 control 80
|
||||
C0: data 1 mirror 1 pot 0 control 80
|
||||
C1: data 1 mirror 1 pot 0 control 04
|
||||
C2: data 1 mirror 1 pot 0 control 04
|
||||
C3: data 1 mirror 1 pot 0 control 04
|
||||
C4: data 0 mirror 0 pot 0 control 84
|
||||
C5: data 1 mirror 1 pot 0 control 04
|
||||
C6: data 1 mirror 1 pot 0 control 40
|
||||
C7: data 1 mirror 1 pot 0 control 44
|
||||
D0: data 1 mirror 1 pot 0 control 44
|
||||
D1: data 1 mirror 1 pot 0 control 44
|
||||
D2: data 1 mirror 1 pot 0 control 00
|
||||
D3: data 0 mirror 0 pot 0 control 40
|
||||
D4: data 0 mirror 0 pot 0 control 80
|
||||
D5: data 1 mirror 1 pot 0 control 44
|
||||
D6: data 1 mirror 1 pot 0 control 02
|
||||
D7: data 1 mirror 1 pot 0 control 02
|
||||
E0: data 1 mirror 1 pot 0 control 04
|
||||
E1: data 1 mirror 1 pot 0 control 44
|
||||
E2: data 0 mirror 0 pot 0 control 84
|
||||
E3: data 1 mirror 1 pot 0 control 40
|
||||
E4: data 1 mirror 1 pot 0 control 42
|
||||
E5: data 1 mirror 1 pot 0 control 40
|
||||
E6: data 0 mirror 0 pot 0 control 80
|
||||
E7: data 1 mirror 1 pot 0 control 04
|
||||
F0: data 0 mirror 0 pot 0 control 44
|
||||
F1: data 1 mirror 1 pot 0 control 44
|
||||
F2: data 1 mirror 1 pot 0 control 44
|
||||
F3: data 1 mirror 1 pot 0 control 40
|
||||
F4: data 1 mirror 1 pot 0 control 04
|
||||
F5: data 1 mirror 1 pot 0 control 04
|
||||
F6: data 0 mirror 0 pot 0 control 40
|
||||
F7: data 0 mirror 0 pot 0 control 40
|
||||
G0: data 1 mirror 1 pot 0 control 40
|
||||
G1: data 1 mirror 1 pot 0 control 44
|
||||
G2: data 1 mirror 1 pot 0 control 80
|
||||
G3: data 0 mirror 0 pot 0 control 00
|
||||
G4: data 0 mirror 0 pot 0 control 00
|
||||
G5: data 0 mirror 0 pot 0 control 00
|
||||
G6: data 0 mirror 0 pot 0 control 40
|
||||
G7: data 0 mirror 0 pot 0 control 00
|
||||
H0: data 1 mirror 1 pot 0 control 80
|
||||
H1: data 0 mirror 0 pot 0 control 82
|
||||
H2: data 0 mirror 0 pot 0 control 40
|
||||
H3: data 1 mirror 1 pot 0 control 44
|
||||
H4: data 1 mirror 1 pot 0 control 80
|
||||
H5: data 1 mirror 1 pot 0 control 40
|
||||
H6: data 1 mirror 1 pot 0 control 80
|
||||
H7: data 1 mirror 1 pot 0 control 80
|
||||
I0: data 0 mirror 0 pot 0 control 00
|
||||
I1: data 0 mirror 0 pot 0 control 00
|
||||
I2: data 0 mirror 0 pot 0 control 80
|
||||
I3: data 0 mirror 0 pot 0 control 00
|
||||
I4: data 0 mirror 0 pot 0 control 00
|
||||
I5: data 0 mirror 0 pot 0 control 00
|
||||
I6: data 0 mirror 0 pot 0 control 00
|
||||
I7: data 0 mirror 0 pot 0 control 00
|
||||
J0: data 0 mirror 0 pot 0 control 40
|
||||
J1: data 1 mirror 1 pot 0 control 40
|
||||
J2: data 0 mirror 0 pot 0 control 40
|
||||
J3: data 0 mirror 0 pot 0 control 82
|
||||
J4: data 1 mirror 1 pot 0 control 40
|
||||
J5: data 1 mirror 1 pot 0 control 80
|
||||
J6: data 0 mirror 0 pot 0 control 44
|
||||
J7: data 1 mirror 1 pot 0 control 40
|
||||
M0: data 0 mirror 0 control 06
|
||||
M1: data 0 mirror 1 control 06
|
||||
M2: data 1 mirror 1 control 06
|
||||
M3: data 1 mirror 1 control 06
|
||||
M4: data 0 mirror 1 control 06
|
||||
M5: data 0 mirror 0 control 00
|
||||
M6: data 1 mirror 1 control 86
|
||||
M7: data 0 mirror 0 control 00
|
||||
@ -1,9 +0,0 @@
|
||||
BOOTLOADER=COREBOOT
|
||||
DISABLE_SERIAL_TERMINAL=TRUE
|
||||
PLATFORM_BOOT_TIMEOUT=2
|
||||
PS2_KEYBOARD_ENABLE=TRUE
|
||||
SECURE_BOOT_ENABLE=TRUE
|
||||
SERIAL_DRIVER_ENABLE=FALSE
|
||||
SHELL_TYPE=NONE
|
||||
TPM_ENABLE=TRUE
|
||||
#SYSTEM76_EC_LOGGING=TRUE
|
||||
BIN
models/addw4/fd.rom
(Stored with Git LFS)
BIN
models/addw4/fd.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw4/me.rom
(Stored with Git LFS)
BIN
models/addw4/me.rom
(Stored with Git LFS)
Binary file not shown.
BIN
models/addw4/vbt.rom
(Stored with Git LFS)
BIN
models/addw4/vbt.rom
(Stored with Git LFS)
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user