Sync galp5 with oryp8

Update coreboot
Update galp5 ME settings
2022-02-03 11:43:40 -07:00 · 2022-02-03 11:21:37 -07:00 · 2022-02-03 11:21:31 -07:00 · 2022-02-03 08:58:49 -07:00 · 2022-02-03 08:58:23 -07:00 · 2022-01-18 11:57:12 -07:00
274 changed files with 509 additions and 67528 deletions
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -0,0 +1,30 @@
+---
+name: Bug report
+about: Report a problem
+title: ''
+labels: []
+assignees: []
+---
+
+- Model: <!-- `cat /sys/class/dmi/id/product_version` (e.g.: gaze16-3050) -->
+- BIOS version: <!-- `cat /sys/class/dmi/id/bios_version` (e.g.: 2021-09-30_14b8a6e)-->
+- EC version: <!-- This will match the BIOS version unless you flashed it separately. -->
+- OS: <!-- e.g.: Pop!_OS 21.10, Fedora 35, Windows 11 -->
+
+<!-- Briefly describe the problem. -->
+
+### Steps to reproduce
+
+<!-- Provide a list of steps to reproduce the issue. -->
+
+### Expected behavior
+
+<!-- Describe what you think should happen. -->
+
+### Actual behavior
+
+<!-- Describe what actually happens. -->
+
+### Additional info
+
+<!-- Any extra info you think may be relevant. -->
--- a/.github/ISSUE_TEMPLATE/config.yml
+++ b/.github/ISSUE_TEMPLATE/config.yml
@@ -0,0 +1,8 @@
+blank_issues_enabled: true
+contact_links:
+  - name: Open a Support Ticket
+    url: https://system76.com/my-account/support-tickets/new
+    about: Get support for your System76 hardware
+  - name: Pop!_OS chat
+    url: https://chat.pop-os.org/
+    about: Pop!_OS Mattermost
--- a/.gitmodules
+++ b/.gitmodules
@@ -82,10 +82,6 @@
 	path = FSP
 	url = https://github.com/IntelFsp/FSP.git
 	branch = master
-[submodule "libs/smmstore"]
-	path = libs/smmstore
-	url = https://github.com/system76/smmstore.git
-	branch = master
 [submodule "apps/firmware-smmstore"]
 	path = apps/firmware-smmstore
 	url = https://github.com/system76/firmware-smmstore.git
@@ -102,7 +98,3 @@
 	path = tools/apobtool
 	url = https://github.com/system76/apobtool.git
 	branch = master
-[submodule "tools/PSPTool"]
-	path = tools/PSPTool
-	url = https://github.com/PSPReverse/PSPTool.git
-	branch = master
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,12 +4,22 @@ Changes are identified by the date of the released firmware including them. If
 you are running System76 Open Firmware, opening the boot menu will show this
 date followed by an underscore and a short git revision.

+## 2022-01-06
+
+- Added support to enable/disable Intel ME via the CMOS option `me_state`
+- Enabled coreboot measured boot
+- Updated Rust toolchain to nightly-2021-06-15
+- Updated coreboot to 4.15
+- Updated EDK2 to edk2-stabke202108
+- Updated TGL-U microcode blobs to revision 0x9a
+- Updated TGL-H microcode blobs to revision 0x3c
+- Updated all other boards to use microcode blobs from Intel's public repo
+- Updated TGL FSP to A.0.51.31 from Intel's public repo
+- Removed behavior of erasing NVRAM on CMOS reset
+
 ## 2021-09-30

 - gaze16: Do not require unplugging the AC adapter after flashing
-
-## 2021-09-29
-
 - gaze16: Fix using USB 2.0 devices in Type-C port

 ## 2021-09-23
--- a/README.md
+++ b/README.md
@@ -10,15 +10,14 @@ manager:

 - addw2
 - bonw14
- darp5
 - darp6
 - darp7
- galp3-c
 - galp4
 - galp5
 - gaze15
 - gaze16-3050
 - gaze16-3060
+- gaze16-3060-b
 - lemp9
 - lemp10
 - oryp6
@@ -31,19 +30,19 @@ seen in the `models/` directory.
 If the device becomes bricked it will require restoring the current firmware
 using an external programmer. See [flashing](./docs/flashing.md) for details.

+### Schematics
+
+System76 customers may request board schematics for their system by sending an
+email to firmware@system76.com with the subject line  "Schematics for _model_",
+where _model_ is one of the supported models listed above. Please include the
+serial number of your system for verification.
+
+You may not share these without explicit permission from System76.
+
 ## Changelog

 For a list of important changes please see the [changelog](./CHANGELOG.md).

-## Schematics
-
-System76 customers may request board schematics by sending an email to
-firmware@system76.com with the subject line  "Schematics for _model_", where
-_model_ is the name of a directory in the `models/` directory, such as darp6.
-Please include the serial number of your system for verification.
-
-You may not share these without explicit permission from System76.
-
 ## Dependencies

 ### Install toolchain
@@ -65,18 +64,3 @@ source ~/.cargo/env
 ```
 ./scripts/qemu.sh
 ```
-
-## Contents
-
- [apps](./apps) - Applications
- [coreboot](https://github.com/system76/coreboot.git) - coreboot README
- [docs](./docs) - System76 Open Firmware Documentation
- [ec](https://github.com/system76/ec.git) - System76 EC
- [edk2](https://github.com/system76/edk2.git) - EDK II Project
- [edk2-non-osi](https://github.com/tianocore/edk2-non-osi.git)
- [edk2-platforms](https://github.com/system76/edk2-platforms.git) - This branch holds all platforms actively maintained against the
- [FSP](https://github.com/IntelFsp/FSP.git) - Intel® Firmware Support Package (Intel® FSP) Binaries
- [libs](./libs) - Libraries
- [models](./models) - Models
- [scripts](./scripts)
- [tools](./tools) - Tools
--- a/README.md.in
+++ b/README.md.in
@@ -1,64 +0,0 @@
-# System76 Open Firmware
-
-An open source distribution of firmware utilizing coreboot, EDK2, and System76
-firmware applications.
-
-## Supported models
-
-These models are supported and will receive updates through the firmware
-manager:
-
- addw2
- bonw14
- darp5
- darp6
- darp7
- galp3-c
- galp4
- galp5
- gaze15
- lemp9
- lemp10
- oryp6
- oryp7
-
-Other models may be in development or available without support, and can be
-seen in the `models/` directory.
-
-If the device becomes bricked it will require restoring the current firmware
-using an external programmer. See [flashing](./docs/flashing.md) for details.
-
-## Changelog
-
-For a list of important changes please see the [changelog](./CHANGELOG.md).
-
-## Schematics
-
-System76 customers may request board schematics by sending an email to
-firmware@system76.com with the subject line  "Schematics for _model_", where
-_model_ is the name of a directory in the `models/` directory, such as darp6.
-Please include the serial number of your system for verification.
-
-You may not share these without explicit permission from System76.
-
-## Dependencies
-
-### Install toolchain
-```
-./scripts/deps.sh
-```
-
-### Load Rust environment (or optionally reboot)
-```
-source ~/.cargo/env
-```
-
-### Build firmware, replace qemu with your model (look in the models directory for examples)
-```
-./scripts/build.sh qemu
-```
-
-### Emulate firmware, only available after building the qemu model
-```
-./scripts/qemu.sh
-```
--- a/apps/firmware-setup
+++ b/apps/firmware-setup
--- a/apps/firmware-smmstore
+++ b/apps/firmware-smmstore
--- a/apps/firmware-update
+++ b/apps/firmware-update
--- a/apps/gop-policy
+++ b/apps/gop-policy
--- a/2
+++ b/2
--- a/docs/intel-me.md
+++ b/docs/intel-me.md
@@ -1,19 +1,35 @@
 # Intel Management Engine

-Intel-based machines by System76 come with the [Intel Management Engine][wiki]
-disabled. It is a proprietary, mostly undocumented, system that provides many
-extraneous features that are generally not usable or useful to our users, with
-multiple known vulnerabilities that compromise the entire system.
+[Intel Management Engine][wiki] is a proprietary, mostly undocumented, firmware
+system that provides many extraneous features that are generally not usable or
+useful to our users, with multiple known vulnerabilities that compromise the
+entire system.

 The Intel ME is _required_ (since Nehalem, 2008), so cannot be removed. The
-[me\_cleaner] project is able to remove non-essential components, but currently
-does not support the ME version used on many of our systems. Instead, we [send
-a HECI command][heci_disable] to tell the Intel ME to disable runtime
-components during early boot.
+[me\_cleaner] project is able to remove non-essential components, but does not
+support the ME version used on many of our systems. Instead, we [send a HECI
+command][CB52800] to tell the Intel ME to disable runtime components during
+early boot.
+
+Most Intel-based machines from System76 come with the IME disabled.
+
+## Configuring
+
+The IME can be enabled or disabled via the coreboot CMOS option `me_state`.
+The value can be set using coreboot's nvramtool.
+
+```
+make -C coreboot/util/nvramtool
+sudo ./coreboot/util/nvramtool/nvramtool -w me_state={Enable,Disable}
+```
+
+A restart is required for the change to take effect. On the boot after changing
+the value, the system will perform a global reset (power off again) to complete
+the change and ensure the IME is operating in a valid state.

 ## Tiger Lake-U

-Models using TGL-U processors currently leave the IME enabled. TGL-U removes
+Models using TGL-U processors default to having the IME enabled. TGL-U removes
 support for S3 and requires S0ix. This requires all CPU, PCH, and PCIe devices
 to have ACPI defined low power states. With S0ix, the CPU has numerous states
 for low power, with the lowest being C10. In order to reach this C10 state, the
@@ -21,6 +37,7 @@ IME must report that it is in a low power state. Disabling the ME with the HAP
 bit keeps the CPU in the C8 state. This nearly triples the power usage in S0ix
 suspend, from around 1 watt to around 3 watts.

+
 [wiki]: https://en.wikipedia.org/wiki/Intel_Management_Engine
 [me\_cleaner]: https://github.com/corna/me_cleaner
-[heci_disable]: https://github.com/system76/coreboot/blob/011439cb9196d6a71d394ead8c98dfd8ead325d4/src/soc/intel/cannonlake/me.c#L186
+[CB52800]: https://review.coreboot.org/c/coreboot/+/52800
--- a/docs/uefi.md
+++ b/docs/uefi.md
@@ -0,0 +1,27 @@
+# UEFI
+
+System76 uses [EDK2](https://github.com/tianocore/edk2) to implement UEFI.
+
+[coreboot](https://coreboot.org/) is used for Platform Initialization (PI).
+
+## Booting
+
+System76 Open Firmware only supports UEFI booting. Legacy BIOS-MBR booting is
+not supported. `\EFI\BOOT\BOOTX64.EFI` must exist on the EFI System Partition
+to be considered valid.
+
+Network functionality is disabled. Native PXE booting is not supported.
+
+### Secure Boot
+
+Secure Boot support is currently disabled.
+
+The implementation from 9elements is in development. If building a custom
+image, the edk2 config `SECURE_BOOT_ENABLE` can be set to enable support.
+
+There is currently no firmware UI to view or configure Secure Boot.
+
+## Shell
+
+The internal UEFI shell is disabled. A separate binary on a bootable drive
+must be used to access the shell environment.
--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/libs/ecflash
+++ b/libs/ecflash
--- a/libs/intel-spi
+++ b/libs/intel-spi
--- a/libs/smmstore
+++ b/libs/smmstore
--- a/libs/uefi
+++ b/libs/uefi
--- a/libs/uefi_alloc
+++ b/libs/uefi_alloc
--- a/libs/uefi_std
+++ b/libs/uefi_std
--- a/models/README.md
+++ b/models/README.md
@@ -20,7 +20,6 @@
 - [gaze16-3050](./gaze16-3050) - System76 Gazelle (gaze16)
 - [gaze16-3060](./gaze16-3060) - System76 Gazelle (gaze16)
 - [gaze16-3060-b](./gaze16-3060-b) - System76 Gazelle (gaze16)
- [kudu6](./kudu6) - System76 Kudu (kudu6)
 - [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
 - [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
 - [oryp5](./oryp5) - System76 Oryx Pro (oryp5)
--- a/models/addw1/README.md
+++ b/models/addw1/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/addw1
  - HAP: false
 - [ME](./me.rom)
  - Size: 6140 KB
-  - Version: 12.0.49.1536
+  - Version: 12.0.85.1919
--- a/models/addw1/coreboot.config
+++ b/models/addw1/coreboot.config
@@ -14,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x65d1
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/addw1/edk2.config
+++ b/models/addw1/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/addw1/fd.rom
+++ b/models/addw1/fd.rom
--- a/models/addw1/me.rom
+++ b/models/addw1/me.rom
--- a/models/addw2/README.md
+++ b/models/addw2/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/addw2
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.30.1114
+  - Version: 14.0.60.1807
--- a/models/addw2/coreboot.config
+++ b/models/addw2/coreboot.config
@@ -2,8 +2,7 @@ CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_ADDW2=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
@@ -15,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x65e1
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/addw2/edk2.config
+++ b/models/addw2/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/addw2/fd.rom
+++ b/models/addw2/fd.rom
--- a/models/addw2/me.rom
+++ b/models/addw2/me.rom
--- a/models/addw2/microcode.rom
+++ b/models/addw2/microcode.rom
--- a/models/bonw14/README.md
+++ b/models/bonw14/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.30.1114
+  - Version: 14.0.60.1807
--- a/models/bonw14/coreboot.config
+++ b/models/bonw14/coreboot.config
@@ -2,8 +2,7 @@ CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_BONW14=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
@@ -15,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x7714
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/bonw14/edk2.config
+++ b/models/bonw14/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/bonw14/fd.rom
+++ b/models/bonw14/fd.rom
--- a/models/bonw14/me.rom
+++ b/models/bonw14/me.rom
--- a/models/bonw14/microcode.rom
+++ b/models/bonw14/microcode.rom
--- a/models/darp5/coreboot.config
+++ b/models/darp5/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP5=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
-CONFIG_MAINBOARD_VERSION="darp5"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1325
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp5/edk2.config
+++ b/models/darp5/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp6/FSP/Fsp_M.fd
+++ b/models/darp6/FSP/Fsp_M.fd
--- a/models/darp6/FSP/Fsp_S.fd
+++ b/models/darp6/FSP/Fsp_S.fd
--- a/models/darp6/FSP/Fsp_T.fd
+++ b/models/darp6/FSP/Fsp_T.fd
--- a/models/darp6/FSP/Include
+++ b/models/darp6/FSP/Include
@@ -1 +0,0 @@
-../../../FSP/CometLakeFspBinPkg/CometLake1/Include
--- a/models/darp6/FSP/LICENSE
+++ b/models/darp6/FSP/LICENSE
@@ -1,46 +0,0 @@
-************************************************************************
-**                                                                    **
-**                                                                    **
-**      IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING     **
-**                                                                    **
-**                     ANY PORTION OF THE SOFTWARE                    **
-**                                                                    **
-************************************************************************
-
-Copyright (c) 2018 Intel Corporation.
-All rights reserved.
-
-Redistribution.
-
-Redistribution and use in binary form, without modification, are permitted
-provided that the following conditions are met:
-
- Redistributions must reproduce the above copyright notice and the 
-following disclaimer in the documentation and/or other materials provided 
-with the distribution.
-
- Neither the name of Intel Corporation nor the names of its suppliers 
-may be used to endorse or promote products derived from this software 
-without specific prior written permission.
-
- No reverse engineering, decompilation, or disassembly of this software 
-is permitted.
-
-"Binary form" includes any format that is commonly used for electronic 
-conveyance that is a reversible, bit-exact translation of binary 
-representation to ASCII or ISO text, for example "uuencode".
-
-DISCLAIMER.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
-THE POSSIBILITY OF SUCH DAMAGE.
-
--- a/models/darp6/README.md
+++ b/models/darp6/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/darp6
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.10.1204
+  - Version: 14.0.60.1807
--- a/models/darp6/coreboot.config
+++ b/models/darp6/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP6=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
-CONFIG_MAINBOARD_VERSION="darp6"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1404
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp6/edk2.config
+++ b/models/darp6/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp6/fd.rom
+++ b/models/darp6/fd.rom
--- a/models/darp6/me.rom
+++ b/models/darp6/me.rom
--- a/models/darp7/FSP/Fsp_M.fd
+++ b/models/darp7/FSP/Fsp_M.fd
--- a/models/darp7/FSP/Fsp_S.fd
+++ b/models/darp7/FSP/Fsp_S.fd
--- a/models/darp7/FSP/Fsp_T.fd
+++ b/models/darp7/FSP/Fsp_T.fd
--- a/models/darp7/FSP/Include/FirmwareVersionInfoHob.h
+++ b/models/darp7/FSP/Include/FirmwareVersionInfoHob.h
@@ -1,69 +0,0 @@
-/** @file
-  Header file for Firmware Version Information
-
- @copyright
-  INTEL CONFIDENTIAL
-  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
-
-  This program and the accompanying materials are licensed and made available under
-  the terms and conditions of the BSD License which accompanies this distribution.
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
-  UINT8                          MajorVersion;
-  UINT8                          MinorVersion;
-  UINT8                          Revision;
-  UINT16                         BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
-  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
-  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
-  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
-  UINT8                          Type;
-  UINT8                          Length;
-  UINT16                         Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
-  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
-  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
-  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
--- a/models/darp7/FSP/Include/FspInfoHob.h
+++ b/models/darp7/FSP/Include/FspInfoHob.h
@@ -1,56 +0,0 @@
-/** @file
-  Header file for FSP Information HOB.
-
-@copyright
-  INTEL CONFIDENTIAL
-  Copyright 2017 - 2019 Intel Corporation.
-
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-
-#ifndef _FSP_INFO_HOB_H_
-#define _FSP_INFO_HOB_H_
-
-extern EFI_GUID gFspInfoGuid;
-
-#pragma pack (push, 1)
-
-typedef struct {
-UINT8              SiliconInitVersionMajor;
-UINT8              SiliconInitVersionMinor;
-UINT8              SiliconInitVersionRevision;
-UINT8              SiliconInitVersionBuild;
-UINT8              FspVersionRevision;
-UINT8              FspVersionBuild;
-UINT8              TimeStamp [12];
-UINT8              FspVersionMinor;
-} FSP_INFO_HOB;
-
-#pragma pack (pop)
-
-#endif // _FSP_INFO_HOB_H_
--- a/models/darp7/FSP/Include/FspUpd.h
+++ b/models/darp7/FSP/Include/FspUpd.h
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE               0x545F4450554C4754        /* 'TGLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE               0x4D5F4450554C4754        /* 'TGLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE               0x535F4450554C4754        /* 'TGLUPD_S' */
-
-#pragma pack()
-
-#endif
--- a/models/darp7/FSP/Include/FspmUpd.h
+++ b/models/darp7/FSP/Include/FspmUpd.h
--- a/models/darp7/FSP/Include/FspsUpd.h
+++ b/models/darp7/FSP/Include/FspsUpd.h
--- a/models/darp7/FSP/Include/FsptUpd.h
+++ b/models/darp7/FSP/Include/FsptUpd.h
@@ -1,311 +0,0 @@
-/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPTUPD_H__
-#define __FSPTUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
-  UINT32                      MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
-  UINT32                      MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
-  UINT32                      CodeRegionBase;
-
-/** Offset 0x002C
-**/
-  UINT32                      CodeRegionSize;
-
-/** Offset 0x0030
-**/
-  UINT8                       Reserved[16];
-} FSPT_CORE_UPD;
-
-/** Fsp T Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - PcdSerialIoUartDebugEnable
-  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
-  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
-**/
-  UINT8                       PcdSerialIoUartDebugEnable;
-
-/** Offset 0x0041 - PcdSerialIoUartNumber
-  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
-  Core interface, it cannot be used for debug purpose.
-  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
-  UINT8                       PcdSerialIoUartNumber;
-
-/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
-  Select SerialIo Uart Controller mode
-  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
-  4:SerialIoUartSkipInit
-**/
-  UINT8                       PcdSerialIoUartMode;
-
-/** Offset 0x0043
-**/
-  UINT8                       UnusedUpdSpace0;
-
-/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
-  Set default BaudRate Supported from 0 - default to 6000000
-**/
-  UINT32                      PcdSerialIoUartBaudRate;
-
-/** Offset 0x0048 - Pci Express Base Address
-  Base address to be programmed for Pci Express
-**/
-  UINT64                      PcdPciExpressBaseAddress;
-
-/** Offset 0x0050 - Pci Express Region Length
-  Region Length to be programmed for Pci Express
-**/
-  UINT32                      PcdPciExpressRegionLength;
-
-/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
-  Set default Parity.
-  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
-  UINT8                       PcdSerialIoUartParity;
-
-/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
-  Set default word length. 0: Default, 5,6,7,8
-**/
-  UINT8                       PcdSerialIoUartDataBits;
-
-/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
-  Set default stop bits.
-  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
-**/
-  UINT8                       PcdSerialIoUartStopBits;
-
-/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
-  Enables UART hardware flow control, CTS and RTS lines.
-  0: Disable, 1:Enable
-**/
-  UINT8                       PcdSerialIoUartAutoFlow;
-
-/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
-  Select RX pin muxing for SerialIo UART used for debug
-**/
-  UINT32                      PcdSerialIoUartRxPinMux;
-
-/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
-  Select TX pin muxing for SerialIo UART used for debug
-**/
-  UINT32                      PcdSerialIoUartTxPinMux;
-
-/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
-  Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIoUartRtsPinMux;
-
-/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
-  Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIoUartCtsPinMux;
-
-/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
-  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
-  = SerialIoUartPci.
-**/
-  UINT32                      PcdSerialIoUartDebugMmioBase;
-
-/** Offset 0x006C - PcdLpcUartDebugEnable
-  Enable to initialize LPC Uart device in FSP.
-  0:Disable, 1:Enable
-**/
-  UINT8                       PcdLpcUartDebugEnable;
-
-/** Offset 0x006D - Debug Interfaces
-  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
-  BIT2 - Not used.
-**/
-  UINT8                       PcdDebugInterfaceFlags;
-
-/** Offset 0x006E - PcdSerialDebugLevel
-  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
-  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
-  Info & Verbose.
-  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
-  Error Warnings and Info, 5:Load Error Warnings Info and Verbose
-**/
-  UINT8                       PcdSerialDebugLevel;
-
-/** Offset 0x006F - ISA Serial Base selection
-  Select ISA Serial Base address. Default is 0x3F8.
-  0:0x3F8, 1:0x2F8
-**/
-  UINT8                       PcdIsaSerialUartBase;
-
-/** Offset 0x0070 - PcdSerialIo2ndUartEnable
-  Enable Additional SerialIo Uart device in FSP.
-  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
-**/
-  UINT8                       PcdSerialIo2ndUartEnable;
-
-/** Offset 0x0071 - PcdSerialIo2ndUartNumber
-  Select SerialIo Uart Controller Number
-  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
-  UINT8                       PcdSerialIo2ndUartNumber;
-
-/** Offset 0x0072 - PcdSerialIo2ndUartMode - FSPT
-  Select SerialIo Uart Controller mode
-  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
-  4:SerialIoUartSkipInit
-**/
-  UINT8                       PcdSerialIo2ndUartMode;
-
-/** Offset 0x0073
-**/
-  UINT8                       UnusedUpdSpace1;
-
-/** Offset 0x0074 - PcdSerialIo2ndUartBaudRate - FSPT
-  Set default BaudRate Supported from 0 - default to 6000000
-**/
-  UINT32                      PcdSerialIo2ndUartBaudRate;
-
-/** Offset 0x0078 - PcdSerialIo2ndUartParity - FSPT
-  Set default Parity.
-  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
-  UINT8                       PcdSerialIo2ndUartParity;
-
-/** Offset 0x0079 - PcdSerialIo2ndUartDataBits - FSPT
-  Set default word length. 0: Default, 5,6,7,8
-**/
-  UINT8                       PcdSerialIo2ndUartDataBits;
-
-/** Offset 0x007A - PcdSerialIo2ndUartStopBits - FSPT
-  Set default stop bits.
-  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
-**/
-  UINT8                       PcdSerialIo2ndUartStopBits;
-
-/** Offset 0x007B - PcdSerialIo2ndUartAutoFlow - FSPT
-  Enables UART hardware flow control, CTS and RTS lines.
-  0: Disable, 1:Enable
-**/
-  UINT8                       PcdSerialIo2ndUartAutoFlow;
-
-/** Offset 0x007C - PcdSerialIo2ndUartRxPinMux - FSPT
-  Select RX pin muxing for SerialIo UART
-**/
-  UINT32                      PcdSerialIo2ndUartRxPinMux;
-
-/** Offset 0x0080 - PcdSerialIo2ndUartTxPinMux - FSPT
-  Select TX pin muxing for SerialIo UART
-**/
-  UINT32                      PcdSerialIo2ndUartTxPinMux;
-
-/** Offset 0x0084 - PcdSerialIo2ndUartRtsPinMux - FSPT
-  Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIo2ndUartRtsPinMux;
-
-/** Offset 0x0088 - PcdSerialIo2ndUartCtsPinMux - FSPT
-  Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIo2ndUartCtsPinMux;
-
-/** Offset 0x008C - PcdSerialIo2ndUartMmioBase - FSPT
-  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
-  = SerialIoUartPci.
-**/
-  UINT32                      PcdSerialIo2ndUartMmioBase;
-
-/** Offset 0x0090
-**/
-  UINT32                      TopMemoryCacheSize;
-
-/** Offset 0x0094 - FspDebugHandler
-  <b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
-**/
-  UINT32                      FspDebugHandler;
-
-/** Offset 0x0098
-**/
-  UINT8                       UnusedUpdSpace2[4];
-
-/** Offset 0x009C
-**/
-  UINT8                       ReservedFsptUpd1[20];
-} FSP_T_CONFIG;
-
-/** Fsp T UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
-  FSP_UPD_HEADER              FspUpdHeader;
-
-/** Offset 0x0020
-**/
-  FSPT_CORE_UPD               FsptCoreUpd;
-
-/** Offset 0x0040
-**/
-  FSP_T_CONFIG                FsptConfig;
-
-/** Offset 0x00B0
-**/
-  UINT8                       UnusedUpdSpace3[6];
-
-/** Offset 0x00B6
-**/
-  UINT16                      UpdTerminator;
-} FSPT_UPD;
-
-#pragma pack()
-
-#endif
--- a/models/darp7/FSP/Include/FusaInfoHob.h
+++ b/models/darp7/FSP/Include/FusaInfoHob.h
@@ -1,161 +0,0 @@
-/** @file
-  This file contains definitions required for creation of TGL
-  end-to-end check-the-checker test result hob.
-
-@copyright
-  INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.
-
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-#ifndef _FUSA_INFO_HOB_H_
-#define _FUSA_INFO_HOB_H_
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiFusaInfoGuid;
-
-/**
-  FuSa Info HOB version
-  Use this to compare to the HOB retrieved from the FSP for the
-  exact match
-**/
-#define FUSA_INFO_VERSION 0x00000100
-
-/** Constants used for FUSA_TEST_RESULT->CheckResults[] and
- *  FUSA_TEST_RESULT->TestResult */
-/**@defgroup ResultConstant Check Result Constants*/
-/**@{*/
-#define FUSA_TEST_DEVICE_NOTAVAILABLE  0xFF    /**<device is not available*/
-#define FUSA_TEST_NOTRUN               0x0U    /**<check is not run*/
-#define FUSA_TEST_FAIL                 0xD2U   /**<check fail*/
-#define FUSA_TEST_PASS                 0x2DU   /**<check pass*/
-/**@}*/
-
-/** Fusa test result structure
- **/
-typedef struct
-{
-  UINT32 TestNumber;            /**< test number assigned to this test */
-  UINT32 TotalChecks;           /**< total number of checks in this test */
-  UINT8  TestResult;            /**< if all tests passed then this is FUSA_TEST_PASS.
-                                  if at least one check fails, then this is TEST_FAIL
-                                  if the device (eg. MC channel DIMM) is not available
-                                  then this is FUSA_TEST_DEVICE_NOTAVAILABLE.
-                                  if the test has not been run, then this is FUSA_TEST_NOTRUN*/
-  UINT8  ReservedByte[3];       /**< reserved, as padding for 4 byte-alignment */
-  UINT8  CheckResults[32];      /**< test result for each check.*/
-  UINT32 Crc32;                 /**< crc32 of the structure */
-} FUSA_TEST_RESULT;
-
-
-/**
-  Fusa Test Number assigned to each Fusa test.
-  This will be used for the unique id for each test.
-  FUSA_TEST_RESULT->TestNumber will have this value.
-
-  @note While the core4-7 (cbo4-7) that are strictly related to
-        the TGL-H are listed, there are not within the
-        implementation scope and validation scope yet.
-**/
-typedef enum
-{
-  FusaTestNumMc0Cmi = 0,          ///<Check MC0 CMI path, valid if there is DIMM using MC0
-  FusaTestNumMc1Cmi,              ///<Check MC1 CMI path, valid if there is DIMM using MC1
-  FusaTestNumMc0CmiCh0Data,       ///<Check MC0 CH0 CMI path, valid if there is DIMM using MC0 CH0
-  FusaTestNumMc0CmiCh1Data,       ///<Check MC0 CH1 CMI path, valid if there is DIMM using MC0 CH1
-  FusaTestNumMc0CmiCh2Data,       ///<Check MC0 CH2 CMI path, valid if there is DIMM using MC0 CH2
-  FusaTestNumMc0CmiCh3Data,       ///<Check MC0 CH3 CMI path, valid if there is DIMM using MC0 CH3
-  FusaTestNumMc1CmiCh0Data,       ///<Check MC1 CH0 CMI path, valid if there is DIMM using MC1 CH0
-  FusaTestNumMc1CmiCh1Data,       ///<Check MC1 CH1 CMI path, valid if there is DIMM using MC1 CH1
-  FusaTestNumMc1CmiCh2Data,       ///<Check MC1 CH2 CMI path, valid if there is DIMM using MC1 CH2
-  FusaTestNumMc1CmiCh3Data,       ///<Check MC1 CH3 CMI path, valid if there is DIMM using MC1 CH3
-  FusaTestNumIbecc0Cmi,           ///<Check Ibecc0 CMI path, valid if there is IBECC range covering MC0 DIMMs
-  FusaTestNumIbecc1Cmi,           ///<Check Ibecc1 CMI path, valid if there is IBECC range covering MC1 DIMMs
-  FusaTestNumIbecc0EccCorrError,  ///<Check Ibecc0 ECC correctable error, valid if there is IBECC range covering MC0 DIMMs
-  FusaTestNumIbecc1EccCorrError,  ///<Check Ibecc1 ECC correctable error, valid if there is IBECC range covering MC1 DIMMs
-  FusaTestNumIbecc0EccUncorrError,///<Check Ibecc0 ECC uncorrectable error, valid if there is IBECC range covering MC0 DIMMs
-  FusaTestNumIbecc1EccUncorrError,///<Check Ibecc0 ECC uncorrectable error, valid if there is IBECC range covering MC1 DIMMs
-
-  FusaTestNumMc0Mbist,            ///<Check MC0 MBIST
-  FusaTestNumMc1Mbist,            ///<Check MC1 MBIST
-  FusaTestNumMc0Ch0Mbist,         ///<Check MC0 CH0 MBIST
-  FusaTestNumMc0Ch1Mbist,         ///<Check MC0 CH1 MBIST
-  FusaTestNumMc0Ch2Mbist,         ///<Check MC0 CH2 MBIST
-  FusaTestNumMc0Ch3Mbist,         ///<Check MC0 CH3 MBIST
-  FusaTestNumMc1Ch0Mbist,         ///<Check MC1 CH0 MBIST
-  FusaTestNumMc1Ch1Mbist,         ///<Check MC1 CH1 MBIST
-  FusaTestNumMc1Ch2Mbist,         ///<Check MC1 CH2 MBIST
-  FusaTestNumMc1Ch3Mbist,         ///<Check MC1 CH3 MBIST
-  FusaTestNumIbecc0Mbist,         ///<Check Ibecc0 MBIST
-  FusaTestNumIbecc1Mbist,         ///<Check Ibecc1 MBIST
-
-  FusaTestNumCpu0Idi,             ///<Check core0 IDI path, valid if there is core0 in the SKU
-  FusaTestNumCpu1Idi,             ///<Check core1 IDI path, valid if there is core1 in the SKU
-  FusaTestNumCpu2Idi,             ///<Check core2 IDI path, valid if there is core2 in the SKU
-  FusaTestNumCpu3Idi,             ///<Check core3 IDI path, valid if there is core3 in the SKU
-  FusaTestNumCpu4Idi,             ///<Check core4 IDI path, valid if there is core4 in the SKU
-  FusaTestNumCpu5Idi,             ///<Check core5 IDI path, valid if there is core5 in the SKU
-  FusaTestNumCpu6Idi,             ///<Check core6 IDI path, valid if there is core6 in the SKU
-  FusaTestNumCpu7Idi,             ///<Check core7 IDI path, valid if there is core7 in the SKU
-
-  FusaTestNumCpu0Mbist,             ///<Check core0 Mbist, valid if there is core0 in the SKU
-  FusaTestNumCpu1Mbist,             ///<Check core1 Mbist, valid if there is core1 in the SKU
-  FusaTestNumCpu2Mbist,             ///<Check core2 Mbist, valid if there is core2 in the SKU
-  FusaTestNumCpu3Mbist,             ///<Check core3 Mbist, valid if there is core3 in the SKU
-  FusaTestNumCpu4Mbist,             ///<Check core4 Mbist, valid if there is core4 in the SKU
-  FusaTestNumCpu5Mbist,             ///<Check core5 Mbist, valid if there is core5 in the SKU
-  FusaTestNumCpu6Mbist,             ///<Check core6 Mbist, valid if there is core6 in the SKU
-  FusaTestNumCpu7Mbist,             ///<Check core7 Mbist, valid if there is core7 in the SKU
-
-  FusaTestNumCboSlice0Ingress,    ///<Check CBO0 ingress path, valid if there is core0 in the SKU
-  FusaTestNumCboSlice1Ingress,    ///<Check CBO1 ingress path, valid if there is core1 in the SKU
-  FusaTestNumCboSlice2Ingress,    ///<Check CBO2 ingress path, valid if there is core2 in the SKU
-  FusaTestNumCboSlice3Ingress,    ///<Check CBO3 ingress path, valid if there is core3 in the SKU
-  FusaTestNumCboSlice4Ingress,    ///<Check CBO4 ingress path, valid if there is core4 in the SKU
-  FusaTestNumCboSlice5Ingress,    ///<Check CBO5 ingress path, valid if there is core5 in the SKU
-  FusaTestNumCboSlice6Ingress,    ///<Check CBO6 ingress path, valid if there is core6 in the SKU
-  FusaTestNumCboSlice7Ingress,    ///<Check CBO7 ingress path, valid if there is core7 in the SKU
-
-  FusaTestNumOpiLinkIosfData,     ///<Check OPI Link path
-  FusaTestNumDip,                 ///<Check DIP path
-  FusaTestNumIop,                 ///<Check IOP path
-
-  FusaTestNumTotal                ///<Totak CTC groups count
-} FUSA_TEST_NUMBER;
-
-/**
-  Fusa test result HOB structure
-**/
-typedef struct {
-  UINT32 Version;
-  FUSA_TEST_RESULT FspDxCtcTestResult[FusaTestNumTotal];
-} FUSA_INFO_HOB;
-
-#pragma pack (pop)
-
-#endif // _FUSA_INFO_HOB_H_
--- a/models/darp7/FSP/Include/GpioConfig.h
+++ b/models/darp7/FSP/Include/GpioConfig.h
@@ -1,356 +0,0 @@
-/** @file
-  Header file for GpioConfig structure used by GPIO library.
-
- @copyright
-  INTEL CONFIDENTIAL
-  Copyright 2014 - 2017 Intel Corporation.
-
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-#ifndef _GPIO_CONFIG_H_
-#define _GPIO_CONFIG_H_
-
-#pragma pack(push, 1)
-
-///
-/// For any GpioPad usage in code use GPIO_PAD type
-///
-typedef UINT32 GPIO_PAD;
-
-
-///
-/// For any GpioGroup usage in code use GPIO_GROUP type
-///
-typedef UINT32 GPIO_GROUP;
-
-/**
-  GPIO configuration structure used for pin programming.
-  Structure contains fields that can be used to configure pad.
-**/
-typedef struct {
-  /**
-  Pad Mode
-  Pad can be set as GPIO or one of its native functions.
-  When in native mode setting Direction (except Inversion), OutputState,
-  InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
-  Refer to definition of GPIO_PAD_MODE.
-  Refer to EDS for each native mode according to the pad.
-  **/
-  UINT32 PadMode            : 5;
-  /**
-  Host Software Pad Ownership
-  Set pad to ACPI mode or GPIO Driver Mode.
-  Refer to definition of GPIO_HOSTSW_OWN.
-  **/
-  UINT32 HostSoftPadOwn     : 2;
-  /**
-  GPIO Direction
-  Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
-  Refer to definition of GPIO_DIRECTION for supported settings.
-  **/
-  UINT32 Direction           : 6;
-  /**
-  Output State
-  Set Pad output value.
-  Refer to definition of GPIO_OUTPUT_STATE for supported settings.
-  This setting takes place when output is enabled.
-  **/
-  UINT32 OutputState         : 2;
-  /**
-  GPIO Interrupt Configuration
-  Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
-  This setting is applicable only if GPIO is in GpioMode with input enabled.
-  Refer to definition of GPIO_INT_CONFIG for supported settings.
-  **/
-  UINT32 InterruptConfig     : 9;
-  /**
-  GPIO Power Configuration.
-  This setting controls Pad Reset Configuration.
-  Refer to definition of GPIO_RESET_CONFIG for supported settings.
-  **/
-  UINT32 PowerConfig        : 8;
-  /**
-  GPIO Electrical Configuration
-  This setting controls pads termination and voltage tolerance.
-  Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
-  **/
-  UINT32 ElectricalConfig   : 9;
-  /**
-  GPIO Lock Configuration
-  This setting controls pads lock.
-  Refer to definition of GPIO_LOCK_CONFIG for supported settings.
-  **/
-  UINT32 LockConfig         : 4;
-  /**
-  Additional GPIO configuration
-  Refer to definition of GPIO_OTHER_CONFIG for supported settings.
-  **/
-  UINT32 OtherSettings     :  2;
-  UINT32 RsvdBits          : 17;    ///< Reserved bits for future extension
-} GPIO_CONFIG;
-
-
-typedef enum {
-  GpioHardwareDefault        = 0x0    ///< Leave setting unmodified
-} GPIO_HARDWARE_DEFAULT;
-
-/**
-  GPIO Pad Mode
-  Refer to GPIO documentation on native functions available for certain pad.
-  If GPIO is set to one of NativeX modes then following settings are not applicable
-  and can be skipped:
-  - Interrupt related settings
-  - Host Software Ownership
-  - Output/Input enabling/disabling
-  - Output lock
-**/
-typedef enum {
-  GpioPadModeGpio     = 0x1,
-  GpioPadModeNative1  = 0x3,
-  GpioPadModeNative2  = 0x5,
-  GpioPadModeNative3  = 0x7,
-  GpioPadModeNative4  = 0x9
-} GPIO_PAD_MODE;
-
-/**
-  Host Software Pad Ownership modes
-  This setting affects GPIO interrupt status registers. Depending on chosen ownership
-  some GPIO Interrupt status register get updated and other masked.
-  Please refer to EDS for HOSTSW_OWN register description.
-**/
-typedef enum {
-  GpioHostOwnDefault = 0x0,   ///< Leave ownership value unmodified
-  /**
-  Set HOST ownership to ACPI.
-  Use this setting if pad is not going to be used by GPIO OS driver.
-  If GPIO is configured to generate SCI/SMI/NMI then this setting must be
-  used for interrupts to work
-  **/
-  GpioHostOwnAcpi    = 0x1,
-  /**
-  Set HOST ownership to GPIO Driver mode.
-  Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
-  GPIO OS Driver will be able to control the pad if appropriate entry in
-  ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
-  **/
-  GpioHostOwnGpio    = 0x3
-} GPIO_HOSTSW_OWN;
-
-///
-/// GPIO Direction
-///
-typedef enum {
-  GpioDirDefault         = 0x0,                ///< Leave pad direction setting unmodified
-  GpioDirInOut           = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
-  GpioDirInInvOut        = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
-  GpioDirIn              = (0x3 | (0x1 << 3)), ///< Set pad for input only
-  GpioDirInInv           = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
-  GpioDirOut             = 0x5,                ///< Set pad for output only
-  GpioDirNone            = 0x7                 ///< Disable both output and input
-} GPIO_DIRECTION;
-
-/**
-  GPIO Output State
-  This field is relevant only if output is enabled
-**/
-typedef enum {
-  GpioOutDefault         = 0x0,  ///< Leave output value unmodified
-  GpioOutLow             = 0x1,  ///< Set output to low
-  GpioOutHigh            = 0x3   ///< Set output to high
-} GPIO_OUTPUT_STATE;
-
-/**
-  GPIO interrupt configuration
-  This setting is applicable only if pad is in GPIO mode and has input enabled.
-  GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
-  and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
-  EDS for details on this settings.
-  Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
-  to describe an interrupt e.g. GpioIntApic | GpioIntLevel
-  If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
-  If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
-  Not all GPIO are capable of generating an SMI or NMI interrupt.
-  When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
-  interrupt cannot be shared and its IRQn number is not configurable.
-  Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
-  If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
-  exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
-  This type of GPIO Driver interrupt doesn't have any additional routing setting
-  required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
-**/
-
-typedef enum {
-  GpioIntDefault           = 0x0,  ///< Leave value of interrupt routing unmodified
-  GpioIntDis               = 0x1,  ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
-  GpioIntNmi               = 0x3,  ///< Enable NMI interrupt only
-  GpioIntSmi               = 0x5,  ///< Enable SMI interrupt only
-  GpioIntSci               = 0x9,  ///< Enable SCI interrupt only
-  GpioIntApic              = 0x11, ///< Enable IOxAPIC interrupt only
-  GpioIntLevel       = (0x1 << 5), ///< Set interrupt as level triggered
-  GpioIntEdge        = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
-  GpioIntLvlEdgDis   = (0x5 << 5), ///< Disable interrupt trigger
-  GpioIntBothEdge    = (0x7 << 5)  ///< Set interrupt as both edge triggered
-} GPIO_INT_CONFIG;
-
-#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK  0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
-#define B_GPIO_INT_CONFIG_INT_TYPE_MASK    0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
-
-/**
-  GPIO Power Configuration
-  GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
-  be used to reset certain GPIO settings.
-  Refer to EDS for settings that are controllable by PadRstCfg.
-**/
-typedef enum {
-
-
-  GpioResetDefault   = 0x00,        ///< Leave value of pad reset unmodified
-  ///
-  /// Deprecated settings. Maintained only for compatibility.
-  ///
-  GpioResetPwrGood   = 0x09,        ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
-  GpioResetDeep      = 0x0B,        ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
-  GpioResetNormal    = 0x0D,        ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
-  GpioResetResume    = 0x0F,        ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
-
-  ///
-  /// New GPIO reset configuration options
-  ///
-  /**
-  Resume Reset (RSMRST)
-    GPP: PadRstCfg = 00b = "Powergood"
-    GPD: PadRstCfg = 11b = "Resume Reset"
-  Pad setting will reset on:
-  - DeepSx transition
-  - G3
-  Pad settings will not reset on:
-  - S3/S4/S5 transition
-  - Warm/Cold/Global reset
-  **/
-  GpioResumeReset      = 0x01,
-  /**
-  Host Deep Reset
-    PadRstCfg = 01b = "Deep GPIO Reset"
-  Pad settings will reset on:
-  - Warm/Cold/Global reset
-  - DeepSx transition
-  - G3
-  Pad settings will not reset on:
-  - S3/S4/S5 transition
-  **/
-  GpioHostDeepReset    = 0x03,
-  /**
-  Platform Reset (PLTRST)
-    PadRstCfg = 10b = "GPIO Reset"
-  Pad settings will reset on:
-  - S3/S4/S5 transition
-  - Warm/Cold/Global reset
-  - DeepSx transition
-  - G3
-  **/
-  GpioPlatformReset    = 0x05,
-  /**
-  Deep Sleep Well Reset (DSW_PWROK)
-    GPP: not applicable
-    GPD: PadRstCfg = 00b = "Powergood"
-  Pad settings will reset on:
-  - G3
-  Pad settings will not reset on:
-  - S3/S4/S5 transition
-  - Warm/Cold/Global reset
-  - DeepSx transition
-  **/
-  GpioDswReset         = 0x07
-} GPIO_RESET_CONFIG;
-
-/**
-  GPIO Electrical Configuration
-  Set GPIO termination and Pad Tolerance (applicable only for some pads)
-  Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
-**/
-typedef enum {
-  GpioTermDefault          = 0x0,  ///< Leave termination setting unmodified
-  GpioTermNone             = 0x1,  ///< none
-  GpioTermWpd5K            = 0x5,  ///< 5kOhm weak pull-down
-  GpioTermWpd20K           = 0x9,  ///< 20kOhm weak pull-down
-  GpioTermWpu1K            = 0x13, ///< 1kOhm weak pull-up
-  GpioTermWpu2K            = 0x17, ///< 2kOhm weak pull-up
-  GpioTermWpu5K            = 0x15, ///< 5kOhm weak pull-up
-  GpioTermWpu20K           = 0x19, ///< 20kOhm weak pull-up
-  GpioTermWpu1K2K          = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
-  /**
-  Native function controls pads termination
-  This setting is applicable only to some native modes.
-  Please check EDS to determine which native functionality
-  can control pads termination
-  **/
-  GpioTermNative     = 0x1F,
-  GpioNoTolerance1v8 = (0x1 << 5),   ///< Disable 1.8V pad tolerance
-  GpioTolerance1v8   = (0x3 << 5)    ///< Enable 1.8V pad tolerance
-} GPIO_ELECTRICAL_CONFIG;
-
-#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK    0x1F   ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
-#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK  0x60   ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
-
-/**
-  GPIO LockConfiguration
-  Set GPIO configuration lock and output state lock.
-  GpioLockPadConfig and GpioLockOutputState can be OR'ed.
-  Lock settings reset is in Powergood domain. Care must be taken when using this setting
-  as fields it locks may be reset by a different signal and can be controllable
-  by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
-  functions which allow to unlock a GPIO pad.
-**/
-typedef enum {
-  GpioLockDefault          = 0x0,  ///< Leave lock setting unmodified
-  GpioPadConfigLock        = 0x3,  ///< Lock Pad Configuration
-  GpioOutputStateLock      = 0x5   ///< Lock GPIO pad output value
-} GPIO_LOCK_CONFIG;
-
-#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK  0x3  ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
-#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK    0x5  ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
-
-/**
-  Other GPIO Configuration
-  GPIO_OTHER_CONFIG is used for less often settings and for future extensions
-  Supported settings:
-   - RX raw override to '1' - allows to override input value to '1'
-      This setting is applicable only if in input mode (both in GPIO and native usage).
-      The override takes place at the internal pad state directly from buffer and before the RXINV.
-**/
-typedef enum {
-  GpioRxRaw1Default           = 0x0,  ///< Use default input override value
-  GpioRxRaw1Dis               = 0x1,  ///< Don't override input
-  GpioRxRaw1En                = 0x3   ///< Override input to '1'
-} GPIO_OTHER_CONFIG;
-
-#define B_GPIO_OTHER_CONFIG_RXRAW_MASK  0x3  ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
-
-#pragma pack(pop)
-
-#endif //_GPIO_CONFIG_H_
--- a/models/darp7/FSP/Include/GpioSampleDef.h
+++ b/models/darp7/FSP/Include/GpioSampleDef.h
@@ -1,382 +0,0 @@
-/** @file
-
-Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __GPIOCONFIG_H__
-#define __GPIOCONFIG_H__
-#include <FsptUpd.h>
-#include <FspmUpd.h>
-#include <FspsUpd.h>
-
-/*
-  SKL LP GPIO pins
-  Use below for functions from PCH GPIO Lib which
-  require GpioPad as argument. Encoding used here
-  has all information required by library functions
-*/
-#define GPIO_SKL_LP_GPP_A0      0x02000000
-#define GPIO_SKL_LP_GPP_A1      0x02000001
-#define GPIO_SKL_LP_GPP_A2      0x02000002
-#define GPIO_SKL_LP_GPP_A3      0x02000003
-#define GPIO_SKL_LP_GPP_A4      0x02000004
-#define GPIO_SKL_LP_GPP_A5      0x02000005
-#define GPIO_SKL_LP_GPP_A6      0x02000006
-#define GPIO_SKL_LP_GPP_A7      0x02000007
-#define GPIO_SKL_LP_GPP_A8      0x02000008
-#define GPIO_SKL_LP_GPP_A9      0x02000009
-#define GPIO_SKL_LP_GPP_A10     0x0200000A
-#define GPIO_SKL_LP_GPP_A11     0x0200000B
-#define GPIO_SKL_LP_GPP_A12     0x0200000C
-#define GPIO_SKL_LP_GPP_A13     0x0200000D
-#define GPIO_SKL_LP_GPP_A14     0x0200000E
-#define GPIO_SKL_LP_GPP_A15     0x0200000F
-#define GPIO_SKL_LP_GPP_A16     0x02000010
-#define GPIO_SKL_LP_GPP_A17     0x02000011
-#define GPIO_SKL_LP_GPP_A18     0x02000012
-#define GPIO_SKL_LP_GPP_A19     0x02000013
-#define GPIO_SKL_LP_GPP_A20     0x02000014
-#define GPIO_SKL_LP_GPP_A21     0x02000015
-#define GPIO_SKL_LP_GPP_A22     0x02000016
-#define GPIO_SKL_LP_GPP_A23     0x02000017
-#define GPIO_SKL_LP_GPP_B0      0x02010000
-#define GPIO_SKL_LP_GPP_B1      0x02010001
-#define GPIO_SKL_LP_GPP_B2      0x02010002
-#define GPIO_SKL_LP_GPP_B3      0x02010003
-#define GPIO_SKL_LP_GPP_B4      0x02010004
-#define GPIO_SKL_LP_GPP_B5      0x02010005
-#define GPIO_SKL_LP_GPP_B6      0x02010006
-#define GPIO_SKL_LP_GPP_B7      0x02010007
-#define GPIO_SKL_LP_GPP_B8      0x02010008
-#define GPIO_SKL_LP_GPP_B9      0x02010009
-#define GPIO_SKL_LP_GPP_B10     0x0201000A
-#define GPIO_SKL_LP_GPP_B11     0x0201000B
-#define GPIO_SKL_LP_GPP_B12     0x0201000C
-#define GPIO_SKL_LP_GPP_B13     0x0201000D
-#define GPIO_SKL_LP_GPP_B14     0x0201000E
-#define GPIO_SKL_LP_GPP_B15     0x0201000F
-#define GPIO_SKL_LP_GPP_B16     0x02010010
-#define GPIO_SKL_LP_GPP_B17     0x02010011
-#define GPIO_SKL_LP_GPP_B18     0x02010012
-#define GPIO_SKL_LP_GPP_B19     0x02010013
-#define GPIO_SKL_LP_GPP_B20     0x02010014
-#define GPIO_SKL_LP_GPP_B21     0x02010015
-#define GPIO_SKL_LP_GPP_B22     0x02010016
-#define GPIO_SKL_LP_GPP_B23     0x02010017
-#define GPIO_SKL_LP_GPP_C0      0x02020000
-#define GPIO_SKL_LP_GPP_C1      0x02020001
-#define GPIO_SKL_LP_GPP_C2      0x02020002
-#define GPIO_SKL_LP_GPP_C3      0x02020003
-#define GPIO_SKL_LP_GPP_C4      0x02020004
-#define GPIO_SKL_LP_GPP_C5      0x02020005
-#define GPIO_SKL_LP_GPP_C6      0x02020006
-#define GPIO_SKL_LP_GPP_C7      0x02020007
-#define GPIO_SKL_LP_GPP_C8      0x02020008
-#define GPIO_SKL_LP_GPP_C9      0x02020009
-#define GPIO_SKL_LP_GPP_C10     0x0202000A
-#define GPIO_SKL_LP_GPP_C11     0x0202000B
-#define GPIO_SKL_LP_GPP_C12     0x0202000C
-#define GPIO_SKL_LP_GPP_C13     0x0202000D
-#define GPIO_SKL_LP_GPP_C14     0x0202000E
-#define GPIO_SKL_LP_GPP_C15     0x0202000F
-#define GPIO_SKL_LP_GPP_C16     0x02020010
-#define GPIO_SKL_LP_GPP_C17     0x02020011
-#define GPIO_SKL_LP_GPP_C18     0x02020012
-#define GPIO_SKL_LP_GPP_C19     0x02020013
-#define GPIO_SKL_LP_GPP_C20     0x02020014
-#define GPIO_SKL_LP_GPP_C21     0x02020015
-#define GPIO_SKL_LP_GPP_C22     0x02020016
-#define GPIO_SKL_LP_GPP_C23     0x02020017
-#define GPIO_SKL_LP_GPP_D0      0x02030000
-#define GPIO_SKL_LP_GPP_D1      0x02030001
-#define GPIO_SKL_LP_GPP_D2      0x02030002
-#define GPIO_SKL_LP_GPP_D3      0x02030003
-#define GPIO_SKL_LP_GPP_D4      0x02030004
-#define GPIO_SKL_LP_GPP_D5      0x02030005
-#define GPIO_SKL_LP_GPP_D6      0x02030006
-#define GPIO_SKL_LP_GPP_D7      0x02030007
-#define GPIO_SKL_LP_GPP_D8      0x02030008
-#define GPIO_SKL_LP_GPP_D9      0x02030009
-#define GPIO_SKL_LP_GPP_D10     0x0203000A
-#define GPIO_SKL_LP_GPP_D11     0x0203000B
-#define GPIO_SKL_LP_GPP_D12     0x0203000C
-#define GPIO_SKL_LP_GPP_D13     0x0203000D
-#define GPIO_SKL_LP_GPP_D14     0x0203000E
-#define GPIO_SKL_LP_GPP_D15     0x0203000F
-#define GPIO_SKL_LP_GPP_D16     0x02030010
-#define GPIO_SKL_LP_GPP_D17     0x02030011
-#define GPIO_SKL_LP_GPP_D18     0x02030012
-#define GPIO_SKL_LP_GPP_D19     0x02030013
-#define GPIO_SKL_LP_GPP_D20     0x02030014
-#define GPIO_SKL_LP_GPP_D21     0x02030015
-#define GPIO_SKL_LP_GPP_D22     0x02030016
-#define GPIO_SKL_LP_GPP_D23     0x02030017
-#define GPIO_SKL_LP_GPP_E0      0x02040000
-#define GPIO_SKL_LP_GPP_E1      0x02040001
-#define GPIO_SKL_LP_GPP_E2      0x02040002
-#define GPIO_SKL_LP_GPP_E3      0x02040003
-#define GPIO_SKL_LP_GPP_E4      0x02040004
-#define GPIO_SKL_LP_GPP_E5      0x02040005
-#define GPIO_SKL_LP_GPP_E6      0x02040006
-#define GPIO_SKL_LP_GPP_E7      0x02040007
-#define GPIO_SKL_LP_GPP_E8      0x02040008
-#define GPIO_SKL_LP_GPP_E9      0x02040009
-#define GPIO_SKL_LP_GPP_E10     0x0204000A
-#define GPIO_SKL_LP_GPP_E11     0x0204000B
-#define GPIO_SKL_LP_GPP_E12     0x0204000C
-#define GPIO_SKL_LP_GPP_E13     0x0204000D
-#define GPIO_SKL_LP_GPP_E14     0x0204000E
-#define GPIO_SKL_LP_GPP_E15     0x0204000F
-#define GPIO_SKL_LP_GPP_E16     0x02040010
-#define GPIO_SKL_LP_GPP_E17     0x02040011
-#define GPIO_SKL_LP_GPP_E18     0x02040012
-#define GPIO_SKL_LP_GPP_E19     0x02040013
-#define GPIO_SKL_LP_GPP_E20     0x02040014
-#define GPIO_SKL_LP_GPP_E21     0x02040015
-#define GPIO_SKL_LP_GPP_E22     0x02040016
-#define GPIO_SKL_LP_GPP_E23     0x02040017
-#define GPIO_SKL_LP_GPP_F0      0x02050000
-#define GPIO_SKL_LP_GPP_F1      0x02050001
-#define GPIO_SKL_LP_GPP_F2      0x02050002
-#define GPIO_SKL_LP_GPP_F3      0x02050003
-#define GPIO_SKL_LP_GPP_F4      0x02050004
-#define GPIO_SKL_LP_GPP_F5      0x02050005
-#define GPIO_SKL_LP_GPP_F6      0x02050006
-#define GPIO_SKL_LP_GPP_F7      0x02050007
-#define GPIO_SKL_LP_GPP_F8      0x02050008
-#define GPIO_SKL_LP_GPP_F9      0x02050009
-#define GPIO_SKL_LP_GPP_F10     0x0205000A
-#define GPIO_SKL_LP_GPP_F11     0x0205000B
-#define GPIO_SKL_LP_GPP_F12     0x0205000C
-#define GPIO_SKL_LP_GPP_F13     0x0205000D
-#define GPIO_SKL_LP_GPP_F14     0x0205000E
-#define GPIO_SKL_LP_GPP_F15     0x0205000F
-#define GPIO_SKL_LP_GPP_F16     0x02050010
-#define GPIO_SKL_LP_GPP_F17     0x02050011
-#define GPIO_SKL_LP_GPP_F18     0x02050012
-#define GPIO_SKL_LP_GPP_F19     0x02050013
-#define GPIO_SKL_LP_GPP_F20     0x02050014
-#define GPIO_SKL_LP_GPP_F21     0x02050015
-#define GPIO_SKL_LP_GPP_F22     0x02050016
-#define GPIO_SKL_LP_GPP_F23     0x02050017
-#define GPIO_SKL_LP_GPP_G0      0x02060000
-#define GPIO_SKL_LP_GPP_G1      0x02060001
-#define GPIO_SKL_LP_GPP_G2      0x02060002
-#define GPIO_SKL_LP_GPP_G3      0x02060003
-#define GPIO_SKL_LP_GPP_G4      0x02060004
-#define GPIO_SKL_LP_GPP_G5      0x02060005
-#define GPIO_SKL_LP_GPP_G6      0x02060006
-#define GPIO_SKL_LP_GPP_G7      0x02060007
-#define GPIO_SKL_LP_GPD0        0x02070000
-#define GPIO_SKL_LP_GPD1        0x02070001
-#define GPIO_SKL_LP_GPD2        0x02070002
-#define GPIO_SKL_LP_GPD3        0x02070003
-#define GPIO_SKL_LP_GPD4        0x02070004
-#define GPIO_SKL_LP_GPD5        0x02070005
-#define GPIO_SKL_LP_GPD6        0x02070006
-#define GPIO_SKL_LP_GPD7        0x02070007
-#define GPIO_SKL_LP_GPD8        0x02070008
-#define GPIO_SKL_LP_GPD9        0x02070009
-#define GPIO_SKL_LP_GPD10       0x0207000A
-#define GPIO_SKL_LP_GPD11       0x0207000B
-
-#define END_OF_GPIO_TABLE   0xFFFFFFFF
-
-//Sample GPIO Table
-
-static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
-{
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//H_RCIN_N
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//LPC_FRAME_ESPI_CS_N
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//INT_SERIRQ
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A7,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SLP_S0ix_R_N
-  {GPIO_SKL_LP_GPP_A8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_CLKRUN_N
-//skip for eSPI function    {GPIO_SKL_LP_GPP_A9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
-  {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//PCH_CLK_PCI_TPM
-  {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//EC_HID_INTR
-  {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
-  {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SUS_PWR_ACK_R
-//skip for eSPI function    {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
-  {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SUSACK_R_N
-  {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_1P8_SEL
-  {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_PWR_EN_N
-  {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_0_SENSOR
-  {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_1_SENSOR
-  {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_2_SENSOR
-  {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GNSS_CHUB_IRQ
-  {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//FPS_SLP_N
-  {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//FPS_DRDY
-  {GPIO_SKL_LP_GPP_B0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID0
-  {GPIO_SKL_LP_GPP_B1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID1
-  {GPIO_SKL_LP_GPP_B2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GP_VRALERTB
-  {GPIO_SKL_LP_GPP_B3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,  GpioTermNone}},//TCH_PAD_INTR_R_N
-  {GPIO_SKL_LP_GPP_B4,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//BT_RF_KILL_N
-  {GPIO_SKL_LP_GPP_B5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_BT_UART_WAKE_N
-  // {GPIO_SKL_LP_GPP_B6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT1_N
-  // {GPIO_SKL_LP_GPP_B7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
-  // {GPIO_SKL_LP_GPP_B8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
-  // {GPIO_SKL_LP_GPP_B9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
-  // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WLAN_N
-  {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//MPHY_EXT_PWR_GATEB
-  {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SLP_S0_N
-  {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PLT_RST_N
-  {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_PWREN
-  {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_DFU
-  {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
-  {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset,  GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
-  {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
-  {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,   GpioTermNone}},//FPS_GSPI1_CS_R1_N
-  {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
-  {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
-  {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
-  {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
-  {GPIO_SKL_LP_GPP_C0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SMB_CLK
-  {GPIO_SKL_LP_GPP_C1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SMB_DATA
-  {GPIO_SKL_LP_GPP_C2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
-  {GPIO_SKL_LP_GPP_C3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_CLK
-  {GPIO_SKL_LP_GPP_C4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_DATA
-  {GPIO_SKL_LP_GPP_C5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
-  {GPIO_SKL_LP_GPP_C6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML1_CLK
-  {GPIO_SKL_LP_GPP_C7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SML1_DATA
-  {GPIO_SKL_LP_GPP_C8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RXD
-  {GPIO_SKL_LP_GPP_C9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_TXD
-  {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RTS_N
-  {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_CTS_N
-  {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
-  {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
-  {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
-  {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
-  {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SDA
-  {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SCL
-  {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SDA
-  {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SCL
-  {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RXD
-  {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_TXD
-  {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RTS_N
-  {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_CTS_N
-  {GPIO_SKL_LP_GPP_D0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CS_N
-  {GPIO_SKL_LP_GPP_D1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CLK
-  {GPIO_SKL_LP_GPP_D2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MISO
-  {GPIO_SKL_LP_GPP_D3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MOSI
-  {GPIO_SKL_LP_GPP_D4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CSI2_FLASH_STROBE
-  {GPIO_SKL_LP_GPP_D5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SDA
-  {GPIO_SKL_LP_GPP_D6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SCL
-  {GPIO_SKL_LP_GPP_D7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SDA
-  {GPIO_SKL_LP_GPP_D8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SCL
-  {GPIO_SKL_LP_GPP_D9,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//HOME_BTN
-  {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SCREEN_LOCK_PCH
-  {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_UP_PCH
-  {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_DOWN_PCH
-  {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
-  {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
-  {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RTS_N
-  {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
-  {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_1
-  {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_1
-  {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_0
-  {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_0
-  {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO2
-  {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO3
-  {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP_MCLK
-  {GPIO_SKL_LP_GPP_E0,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//SPI_TPM_HDR_IRQ_N
-  {GPIO_SKL_LP_GPP_E1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA_ODD_PRSNT_N
-  {GPIO_SKL_LP_GPP_E2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
-  {GPIO_SKL_LP_GPP_E3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioResumeReset,  GpioTermNone}},//EINK_SSR_DFU_N
-  {GPIO_SKL_LP_GPP_E4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_RESET
-  {GPIO_SKL_LP_GPP_E5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
-  {GPIO_SKL_LP_GPP_E6,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
-  {GPIO_SKL_LP_GPP_E8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SATA_LED_N
-  {GPIO_SKL_LP_GPP_E9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_0_WP1_OTG_N
-  {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_1_WP4_N
-  {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
-  {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_IRQ
-  {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_HPD_Q
-  {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_HPD_Q
-  {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset,  GpioTermNone}},//SMC_EXTSMI_R_N
-  {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//SMC_RUNTIME_SCI_R_N
-  {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EDP_HPD
-  {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_CTRL_CLK
-  {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI1_CTRL_DATA
-  {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_CTRL_CLK
-  {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI2_CTRL_DATA
-  {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_CODEC_IRQ
-  {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_RST_N
-  {GPIO_SKL_LP_GPP_F0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SCLK
-  {GPIO_SKL_LP_GPP_F1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SFRM
-  {GPIO_SKL_LP_GPP_F2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_TXD
-  {GPIO_SKL_LP_GPP_F3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_RXD
-  {GPIO_SKL_LP_GPP_F4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
-  {GPIO_SKL_LP_GPP_F5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
-  {GPIO_SKL_LP_GPP_F6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
-  {GPIO_SKL_LP_GPP_F7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
-  {GPIO_SKL_LP_GPP_F8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
-  {GPIO_SKL_LP_GPP_F9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
-  {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
-  {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
-  {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CMD
-  {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA0
-  {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA1
-  {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA2
-  {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA3
-  {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA4
-  {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA5
-  {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA6
-  {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA7
-  {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_RCLK
-  {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CLK
-  {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
-  {GPIO_SKL_LP_GPP_G0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CMD
-  {GPIO_SKL_LP_GPP_G1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA0
-  {GPIO_SKL_LP_GPP_G2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA1
-  {GPIO_SKL_LP_GPP_G3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA2
-  {GPIO_SKL_LP_GPP_G4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA3
-  {GPIO_SKL_LP_GPP_G5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CDB
-  {GPIO_SKL_LP_GPP_G6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CLK
-  {GPIO_SKL_LP_GPP_G7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_WP
-  {GPIO_SKL_LP_GPD0,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_BATLOW_R_N
-  {GPIO_SKL_LP_GPD1,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//AC_PRESENT_R
-  {GPIO_SKL_LP_GPD2,   {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset,  GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
-  {GPIO_SKL_LP_GPD3,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermWpu20K}},//PM_PWRBTN_R_N
-  {GPIO_SKL_LP_GPD4,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S3_R_N
-  {GPIO_SKL_LP_GPD5,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S4_R_N
-  {GPIO_SKL_LP_GPD6,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_M_R_N
-  {GPIO_SKL_LP_GPD7,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
-  {GPIO_SKL_LP_GPD8,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SUS_CLK
-  {GPIO_SKL_LP_GPD9,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PCH_SLP_WLAN_N
-  {GPIO_SKL_LP_GPD10,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S5_R_N
-  {GPIO_SKL_LP_GPD11,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_LANPHY_ENABLE
-  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
-};
-
-#endif   //_GPIO_CONFIG_H_
--- a/models/darp7/FSP/Include/MemInfoHob.h
+++ b/models/darp7/FSP/Include/MemInfoHob.h
@@ -1,286 +0,0 @@
-/** @file
-  This file contains definitions required for creation of
-  Memory S3 Save data, Memory Info data and Memory Platform
-  data hobs.
-
-  @copyright
-  Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials are licensed and made available under
-  the terms and conditions of the BSD License that accompanies this distribution.
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-@par Specification Reference:
-**/
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_TRACE_CACHE_TYPE  3
-
-#define MAX_NODE        2
-#define MAX_CH          4
-#define MAX_DIMM        2
-
-///
-/// Host reset states from MRC.
-///
-#define  WARM_BOOT        2
-
-#define R_MC_CHNL_RANK_PRESENT  0x7C
-#define   B_RANK0_PRS           BIT0
-#define   B_RANK1_PRS           BIT1
-#define   B_RANK2_PRS           BIT4
-#define   B_RANK3_PRS           BIT5
-
-// @todo remove and use the MdePkg\Include\Pi\PiHob.h
-#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
-#ifndef __HOB__H__
-typedef struct _EFI_HOB_GENERIC_HEADER {
-  UINT16  HobType;
-  UINT16  HobLength;
-  UINT32  Reserved;
-} EFI_HOB_GENERIC_HEADER;
-
-typedef struct _EFI_HOB_GUID_TYPE {
-  EFI_HOB_GENERIC_HEADER  Header;
-  EFI_GUID                Name;
-  ///
-  /// Guid specific data goes here
-  ///
-} EFI_HOB_GUID_TYPE;
-#endif
-#endif
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
-  UINT8  Major;     ///< Major version number
-  UINT8  Minor;     ///< Minor version number
-  UINT8  Rev;       ///< Revision number
-  UINT8  Build;     ///< Build number
-} SiMrcVersion;
-
-//
-// Matches MrcChannelSts enum in MRC
-//
-#ifndef CHANNEL_NOT_PRESENT
-#define CHANNEL_NOT_PRESENT     0  // There is no channel present on the controller.
-#endif
-#ifndef CHANNEL_DISABLED
-#define CHANNEL_DISABLED     1  // There is a channel present but it is disabled.
-#endif
-#ifndef CHANNEL_PRESENT
-#define CHANNEL_PRESENT     2  // There is a channel present and it is enabled.
-#endif
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED     0  // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED    1  // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT     2  // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3  // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef __MRC_BOOT_MODE__
-#define __MRC_BOOT_MODE__                 //The below values are originated from MrcCommonTypes.h
-  #ifndef INT32_MAX
-  #define INT32_MAX                       (0x7FFFFFFF)
-  #endif  //INT32_MAX
-typedef enum {
-  bmCold,                                 ///< Cold boot
-  bmWarm,                                 ///< Warm boot
-  bmS3,                                   ///< S3 resume
-  bmFast,                                 ///< Fast boot
-  MrcBootModeMax,                         ///< MRC_BOOT_MODE enumeration maximum value.
-  MrcBootModeDelim = INT32_MAX            ///< This value ensures the enum size is consistent on both sides of the PPI.
-} MRC_BOOT_MODE;
-#endif  //__MRC_BOOT_MODE__
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4     0
-#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3     1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3   2
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR4
-#define MRC_DDR_TYPE_LPDDR4   3
-#endif
-#ifndef MRC_DDR_TYPE_WIO2
-#define MRC_DDR_TYPE_WIO2     4
-#endif
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN  5
-#endif
-
-#define MAX_PROFILE_NUM     4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
-
-//
-// DIMM timings
-//
-typedef struct {
-  UINT32 tCK;       ///< Memory cycle time, in femtoseconds.
-  UINT16 NMode;     ///< Number of tCK cycles for the channel DIMM's command rate mode.
-  UINT16 tCL;       ///< Number of tCK cycles for the channel DIMM's CAS latency.
-  UINT16 tCWL;      ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
-  UINT16 tFAW;      ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
-  UINT16 tRAS;      ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
-  UINT16 tRCDtRP;   ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
-  UINT16 tREFI;     ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
-  UINT16 tRFC;      ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
-  UINT16 tRFCpb;    ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
-  UINT16 tRFC2;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
-  UINT16 tRFC4;     ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
-  UINT16 tRPab;     ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
-  UINT16 tRRD;      ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
-  UINT16 tRRD_L;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
-  UINT16 tRRD_S;    ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
-  UINT16 tRTP;      ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
-  UINT16 tWR;       ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
-  UINT16 tWTR;      ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
-  UINT16 tWTR_L;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
-  UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
-  UINT16 tCCD_L;  ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-} MRC_CH_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
-  UINT8            Status;                  ///< See MrcDimmStatus for the definition of this field.
-  UINT8            DimmId;
-  UINT32           DimmCapacity;            ///< DIMM size in MBytes.
-  UINT16           MfgId;
-  UINT8            ModulePartNum[20];       ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
-  UINT8            RankInDimm;              ///< The number of ranks in this DIMM.
-  UINT8            SpdDramDeviceType;       ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
-  UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
-  UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
-  UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
-  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz
-  UINT8            MdSocket;                ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
-  UINT8            Status;                  ///< Indicates whether this channel should be used.
-  UINT8            ChannelId;
-  UINT8            DimmCount;               ///< Number of valid DIMMs that exist in the channel.
-  MRC_CH_TIMING    Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
-  DIMM_INFO        DimmInfo[MAX_DIMM];      ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
-  UINT8            Status;                  ///< Indicates whether this controller should be used.
-  UINT16           DeviceId;                ///< The PCI device id of this memory controller.
-  UINT8            RevisionId;              ///< The PCI revision id of this memory controller.
-  UINT8            ChannelCount;            ///< Number of valid channels that exist on the controller.
-  CHANNEL_INFO     ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
-} CONTROLLER_INFO;
-
-typedef struct {
-  UINT64   BaseAddress;   ///< Trace Base Address
-  UINT64   TotalSize;     ///< Total Trace Region of Same Cache type
-  UINT8    CacheType;     ///< Trace Cache Type
-  UINT8    ErrorCode;     ///< Trace Region Allocation Fail Error code
-  UINT8    Rsvd[2];
-} PSMI_MEM_INFO;
-
-typedef struct {
-  UINT8             Revision;
-  UINT16            DataWidth;              ///< Data width, in bits, of this memory device
-  /** As defined in SMBIOS 3.0 spec
-    Section 7.18.2 and Table 75
-  **/
-  UINT8             MemoryType;             ///< DDR type: DDR3, DDR4, or LPDDR3
-  UINT16            MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
-  UINT16            ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
-  /** As defined in SMBIOS 3.0 spec
-    Section 7.17.3 and Table 72
-  **/
-  UINT8             ErrorCorrectionType;
-
-  SiMrcVersion      Version;
-  BOOLEAN           EccSupport;
-  UINT8             MemoryProfile;
-  UINT32            TotalPhysicalMemorySize;
-  UINT32            DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
-  UINT8             XmpProfileEnable;                  ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
-  UINT8             Ratio;
-  UINT8             RefClk;
-  UINT32            VddVoltage[MAX_PROFILE_NUM];
-  CONTROLLER_INFO   Controller[MAX_NODE];
-} MEMORY_INFO_DATA_HOB;
-
-/**
-  Memory Platform Data Hob
-
-  <b>Revision 1:</b>
-  - Initial version.
-  <b>Revision 2:</b>
-  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
-  UINT8             Revision;
-  UINT8             Reserved[3];
-  UINT32            BootMode;
-  UINT32            TsegSize;
-  UINT32            TsegBase;
-  UINT32            PrmrrSize;
-  UINT64            PrmrrBase;
-  UINT32            PramSize;
-  UINT64            PramBase;
-  UINT64            DismLimit;
-  UINT64            DismBase;
-  UINT32            GttBase;
-  UINT32            MmioSize;
-  UINT32            PciEBaseAddress;
-  PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
-  EFI_HOB_GUID_TYPE    EfiHobGuidType;
-  MEMORY_PLATFORM_DATA Data;
-  UINT8                *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_
--- a/models/darp7/FSP/LICENSE
+++ b/models/darp7/FSP/LICENSE
@@ -1,46 +0,0 @@
-************************************************************************
-**                                                                    **
-**                                                                    **
-**      IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING     **
-**                                                                    **
-**                     ANY PORTION OF THE SOFTWARE                    **
-**                                                                    **
-************************************************************************
-
-Copyright (c) 2018 Intel Corporation.
-All rights reserved.
-
-Redistribution.
-
-Redistribution and use in binary form, without modification, are permitted
-provided that the following conditions are met:
-
- Redistributions must reproduce the above copyright notice and the 
-following disclaimer in the documentation and/or other materials provided 
-with the distribution.
-
- Neither the name of Intel Corporation nor the names of its suppliers 
-may be used to endorse or promote products derived from this software 
-without specific prior written permission.
-
- No reverse engineering, decompilation, or disassembly of this software 
-is permitted.
-
-"Binary form" includes any format that is commonly used for electronic 
-conveyance that is a reversible, bit-exact translation of binary 
-representation to ASCII or ISO text, for example "uuencode".
-
-DISCLAIMER.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
-THE POSSIBILITY OF SUCH DAMAGE.
-
--- a/models/darp7/README.md
+++ b/models/darp7/README.md
@@ -9,4 +9,4 @@
  - HAP: false
 - [ME](./me.rom)
  - Size: 5116 KB
-  - Version: 15.0.10.1447
+  - Version: 15.0.35.2039
--- a/models/darp7/coreboot.config
+++ b/models/darp7/coreboot.config
@@ -1,29 +1,20 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_DARP7=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
-CONFIG_MAINBOARD_VERSION="darp7"
-CONFIG_ADD_FSP_BINARIES=y
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
-CONFIG_FSP_M_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_M.fd"
-CONFIG_FSP_S_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Fsp_S.fd"
-CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/FSP/Include"
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
-CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x51a1
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/darp7/edk2.config
+++ b/models/darp7/edk2.config
@@ -1,2 +1,9 @@
-PCIE_BASE=0xC0000000
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
 #SYSTEM76_EC_LOGGING=TRUE
--- a/models/darp7/me.rom
+++ b/models/darp7/me.rom
--- a/models/darp7/microcode.rom
+++ b/models/darp7/microcode.rom
--- a/models/galp2/coreboot.config
+++ b/models/galp2/coreboot.config
@@ -1,7 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP2=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
-CONFIG_MAINBOARD_VERSION="galp2"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -9,15 +7,15 @@ CONFIG_DEBUG_TPM=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1303
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_USE_ME_CLEANER=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp2/edk2.config
+++ b/models/galp2/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp3-b/coreboot.config
+++ b/models/galp3-b/coreboot.config
@@ -1,7 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP3_B=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
-CONFIG_MAINBOARD_VERSION="galp3-b"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -9,15 +7,15 @@ CONFIG_DEBUG_TPM=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1413
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_USE_ME_CLEANER=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp3-b/edk2.config
+++ b/models/galp3-b/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp3-c/coreboot.config
+++ b/models/galp3-c/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP3_C=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
-CONFIG_MAINBOARD_VERSION="galp3-c"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1323
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp3-c/edk2.config
+++ b/models/galp3-c/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp3/coreboot.config
+++ b/models/galp3/coreboot.config
@@ -1,7 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP3=y
-CONFIG_MAINBOARD_VERSION="galp3"
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
@@ -9,15 +7,15 @@ CONFIG_DEBUG_TPM=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1313
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_USE_ME_CLEANER=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp3/edk2.config
+++ b/models/galp3/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp4/FSP/Fsp_M.fd
+++ b/models/galp4/FSP/Fsp_M.fd
--- a/models/galp4/FSP/Fsp_S.fd
+++ b/models/galp4/FSP/Fsp_S.fd
--- a/models/galp4/FSP/Fsp_T.fd
+++ b/models/galp4/FSP/Fsp_T.fd
--- a/models/galp4/FSP/Include
+++ b/models/galp4/FSP/Include
@@ -1 +0,0 @@
-../../../FSP/CometLakeFspBinPkg/CometLake1/Include
--- a/models/galp4/FSP/LICENSE
+++ b/models/galp4/FSP/LICENSE
@@ -1,46 +0,0 @@
-************************************************************************
-**                                                                    **
-**                                                                    **
-**      IMPORTANT - READ THIS BEFORE COPYING, INSTALLING OR USING     **
-**                                                                    **
-**                     ANY PORTION OF THE SOFTWARE                    **
-**                                                                    **
-************************************************************************
-
-Copyright (c) 2018 Intel Corporation.
-All rights reserved.
-
-Redistribution.
-
-Redistribution and use in binary form, without modification, are permitted
-provided that the following conditions are met:
-
- Redistributions must reproduce the above copyright notice and the 
-following disclaimer in the documentation and/or other materials provided 
-with the distribution.
-
- Neither the name of Intel Corporation nor the names of its suppliers 
-may be used to endorse or promote products derived from this software 
-without specific prior written permission.
-
- No reverse engineering, decompilation, or disassembly of this software 
-is permitted.
-
-"Binary form" includes any format that is commonly used for electronic 
-conveyance that is a reversible, bit-exact translation of binary 
-representation to ASCII or ISO text, for example "uuencode".
-
-DISCLAIMER.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
-THE POSSIBILITY OF SUCH DAMAGE.
-
--- a/models/galp4/README.md
+++ b/models/galp4/README.md
@@ -11,4 +11,4 @@ https://system76.com/guides/galp4
  - HAP: false
 - [ME](./me.rom)
  - Size: 4092 KB
-  - Version: 14.0.10.1204
+  - Version: 14.0.60.1807
--- a/models/galp4/coreboot.config
+++ b/models/galp4/coreboot.config
@@ -1,14 +1,11 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GALP4=y
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro"
-CONFIG_MAINBOARD_VERSION="galp4"
 CONFIG_CCACHE=y
 CONFIG_CONSOLE_SERIAL=n
 CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
-CONFIG_INTEL_GMA_VBT_FILE="$(FIRMWARE_OPEN_MODEL_DIR)/vbt.rom"
 CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
@@ -17,7 +14,8 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y
-CONFIG_SUBSYSTEM_DEVICE_ID=0x1403
-CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SMMSTORE_V2=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_USE_OPTION_TABLE=y
 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
 #CONFIG_CONSOLE_SYSTEM76_EC=y
--- a/models/galp4/edk2.config
+++ b/models/galp4/edk2.config
@@ -0,0 +1,9 @@
+BOOTLOADER=COREBOOT
+DISABLE_SERIAL_TERMINAL=TRUE
+PLATFORM_BOOT_TIMEOUT=2
+PS2_KEYBOARD_ENABLE=TRUE
+#SECURE_BOOT_ENABLE=TRUE
+SERIAL_DRIVER_ENABLE=FALSE
+SHELL_TYPE=NONE
+TPM_ENABLE=TRUE
+#SYSTEM76_EC_LOGGING=TRUE
--- a/models/galp4/fd.rom
+++ b/models/galp4/fd.rom
--- a/models/galp4/me.rom
+++ b/models/galp4/me.rom
--- a/models/galp5/FSP/Fsp_M.fd
+++ b/models/galp5/FSP/Fsp_M.fd
--- a/models/galp5/FSP/Fsp_S.fd
+++ b/models/galp5/FSP/Fsp_S.fd
--- a/models/galp5/FSP/Fsp_T.fd
+++ b/models/galp5/FSP/Fsp_T.fd
--- a/models/galp5/FSP/Include/FirmwareVersionInfoHob.h
+++ b/models/galp5/FSP/Include/FirmwareVersionInfoHob.h
@@ -1,69 +0,0 @@
-/** @file
-  Header file for Firmware Version Information
-
- @copyright
-  INTEL CONFIDENTIAL
-  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
-
-  This program and the accompanying materials are licensed and made available under
-  the terms and conditions of the BSD License which accompanies this distribution.
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
-  UINT8                          MajorVersion;
-  UINT8                          MinorVersion;
-  UINT8                          Revision;
-  UINT16                         BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
-  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
-  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
-  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
-  UINT8                          Type;
-  UINT8                          Length;
-  UINT16                         Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
-  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
-  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
-  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
--- a/models/galp5/FSP/Include/FspInfoHob.h
+++ b/models/galp5/FSP/Include/FspInfoHob.h
@@ -1,56 +0,0 @@
-/** @file
-  Header file for FSP Information HOB.
-
-@copyright
-  INTEL CONFIDENTIAL
-  Copyright 2017 - 2019 Intel Corporation.
-
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-
-#ifndef _FSP_INFO_HOB_H_
-#define _FSP_INFO_HOB_H_
-
-extern EFI_GUID gFspInfoGuid;
-
-#pragma pack (push, 1)
-
-typedef struct {
-UINT8              SiliconInitVersionMajor;
-UINT8              SiliconInitVersionMinor;
-UINT8              SiliconInitVersionRevision;
-UINT8              SiliconInitVersionBuild;
-UINT8              FspVersionRevision;
-UINT8              FspVersionBuild;
-UINT8              TimeStamp [12];
-UINT8              FspVersionMinor;
-} FSP_INFO_HOB;
-
-#pragma pack (pop)
-
-#endif // _FSP_INFO_HOB_H_
--- a/models/galp5/FSP/Include/FspUpd.h
+++ b/models/galp5/FSP/Include/FspUpd.h
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE               0x545F4450554C4754        /* 'TGLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE               0x4D5F4450554C4754        /* 'TGLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE               0x535F4450554C4754        /* 'TGLUPD_S' */
-
-#pragma pack()
-
-#endif
--- a/models/galp5/FSP/Include/FspmUpd.h
+++ b/models/galp5/FSP/Include/FspmUpd.h
--- a/models/galp5/FSP/Include/FspsUpd.h
+++ b/models/galp5/FSP/Include/FspsUpd.h
--- a/models/galp5/FSP/Include/FsptUpd.h
+++ b/models/galp5/FSP/Include/FsptUpd.h
@@ -1,311 +0,0 @@
-/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPTUPD_H__
-#define __FSPTUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
-  UINT32                      MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
-  UINT32                      MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
-  UINT32                      CodeRegionBase;
-
-/** Offset 0x002C
-**/
-  UINT32                      CodeRegionSize;
-
-/** Offset 0x0030
-**/
-  UINT8                       Reserved[16];
-} FSPT_CORE_UPD;
-
-/** Fsp T Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - PcdSerialIoUartDebugEnable
-  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
-  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
-**/
-  UINT8                       PcdSerialIoUartDebugEnable;
-
-/** Offset 0x0041 - PcdSerialIoUartNumber
-  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
-  Core interface, it cannot be used for debug purpose.
-  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
-  UINT8                       PcdSerialIoUartNumber;
-
-/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
-  Select SerialIo Uart Controller mode
-  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
-  4:SerialIoUartSkipInit
-**/
-  UINT8                       PcdSerialIoUartMode;
-
-/** Offset 0x0043
-**/
-  UINT8                       UnusedUpdSpace0;
-
-/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
-  Set default BaudRate Supported from 0 - default to 6000000
-**/
-  UINT32                      PcdSerialIoUartBaudRate;
-
-/** Offset 0x0048 - Pci Express Base Address
-  Base address to be programmed for Pci Express
-**/
-  UINT64                      PcdPciExpressBaseAddress;
-
-/** Offset 0x0050 - Pci Express Region Length
-  Region Length to be programmed for Pci Express
-**/
-  UINT32                      PcdPciExpressRegionLength;
-
-/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
-  Set default Parity.
-  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
-  UINT8                       PcdSerialIoUartParity;
-
-/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
-  Set default word length. 0: Default, 5,6,7,8
-**/
-  UINT8                       PcdSerialIoUartDataBits;
-
-/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
-  Set default stop bits.
-  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
-**/
-  UINT8                       PcdSerialIoUartStopBits;
-
-/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
-  Enables UART hardware flow control, CTS and RTS lines.
-  0: Disable, 1:Enable
-**/
-  UINT8                       PcdSerialIoUartAutoFlow;
-
-/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
-  Select RX pin muxing for SerialIo UART used for debug
-**/
-  UINT32                      PcdSerialIoUartRxPinMux;
-
-/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
-  Select TX pin muxing for SerialIo UART used for debug
-**/
-  UINT32                      PcdSerialIoUartTxPinMux;
-
-/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
-  Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIoUartRtsPinMux;
-
-/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
-  Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIoUartCtsPinMux;
-
-/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
-  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
-  = SerialIoUartPci.
-**/
-  UINT32                      PcdSerialIoUartDebugMmioBase;
-
-/** Offset 0x006C - PcdLpcUartDebugEnable
-  Enable to initialize LPC Uart device in FSP.
-  0:Disable, 1:Enable
-**/
-  UINT8                       PcdLpcUartDebugEnable;
-
-/** Offset 0x006D - Debug Interfaces
-  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
-  BIT2 - Not used.
-**/
-  UINT8                       PcdDebugInterfaceFlags;
-
-/** Offset 0x006E - PcdSerialDebugLevel
-  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
-  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
-  Info & Verbose.
-  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
-  Error Warnings and Info, 5:Load Error Warnings Info and Verbose
-**/
-  UINT8                       PcdSerialDebugLevel;
-
-/** Offset 0x006F - ISA Serial Base selection
-  Select ISA Serial Base address. Default is 0x3F8.
-  0:0x3F8, 1:0x2F8
-**/
-  UINT8                       PcdIsaSerialUartBase;
-
-/** Offset 0x0070 - PcdSerialIo2ndUartEnable
-  Enable Additional SerialIo Uart device in FSP.
-  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
-**/
-  UINT8                       PcdSerialIo2ndUartEnable;
-
-/** Offset 0x0071 - PcdSerialIo2ndUartNumber
-  Select SerialIo Uart Controller Number
-  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
-  UINT8                       PcdSerialIo2ndUartNumber;
-
-/** Offset 0x0072 - PcdSerialIo2ndUartMode - FSPT
-  Select SerialIo Uart Controller mode
-  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
-  4:SerialIoUartSkipInit
-**/
-  UINT8                       PcdSerialIo2ndUartMode;
-
-/** Offset 0x0073
-**/
-  UINT8                       UnusedUpdSpace1;
-
-/** Offset 0x0074 - PcdSerialIo2ndUartBaudRate - FSPT
-  Set default BaudRate Supported from 0 - default to 6000000
-**/
-  UINT32                      PcdSerialIo2ndUartBaudRate;
-
-/** Offset 0x0078 - PcdSerialIo2ndUartParity - FSPT
-  Set default Parity.
-  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
-  UINT8                       PcdSerialIo2ndUartParity;
-
-/** Offset 0x0079 - PcdSerialIo2ndUartDataBits - FSPT
-  Set default word length. 0: Default, 5,6,7,8
-**/
-  UINT8                       PcdSerialIo2ndUartDataBits;
-
-/** Offset 0x007A - PcdSerialIo2ndUartStopBits - FSPT
-  Set default stop bits.
-  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
-**/
-  UINT8                       PcdSerialIo2ndUartStopBits;
-
-/** Offset 0x007B - PcdSerialIo2ndUartAutoFlow - FSPT
-  Enables UART hardware flow control, CTS and RTS lines.
-  0: Disable, 1:Enable
-**/
-  UINT8                       PcdSerialIo2ndUartAutoFlow;
-
-/** Offset 0x007C - PcdSerialIo2ndUartRxPinMux - FSPT
-  Select RX pin muxing for SerialIo UART
-**/
-  UINT32                      PcdSerialIo2ndUartRxPinMux;
-
-/** Offset 0x0080 - PcdSerialIo2ndUartTxPinMux - FSPT
-  Select TX pin muxing for SerialIo UART
-**/
-  UINT32                      PcdSerialIo2ndUartTxPinMux;
-
-/** Offset 0x0084 - PcdSerialIo2ndUartRtsPinMux - FSPT
-  Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIo2ndUartRtsPinMux;
-
-/** Offset 0x0088 - PcdSerialIo2ndUartCtsPinMux - FSPT
-  Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
-  for possible values.
-**/
-  UINT32                      PcdSerialIo2ndUartCtsPinMux;
-
-/** Offset 0x008C - PcdSerialIo2ndUartMmioBase - FSPT
-  Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
-  = SerialIoUartPci.
-**/
-  UINT32                      PcdSerialIo2ndUartMmioBase;
-
-/** Offset 0x0090
-**/
-  UINT32                      TopMemoryCacheSize;
-
-/** Offset 0x0094 - FspDebugHandler
-  <b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
-**/
-  UINT32                      FspDebugHandler;
-
-/** Offset 0x0098
-**/
-  UINT8                       UnusedUpdSpace2[4];
-
-/** Offset 0x009C
-**/
-  UINT8                       ReservedFsptUpd1[20];
-} FSP_T_CONFIG;
-
-/** Fsp T UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
-  FSP_UPD_HEADER              FspUpdHeader;
-
-/** Offset 0x0020
-**/
-  FSPT_CORE_UPD               FsptCoreUpd;
-
-/** Offset 0x0040
-**/
-  FSP_T_CONFIG                FsptConfig;
-
-/** Offset 0x00B0
-**/
-  UINT8                       UnusedUpdSpace3[6];
-
-/** Offset 0x00B6
-**/
-  UINT16                      UpdTerminator;
-} FSPT_UPD;
-
-#pragma pack()
-
-#endif
--- a/models/galp5/FSP/Include/FusaInfoHob.h
+++ b/models/galp5/FSP/Include/FusaInfoHob.h
@@ -1,161 +0,0 @@
-/** @file
-  This file contains definitions required for creation of TGL
-  end-to-end check-the-checker test result hob.
-
-@copyright
-  INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.
-
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-#ifndef _FUSA_INFO_HOB_H_
-#define _FUSA_INFO_HOB_H_
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiFusaInfoGuid;
-
-/**
-  FuSa Info HOB version
-  Use this to compare to the HOB retrieved from the FSP for the
-  exact match
-**/
-#define FUSA_INFO_VERSION 0x00000100
-
-/** Constants used for FUSA_TEST_RESULT->CheckResults[] and
- *  FUSA_TEST_RESULT->TestResult */
-/**@defgroup ResultConstant Check Result Constants*/
-/**@{*/
-#define FUSA_TEST_DEVICE_NOTAVAILABLE  0xFF    /**<device is not available*/
-#define FUSA_TEST_NOTRUN               0x0U    /**<check is not run*/
-#define FUSA_TEST_FAIL                 0xD2U   /**<check fail*/
-#define FUSA_TEST_PASS                 0x2DU   /**<check pass*/
-/**@}*/
-
-/** Fusa test result structure
- **/
-typedef struct
-{
-  UINT32 TestNumber;            /**< test number assigned to this test */
-  UINT32 TotalChecks;           /**< total number of checks in this test */
-  UINT8  TestResult;            /**< if all tests passed then this is FUSA_TEST_PASS.
-                                  if at least one check fails, then this is TEST_FAIL
-                                  if the device (eg. MC channel DIMM) is not available
-                                  then this is FUSA_TEST_DEVICE_NOTAVAILABLE.
-                                  if the test has not been run, then this is FUSA_TEST_NOTRUN*/
-  UINT8  ReservedByte[3];       /**< reserved, as padding for 4 byte-alignment */
-  UINT8  CheckResults[32];      /**< test result for each check.*/
-  UINT32 Crc32;                 /**< crc32 of the structure */
-} FUSA_TEST_RESULT;
-
-
-/**
-  Fusa Test Number assigned to each Fusa test.
-  This will be used for the unique id for each test.
-  FUSA_TEST_RESULT->TestNumber will have this value.
-
-  @note While the core4-7 (cbo4-7) that are strictly related to
-        the TGL-H are listed, there are not within the
-        implementation scope and validation scope yet.
-**/
-typedef enum
-{
-  FusaTestNumMc0Cmi = 0,          ///<Check MC0 CMI path, valid if there is DIMM using MC0
-  FusaTestNumMc1Cmi,              ///<Check MC1 CMI path, valid if there is DIMM using MC1
-  FusaTestNumMc0CmiCh0Data,       ///<Check MC0 CH0 CMI path, valid if there is DIMM using MC0 CH0
-  FusaTestNumMc0CmiCh1Data,       ///<Check MC0 CH1 CMI path, valid if there is DIMM using MC0 CH1
-  FusaTestNumMc0CmiCh2Data,       ///<Check MC0 CH2 CMI path, valid if there is DIMM using MC0 CH2
-  FusaTestNumMc0CmiCh3Data,       ///<Check MC0 CH3 CMI path, valid if there is DIMM using MC0 CH3
-  FusaTestNumMc1CmiCh0Data,       ///<Check MC1 CH0 CMI path, valid if there is DIMM using MC1 CH0
-  FusaTestNumMc1CmiCh1Data,       ///<Check MC1 CH1 CMI path, valid if there is DIMM using MC1 CH1
-  FusaTestNumMc1CmiCh2Data,       ///<Check MC1 CH2 CMI path, valid if there is DIMM using MC1 CH2
-  FusaTestNumMc1CmiCh3Data,       ///<Check MC1 CH3 CMI path, valid if there is DIMM using MC1 CH3
-  FusaTestNumIbecc0Cmi,           ///<Check Ibecc0 CMI path, valid if there is IBECC range covering MC0 DIMMs
-  FusaTestNumIbecc1Cmi,           ///<Check Ibecc1 CMI path, valid if there is IBECC range covering MC1 DIMMs
-  FusaTestNumIbecc0EccCorrError,  ///<Check Ibecc0 ECC correctable error, valid if there is IBECC range covering MC0 DIMMs
-  FusaTestNumIbecc1EccCorrError,  ///<Check Ibecc1 ECC correctable error, valid if there is IBECC range covering MC1 DIMMs
-  FusaTestNumIbecc0EccUncorrError,///<Check Ibecc0 ECC uncorrectable error, valid if there is IBECC range covering MC0 DIMMs
-  FusaTestNumIbecc1EccUncorrError,///<Check Ibecc0 ECC uncorrectable error, valid if there is IBECC range covering MC1 DIMMs
-
-  FusaTestNumMc0Mbist,            ///<Check MC0 MBIST
-  FusaTestNumMc1Mbist,            ///<Check MC1 MBIST
-  FusaTestNumMc0Ch0Mbist,         ///<Check MC0 CH0 MBIST
-  FusaTestNumMc0Ch1Mbist,         ///<Check MC0 CH1 MBIST
-  FusaTestNumMc0Ch2Mbist,         ///<Check MC0 CH2 MBIST
-  FusaTestNumMc0Ch3Mbist,         ///<Check MC0 CH3 MBIST
-  FusaTestNumMc1Ch0Mbist,         ///<Check MC1 CH0 MBIST
-  FusaTestNumMc1Ch1Mbist,         ///<Check MC1 CH1 MBIST
-  FusaTestNumMc1Ch2Mbist,         ///<Check MC1 CH2 MBIST
-  FusaTestNumMc1Ch3Mbist,         ///<Check MC1 CH3 MBIST
-  FusaTestNumIbecc0Mbist,         ///<Check Ibecc0 MBIST
-  FusaTestNumIbecc1Mbist,         ///<Check Ibecc1 MBIST
-
-  FusaTestNumCpu0Idi,             ///<Check core0 IDI path, valid if there is core0 in the SKU
-  FusaTestNumCpu1Idi,             ///<Check core1 IDI path, valid if there is core1 in the SKU
-  FusaTestNumCpu2Idi,             ///<Check core2 IDI path, valid if there is core2 in the SKU
-  FusaTestNumCpu3Idi,             ///<Check core3 IDI path, valid if there is core3 in the SKU
-  FusaTestNumCpu4Idi,             ///<Check core4 IDI path, valid if there is core4 in the SKU
-  FusaTestNumCpu5Idi,             ///<Check core5 IDI path, valid if there is core5 in the SKU
-  FusaTestNumCpu6Idi,             ///<Check core6 IDI path, valid if there is core6 in the SKU
-  FusaTestNumCpu7Idi,             ///<Check core7 IDI path, valid if there is core7 in the SKU
-
-  FusaTestNumCpu0Mbist,             ///<Check core0 Mbist, valid if there is core0 in the SKU
-  FusaTestNumCpu1Mbist,             ///<Check core1 Mbist, valid if there is core1 in the SKU
-  FusaTestNumCpu2Mbist,             ///<Check core2 Mbist, valid if there is core2 in the SKU
-  FusaTestNumCpu3Mbist,             ///<Check core3 Mbist, valid if there is core3 in the SKU
-  FusaTestNumCpu4Mbist,             ///<Check core4 Mbist, valid if there is core4 in the SKU
-  FusaTestNumCpu5Mbist,             ///<Check core5 Mbist, valid if there is core5 in the SKU
-  FusaTestNumCpu6Mbist,             ///<Check core6 Mbist, valid if there is core6 in the SKU
-  FusaTestNumCpu7Mbist,             ///<Check core7 Mbist, valid if there is core7 in the SKU
-
-  FusaTestNumCboSlice0Ingress,    ///<Check CBO0 ingress path, valid if there is core0 in the SKU
-  FusaTestNumCboSlice1Ingress,    ///<Check CBO1 ingress path, valid if there is core1 in the SKU
-  FusaTestNumCboSlice2Ingress,    ///<Check CBO2 ingress path, valid if there is core2 in the SKU
-  FusaTestNumCboSlice3Ingress,    ///<Check CBO3 ingress path, valid if there is core3 in the SKU
-  FusaTestNumCboSlice4Ingress,    ///<Check CBO4 ingress path, valid if there is core4 in the SKU
-  FusaTestNumCboSlice5Ingress,    ///<Check CBO5 ingress path, valid if there is core5 in the SKU
-  FusaTestNumCboSlice6Ingress,    ///<Check CBO6 ingress path, valid if there is core6 in the SKU
-  FusaTestNumCboSlice7Ingress,    ///<Check CBO7 ingress path, valid if there is core7 in the SKU
-
-  FusaTestNumOpiLinkIosfData,     ///<Check OPI Link path
-  FusaTestNumDip,                 ///<Check DIP path
-  FusaTestNumIop,                 ///<Check IOP path
-
-  FusaTestNumTotal                ///<Totak CTC groups count
-} FUSA_TEST_NUMBER;
-
-/**
-  Fusa test result HOB structure
-**/
-typedef struct {
-  UINT32 Version;
-  FUSA_TEST_RESULT FspDxCtcTestResult[FusaTestNumTotal];
-} FUSA_INFO_HOB;
-
-#pragma pack (pop)
-
-#endif // _FUSA_INFO_HOB_H_
--- a/models/galp5/FSP/Include/GpioConfig.h
+++ b/models/galp5/FSP/Include/GpioConfig.h
@@ -1,356 +0,0 @@
-/** @file
-  Header file for GpioConfig structure used by GPIO library.
-
- @copyright
-  INTEL CONFIDENTIAL
-  Copyright 2014 - 2017 Intel Corporation.
-
-  The source code contained or described herein and all documents related to the
-  source code ("Material") are owned by Intel Corporation or its suppliers or
-  licensors. Title to the Material remains with Intel Corporation or its suppliers
-  and licensors. The Material may contain trade secrets and proprietary and
-  confidential information of Intel Corporation and its suppliers and licensors,
-  and is protected by worldwide copyright and trade secret laws and treaty
-  provisions. No part of the Material may be used, copied, reproduced, modified,
-  published, uploaded, posted, transmitted, distributed, or disclosed in any way
-  without Intel's prior express written permission.
-
-  No license under any patent, copyright, trade secret or other intellectual
-  property right is granted to or conferred upon you by disclosure or delivery
-  of the Materials, either expressly, by implication, inducement, estoppel or
-  otherwise. Any license under such intellectual property rights must be
-  express and approved by Intel in writing.
-
-  Unless otherwise agreed by Intel in writing, you may not remove or alter
-  this notice or any other notice embedded in Materials by Intel or
-  Intel's suppliers or licensors in any way.
-
-  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
-  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
-  the terms of your license agreement with Intel or your vendor. This file may
-  be modified by the user, subject to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-#ifndef _GPIO_CONFIG_H_
-#define _GPIO_CONFIG_H_
-
-#pragma pack(push, 1)
-
-///
-/// For any GpioPad usage in code use GPIO_PAD type
-///
-typedef UINT32 GPIO_PAD;
-
-
-///
-/// For any GpioGroup usage in code use GPIO_GROUP type
-///
-typedef UINT32 GPIO_GROUP;
-
-/**
-  GPIO configuration structure used for pin programming.
-  Structure contains fields that can be used to configure pad.
-**/
-typedef struct {
-  /**
-  Pad Mode
-  Pad can be set as GPIO or one of its native functions.
-  When in native mode setting Direction (except Inversion), OutputState,
-  InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
-  Refer to definition of GPIO_PAD_MODE.
-  Refer to EDS for each native mode according to the pad.
-  **/
-  UINT32 PadMode            : 5;
-  /**
-  Host Software Pad Ownership
-  Set pad to ACPI mode or GPIO Driver Mode.
-  Refer to definition of GPIO_HOSTSW_OWN.
-  **/
-  UINT32 HostSoftPadOwn     : 2;
-  /**
-  GPIO Direction
-  Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
-  Refer to definition of GPIO_DIRECTION for supported settings.
-  **/
-  UINT32 Direction           : 6;
-  /**
-  Output State
-  Set Pad output value.
-  Refer to definition of GPIO_OUTPUT_STATE for supported settings.
-  This setting takes place when output is enabled.
-  **/
-  UINT32 OutputState         : 2;
-  /**
-  GPIO Interrupt Configuration
-  Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
-  This setting is applicable only if GPIO is in GpioMode with input enabled.
-  Refer to definition of GPIO_INT_CONFIG for supported settings.
-  **/
-  UINT32 InterruptConfig     : 9;
-  /**
-  GPIO Power Configuration.
-  This setting controls Pad Reset Configuration.
-  Refer to definition of GPIO_RESET_CONFIG for supported settings.
-  **/
-  UINT32 PowerConfig        : 8;
-  /**
-  GPIO Electrical Configuration
-  This setting controls pads termination and voltage tolerance.
-  Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
-  **/
-  UINT32 ElectricalConfig   : 9;
-  /**
-  GPIO Lock Configuration
-  This setting controls pads lock.
-  Refer to definition of GPIO_LOCK_CONFIG for supported settings.
-  **/
-  UINT32 LockConfig         : 4;
-  /**
-  Additional GPIO configuration
-  Refer to definition of GPIO_OTHER_CONFIG for supported settings.
-  **/
-  UINT32 OtherSettings     :  2;
-  UINT32 RsvdBits          : 17;    ///< Reserved bits for future extension
-} GPIO_CONFIG;
-
-
-typedef enum {
-  GpioHardwareDefault        = 0x0    ///< Leave setting unmodified
-} GPIO_HARDWARE_DEFAULT;
-
-/**
-  GPIO Pad Mode
-  Refer to GPIO documentation on native functions available for certain pad.
-  If GPIO is set to one of NativeX modes then following settings are not applicable
-  and can be skipped:
-  - Interrupt related settings
-  - Host Software Ownership
-  - Output/Input enabling/disabling
-  - Output lock
-**/
-typedef enum {
-  GpioPadModeGpio     = 0x1,
-  GpioPadModeNative1  = 0x3,
-  GpioPadModeNative2  = 0x5,
-  GpioPadModeNative3  = 0x7,
-  GpioPadModeNative4  = 0x9
-} GPIO_PAD_MODE;
-
-/**
-  Host Software Pad Ownership modes
-  This setting affects GPIO interrupt status registers. Depending on chosen ownership
-  some GPIO Interrupt status register get updated and other masked.
-  Please refer to EDS for HOSTSW_OWN register description.
-**/
-typedef enum {
-  GpioHostOwnDefault = 0x0,   ///< Leave ownership value unmodified
-  /**
-  Set HOST ownership to ACPI.
-  Use this setting if pad is not going to be used by GPIO OS driver.
-  If GPIO is configured to generate SCI/SMI/NMI then this setting must be
-  used for interrupts to work
-  **/
-  GpioHostOwnAcpi    = 0x1,
-  /**
-  Set HOST ownership to GPIO Driver mode.
-  Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
-  GPIO OS Driver will be able to control the pad if appropriate entry in
-  ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
-  **/
-  GpioHostOwnGpio    = 0x3
-} GPIO_HOSTSW_OWN;
-
-///
-/// GPIO Direction
-///
-typedef enum {
-  GpioDirDefault         = 0x0,                ///< Leave pad direction setting unmodified
-  GpioDirInOut           = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
-  GpioDirInInvOut        = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
-  GpioDirIn              = (0x3 | (0x1 << 3)), ///< Set pad for input only
-  GpioDirInInv           = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
-  GpioDirOut             = 0x5,                ///< Set pad for output only
-  GpioDirNone            = 0x7                 ///< Disable both output and input
-} GPIO_DIRECTION;
-
-/**
-  GPIO Output State
-  This field is relevant only if output is enabled
-**/
-typedef enum {
-  GpioOutDefault         = 0x0,  ///< Leave output value unmodified
-  GpioOutLow             = 0x1,  ///< Set output to low
-  GpioOutHigh            = 0x3   ///< Set output to high
-} GPIO_OUTPUT_STATE;
-
-/**
-  GPIO interrupt configuration
-  This setting is applicable only if pad is in GPIO mode and has input enabled.
-  GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
-  and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
-  EDS for details on this settings.
-  Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
-  to describe an interrupt e.g. GpioIntApic | GpioIntLevel
-  If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
-  If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
-  Not all GPIO are capable of generating an SMI or NMI interrupt.
-  When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
-  interrupt cannot be shared and its IRQn number is not configurable.
-  Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
-  If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
-  exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
-  This type of GPIO Driver interrupt doesn't have any additional routing setting
-  required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
-**/
-
-typedef enum {
-  GpioIntDefault           = 0x0,  ///< Leave value of interrupt routing unmodified
-  GpioIntDis               = 0x1,  ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
-  GpioIntNmi               = 0x3,  ///< Enable NMI interrupt only
-  GpioIntSmi               = 0x5,  ///< Enable SMI interrupt only
-  GpioIntSci               = 0x9,  ///< Enable SCI interrupt only
-  GpioIntApic              = 0x11, ///< Enable IOxAPIC interrupt only
-  GpioIntLevel       = (0x1 << 5), ///< Set interrupt as level triggered
-  GpioIntEdge        = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
-  GpioIntLvlEdgDis   = (0x5 << 5), ///< Disable interrupt trigger
-  GpioIntBothEdge    = (0x7 << 5)  ///< Set interrupt as both edge triggered
-} GPIO_INT_CONFIG;
-
-#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK  0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
-#define B_GPIO_INT_CONFIG_INT_TYPE_MASK    0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
-
-/**
-  GPIO Power Configuration
-  GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
-  be used to reset certain GPIO settings.
-  Refer to EDS for settings that are controllable by PadRstCfg.
-**/
-typedef enum {
-
-
-  GpioResetDefault   = 0x00,        ///< Leave value of pad reset unmodified
-  ///
-  /// Deprecated settings. Maintained only for compatibility.
-  ///
-  GpioResetPwrGood   = 0x09,        ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
-  GpioResetDeep      = 0x0B,        ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
-  GpioResetNormal    = 0x0D,        ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
-  GpioResetResume    = 0x0F,        ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
-
-  ///
-  /// New GPIO reset configuration options
-  ///
-  /**
-  Resume Reset (RSMRST)
-    GPP: PadRstCfg = 00b = "Powergood"
-    GPD: PadRstCfg = 11b = "Resume Reset"
-  Pad setting will reset on:
-  - DeepSx transition
-  - G3
-  Pad settings will not reset on:
-  - S3/S4/S5 transition
-  - Warm/Cold/Global reset
-  **/
-  GpioResumeReset      = 0x01,
-  /**
-  Host Deep Reset
-    PadRstCfg = 01b = "Deep GPIO Reset"
-  Pad settings will reset on:
-  - Warm/Cold/Global reset
-  - DeepSx transition
-  - G3
-  Pad settings will not reset on:
-  - S3/S4/S5 transition
-  **/
-  GpioHostDeepReset    = 0x03,
-  /**
-  Platform Reset (PLTRST)
-    PadRstCfg = 10b = "GPIO Reset"
-  Pad settings will reset on:
-  - S3/S4/S5 transition
-  - Warm/Cold/Global reset
-  - DeepSx transition
-  - G3
-  **/
-  GpioPlatformReset    = 0x05,
-  /**
-  Deep Sleep Well Reset (DSW_PWROK)
-    GPP: not applicable
-    GPD: PadRstCfg = 00b = "Powergood"
-  Pad settings will reset on:
-  - G3
-  Pad settings will not reset on:
-  - S3/S4/S5 transition
-  - Warm/Cold/Global reset
-  - DeepSx transition
-  **/
-  GpioDswReset         = 0x07
-} GPIO_RESET_CONFIG;
-
-/**
-  GPIO Electrical Configuration
-  Set GPIO termination and Pad Tolerance (applicable only for some pads)
-  Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
-**/
-typedef enum {
-  GpioTermDefault          = 0x0,  ///< Leave termination setting unmodified
-  GpioTermNone             = 0x1,  ///< none
-  GpioTermWpd5K            = 0x5,  ///< 5kOhm weak pull-down
-  GpioTermWpd20K           = 0x9,  ///< 20kOhm weak pull-down
-  GpioTermWpu1K            = 0x13, ///< 1kOhm weak pull-up
-  GpioTermWpu2K            = 0x17, ///< 2kOhm weak pull-up
-  GpioTermWpu5K            = 0x15, ///< 5kOhm weak pull-up
-  GpioTermWpu20K           = 0x19, ///< 20kOhm weak pull-up
-  GpioTermWpu1K2K          = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
-  /**
-  Native function controls pads termination
-  This setting is applicable only to some native modes.
-  Please check EDS to determine which native functionality
-  can control pads termination
-  **/
-  GpioTermNative     = 0x1F,
-  GpioNoTolerance1v8 = (0x1 << 5),   ///< Disable 1.8V pad tolerance
-  GpioTolerance1v8   = (0x3 << 5)    ///< Enable 1.8V pad tolerance
-} GPIO_ELECTRICAL_CONFIG;
-
-#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK    0x1F   ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
-#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK  0x60   ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
-
-/**
-  GPIO LockConfiguration
-  Set GPIO configuration lock and output state lock.
-  GpioLockPadConfig and GpioLockOutputState can be OR'ed.
-  Lock settings reset is in Powergood domain. Care must be taken when using this setting
-  as fields it locks may be reset by a different signal and can be controllable
-  by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
-  functions which allow to unlock a GPIO pad.
-**/
-typedef enum {
-  GpioLockDefault          = 0x0,  ///< Leave lock setting unmodified
-  GpioPadConfigLock        = 0x3,  ///< Lock Pad Configuration
-  GpioOutputStateLock      = 0x5   ///< Lock GPIO pad output value
-} GPIO_LOCK_CONFIG;
-
-#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK  0x3  ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
-#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK    0x5  ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
-
-/**
-  Other GPIO Configuration
-  GPIO_OTHER_CONFIG is used for less often settings and for future extensions
-  Supported settings:
-   - RX raw override to '1' - allows to override input value to '1'
-      This setting is applicable only if in input mode (both in GPIO and native usage).
-      The override takes place at the internal pad state directly from buffer and before the RXINV.
-**/
-typedef enum {
-  GpioRxRaw1Default           = 0x0,  ///< Use default input override value
-  GpioRxRaw1Dis               = 0x1,  ///< Don't override input
-  GpioRxRaw1En                = 0x3   ///< Override input to '1'
-} GPIO_OTHER_CONFIG;
-
-#define B_GPIO_OTHER_CONFIG_RXRAW_MASK  0x3  ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
-
-#pragma pack(pop)
-
-#endif //_GPIO_CONFIG_H_
--- a/models/galp5/FSP/Include/GpioSampleDef.h
+++ b/models/galp5/FSP/Include/GpioSampleDef.h
@@ -1,382 +0,0 @@
-/** @file
-
-Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __GPIOCONFIG_H__
-#define __GPIOCONFIG_H__
-#include <FsptUpd.h>
-#include <FspmUpd.h>
-#include <FspsUpd.h>
-
-/*
-  SKL LP GPIO pins
-  Use below for functions from PCH GPIO Lib which
-  require GpioPad as argument. Encoding used here
-  has all information required by library functions
-*/
-#define GPIO_SKL_LP_GPP_A0      0x02000000
-#define GPIO_SKL_LP_GPP_A1      0x02000001
-#define GPIO_SKL_LP_GPP_A2      0x02000002
-#define GPIO_SKL_LP_GPP_A3      0x02000003
-#define GPIO_SKL_LP_GPP_A4      0x02000004
-#define GPIO_SKL_LP_GPP_A5      0x02000005
-#define GPIO_SKL_LP_GPP_A6      0x02000006
-#define GPIO_SKL_LP_GPP_A7      0x02000007
-#define GPIO_SKL_LP_GPP_A8      0x02000008
-#define GPIO_SKL_LP_GPP_A9      0x02000009
-#define GPIO_SKL_LP_GPP_A10     0x0200000A
-#define GPIO_SKL_LP_GPP_A11     0x0200000B
-#define GPIO_SKL_LP_GPP_A12     0x0200000C
-#define GPIO_SKL_LP_GPP_A13     0x0200000D
-#define GPIO_SKL_LP_GPP_A14     0x0200000E
-#define GPIO_SKL_LP_GPP_A15     0x0200000F
-#define GPIO_SKL_LP_GPP_A16     0x02000010
-#define GPIO_SKL_LP_GPP_A17     0x02000011
-#define GPIO_SKL_LP_GPP_A18     0x02000012
-#define GPIO_SKL_LP_GPP_A19     0x02000013
-#define GPIO_SKL_LP_GPP_A20     0x02000014
-#define GPIO_SKL_LP_GPP_A21     0x02000015
-#define GPIO_SKL_LP_GPP_A22     0x02000016
-#define GPIO_SKL_LP_GPP_A23     0x02000017
-#define GPIO_SKL_LP_GPP_B0      0x02010000
-#define GPIO_SKL_LP_GPP_B1      0x02010001
-#define GPIO_SKL_LP_GPP_B2      0x02010002
-#define GPIO_SKL_LP_GPP_B3      0x02010003
-#define GPIO_SKL_LP_GPP_B4      0x02010004
-#define GPIO_SKL_LP_GPP_B5      0x02010005
-#define GPIO_SKL_LP_GPP_B6      0x02010006
-#define GPIO_SKL_LP_GPP_B7      0x02010007
-#define GPIO_SKL_LP_GPP_B8      0x02010008
-#define GPIO_SKL_LP_GPP_B9      0x02010009
-#define GPIO_SKL_LP_GPP_B10     0x0201000A
-#define GPIO_SKL_LP_GPP_B11     0x0201000B
-#define GPIO_SKL_LP_GPP_B12     0x0201000C
-#define GPIO_SKL_LP_GPP_B13     0x0201000D
-#define GPIO_SKL_LP_GPP_B14     0x0201000E
-#define GPIO_SKL_LP_GPP_B15     0x0201000F
-#define GPIO_SKL_LP_GPP_B16     0x02010010
-#define GPIO_SKL_LP_GPP_B17     0x02010011
-#define GPIO_SKL_LP_GPP_B18     0x02010012
-#define GPIO_SKL_LP_GPP_B19     0x02010013
-#define GPIO_SKL_LP_GPP_B20     0x02010014
-#define GPIO_SKL_LP_GPP_B21     0x02010015
-#define GPIO_SKL_LP_GPP_B22     0x02010016
-#define GPIO_SKL_LP_GPP_B23     0x02010017
-#define GPIO_SKL_LP_GPP_C0      0x02020000
-#define GPIO_SKL_LP_GPP_C1      0x02020001
-#define GPIO_SKL_LP_GPP_C2      0x02020002
-#define GPIO_SKL_LP_GPP_C3      0x02020003
-#define GPIO_SKL_LP_GPP_C4      0x02020004
-#define GPIO_SKL_LP_GPP_C5      0x02020005
-#define GPIO_SKL_LP_GPP_C6      0x02020006
-#define GPIO_SKL_LP_GPP_C7      0x02020007
-#define GPIO_SKL_LP_GPP_C8      0x02020008
-#define GPIO_SKL_LP_GPP_C9      0x02020009
-#define GPIO_SKL_LP_GPP_C10     0x0202000A
-#define GPIO_SKL_LP_GPP_C11     0x0202000B
-#define GPIO_SKL_LP_GPP_C12     0x0202000C
-#define GPIO_SKL_LP_GPP_C13     0x0202000D
-#define GPIO_SKL_LP_GPP_C14     0x0202000E
-#define GPIO_SKL_LP_GPP_C15     0x0202000F
-#define GPIO_SKL_LP_GPP_C16     0x02020010
-#define GPIO_SKL_LP_GPP_C17     0x02020011
-#define GPIO_SKL_LP_GPP_C18     0x02020012
-#define GPIO_SKL_LP_GPP_C19     0x02020013
-#define GPIO_SKL_LP_GPP_C20     0x02020014
-#define GPIO_SKL_LP_GPP_C21     0x02020015
-#define GPIO_SKL_LP_GPP_C22     0x02020016
-#define GPIO_SKL_LP_GPP_C23     0x02020017
-#define GPIO_SKL_LP_GPP_D0      0x02030000
-#define GPIO_SKL_LP_GPP_D1      0x02030001
-#define GPIO_SKL_LP_GPP_D2      0x02030002
-#define GPIO_SKL_LP_GPP_D3      0x02030003
-#define GPIO_SKL_LP_GPP_D4      0x02030004
-#define GPIO_SKL_LP_GPP_D5      0x02030005
-#define GPIO_SKL_LP_GPP_D6      0x02030006
-#define GPIO_SKL_LP_GPP_D7      0x02030007
-#define GPIO_SKL_LP_GPP_D8      0x02030008
-#define GPIO_SKL_LP_GPP_D9      0x02030009
-#define GPIO_SKL_LP_GPP_D10     0x0203000A
-#define GPIO_SKL_LP_GPP_D11     0x0203000B
-#define GPIO_SKL_LP_GPP_D12     0x0203000C
-#define GPIO_SKL_LP_GPP_D13     0x0203000D
-#define GPIO_SKL_LP_GPP_D14     0x0203000E
-#define GPIO_SKL_LP_GPP_D15     0x0203000F
-#define GPIO_SKL_LP_GPP_D16     0x02030010
-#define GPIO_SKL_LP_GPP_D17     0x02030011
-#define GPIO_SKL_LP_GPP_D18     0x02030012
-#define GPIO_SKL_LP_GPP_D19     0x02030013
-#define GPIO_SKL_LP_GPP_D20     0x02030014
-#define GPIO_SKL_LP_GPP_D21     0x02030015
-#define GPIO_SKL_LP_GPP_D22     0x02030016
-#define GPIO_SKL_LP_GPP_D23     0x02030017
-#define GPIO_SKL_LP_GPP_E0      0x02040000
-#define GPIO_SKL_LP_GPP_E1      0x02040001
-#define GPIO_SKL_LP_GPP_E2      0x02040002
-#define GPIO_SKL_LP_GPP_E3      0x02040003
-#define GPIO_SKL_LP_GPP_E4      0x02040004
-#define GPIO_SKL_LP_GPP_E5      0x02040005
-#define GPIO_SKL_LP_GPP_E6      0x02040006
-#define GPIO_SKL_LP_GPP_E7      0x02040007
-#define GPIO_SKL_LP_GPP_E8      0x02040008
-#define GPIO_SKL_LP_GPP_E9      0x02040009
-#define GPIO_SKL_LP_GPP_E10     0x0204000A
-#define GPIO_SKL_LP_GPP_E11     0x0204000B
-#define GPIO_SKL_LP_GPP_E12     0x0204000C
-#define GPIO_SKL_LP_GPP_E13     0x0204000D
-#define GPIO_SKL_LP_GPP_E14     0x0204000E
-#define GPIO_SKL_LP_GPP_E15     0x0204000F
-#define GPIO_SKL_LP_GPP_E16     0x02040010
-#define GPIO_SKL_LP_GPP_E17     0x02040011
-#define GPIO_SKL_LP_GPP_E18     0x02040012
-#define GPIO_SKL_LP_GPP_E19     0x02040013
-#define GPIO_SKL_LP_GPP_E20     0x02040014
-#define GPIO_SKL_LP_GPP_E21     0x02040015
-#define GPIO_SKL_LP_GPP_E22     0x02040016
-#define GPIO_SKL_LP_GPP_E23     0x02040017
-#define GPIO_SKL_LP_GPP_F0      0x02050000
-#define GPIO_SKL_LP_GPP_F1      0x02050001
-#define GPIO_SKL_LP_GPP_F2      0x02050002
-#define GPIO_SKL_LP_GPP_F3      0x02050003
-#define GPIO_SKL_LP_GPP_F4      0x02050004
-#define GPIO_SKL_LP_GPP_F5      0x02050005
-#define GPIO_SKL_LP_GPP_F6      0x02050006
-#define GPIO_SKL_LP_GPP_F7      0x02050007
-#define GPIO_SKL_LP_GPP_F8      0x02050008
-#define GPIO_SKL_LP_GPP_F9      0x02050009
-#define GPIO_SKL_LP_GPP_F10     0x0205000A
-#define GPIO_SKL_LP_GPP_F11     0x0205000B
-#define GPIO_SKL_LP_GPP_F12     0x0205000C
-#define GPIO_SKL_LP_GPP_F13     0x0205000D
-#define GPIO_SKL_LP_GPP_F14     0x0205000E
-#define GPIO_SKL_LP_GPP_F15     0x0205000F
-#define GPIO_SKL_LP_GPP_F16     0x02050010
-#define GPIO_SKL_LP_GPP_F17     0x02050011
-#define GPIO_SKL_LP_GPP_F18     0x02050012
-#define GPIO_SKL_LP_GPP_F19     0x02050013
-#define GPIO_SKL_LP_GPP_F20     0x02050014
-#define GPIO_SKL_LP_GPP_F21     0x02050015
-#define GPIO_SKL_LP_GPP_F22     0x02050016
-#define GPIO_SKL_LP_GPP_F23     0x02050017
-#define GPIO_SKL_LP_GPP_G0      0x02060000
-#define GPIO_SKL_LP_GPP_G1      0x02060001
-#define GPIO_SKL_LP_GPP_G2      0x02060002
-#define GPIO_SKL_LP_GPP_G3      0x02060003
-#define GPIO_SKL_LP_GPP_G4      0x02060004
-#define GPIO_SKL_LP_GPP_G5      0x02060005
-#define GPIO_SKL_LP_GPP_G6      0x02060006
-#define GPIO_SKL_LP_GPP_G7      0x02060007
-#define GPIO_SKL_LP_GPD0        0x02070000
-#define GPIO_SKL_LP_GPD1        0x02070001
-#define GPIO_SKL_LP_GPD2        0x02070002
-#define GPIO_SKL_LP_GPD3        0x02070003
-#define GPIO_SKL_LP_GPD4        0x02070004
-#define GPIO_SKL_LP_GPD5        0x02070005
-#define GPIO_SKL_LP_GPD6        0x02070006
-#define GPIO_SKL_LP_GPD7        0x02070007
-#define GPIO_SKL_LP_GPD8        0x02070008
-#define GPIO_SKL_LP_GPD9        0x02070009
-#define GPIO_SKL_LP_GPD10       0x0207000A
-#define GPIO_SKL_LP_GPD11       0x0207000B
-
-#define END_OF_GPIO_TABLE   0xFFFFFFFF
-
-//Sample GPIO Table
-
-static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
-{
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//H_RCIN_N
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//LPC_FRAME_ESPI_CS_N
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//INT_SERIRQ
-//skip for eSPI function  {GPIO_SKL_LP_GPP_A7,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SLP_S0ix_R_N
-  {GPIO_SKL_LP_GPP_A8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_CLKRUN_N
-//skip for eSPI function    {GPIO_SKL_LP_GPP_A9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
-  {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//PCH_CLK_PCI_TPM
-  {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//EC_HID_INTR
-  {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
-  {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SUS_PWR_ACK_R
-//skip for eSPI function    {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
-  {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SUSACK_R_N
-  {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_1P8_SEL
-  {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_PWR_EN_N
-  {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_0_SENSOR
-  {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_1_SENSOR
-  {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_2_SENSOR
-  {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GNSS_CHUB_IRQ
-  {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//FPS_SLP_N
-  {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//FPS_DRDY
-  {GPIO_SKL_LP_GPP_B0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID0
-  {GPIO_SKL_LP_GPP_B1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID1
-  {GPIO_SKL_LP_GPP_B2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GP_VRALERTB
-  {GPIO_SKL_LP_GPP_B3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,  GpioTermNone}},//TCH_PAD_INTR_R_N
-  {GPIO_SKL_LP_GPP_B4,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//BT_RF_KILL_N
-  {GPIO_SKL_LP_GPP_B5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_BT_UART_WAKE_N
-  // {GPIO_SKL_LP_GPP_B6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT1_N
-  // {GPIO_SKL_LP_GPP_B7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
-  // {GPIO_SKL_LP_GPP_B8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
-  // {GPIO_SKL_LP_GPP_B9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
-  // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WLAN_N
-  {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//MPHY_EXT_PWR_GATEB
-  {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SLP_S0_N
-  {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PLT_RST_N
-  {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_PWREN
-  {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_DFU
-  {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
-  {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset,  GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
-  {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
-  {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,   GpioTermNone}},//FPS_GSPI1_CS_R1_N
-  {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
-  {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
-  {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
-  {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
-  {GPIO_SKL_LP_GPP_C0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SMB_CLK
-  {GPIO_SKL_LP_GPP_C1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SMB_DATA
-  {GPIO_SKL_LP_GPP_C2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
-  {GPIO_SKL_LP_GPP_C3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_CLK
-  {GPIO_SKL_LP_GPP_C4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_DATA
-  {GPIO_SKL_LP_GPP_C5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
-  {GPIO_SKL_LP_GPP_C6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML1_CLK
-  {GPIO_SKL_LP_GPP_C7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SML1_DATA
-  {GPIO_SKL_LP_GPP_C8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RXD
-  {GPIO_SKL_LP_GPP_C9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_TXD
-  {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RTS_N
-  {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_CTS_N
-  {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
-  {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
-  {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
-  {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
-  {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SDA
-  {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SCL
-  {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SDA
-  {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SCL
-  {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RXD
-  {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_TXD
-  {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RTS_N
-  {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_CTS_N
-  {GPIO_SKL_LP_GPP_D0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CS_N
-  {GPIO_SKL_LP_GPP_D1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CLK
-  {GPIO_SKL_LP_GPP_D2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MISO
-  {GPIO_SKL_LP_GPP_D3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MOSI
-  {GPIO_SKL_LP_GPP_D4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CSI2_FLASH_STROBE
-  {GPIO_SKL_LP_GPP_D5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SDA
-  {GPIO_SKL_LP_GPP_D6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SCL
-  {GPIO_SKL_LP_GPP_D7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SDA
-  {GPIO_SKL_LP_GPP_D8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SCL
-  {GPIO_SKL_LP_GPP_D9,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//HOME_BTN
-  {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SCREEN_LOCK_PCH
-  {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_UP_PCH
-  {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_DOWN_PCH
-  {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
-  {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
-  {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RTS_N
-  {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
-  {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_1
-  {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_1
-  {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_0
-  {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_DATA_0
-  {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO2
-  {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO3
-  {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP_MCLK
-  {GPIO_SKL_LP_GPP_E0,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//SPI_TPM_HDR_IRQ_N
-  {GPIO_SKL_LP_GPP_E1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA_ODD_PRSNT_N
-  {GPIO_SKL_LP_GPP_E2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
-  {GPIO_SKL_LP_GPP_E3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioResumeReset,  GpioTermNone}},//EINK_SSR_DFU_N
-  {GPIO_SKL_LP_GPP_E4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_RESET
-  {GPIO_SKL_LP_GPP_E5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
-  {GPIO_SKL_LP_GPP_E6,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
-  {GPIO_SKL_LP_GPP_E8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SATA_LED_N
-  {GPIO_SKL_LP_GPP_E9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_0_WP1_OTG_N
-  {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_1_WP4_N
-  {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
-  {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_IRQ
-  {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_HPD_Q
-  {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_HPD_Q
-  {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset,  GpioTermNone}},//SMC_EXTSMI_R_N
-  {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//SMC_RUNTIME_SCI_R_N
-  {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EDP_HPD
-  {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_CTRL_CLK
-  {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI1_CTRL_DATA
-  {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_CTRL_CLK
-  {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI2_CTRL_DATA
-  {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_CODEC_IRQ
-  {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_RST_N
-  {GPIO_SKL_LP_GPP_F0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SCLK
-  {GPIO_SKL_LP_GPP_F1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SFRM
-  {GPIO_SKL_LP_GPP_F2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_TXD
-  {GPIO_SKL_LP_GPP_F3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_RXD
-  {GPIO_SKL_LP_GPP_F4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
-  {GPIO_SKL_LP_GPP_F5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
-  {GPIO_SKL_LP_GPP_F6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
-  {GPIO_SKL_LP_GPP_F7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
-  {GPIO_SKL_LP_GPP_F8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
-  {GPIO_SKL_LP_GPP_F9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
-  {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
-  {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
-  {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CMD
-  {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA0
-  {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA1
-  {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA2
-  {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA3
-  {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA4
-  {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA5
-  {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA6
-  {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA7
-  {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_RCLK
-  {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CLK
-  {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
-  {GPIO_SKL_LP_GPP_G0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CMD
-  {GPIO_SKL_LP_GPP_G1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA0
-  {GPIO_SKL_LP_GPP_G2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA1
-  {GPIO_SKL_LP_GPP_G3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA2
-  {GPIO_SKL_LP_GPP_G4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA3
-  {GPIO_SKL_LP_GPP_G5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CDB
-  {GPIO_SKL_LP_GPP_G6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CLK
-  {GPIO_SKL_LP_GPP_G7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_WP
-  {GPIO_SKL_LP_GPD0,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_BATLOW_R_N
-  {GPIO_SKL_LP_GPD1,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//AC_PRESENT_R
-  {GPIO_SKL_LP_GPD2,   {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset,  GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
-  {GPIO_SKL_LP_GPD3,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermWpu20K}},//PM_PWRBTN_R_N
-  {GPIO_SKL_LP_GPD4,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S3_R_N
-  {GPIO_SKL_LP_GPD5,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S4_R_N
-  {GPIO_SKL_LP_GPD6,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_M_R_N
-  {GPIO_SKL_LP_GPD7,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
-  {GPIO_SKL_LP_GPD8,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SUS_CLK
-  {GPIO_SKL_LP_GPD9,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PCH_SLP_WLAN_N
-  {GPIO_SKL_LP_GPD10,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S5_R_N
-  {GPIO_SKL_LP_GPD11,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_LANPHY_ENABLE
-  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
-};
-
-#endif   //_GPIO_CONFIG_H_
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Jeremy Soller	b7504e5e18	Sync galp5 with oryp8	2022-02-03 11:43:40 -07:00
Jeremy Soller	1feff769f1	Update coreboot	2022-02-03 11:21:37 -07:00
Jeremy Soller	0d76bcf960	Update galp5 ME settings	2022-02-03 11:21:31 -07:00
Jeremy Soller	c89f7e266f	WIP: enable S3 for TGL-U systems	2022-02-03 08:58:49 -07:00
Jeremy Soller	e8d7c8e636	Update IFD and ME for all models	2022-02-03 08:58:23 -07:00
Tim Crawford	239e2cbaed	build.sh: Set git-describe length Specify `abbrev` to ensure the length of the commit hash is always the same, in case `core.abbrev` is set or the default changes. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-18 11:57:12 -07:00
Tim Crawford	417e5898da	models: Set coreboot, PS/2 keyboard in edk2 config Set BOOTLOADER and PS2_KEYBOARD_ENABLE in the edk2 config. This will allow us to drop the corresponding commits in edk2 when rebasing on the next stable release. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-12 13:49:19 -07:00
Tim Crawford	17cf8b1334	github: Add issue template Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-07 18:32:50 -07:00
Tim Crawford	c73e48228b	coreboot: Fix lemp10 boot - Fix lemp10 memory info to prevent an error message in cbmem. - Fix booting lemp10 with DIMM not present. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2022-01-06 13:20:17 -07:00
Tim Crawford	1dc7780b1c	edk2: Add back boot text about Pop!_OS Recovery Preserve existing UI and add the note about pressing Space to go to the systemd-boot menu for Pop!_OS Recovery. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 15:43:49 -07:00
Tim Crawford	d38ec4e972	changelog: Set date for release Use the date of this commit as the release date. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	8d9fbd1e3c	models: Enable coreboot measured boot All the laptops contain a TPM 2.0 chip. Enable the measured boot security feature by default. Link: https://doc.coreboot.org/security/vboot/measured_boot.html Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	8c88ca0252	docs: Add notes about UEFI features Document that only UEFI booting is supported, the current status of Secure Boot, and that the shell and networking are disabled. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	9c63db4c9f	docs: Update Intel ME info Document the new CMOS option for enabling/disabling the IME. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	92a601fbb7	Add changelog entry Remove 2021-09-29 section, as the change was released in 2021-09-30. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	dbe7213ecf	Remove top-level README.md.in - The generated "Contents" section isn't useful - Non-standard, causing confusion on how to update README.md - It's already out of sync Remove galp3-c and darp5, as we never released the firmware due to issues with the touchpad and keyboard. Add gaze16-3060-b variant. Make "Schematics" a subsection of "Supported models". Remove directory from list of paths to update in `scripts/readmes.sh`. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	3e4688fcbc	Remove libs/smmstore Replace the stand-alone smmstore app in favor of the read example in firmware-smmstore. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	ffdceb5f0b	Update Rust toolchain to 2021-06-15 Update the toolchain to the version used by Redox. Update a lot of the submodules, which have been updated to build on the new toolchain. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	fa98ecae1f	edk2: Rebase on edk2-stable202108 Set options in edk2.config for each board. PCIE_BASE is no longer an edk2 option. The value is expected to be in AcpiBoardInfo HOB, generated from the bootloader's ACPI table. Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	af955613e0	models: Enable SMMSTOREv2 in coreboot Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
Tim Crawford	5b4dbd9c53	coreboot: Rebase on 4.15 Rebase on upstream coreboot/coreboot@5622666396. The is slightly ahead of the 4.15 tag, but includes all of our boards and most Intel SoC changes we need. We are now ~10 patches on top of upstream. The following boards have been upstreamed: - addw1 - addw2 - bonw14 - darp5 - darp6 - darp7 - galp2 - galp3-b - galp3-c - galp4 - galp5 - gaze14 - gaze15 - gaze16 - lemp10 - oryp5 - oryp6 - oryp7 - oryp8 The following drivers have been upstreamed: - tas5825m microcode: - TGL-U boards have been updated to rev 0x9a from private repo - TGL-H boards have been updated to rev 0x3c from private repo - Remaining boards changed to use blobs from public repo FSP: - TGL changed to use A.0.51.31 from public repo Signed-off-by: Tim Crawford <tcrawford@system76.com>	2021-12-21 13:11:09 -07:00
				`@@ -1 +0,0 @@`
				`../../../FSP/CometLakeFspBinPkg/CometLake1/Include`