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treewide: Unify Google branding

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Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).

This CL also includes changing Chromium OS to ChromiumOS as well.

BUG=None
TEST=N/A

Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Jon Murphy
2022-06-28 10:36:23 -06:00
committed by Felix Held
parent dc86804a7d
commit c4e90454f4
82 changed files with 126 additions and 126 deletions
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4
Documentation/acronyms.md
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@ -185,7 +185,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Unit**](http://en.wikipedia.org/wiki/Central_processing_unit) Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode * CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
* Cr50 - Google: The first generation Google Security Chip (GSC) used on * Cr50 - Google: The first generation Google Security Chip (GSC) used on
Chrome OS devices. ChromeOS devices.
* CRB - Customer Reference Board * CRB - Customer Reference Board
* CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
(End-of-Line) marker. (End-of-Line) marker.
@ -914,7 +914,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* TGL - Intel: Tigerlake * TGL - Intel: Tigerlake
* THC - Touch Host Controller * THC - Touch Host Controller
* Ti50 - Google: The next generation GSC (Google Security chip) on * Ti50 - Google: The next generation GSC (Google Security chip) on
Chrome OS devices after Cr50 ChromeOS devices after Cr50
* TLA - Techtronics Logic Analyzer * TLA - Techtronics Logic Analyzer
* TLA - Three Letter Acronym * TLA - Three Letter Acronym
* TLB - [**Translation Lookside * TLB - [**Translation Lookside

2
Documentation/lib/flashmap.md
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@ -4,7 +4,7 @@
[Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to [Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to
describe partitions in a flash chip. It was added to coreboot to support the describe partitions in a flash chip. It was added to coreboot to support the
requirements of Chromium OS firmware but then was also used in other scenarios requirements of ChromiumOS firmware but then was also used in other scenarios
where precise placement of data in flash was necessary, or for data that is where precise placement of data in flash was necessary, or for data that is
written to at runtime, as CBFS is considered too fragile for such situations. written to at runtime, as CBFS is considered too fragile for such situations.
The Flashmap implementation inside coreboot is the de facto standard today. The Flashmap implementation inside coreboot is the de facto standard today.

10
Documentation/lib/fw_config.md
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@ -8,8 +8,8 @@ BIOS image to be used across a wide variety of devices which may have key differ
otherwise similar enough to use the same coreboot build target. otherwise similar enough to use the same coreboot build target.
The initial implementation is designed to take advantage of a bitmask returned by the Embedded The initial implementation is designed to take advantage of a bitmask returned by the Embedded
Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
image across multiple devices by selecting various options at runtime. See the Chromium OS image across multiple devices by selecting various options at runtime. See the ChromiumOS
[Firmware Config][1] documentation for more information. [Firmware Config][1] documentation for more information.
This firmware configuration interface differs from the CMOS option interface in that this This firmware configuration interface differs from the CMOS option interface in that this
@ -91,7 +91,7 @@ file in CBFS use the value it contains when matching fields and options.
### Embedded Controller ### Embedded Controller
Google Chrome OS devices support an Embedded Controller interface for reading and writing the Google ChromeOS devices support an Embedded Controller interface for reading and writing the
firmware configuration value, along with other board-specific information. It is possible for firmware configuration value, along with other board-specific information. It is possible for
coreboot to read this value at boot on systems that support this feature. coreboot to read this value at boot on systems that support this feature.
@ -101,9 +101,9 @@ possible by enabling the CBFS source and coreboot will look in CBFS first for a
before asking the embedded controller. before asking the embedded controller.
It is also possible to adjust the value in the embedded controller *(after disabling write It is also possible to adjust the value in the embedded controller *(after disabling write
protection)* with the `ectool` command in a Chrome OS environment. protection)* with the `ectool` command in a ChromeOS environment.
For more information on the firmware configuration field on Chrome OS devices see the Chromium For more information on the firmware configuration field on ChromeOS devices see the Chromium
documentation for [Firmware Config][1] and [Board Info][2]. documentation for [Firmware Config][1] and [Board Info][2].
[1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md [1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md

2
Documentation/northbridge/intel/haswell/mrc.bin.md
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@ -3,7 +3,7 @@
All Haswell boards supported by coreboot currently require a proprietary All Haswell boards supported by coreboot currently require a proprietary
blob in order to initialise the DRAM and a few other components. The blob in order to initialise the DRAM and a few other components. The
blob, named `mrc.bin`, largely consists of Intel's memory reference code blob, named `mrc.bin`, largely consists of Intel's memory reference code
(MRC), but it has been tailored specifically for Chrome OS. It is just (MRC), but it has been tailored specifically for ChromeOS. It is just
under 200 KiB in size. Another name for `mrc.bin` is the system agent under 200 KiB in size. Another name for `mrc.bin` is the system agent
binary. binary.

2
Documentation/security/vboot/index.md
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@ -328,7 +328,7 @@ Google's Chromebooks have some special features:
### Developer Mode ### Developer Mode
Developer mode allows the user to use coreboot to boot another operating system. Developer mode allows the user to use coreboot to boot another operating system.
This may be a another (beta) version of Chrome OS, or another flavor of This may be a another (beta) version of ChromeOS, or another flavor of
GNU/Linux. Use of developer mode does not void the system warranty. Upon entry GNU/Linux. Use of developer mode does not void the system warranty. Upon entry
into developer mode, all locally saved data on the system is lost. into developer mode, all locally saved data on the system is lost.
This prevents someone from entering developer mode to subvert the system This prevents someone from entering developer mode to subvert the system

2
Documentation/soc/intel/cse_fw_update/cse_fw_update.md
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@ -8,7 +8,7 @@ power transition flows.
## Problem Statement ## Problem Statement
Currently, on Chromium OS Systems, CSE region is not updatable. So, new CSE FW Currently, on ChromiumOS Systems, CSE region is not updatable. So, new CSE FW
versions that are released by Intel to address important functional and security versions that are released by Intel to address important functional and security
bugs post-product launch will not be available to the end-user. Hence, the proposed bugs post-product launch will not be available to the end-user. Hence, the proposed
solution allows in-field CSE FW update to propagate those bug fixes solution allows in-field CSE FW update to propagate those bug fixes

16
Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md
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@ -3,7 +3,7 @@ Rebuilding coreboot image generation
Current situation Current situation
----------------- -----------------
Chrome OS (CrOS) probably has the most complex image bundling process in the ChromeOS (CrOS) probably has the most complex image bundling process in the
coreboot ecosystem. To make CrOS features more accessible to the wider coreboot ecosystem. To make CrOS features more accessible to the wider
coreboot community, we want to move these capabilities into upstream coreboot community, we want to move these capabilities into upstream
coreboot’s build system. coreboot’s build system.
@ -21,7 +21,7 @@ putting more data (eg. the bitmap data, keys) as raw data into other fmap
regions. regions.
With the recent addition of more files to CBFS, both on the coreboot side With the recent addition of more files to CBFS, both on the coreboot side
(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing (dsdt, FSP, and so on) and with ChromeOS specifics (eg. more files describing
boot screens) we either need to expand the scope of bundle\_firmware or move boot screens) we either need to expand the scope of bundle\_firmware or move
the capability to build complex images to upstream coreboot’s build system. the capability to build complex images to upstream coreboot’s build system.
This document proposes to do the latter and outlines how this could be This document proposes to do the latter and outlines how this could be
@ -41,14 +41,14 @@ images:
variable to guarantee success if there’s enough room for the files. While that variable to guarantee success if there’s enough room for the files. While that
could be added, that becomes more make macro work indistinguishable from magic could be added, that becomes more make macro work indistinguishable from magic
that people fail to understand, break and with good reason complain about that people fail to understand, break and with good reason complain about
to work around such issues, Chrome OS firmware uses a custom tool with even to work around such issues, ChromeOS firmware uses a custom tool with even
more special cases to finally build the image it needs. If coreboot upstream more special cases to finally build the image it needs. If coreboot upstream
is to support vboot, it should also be powerful enough not to need magic tools is to support vboot, it should also be powerful enough not to need magic tools
that only live within downstream projects. that only live within downstream projects.
Requirements Requirements
------------ ------------
A complete Chrome OS coreboot image consists of (depending on the device) A complete ChromeOS coreboot image consists of (depending on the device)
* platform specific data in raw fmap regions (eg IFD, ME firmware), * platform specific data in raw fmap regions (eg IFD, ME firmware),
* the bootblock (coming from the bootblock), * the bootblock (coming from the bootblock),
* three copies of coreboot, consisting of the stages (verstage, romstage, * three copies of coreboot, consisting of the stages (verstage, romstage,
@ -68,7 +68,7 @@ using a yet to be implemented switching scheme based on fmaps) consists of
* payload plus data (with each of the coreboot copies), * payload plus data (with each of the coreboot copies),
Since a single platform is potentially built with different payload Since a single platform is potentially built with different payload
configurations (eg. modding a Chromebook to not use the verified Chrome OS configurations (eg. modding a Chromebook to not use the verified ChromeOS
boot scheme), some concerns need to be kept separate: boot scheme), some concerns need to be kept separate:
* Platform requirements that have nothing to do with the payload or boot schemes * Platform requirements that have nothing to do with the payload or boot schemes
* IFD, ME, … need to copied to the right place * IFD, ME, … need to copied to the right place
@ -111,11 +111,11 @@ Boot method manifest
-------------------- --------------------
The boot method manifest can subdivide the BIOS region, eg. using it directly The boot method manifest can subdivide the BIOS region, eg. using it directly
(for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s (for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s
fallback/normal) or in many parts (for Chrome OS, which requires two CBFS fallback/normal) or in many parts (for ChromeOS, which requires two CBFS
regions, one for GBB, several for VPD, …). regions, one for GBB, several for VPD, …).
It also specifies which of the file lists specified earlier belong in which It also specifies which of the file lists specified earlier belong in which
region (eg. with verstage verifying romstage, verstage needs to be only in region (eg. with verstage verifying romstage, verstage needs to be only in
Chrome OS’ RO region, while romstage belongs in RO and both RW regions). ChromeOS’ RO region, while romstage belongs in RO and both RW regions).
It can also specify a post processing step that is executed before the It can also specify a post processing step that is executed before the
chipset’s. chipset’s.
@ -148,7 +148,7 @@ It specifies an IFD region, an ME, and the BIOS region. After the image is
built, the entire image needs to be processed (although the tool likely works built, the entire image needs to be processed (although the tool likely works
only on a small part of it) only on a small part of it)
It’s built in a Chrome OS-like configuration (simplified at places to avoid It’s built in a ChromeOS-like configuration (simplified at places to avoid
distracting from the important parts), so it has three CBFS regions, and distracting from the important parts), so it has three CBFS regions, and
several data regions for its own purpose (similar to GBB, FWID, VPD, …). After several data regions for its own purpose (similar to GBB, FWID, VPD, …). After
the regions are filled, one data region must be post-processed to contain the regions are filled, one data region must be post-processed to contain

4
Documentation/util.md
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@ -47,9 +47,9 @@ file `Python`
* _rmodtool_ - Creates rmodules `C` * _rmodtool_ - Creates rmodules `C`
* _ifwitool_ - For manipulating IFWI `C` * _ifwitool_ - For manipulating IFWI `C`
* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
* __chromeos__ - These scripts can be used to access Chrome OS * __chromeos__ - These scripts can be used to access ChromeOS
resources, for example to extract System Agent reference code and other resources, for example to extract System Agent reference code and other
blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
recovery image. `C` recovery image. `C`
* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
libc support) `Bash` libc support) `Bash`

2
Documentation/util/ifdtool/layout.md
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@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
+------------+------------------+-----------+-------------------------------------------+ +------------+------------------+-----------+-------------------------------------------+
| 4 | Platform Data | SI_PDR | | | 4 | Platform Data | SI_PDR | |
+------------+------------------+-----------+-------------------------------------------+ +------------+------------------+-----------+-------------------------------------------+
| 8 | EC Firmware | SI_EC | Most Chrome OS devices do not use this | | 8 | EC Firmware | SI_EC | Most ChromeOS devices do not use this |
| | | | region; EC firmware is stored in BIOS | | | | | region; EC firmware is stored in BIOS |
| | | | region of flash | | | | | region of flash |
+------------+------------------+-----------+-------------------------------------------+ +------------+------------------+-----------+-------------------------------------------+

16
LICENSES/retained-copyrights.txt
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@ -7,17 +7,17 @@ Copyright © 2012 Intel Corporation
Copyright 2012 Red Hat Inc. Copyright 2012 Red Hat Inc.
Copyright 2013 Google Inc. Copyright 2013 Google Inc.
Copyright 2014 Google Inc. Copyright 2014 Google Inc.
Copyright 2014 The Chromium OS Authors. All rights reserved. Copyright 2014 The ChromiumOS Authors. All rights reserved.
Copyright 2015 Google Inc. Copyright 2015 Google Inc.
Copyright 2015, Google Inc. Copyright 2015, Google Inc.
Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net> Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Copyright 2016 The Chromium OS Authors. All rights reserved. Copyright 2016 The ChromiumOS Authors. All rights reserved.
Copyright 2017-2019 Eltan B.V. Copyright 2017-2019 Eltan B.V.
Copyright 2017 Google Inc. Copyright 2017 Google Inc.
Copyright 2018 Generated Code Copyright 2018 Generated Code
Copyright 2018-present Facebook, Inc. Copyright 2018-present Facebook, Inc.
Copyright 2019 9Elements Agency GmbH <patrick.rudolph@9elements.com> Copyright 2019 9Elements Agency GmbH <patrick.rudolph@9elements.com>
Copyright 2019 The Chromium OS Authors. All rights reserved. Copyright 2019 The ChromiumOS Authors. All rights reserved.
Copyright (C) 2002 David S. Peterson. All rights reserved. Copyright (C) 2002 David S. Peterson. All rights reserved.
Copyright (c) 2003-2016 Cavium Inc. (support@cavium.com). All rights Copyright (c) 2003-2016 Cavium Inc. (support@cavium.com). All rights
Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights
@ -35,7 +35,7 @@ Copyright (c) 2010-2017, The Regents of the University of California
Copyright (c) 2010, Code Aurora Forum. All rights reserved. Copyright (c) 2010, Code Aurora Forum. All rights reserved.
Copyright (C) 2010 coresystems GmbH Copyright (C) 2010 coresystems GmbH
Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se> Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
Copyright (c) 2010 The Chromium OS Authors. All rights reserved. Copyright (c) 2010 The ChromiumOS Authors. All rights reserved.
Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. Copyright (c) 2011-2012 The Linux Foundation. All rights reserved.
Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
@ -52,14 +52,14 @@ Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc.
Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.* Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.*
Copyright (c) 2012, Code Aurora Forum. All rights reserved. Copyright (c) 2012, Code Aurora Forum. All rights reserved.
Copyright (c) 2012 The Chromium OS Authors. All rights reserved. Copyright (c) 2012 The ChromiumOS Authors. All rights reserved.
Copyright (c) 2012 The Linux Foundation. All rights reserved. Copyright (c) 2012 The Linux Foundation. All rights reserved.
Copyright (c) 2012 The Linux Foundation. All rights reserved.* Copyright (c) 2012 The Linux Foundation. All rights reserved.*
Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Copyright (c) 2013-2015 Intel Corporation. Copyright (c) 2013-2015 Intel Corporation.
Copyright (c) 2013-2017 Intel Corporation. Copyright (c) 2013-2017 Intel Corporation.
Copyright (C) 2013 Google Inc. Copyright (C) 2013 Google Inc.
Copyright (c) 2013 The Chromium OS Authors. All rights reserved. Copyright (c) 2013 The ChromiumOS Authors. All rights reserved.
Copyright (c) 2013 The Linux Foundation. All rights reserved. Copyright (c) 2013 The Linux Foundation. All rights reserved.
Copyright (c) 2013, The Regents of the University of California (Regents). Copyright (c) 2013, The Regents of the University of California (Regents).
Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
@ -69,14 +69,14 @@ Copyright (C) 2014 - 2016 The Linux Foundation. All rights reserved.
Copyright (c) 2014 Google Inc. Copyright (c) 2014 Google Inc.
Copyright (C) 2014 Google Inc. Copyright (C) 2014 Google Inc.
Copyright (c) 2014 Google Inc. All rights reserved. Copyright (c) 2014 Google Inc. All rights reserved.
Copyright (c) 2014 The Chromium OS Authors. All rights reserved. Copyright (c) 2014 The ChromiumOS Authors. All rights reserved.
Copyright (C) 2014 The Linux Foundation. All rights reserved. Copyright (C) 2014 The Linux Foundation. All rights reserved.
Copyright (C) 2015-2016 Intel Corporation. Copyright (C) 2015-2016 Intel Corporation.
Copyright (C) 2015-2016, Intel Corporation Copyright (C) 2015-2016, Intel Corporation
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
Copyright (C) 2015 Google Inc. Copyright (C) 2015 Google Inc.
Copyright (c) 2015, Intel Corporation. All rights reserved. Copyright (c) 2015, Intel Corporation. All rights reserved.
Copyright (c) 2015 The Chromium OS Authors. All rights reserved. Copyright (c) 2015 The ChromiumOS Authors. All rights reserved.
Copyright (C) 2015 The Linux Foundation. All rights reserved. Copyright (C) 2015 The Linux Foundation. All rights reserved.
Copyright (c) 2015, The Linux Foundation. All rights reserved. Copyright (c) 2015, The Linux Foundation. All rights reserved.
Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering

2
configs/config.google_meep_cros
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@ -7,7 +7,7 @@ CONFIG_SPI_FLASH_SMM=y
CONFIG_USE_BLOBS=y CONFIG_USE_BLOBS=y
CONFIG_ANY_TOOLCHAIN=y CONFIG_ANY_TOOLCHAIN=y
# Chrome OS # ChromeOS
CONFIG_CHROMEOS=y CONFIG_CHROMEOS=y
CONFIG_HAS_RECOVERY_MRC_CACHE=y CONFIG_HAS_RECOVERY_MRC_CACHE=y
CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y

4
payloads/libpayload/Kconfig
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@ -56,10 +56,10 @@ config DEVELOPER
libpayload developers. libpayload developers.
config CHROMEOS config CHROMEOS
bool "Chrome OS Options" bool "ChromeOS Options"
default n default n
help help
Select configuration defaults appropriate for Chrome OS boards. Select configuration defaults appropriate for ChromeOS boards.
choice choice
prompt "Compiler to use" prompt "Compiler to use"

2
payloads/libpayload/arch/x86/string.c
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@ -1,6 +1,6 @@
/* /*
* Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc. * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
* Copyright (c) 2011 The Chromium OS Authors. * Copyright (c) 2011 The ChromiumOS Authors.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as

2
payloads/libpayload/drivers/serial/ipq806x.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014 Chromium OS authors * Copyright (c) 2014 ChromiumOS authors
*/ */
#include <libpayload.h> #include <libpayload.h>

2
payloads/libpayload/include/endian.h
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@ -1,6 +1,6 @@
/* /*
* *
* Copyright (c) 2012 The Chromium OS Authors. * Copyright (c) 2012 The ChromiumOS Authors.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions

2
payloads/libpayload/include/ipchksum.h
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@ -1,6 +1,6 @@
/* /*
* *
* Copyright (c) 2012 The Chromium OS Authors. * Copyright (c) 2012 The ChromiumOS Authors.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions

2
src/acpi/dsdt_top.asl
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@ -3,7 +3,7 @@
#include <acpi/acpigen_extern.asl> #include <acpi/acpigen_extern.asl>
#if CONFIG(CHROMEOS_NVS) #if CONFIG(CHROMEOS_NVS)
/* Chrome OS specific */ /* ChromeOS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif

4
src/commonlib/bsd/include/commonlib/bsd/elog.h
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@ -203,7 +203,7 @@ struct elog_event_data_wake {
uint32_t instance; uint32_t instance;
} __packed; } __packed;
/* Chrome OS related events */ /* ChromeOS related events */
#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 #define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0
#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 #define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1
#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 #define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02
@ -305,7 +305,7 @@ struct elog_event_mem_cache_update {
#define ELOG_TYPE_MI_HRPC 0xb4 #define ELOG_TYPE_MI_HRPC 0xb4
#define ELOG_TYPE_MI_HR 0xb5 #define ELOG_TYPE_MI_HR 0xb5
/* Chrome OS diagnostics-related events */ /* ChromeOS diagnostics-related events */
#define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6 #define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6
#define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01 #define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01

10
src/commonlib/include/commonlib/timestamp_serialized.h
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@ -165,7 +165,7 @@ enum timestamp_id {
TS_KERNEL_START = 1101, TS_KERNEL_START = 1101,
TS_KERNEL_DECOMPRESSION = 1102, TS_KERNEL_DECOMPRESSION = 1102,
/* 1200-1300: Chrome OS Hypervisor */ /* 1200-1300: ChromeOS Hypervisor */
TS_CRHV_BOOT = 1200, TS_CRHV_BOOT = 1200,
TS_CRHV_PLATFORM_INIT = 1201, TS_CRHV_PLATFORM_INIT = 1201,
TS_CRHV_SERVICES_STARTED = 1202, TS_CRHV_SERVICES_STARTED = 1202,
@ -247,10 +247,10 @@ static const struct timestamp_id_to_name {
TS_NAME_DEF(TS_EC_HASH_READY, 0, "EC vboot hash ready"), TS_NAME_DEF(TS_EC_HASH_READY, 0, "EC vboot hash ready"),
TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, 0, "waiting for EC to allow higher power draw"), TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, 0, "waiting for EC to allow higher power draw"),
TS_NAME_DEF(TS_EC_SYNC_END, 0, "finished EC software sync"), TS_NAME_DEF(TS_EC_SYNC_END, 0, "finished EC software sync"),
TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load Chrome OS VPD"), TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load ChromeOS VPD"),
TS_NAME_DEF(TS_COPYVPD_RO_END, TS_COPYVPD_RW_END, TS_NAME_DEF(TS_COPYVPD_RO_END, TS_COPYVPD_RW_END,
"finished loading Chrome OS VPD (RO)"), "finished loading ChromeOS VPD (RO)"),
TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading Chrome OS VPD (RW)"), TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading ChromeOS VPD (RW)"),
TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END, TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END,
"started TPM enable update"), "started TPM enable update"),
TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"), TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"),
@ -344,7 +344,7 @@ static const struct timestamp_id_to_name {
TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"), TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"),
TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"), TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"),
/* Chrome OS hypervisor */ /* ChromeOS hypervisor */
TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"), TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"), TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),
TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"), TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"),

2
src/drivers/camera/Kconfig
View File

@ -2,6 +2,6 @@ config CHROMEOS_CAMERA
bool bool
default n default n
help help
Camera with identifiers following Chrome OS Camera Info. The info is Camera with identifiers following ChromeOS Camera Info. The info is
usually available on MIPI camera EEPROM for identifying correct usually available on MIPI camera EEPROM for identifying correct
drivers and config. drivers and config.

2
src/drivers/intel/fsp2_0/memory_init.c
View File

@ -42,7 +42,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
/* /*
* Save MRC Data to CBMEM. By always saving the data this forces * Save MRC Data to CBMEM. By always saving the data this forces
* a retrain after a trip through Chrome OS recovery path. The * a retrain after a trip through ChromeOS recovery path. The
* code which saves the data to flash doesn't write if the latest * code which saves the data to flash doesn't write if the latest
* training data matches this one. * training data matches this one.
*/ */

6
src/ec/google/chromeec/Kconfig
View File

@ -125,9 +125,9 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
config EC_GOOGLE_CHROMEEC_RTC config EC_GOOGLE_CHROMEEC_RTC
depends on EC_GOOGLE_CHROMEEC depends on EC_GOOGLE_CHROMEEC
bool "Enable Chrome OS EC RTC" bool "Enable ChromeOS EC RTC"
help help
Enable support for the real-time clock on the Chrome OS EC. This Enable support for the real-time clock on the ChromeOS EC. This
uses the EC_CMD_RTC_GET_VALUE command to read the current time. uses the EC_CMD_RTC_GET_VALUE command to read the current time.
choice choice
@ -194,7 +194,7 @@ config EC_GOOGLE_CHROMEEC_SWITCHES
depends on EC_GOOGLE_CHROMEEC && VBOOT depends on EC_GOOGLE_CHROMEEC && VBOOT
bool bool
help help
Enable support for Chrome OS mode switches provided by the Chrome OS Enable support for ChromeOS mode switches provided by the ChromeOS
EC. EC.
config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

2
src/ec/google/chromeec/acpi/superio.asl
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Chrome OS Embedded Controller interface * ChromeOS Embedded Controller interface
* *
* Constants that should be defined: * Constants that should be defined:
* *

4
src/ec/google/chromeec/ec_message.h
View File

@ -1,5 +1,5 @@
/* /*
* Chromium OS Matrix Keyboard Message Protocol definitions * ChromiumOS Matrix Keyboard Message Protocol definitions
*/ */
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
@ -9,7 +9,7 @@
/* /*
* Command interface between EC and AP, for LPC, I2C and SPI interfaces. * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
* *
* This is copied from the Chromium OS Open Source Embedded Controller code. * This is copied from the ChromiumOS Open Source Embedded Controller code.
*/ */
enum { enum {
/* The header byte, which follows the preamble */ /* The header byte, which follows the preamble */

2
src/mainboard/google/asurada/chromeos.fmd
View File

@ -1,4 +1,4 @@
# Firmware Layout Description for Chrome OS. # Firmware Layout Description for ChromeOS.
# #
# The size and address of every section must be aligned to at least 4K, except: # The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.

2
src/mainboard/google/brya/Kconfig
View File

@ -97,7 +97,7 @@ config CHROMEOS
select HAS_RECOVERY_MRC_CACHE select HAS_RECOVERY_MRC_CACHE
config CHROMEOS_WIFI_SAR config CHROMEOS_WIFI_SAR
bool "Enable SAR options for Chrome OS build" bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS depends on CHROMEOS
select DSAR_ENABLE select DSAR_ENABLE
select GEO_SAR_ENABLE select GEO_SAR_ENABLE

2
src/mainboard/google/brya/dsdt.asl
View File

@ -36,7 +36,7 @@ DefinitionBlock(
/* Chipset specific sleep states */ /* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/brya/variants/anahera/overridetree.cb
View File

@ -79,7 +79,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic chip drivers/gfx/generic
register "device_count" = "1" register "device_count" = "1"
register "device[0].name" = ""LCD"" register "device[0].name" = ""LCD""
# Use Chrome OS privacy screen _HID # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010"" register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip # Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400" register "device[0].addr" = "0x80010400"

2
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View File

@ -71,7 +71,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic chip drivers/gfx/generic
register "device_count" = "1" register "device_count" = "1"
register "device[0].name" = ""LCD"" register "device[0].name" = ""LCD""
# Use Chrome OS privacy screen _HID # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010"" register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip # Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400" register "device[0].addr" = "0x80010400"

2
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@ -570,7 +570,7 @@ chip soc/intel/alderlake
end end
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""GOOG0020"" register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS"" register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51. # HPS uses I2C addresses 0x30 and 0x51.

2
src/mainboard/google/brya/variants/brya4es/overridetree.cb
View File

@ -571,7 +571,7 @@ chip soc/intel/alderlake
end end
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""GOOG0020"" register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS"" register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51. # HPS uses I2C addresses 0x30 and 0x51.

2
src/mainboard/google/brya/variants/redrix/overridetree.cb
View File

@ -99,7 +99,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic chip drivers/gfx/generic
register "device_count" = "1" register "device_count" = "1"
register "device[0].name" = ""LCD"" register "device[0].name" = ""LCD""
# Use Chrome OS privacy screen _HID # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010"" register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip # Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400" register "device[0].addr" = "0x80010400"

2
src/mainboard/google/brya/variants/redrix4es/overridetree.cb
View File

@ -85,7 +85,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic chip drivers/gfx/generic
register "device_count" = "1" register "device_count" = "1"
register "device[0].name" = ""LCD"" register "device[0].name" = ""LCD""
# Use Chrome OS privacy screen _HID # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010"" register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip # Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400" register "device[0].addr" = "0x80010400"

2
src/mainboard/google/brya/variants/skolas4es/overridetree.cb
View File

@ -570,7 +570,7 @@ chip soc/intel/alderlake
end end
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""GOOG0020"" register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS"" register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51. # HPS uses I2C addresses 0x30 and 0x51.

2
src/mainboard/google/brya/variants/taeko/overridetree.cb
View File

@ -416,7 +416,7 @@ chip soc/intel/alderlake
device ref i2c2 on device ref i2c2 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""GOOG0020"" register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS"" register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51. # HPS uses I2C addresses 0x30 and 0x51.

2
src/mainboard/google/brya/variants/taeko4es/overridetree.cb
View File

@ -320,7 +320,7 @@ chip soc/intel/alderlake
device ref i2c2 on device ref i2c2 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""GOOG0020"" register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS"" register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51. # HPS uses I2C addresses 0x30 and 0x51.

2
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@ -94,7 +94,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic chip drivers/gfx/generic
register "device_count" = "1" register "device_count" = "1"
register "device[0].name" = ""LCD"" register "device[0].name" = ""LCD""
# Use Chrome OS privacy screen _HID # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010"" register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip # Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400" register "device[0].addr" = "0x80010400"

2
src/mainboard/google/cherry/chromeos.fmd
View File

@ -1,4 +1,4 @@
# Firmware Layout Description for Chrome OS. # Firmware Layout Description for ChromeOS.
# #
# The size and address of every section must be aligned to at least 4K, except: # The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.

2
src/mainboard/google/corsola/chromeos.fmd
View File

@ -1,4 +1,4 @@
# Firmware Layout Description for Chrome OS. # Firmware Layout Description for ChromeOS.
# #
# The size and address of every section must be aligned to at least 4K, except: # The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.

2
src/mainboard/google/dedede/Kconfig
View File

@ -65,7 +65,7 @@ config CHROMEOS
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
config CHROMEOS_WIFI_SAR config CHROMEOS_WIFI_SAR
bool "Enable SAR options for Chrome OS build" bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS depends on CHROMEOS
select DSAR_ENABLE select DSAR_ENABLE
select SAR_ENABLE select SAR_ENABLE

2
src/mainboard/google/dedede/dsdt.asl
View File

@ -37,7 +37,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/drallion/Kconfig
View File

@ -39,7 +39,7 @@ config CHROMEOS
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
config CHROMEOS_WIFI_SAR config CHROMEOS_WIFI_SAR
bool "Enable SAR options for Chrome OS build" bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS depends on CHROMEOS
select DSAR_ENABLE select DSAR_ENABLE
select GEO_SAR_ENABLE select GEO_SAR_ENABLE

2
src/mainboard/google/drallion/dsdt.asl
View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/eve/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/fizz/dsdt.asl
View File

@ -33,7 +33,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/guybrush/dsdt.asl
View File

@ -15,7 +15,7 @@ DefinitionBlock (
#include <acpi/dsdt_top.asl> #include <acpi/dsdt_top.asl>
#include <soc.asl> #include <soc.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
View File

@ -182,7 +182,7 @@ chip soc/amd/cezanne
chip drivers/gfx/generic chip drivers/gfx/generic
register "device_count" = "1" register "device_count" = "1"
register "device[0].name" = ""LCD"" register "device[0].name" = ""LCD""
# Use Chrome OS privacy screen _HID # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010"" register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip # Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400" register "device[0].addr" = "0x80010400"

2
src/mainboard/google/hatch/Kconfig
View File

@ -166,7 +166,7 @@ config CHROMEOS
select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
config CHROMEOS_WIFI_SAR config CHROMEOS_WIFI_SAR
bool "Enable SAR options for Chrome OS build" bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS depends on CHROMEOS
select DSAR_ENABLE select DSAR_ENABLE
select GEO_SAR_ENABLE select GEO_SAR_ENABLE

2
src/mainboard/google/hatch/dsdt.asl
View File

@ -35,7 +35,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/kahlee/dsdt.asl
View File

@ -52,7 +52,7 @@ DefinitionBlock (
/* Thermal handler */ /* Thermal handler */
#include <variant/acpi/thermal.asl> #include <variant/acpi/thermal.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/kukui/chromeos.fmd
View File

@ -1,4 +1,4 @@
# Firmware Layout Description for Chrome OS. # Firmware Layout Description for ChromeOS.
# #
# The size and address of every section must be aligned to at least 4K, except: # The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.

2
src/mainboard/google/octopus/dsdt.asl
View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/poppy/dsdt.asl
View File

@ -41,7 +41,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/reef/dsdt.asl
View File

@ -32,7 +32,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/sarien/dsdt.asl
View File

@ -34,7 +34,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
#if CONFIG(EC_GOOGLE_WILCO) #if CONFIG(EC_GOOGLE_WILCO)
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/skyrim/dsdt.asl
View File

@ -15,7 +15,7 @@ DefinitionBlock (
#include <acpi/dsdt_top.asl> #include <acpi/dsdt_top.asl>
#include <soc.asl> #include <soc.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/google/volteer/Kconfig
View File

@ -140,7 +140,7 @@ config VBOOT_GSCVD
default n default n
config CHROMEOS_WIFI_SAR config CHROMEOS_WIFI_SAR
bool "Enable SAR options for Chrome OS build" bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS depends on CHROMEOS
select DSAR_ENABLE select DSAR_ENABLE
select GEO_SAR_ENABLE select GEO_SAR_ENABLE

2
src/mainboard/google/volteer/dsdt.asl
View File

@ -36,7 +36,7 @@ DefinitionBlock(
#include "mainboard.asl" #include "mainboard.asl"
} }
// Chrome OS Embedded Controller // ChromeOS Embedded Controller
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
// ACPI code for EC SuperIO functions // ACPI code for EC SuperIO functions

2
src/mainboard/google/zork/dsdt.asl
View File

@ -44,7 +44,7 @@ DefinitionBlock (
/* Thermal handler */ /* Thermal handler */
#include <variant/acpi/thermal.asl> #include <variant/acpi/thermal.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/intel/adlrvp/dsdt.asl
View File

@ -28,7 +28,7 @@ DefinitionBlock(
} }
#if CONFIG(EC_GOOGLE_CHROMEEC) #if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/intel/glkrvp/dsdt.asl
View File

@ -31,7 +31,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/intel/icelake_rvp/dsdt.asl
View File

@ -31,7 +31,7 @@ DefinitionBlock(
} }
#if CONFIG(EC_GOOGLE_CHROMEEC) #if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/intel/jasperlake_rvp/dsdt.asl
View File

@ -31,7 +31,7 @@ DefinitionBlock(
} }
#if CONFIG(EC_GOOGLE_CHROMEEC) #if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

2
src/mainboard/intel/shadowmountain/dsdt.asl
View File

@ -30,7 +30,7 @@ DefinitionBlock(
} }
} }
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
// ACPI code for EC SuperIO functions // ACPI code for EC SuperIO functions

2
src/mainboard/intel/tglrvp/dsdt.asl
View File

@ -33,7 +33,7 @@ DefinitionBlock(
} }
#if CONFIG(EC_GOOGLE_CHROMEEC) #if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {
/* ACPI code for EC SuperIO functions */ /* ACPI code for EC SuperIO functions */

8
src/security/vboot/Kconfig
View File

@ -103,7 +103,7 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY
bool bool
default n default n
help help
When this option is enabled, the Chrome OS device leaves the When this option is enabled, the ChromeOS device leaves the
developer mode as soon as recovery request is detected. This is developer mode as soon as recovery request is detected. This is
handy on embedded devices with limited input capabilities. handy on embedded devices with limited input capabilities.
@ -321,10 +321,10 @@ config GBB_HWID
string "Hardware ID" string "Hardware ID"
default "" default ""
help help
A hardware identifier for device. On Chrome OS this is used for auto A hardware identifier for device. On ChromeOS this is used for auto
update and recovery, and will be generated when manufacturing by the update and recovery, and will be generated when manufacturing by the
factory software, in a strictly defined format. factory software, in a strictly defined format.
Leave empty to get a test-only Chrome OS HWID v2 string generated. Leave empty to get a test-only ChromeOS HWID v2 string generated.
config GBB_BMPFV_FILE config GBB_BMPFV_FILE
string "Path to bmpfv image" string "Path to bmpfv image"
@ -339,7 +339,7 @@ config GBB_FLAG_LOAD_OPTION_ROMS
default n default n
config GBB_FLAG_ENABLE_ALTERNATE_OS config GBB_FLAG_ENABLE_ALTERNATE_OS
bool "Allow booting a non-Chrome OS kernel if dev switch is on" bool "Allow booting a non-ChromeOS kernel if dev switch is on"
default n default n
config GBB_FLAG_FORCE_DEV_SWITCH_ON config GBB_FLAG_FORCE_DEV_SWITCH_ON

2
src/soc/amd/cezanne/Kconfig
View File

@ -434,7 +434,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7 select ARCH_VERSTAGE_ARMV7
help help
Runs verstage on the PSP. Only available on Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD. certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE config VBOOT_HASH_BLOCK_SIZE
hex hex

2
src/soc/amd/picasso/Kconfig
View File

@ -466,7 +466,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7 select ARCH_VERSTAGE_ARMV7
help help
Runs verstage on the PSP. Only available on Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD. certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE config VBOOT_HASH_BLOCK_SIZE
hex hex

2
src/soc/amd/sabrina/Kconfig
View File

@ -454,7 +454,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7 select ARCH_VERSTAGE_ARMV7
help help
Runs verstage on the PSP. Only available on Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD. certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE config VBOOT_HASH_BLOCK_SIZE
hex hex

2
src/soc/intel/common/block/include/intelblocks/cse.h
View File

@ -490,7 +490,7 @@ uint8_t cse_wait_com_soft_temp_disable(void);
/* /*
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
* CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
* boot from RW and triggers recovery mode if CSE fails to jump to RW. * boot from RW and triggers recovery mode if CSE fails to jump to RW.
* In software triggered recovery mode, the function allows CSE to boot from whatever is * In software triggered recovery mode, the function allows CSE to boot from whatever is
* currently selected partition. * currently selected partition.

2
src/soc/rockchip/rk3399/spi_bitbang.c
View File

@ -46,7 +46,7 @@ static void set_cs(const struct spi_bitbang_ops *ops, int value)
gpio_set(slave->cs, value); gpio_set(slave->cs, value);
} }
/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */ /* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */
static const struct rockchip_bitbang_slave slaves[] = { static const struct rockchip_bitbang_slave slaves[] = {
[0] = { [0] = {
.ops = { get_miso, set_mosi, set_clk, set_cs }, .ops = { get_miso, set_mosi, set_clk, set_cs },

2
src/vendorcode/google/chromeos/Kconfig
View File

@ -23,7 +23,7 @@ config CHROMEOS
if CHROMEOS if CHROMEOS
config CHROMEOS_RAMOOPS config CHROMEOS_RAMOOPS
bool "Reserve space for Chrome OS ramoops" bool "Reserve space for ChromeOS ramoops"
default y default y
config CHROMEOS_RAMOOPS_RAM_SIZE config CHROMEOS_RAMOOPS_RAM_SIZE

2
src/vendorcode/google/chromeos/acpi/amac.asl
View File

@ -11,7 +11,7 @@
* The Linux kernel implementation can be found at * The Linux kernel implementation can be found at
* drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read() * drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read()
* *
* For Chrome OS, the policy which controls where the dock MAC address * For ChromeOS, the policy which controls where the dock MAC address
* comes from is written into RW_VPD property "dock_passthrough": * comes from is written into RW_VPD property "dock_passthrough":
* *
* "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac" * "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac"

2
src/vendorcode/google/chromeos/chromeos.h
View File

@ -38,7 +38,7 @@ void chromeos_set_ramoops(void *ram_oops, size_t size);
enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value); enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value);
/* /*
* Declaration for mainboards to use to generate ACPI-specific Chrome OS needs. * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.
*/ */
void chromeos_acpi_gpio_generate(void); void chromeos_acpi_gpio_generate(void);

4
util/README.md
View File

@ -36,9 +36,9 @@ file `Python`
* _rmodtool_ - Creates rmodules `C` * _rmodtool_ - Creates rmodules `C`
* _ifwitool_ - For manipulating IFWI `C` * _ifwitool_ - For manipulating IFWI `C`
* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
* __chromeos__ - These scripts can be used to access Chrome OS * __chromeos__ - These scripts can be used to access ChromeOS
resources, for example to extract System Agent reference code and other resources, for example to extract System Agent reference code and other
blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
recovery image. `C` recovery image. `C`
* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
libc support) `Bash` libc support) `Bash`

8
util/abuild/abuild
View File

@ -426,7 +426,7 @@ function build_config
export HOSTCC='gcc' export HOSTCC='gcc'
if [ "$chromeos" = true ] && [ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS\>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]; then if [ "$chromeos" = true ] && [ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS\>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]; then
echo "${BUILD_NAME} doesn't support Chrome OS, skipping." echo "${BUILD_NAME} doesn't support ChromeOS, skipping."
return return
fi fi
@ -450,7 +450,7 @@ function build_config
# Skip this rule for configs created from templates that already # Skip this rule for configs created from templates that already
# come with CHROMEOS enabled. # come with CHROMEOS enabled.
grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \ grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \
check_config "$build_dir" "Chrome OS" "CONFIG_CHROMEOS=y" negate check_config "$build_dir" "ChromeOS" "CONFIG_CHROMEOS=y" negate
local FORCE_ENABLED_CROS=$? local FORCE_ENABLED_CROS=$?
else else
local FORCE_ENABLED_CROS=0 local FORCE_ENABLED_CROS=0
@ -611,7 +611,7 @@ Options:\n"
[-u|--update] Update existing image [-u|--update] Update existing image
[-v|--verbose] Print more messages [-v|--verbose] Print more messages
[-x|--chromeos] Build with CHROMEOS enabled [-x|--chromeos] Build with CHROMEOS enabled
Skip boards without Chrome OS support Skip boards without ChromeOS support
[-X|--xmlfile <name>] Set JUnit XML log file filename [-X|--xmlfile <name>] Set JUnit XML log file filename
(defaults to $XMLFILE) (defaults to $XMLFILE)
[-y|--ccache] Use ccache [-y|--ccache] Use ccache
@ -765,7 +765,7 @@ while true ; do
-x|--chromeos) shift -x|--chromeos) shift
chromeos=true chromeos=true
testclass=chromeos testclass=chromeos
customizing="${customizing}, chrome os" customizing="${customizing}, chromeos"
configoptions="${configoptions}CONFIG_CHROMEOS=y\nCONFIG_VBOOT_MEASURED_BOOT=y\n" configoptions="${configoptions}CONFIG_CHROMEOS=y\nCONFIG_VBOOT_MEASURED_BOOT=y\n"
;; ;;
-X|--xmlfile) shift; XMLFILE=$1; REAL_XMLFILE=$1; shift;; -X|--xmlfile) shift; XMLFILE=$1; REAL_XMLFILE=$1; shift;;

4
util/cbfstool/eventlog.c
View File

@ -141,8 +141,8 @@ static void eventlog_print_type(const struct event_header *event)
{ELOG_TYPE_S0IX_ENTER, "S0ix Enter"}, {ELOG_TYPE_S0IX_ENTER, "S0ix Enter"},
{ELOG_TYPE_S0IX_EXIT, "S0ix Exit"}, {ELOG_TYPE_S0IX_EXIT, "S0ix Exit"},
{ELOG_TYPE_WAKE_SOURCE, "Wake Source"}, {ELOG_TYPE_WAKE_SOURCE, "Wake Source"},
{ELOG_TYPE_CROS_DEVELOPER_MODE, "Chrome OS Developer Mode"}, {ELOG_TYPE_CROS_DEVELOPER_MODE, "ChromeOS Developer Mode"},
{ELOG_TYPE_CROS_RECOVERY_MODE, "Chrome OS Recovery Mode"}, {ELOG_TYPE_CROS_RECOVERY_MODE, "ChromeOS Recovery Mode"},
{ELOG_TYPE_MANAGEMENT_ENGINE, "Management Engine"}, {ELOG_TYPE_MANAGEMENT_ENGINE, "Management Engine"},
{ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Management Engine Extra"}, {ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Management Engine Extra"},
{ELOG_TYPE_LAST_POST_CODE, "Last post code in previous boot"}, {ELOG_TYPE_LAST_POST_CODE, "Last post code in previous boot"},

2
util/cbfstool/flashrom.c
View File

@ -1,4 +1,4 @@
/* Copyright 2020 The Chromium OS Authors. All rights reserved. /* Copyright 2020 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be * Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file. * found in the LICENSE file.
*/ */

2
util/cbfstool/flashrom.h
View File

@ -1,4 +1,4 @@
/* Copyright 2020 The Chromium OS Authors. All rights reserved. /* Copyright 2020 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be * Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file. * found in the LICENSE file.
* *

14
util/chromeos/README.md
View File

@ -1,16 +1,16 @@
# Chrome OS Scripts # ChromeOS Scripts
These scripts can be used to access or generate Chrome OS resources, for example These scripts can be used to access or generate ChromeOS resources, for example
to extract System Agent reference code and other blobs (e.g. `mrc.bin`, refcode, to extract System Agent reference code and other blobs (e.g. `mrc.bin`, refcode,
VGA option roms) from a Chrome OS recovery image. VGA option roms) from a ChromeOS recovery image.
## crosfirmware.sh ## crosfirmware.sh
`crosfirmware.sh` downloads a Chrome OS recovery image from the recovery `crosfirmware.sh` downloads a ChromeOS recovery image from the recovery
image server, unpacks it, extracts the firmware update shell archive, image server, unpacks it, extracts the firmware update shell archive,
extracts the firmware images from the shell archive. extracts the firmware images from the shell archive.
To download all Chrome OS firmware images, run To download all ChromeOS firmware images, run
$ ./crosfirmware.sh $ ./crosfirmware.sh
@ -21,14 +21,14 @@ To download, e.g. the Panther firmware image, run
## extract_blobs.sh ## extract_blobs.sh
`extract_blobs.sh` extracts the blobs from a Chrome OS firmware image. `extract_blobs.sh` extracts the blobs from a ChromeOS firmware image.
Right now it will produce the ME firmware blob, IFD, VGA option rom, Right now it will produce the ME firmware blob, IFD, VGA option rom,
and `mrc.bin`. and `mrc.bin`.
## gen_test_hwid.sh ## gen_test_hwid.sh
`gen_test_hwid.sh` generates a test-only identifier in Chrome OS HWID v2 `gen_test_hwid.sh` generates a test-only identifier in ChromeOS HWID v2
compatible format. compatible format.
Usage: Usage:

4
util/chromeos/description.md
View File

@ -1,3 +1,3 @@
These scripts can be used to access Chrome OS resources, for example to extract These scripts can be used to access ChromeOS resources, for example to extract
System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option
roms) from a Chrome OS recovery image. `C` roms) from a ChromeOS recovery image. `C`

2
util/chromeos/gen_test_hwid.sh
View File

@ -8,7 +8,7 @@ main() {
exit 1 exit 1
fi fi
# Generate a test-only Chrome OS HWID v2 string # Generate a test-only ChromeOS HWID v2 string
local board="$1" local board="$1"
local prefix="$(echo "${board}" | tr a-z A-Z) TEST" local prefix="$(echo "${board}" | tr a-z A-Z) TEST"
# gzip has second-to-last 4 bytes in CRC32. # gzip has second-to-last 4 bytes in CRC32.