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AGESA f14: Drop PlatformGnbPcieComplex.h

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These were OEM configurations hidden inside a header file, notation
was already dropped for f15tb and f16kb.

Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Kyösti Mälkki
2017-09-23 19:12:38 +03:00
parent 57760e3cdf
commit c700829cd3
22 changed files with 101 additions and 828 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/amd/inagua/OemCustomize.c
View File

@@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "PlatformGnbPcieComplex.h"
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -24,25 +23,25 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

59
src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
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@@ -1,59 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

11
src/mainboard/amd/persimmon/OemCustomize.c
View File

@@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "PlatformGnbPcieComplex.h"
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -25,31 +24,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

60
src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
View File

@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

11
src/mainboard/amd/south_station/OemCustomize.c
View File

@@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "PlatformGnbPcieComplex.h"
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -24,31 +23,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

60
src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
View File

@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

61
src/mainboard/amd/union_station/OemCustomize.c
View File

@@ -15,42 +15,41 @@
#include "AGESA.h" #include "AGESA.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include <string.h> #include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };
static const PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {

60
src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
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@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

5
src/mainboard/asrock/e350m1/OemCustomize.c
View File

@@ -15,7 +15,6 @@
#include "AGESA.h" #include "AGESA.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -24,13 +23,13 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

60
src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
View File

@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

11
src/mainboard/elmex/pcm205400/OemCustomize.c
View File

@@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "PlatformGnbPcieComplex.h"
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -24,31 +23,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

100
src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h
View File

@@ -1,100 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
/*
* GNB GPP Port4
* GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable
* GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
* GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
* GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
* 2:Half-swing(0db) 3:Half-swing(-3.5db)
* 4:extended length(-6db) 5:extended length(-8db)
* GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
*/
#define GNB_GPP_PORT4_PORT_PRESENT 1
#define GNB_GPP_PORT4_SPEED_MODE 2
#define GNB_GPP_PORT4_LINK_ASPM 3
#define GNB_GPP_PORT4_CHANNEL_TYPE 4
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
/*
* GNB GPP Port5
* GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable
* GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
* GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
* GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
* 2:Half-swing(0db) 3:Half-swing(-3.5db)
* 4:extended length(-6db) 5:extended length(-8db)
* GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
*/
#define GNB_GPP_PORT5_PORT_PRESENT 0
#define GNB_GPP_PORT5_SPEED_MODE 2
#define GNB_GPP_PORT5_LINK_ASPM 3
#define GNB_GPP_PORT5_CHANNEL_TYPE 4
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
/*
* GNB GPP Port6
* GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable
* GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
* GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
* GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
* 2:Half-swing(0db) 3:Half-swing(-3.5db)
* 4:extended length(-6db) 5:extended length(-8db)
* GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
*/
#define GNB_GPP_PORT6_PORT_PRESENT 0
#define GNB_GPP_PORT6_SPEED_MODE 2
#define GNB_GPP_PORT6_LINK_ASPM 3
#define GNB_GPP_PORT6_CHANNEL_TYPE 4
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
/*
* GNB GPP Port7
* GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable
* GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
* GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
* GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
* 2:Half-swing(0db) 3:Half-swing(-3.5db)
* 4:extended length(-6db) 5:extended length(-8db)
* GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
*/
#define GNB_GPP_PORT7_PORT_PRESENT 0
#define GNB_GPP_PORT7_SPEED_MODE 2
#define GNB_GPP_PORT7_LINK_ASPM 3
#define GNB_GPP_PORT7_CHANNEL_TYPE 4
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
/*
* GNB GPP Port8
* GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable
* GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
* GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
* GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
* 2:Half-swing(0db) 3:Half-swing(-3.5db)
* 4:extended length(-6db) 5:extended length(-8db)
* GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
*/
#define GNB_GPP_PORT8_PORT_PRESENT 1
#define GNB_GPP_PORT8_SPEED_MODE 2
#define GNB_GPP_PORT8_LINK_ASPM 3
#define GNB_GPP_PORT8_CHANNEL_TYPE 4
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

11
src/mainboard/gizmosphere/gizmo/OemCustomize.c
View File

@@ -16,7 +16,6 @@
#include "AGESA.h" #include "AGESA.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -25,31 +24,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

61
src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h
View File

@@ -1,61 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

61
src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
View File

@@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "PlatformGnbPcieComplex.h"
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -25,65 +24,65 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(PortEnabled,
GNB_GPP_PORT4_CHANNEL_TYPE, ChannelTypeExt6db,
4, 4,
GNB_GPP_PORT4_HOTPLUG_SUPPORT, HotplugDisabled,
GNB_GPP_PORT4_SPEED_MODE, PcieGen2,
GNB_GPP_PORT4_SPEED_MODE, PcieGen2,
GNB_GPP_PORT4_LINK_ASPM, AspmL0sL1,
46) 46)
}, },
/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(PortEnabled,
GNB_GPP_PORT5_CHANNEL_TYPE, ChannelTypeExt6db,
5, 5,
GNB_GPP_PORT5_HOTPLUG_SUPPORT, HotplugDisabled,
GNB_GPP_PORT5_SPEED_MODE, PcieGen2,
GNB_GPP_PORT5_SPEED_MODE, PcieGen2,
GNB_GPP_PORT5_LINK_ASPM, AspmL0sL1,
46) 46)
}, },
/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(PortEnabled,
GNB_GPP_PORT6_CHANNEL_TYPE, ChannelTypeExt6db,
6, 6,
GNB_GPP_PORT6_HOTPLUG_SUPPORT, HotplugDisabled,
GNB_GPP_PORT6_SPEED_MODE, PcieGen2,
GNB_GPP_PORT6_SPEED_MODE, PcieGen2,
GNB_GPP_PORT6_LINK_ASPM, AspmL0sL1,
46) 46)
}, },
/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(PortDisabled,
GNB_GPP_PORT7_CHANNEL_TYPE, ChannelTypeExt6db,
7, 7,
GNB_GPP_PORT7_HOTPLUG_SUPPORT, HotplugDisabled,
GNB_GPP_PORT7_SPEED_MODE, PcieGen2,
GNB_GPP_PORT7_SPEED_MODE, PcieGen2,
GNB_GPP_PORT7_LINK_ASPM, AspmL0sL1,
0) 0)
}, },
/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, PCIE_PORT_DATA_INITIALIZER(PortEnabled,
GNB_GPP_PORT8_CHANNEL_TYPE, ChannelTypeExt6db,
8, 8,
GNB_GPP_PORT8_HOTPLUG_SUPPORT, HotplugDisabled,
GNB_GPP_PORT8_SPEED_MODE, PcieGen2,
GNB_GPP_PORT8_SPEED_MODE, PcieGen2,
GNB_GPP_PORT8_LINK_ASPM, AspmL0sL1,
0) 0)
} }
}; };

75
src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
View File

@@ -1,75 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
/**
* @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
*
* GNB_GPP_PORT?_PORT_PRESENT
* 0:Disable 1:Enable
*
* GNB_GPP_PORT?_SPEED_MODE
* 0:Auto 1:GEN1 2:GEN2
*
* GNB_GPP_PORT?_LINK_ASPM
* 0:Disable 1:L0s 2:L1 3:L0s+L1
*
* GNB_GPP_PORT?_CHANNEL_TYPE -
* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
*
* GNB_GPP_PORT?_HOTPLUG_SUPPORT
* 0:Disable 1:Basic 3:Enhanced
*/
/* GNB GPP 4 */
#define GNB_GPP_PORT4_PORT_PRESENT 1
#define GNB_GPP_PORT4_SPEED_MODE 2
#define GNB_GPP_PORT4_LINK_ASPM 3
#define GNB_GPP_PORT4_CHANNEL_TYPE 4
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
/* GNB GPP 5 */
#define GNB_GPP_PORT5_PORT_PRESENT 1
#define GNB_GPP_PORT5_SPEED_MODE 2
#define GNB_GPP_PORT5_LINK_ASPM 3
#define GNB_GPP_PORT5_CHANNEL_TYPE 4
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
/* GNB GPP 6 */
#define GNB_GPP_PORT6_PORT_PRESENT 1
#define GNB_GPP_PORT6_SPEED_MODE 2
#define GNB_GPP_PORT6_LINK_ASPM 3
#define GNB_GPP_PORT6_CHANNEL_TYPE 4
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
/* GNB GPP 7 */
#define GNB_GPP_PORT7_PORT_PRESENT 0
#define GNB_GPP_PORT7_SPEED_MODE 2
#define GNB_GPP_PORT7_LINK_ASPM 3
#define GNB_GPP_PORT7_CHANNEL_TYPE 4
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
/* GNB GPP 8 */
#define GNB_GPP_PORT8_PORT_PRESENT 1
#define GNB_GPP_PORT8_SPEED_MODE 2
#define GNB_GPP_PORT8_LINK_ASPM 3
#define GNB_GPP_PORT8_CHANNEL_TYPE 4
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */

11
src/mainboard/lippert/frontrunner-af/OemCustomize.c
View File

@@ -15,7 +15,6 @@
#include "AGESA.h" #include "AGESA.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -24,31 +23,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

60
src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h
View File

@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 0 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 0 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

11
src/mainboard/lippert/toucan-af/OemCustomize.c
View File

@@ -15,7 +15,6 @@
#include "AGESA.h" #include "AGESA.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -24,31 +23,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

60
src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h
View File

@@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

11
src/mainboard/pcengines/apu1/OemCustomize.c
View File

@@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "PlatformGnbPcieComplex.h"
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@@ -25,31 +24,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
} }
}; };

61
src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h
View File

@@ -1,61 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H