22 Commits

Author SHA1 Message Date
Nicholas Chin
cf2bf984f0 Docs: Fix broken header references
MyST Parser automatically generates label "slugs" for headers which
should be used to reference them from links [1]. These labels are in
"slug-case", i.e. the original header text in lower case separated by
dashes, with punctuation removed. This fixes a few "cross-reference
target not found" warnings.

[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#anchor-slug-structure

Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-21 16:18:23 +00:00
Nicholas Chin
35599f9a66 Docs: Replace Recommonmark with MyST Parser
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.

For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:

* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)

MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:

```{toctree}
:maxdepth: 1

Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```

Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.

The toctrees were converted to the MyST syntax using the following
command and Python script:

`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`

```
import re
import sys

in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()

with open(sys.argv[1], "w") as f:
    for line in lines:
        match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
        if match is not None:
            if not in_list:
                in_list = True
                f.write("```{toctree}\n")
                f.write(":maxdepth: 1\n\n")
            f.write(match.group(1) + " <" + match.group(2) + ">\n")
        else:
            if in_list:
                f.write("```\n")
            f.write(line)
            in_list = False

    if in_list:
        f.write("```\n")
```

While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.

This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.

Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.

These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`

Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.

From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.

TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.

[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html

Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 16:11:56 +00:00
Jon Murphy
c4e90454f4 treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).

This CL also includes changing Chromium OS to ChromiumOS as well.

BUG=None
TEST=N/A

Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04 14:02:26 +00:00
Martin Roth
bbe876250f Documentation: Fix a few spelling issues
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I47add663f3021170b840203ce229acf836b7a1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:24:57 +00:00
Felix Singer
d55fa332d8 Documentation: Move firmware flashing tutorial to tutorial section
There is no need that the tutorial for flashing firmware has its own
point in the main menu. Thus, move it to the tutorial section.

Change-Id: Ife6d97254af4c006fe01480a78c76303f9cb34bb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
2022-03-11 19:56:22 +00:00
Martin Roth
6c3ece9c9e Documentation: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:06:24 +00:00
Patrick Rudolph
ad82106eb9 Documentation: Mark ECC as working on Sandy Bridge
Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-16 14:46:13 +00:00
Angel Pons
918e5352b7 Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-12 08:01:00 +00:00
Patrick Rudolph
0751d7bded Documentation: Add tutorial for me_cleaner on Lenovo devices
Add a tutorial how to use ME cleaner, and give some basic steps to
strip the ME. Update the Lenovo Sandy Bridge documentation that no
issues could be observed on X220 and give an example flash layout.

Tested on Lenovo X220 with stripped ME and found no issues:
commit: cbc5b99ac9e5856631109b1e7f20e80799beb1e4

* Displayport
* VGA
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* Battery events
* CPU temperature reporting
* FAN managment
* Stress test stable
  * Youtube videos over Wifi
  * stress -c 2 -m 1 -d 1
  * glxgears

Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 11:39:05 +00:00
Patrick Rudolph
edbcd057e6 Documentation: Warn about ME cleaner on Sandy Bridge
Document known issues with 'disabled' ME.

Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32889
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:01:12 +00:00
Daniel Maslowski
e7168edeb8 Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e
Signed-off-by: Daniel Maslowski <dan@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-28 00:17:14 +00:00
Tristan Corrick
a6fe456cb5 Doc/nb/intel/haswell: Add a list of known issues
Change-Id: If0339831550f6c70e8056f78633e9a402f35a793
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30455
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03 20:07:41 +00:00
Tristan Corrick
1ccf83c971 Doc/nb/intel/haswell: Mention util/chromeos as a way to get mrc.bin
Change-Id: Ic099d0f052db5ef6a699d54b26028bae2fae4770
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-03 16:52:13 +00:00
Tristan Corrick
cbc561f64a Documentation/nb/intel: Add Haswell documentation
At the moment, this just gives some details on the MRC.

Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-24 08:16:06 +00:00
Jonathan Neuschäfer
2fd4907a4d Documentation: Spell "blob" in lowercase
It's not an acronym (outside of database software).

Change-Id: I529561e4fc9889be7f9d6bd6d5f9a876e2007671
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 09:39:32 +00:00
Tom Hiller
3a7e7c1998 Documentation: fix sphinx warnings
Fix warning from list in table cells for nri_registers.md

Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-21 14:08:47 +00:00
Jonathan Neuschäfer
d91b5cf5c9 Documentation/mb/intel/sandybridge/nri: Change column name to "Comments"
This column doesn't really contain a description, but additional
comments.

Change-Id: I714972ee336bc1f8a4feb75292ee9efa583f0bb1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-16 13:04:41 +00:00
Angel Pons
8120759d90 Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake
According to a comment on fa1a07b, the 100MHz clock is the Ivy Bridge
only clock, not the 133MHz one.

Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28377
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30 14:47:41 +00:00
Tom Hiller
993869e3fc Documentation: Fix formatting
Fix formatting and missing close block quotes in nri_registers.md

Change-Id: I5fa0136f4d7f05737a0d53ff9da7d2c77b22d675
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-27 16:53:06 +00:00
Angel Pons
fa1a07bf50 Documentation/northbridge/intel/sandybridge/*: fix typos
Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in
text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy
Bridge".

Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-22 07:03:13 +00:00
Patrick Rudolph
0d42a2c421 Documentation: Add SandyBridge NRI feature matrix
Change-Id: I69b014430802de132c8d9b6c8409bc762b995468
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27093
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15 09:15:20 +00:00
Philipp Deppenwiese
438b463a8f Documentation: Update index.md and move files
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files

Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30 09:14:48 +00:00