Commit Graph

57382 Commits

Author SHA1 Message Date
Sergii Dmytruk
1a8b9c20f8 drivers/efi: add optional ESRT-friendly coreboot table tag
EFI System Resource Table (ESRT) is an informational structure that
reports basic details about current system or device firmware.  This is
chiefly used to perform firmware updates.

New CONFIG_DRIVERS_EFI_FW_INFO is off by default, enabling it adds
DRIVERS_EFI_FW_{GUID,VERSION,LSV} to be used to specify firmware
version/update information.

Existing forms of versions wouldn't be sufficient because there is no
universal way of converting string versions to 32-bit unsigned integers
and there are no GUIDs or lowest supported versions.

Change-Id: Ic1b768d7bed43edf7ca8e41552087734054de033
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83421
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19 14:30:20 +00:00
Maximilian Brune
2355aa7d3b util/cbfstool/cbfs-payload-linux: Do not compress bzImage
Compressing the already compressed bzImage does not yield any
fruit. If you are lucky it actually makes the image a little bit
smaller. If you are unlucky the image actually gets bigger and since the
compressing function is not checked for any errors, coreboot just builds
successfully even though the payload is broken through compression.

Before this patch you could possibly get this error during compilation:
```
E: LZMA: LzmaEnc_Encode failed 9.
```
and your linux payload would end up something like this in CBFS:
```
FMAP REGION: COREBOOT
Name                           Offset     Type           Size   Comp
....
fallback/payload               0x1c9c0    simple elf        511 none
....
```

That doesn't stop coreboot from finishing the build though, since we
currently don't check for errors from the compression. That is an issue
for another patch though.

Tested:
Build and run QEMU-Q35 with Linux bzImage as payload.

Change-Id: I022982667515ce721d98af534414d9e336b5f35a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83615
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19 14:10:21 +00:00
Morris Hsu
5d661b81ae mb/google/brox/jubilant: Update fw_config
Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting.

BUG=None
TEST=emerge-brox coreboot
Set STORAGE_UNKNOWN  on jubilant, check that NVMe and UFS can boot.

Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83935
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
2024-08-19 13:26:30 +00:00
Wei Hualin
d9a625e052 mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHz
Before:
I2C2 - 431KHz
I2C4 - 413KHz

After:
I2C2 - 364KHz
I2C4 - 370KHz

BUG=b:351968527
TEST=Rate of the actual measured machine is pass.

Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83906
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-08-19 13:25:40 +00:00
Kenneth Chan
5137e1e199 mb/google/brya/var/nova: Set up soundbar-related GPIOs
Set up soundbar-related GPIOs for updating.

BUG=b:358435383
TEST=emerge-constitution coreboot chromeos-bootimage

Change-Id: I517da8de90487533e49e46649c5acf4ccfcc5160
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19 13:25:30 +00:00
Julius Werner
f9ab107d32 commonlib/bsd: Optimize strnlen()
This patch changes the strnlen() implementation to fix a small issue
where we would dereference once more byte than intended when not finding
a NUL-byte within the specified amount of characters. It also changes
the implementation to rely on a pre-calculated end pointer rather than a
running counter, since this seems to lead to slightly better assembly
(one less instruction in the inner loop) on most architectures.

Change-Id: Ic36768fd3a26e2b64143904e78cd0b52ba66898d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-19 13:25:05 +00:00
Roger Wang
82c0dd2909 mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
This patch removes WWAN configuration from the bootblock.
It appears that setting it up in the bootblock may not be necessary.
Configure in bootblock,the seq will be triggered at the same time.
The customer would like us to leave some buffer for EN to RST.

BUG=b:357764679
TEST=Build and verified test result by EE team

Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83792
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19 13:22:28 +00:00
Nigel Tao
efad423f84 lib/jpeg: avoid calling malloc and free
Since commit 1d029b40c9 ("lib/jpeg: Replace decoder with Wuffs'
implementation"), a relatively large heap allocation is needed to decode
many JPEGs for use as work area. The prior decoder did not need this,
but also had many limitations in the JPEGs it could decode, was not as
memory-safe and quickly crashed under fuzzing.

This commit keeps using Wuffs' JPEG decoder, but it no longer requires
any heap allocation (and thus configuring the heap size depending on how
big a bootsplash image you want to support).

Change-Id: Ie4c52520cbce498539517c4898ff765365a6beba
Signed-off-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-08-19 12:32:21 +00:00
Nigel Tao
b598d05d38 vc/wuffs: upgrade to Wuffs 0.4.0-alpha.8
We were previously at Wuffs 0.4.0-alpha.2. The C file was copied from
https://github.com/google/wuffs-mirror-release-c and its hash matches
90e4d81a6a/sync.txt (L9-L10)

$ sha256sum src/vendorcode/wuffs/wuffs-v0.4.c
6c22caff4af929112601379a73f72461bc4719a5215366bcc90d599cbc442bb6  src/vendorcode/wuffs/wuffs-v0.4.c

Change-Id: Ie90d989384e0db2b23d7d1b3d9a57920ac8a95a2
Signed-off-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83894
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19 12:31:50 +00:00
Julia Kittlinger
957b6982f6 mb/acer/g43t-am3: Add Acer Q45T-AM as a variant
This adds a new board as a variant of the Acer G43T-AM3 with the
following prominent changes:

* Intel Q45 northbridge (GMCH) instead of a G43
* 4 MiB of flash instead of 2 MiB
* Two serial ports (one external, one internal)
* A parallel port connector (internal)
* An FDD connector
* DVI-D instead of HDMI
* No Firewire

The port was done based on logs and info received via private email. It
was only tested on the Acer G43T-AM3 so far, which still builds and works.

Change-Id: Ic2654ca4b198bfea409992be14e89702cf67ea50
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-18 10:55:38 +00:00
Michael Büchler
26b1a5f62b mb/acer/g43t-am3: Rework mainboard for variant mechanism
In preparation for CB:83968, rework the configuration files and move
files specific to G43T-AM3 to its own variant directory.

Change-Id: I425852f4bdacf7cb6688a5fb845ac3001373262e
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57764
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-18 10:55:22 +00:00
Subrata Banik
86ff4d12f1 mb/google/brya: Reset XHCI controller while preparing for S5
This patch calls `xhci_host_reset()` function to perform XHCI
controller reset.

Currently, the PMC IPC times out while sending the USB-C (0xA7) command
during poweron from S5 (S5->S4->S3->S0).

On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:

localhost ~ # cbmem -c | grep ERROR

[ERROR]  PMC IPC timeout after 1000 ms
[ERROR]  PMC IPC command 0x200a7 failed
[ERROR]  pmc_send_ipc_cmd failed
[ERROR]  Failed to setup port:0 to initial state
[ERROR]  PMC IPC timeout after 1000 ms
[ERROR]  PMC IPC command 0x200a7 failed
[ERROR]  pmc_send_ipc_cmd failed
[ERROR]  Failed to setup port:1 to initial state
[ERROR]  PMC IPC timeout after 1000 ms
[ERROR]  PMC IPC command 0x20a0 failed

This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).

During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.

This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.

Supporting Doc=Intel expected to release a TA (Technical Advisory)
document to acknowledge this observation and supported W/A for ADL
generation platforms.
Till that time, keeping this W/A as part of the google/brya specific
mainboard alone.
Note: other ADL-SoC based mainboards might need to apply the similar
W/A.

BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.

Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR

No PMC timeout error is observed with this CL.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-17 19:35:37 +00:00
Nico Huber
03401d259f mb/qemu-aarch64: Fix include path for device_tree.h
Recently merged commit 8cc1d79ed0 (mainboard/qemu-aarch64: Get top
of memory from device-tree blob) missed a rebase and hence needs the
include path updated.

Tested `make qemu` for qemu-aarch64.

Change-Id: Id669eeaabbc1710bb7e408659f2d79f682427919
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-16 19:16:56 +00:00
Alper Nebi Yasak
8cc1d79ed0 mainboard/qemu-aarch64: Get top of memory from device-tree blob
Trying to probe RAM space to figure out top of memory causes an
exception on AArch64 virtual machines with recent versions of QEMU, but
we temporarily enable exception handlers for that and use it to help
detect if a RAM address is usable or not. However, QEMU docs recommend
reading device information from the device-tree blob it provides us at
the start of RAM.

A previous commit adds a library function to parse device-tree blob that
QEMU provides us. Use it to determine top of memory in AArch64 QEMU
virtual machines, but still fall back to the RAM probing approach as a
last-ditch effort.

Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80364
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-16 16:17:29 +00:00
Saurabh Mishra
de1a74454f soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
	Panther Lake U/H 12Xe/H 4Xe External Design
	Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
	Volume 2 of 2 #813030

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-16 06:21:08 +00:00
Morris Hsu
4c749d765d mb/google/brox/jubilant: Disable devcies and GPIOs by fw_config
1.Set unused device's GPIOs to NC based on fw_config.
2.Disable config for nvme, ufs and CNVi based on fw_config.
3.Add fw_config STORAGE_UNKNOWN to enable all storages
  for the first boot in factory.

  BUG=None
  TEST=emerge-brox coreboot chromeos-bootiamge
       check fw_config messages in ap log
       verify devices on/off by fw_config on jubilant

Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-15 21:56:06 +00:00
Nick Vaccaro
27c8599b63 mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)
Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to
correctly power down and stay powered down.  This pin does not need to
be locked.

BUG=b:359692570, b:356750516
BRANCH=firmware-brya-14505.B
TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and
boot gimble into developer mode, then reboot into dev screen and select
the "Power off" button and verify gimble powers off and does not power
itself back up.

Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-15 21:52:01 +00:00
Weimin Wu
fbb11f3cdb mb/google/dedede/var/awasuki: Enable HECI 1
The AP console log contains "HECI: No CSE device" and the system cannot be entered.

BUG=b:359474142
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
     The "HECI: No CSE device" message for AP log disappered

Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905
Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-15 21:48:30 +00:00
Sean Rhodes
f5055feb4d Revert "mb/starlabs/starbook/adl: Update the VBT"
This reverts commit 2eb5c1e83e.

Reason for revert: The latest release of FSP will not boot
without a display being connected using this VBT. The original
VBT does not have this issue, nor is the original issue that
commit 2eb5c1e83e fixed.

Revert it to restore booting when there is no display.

Change-Id: I05f9037cd68b8b29e69156e2372a544985f4442e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-15 21:47:18 +00:00
Felix Held
1c25c63c78 include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since
it was defined as unsigned long in AGESA.h, a workaround was needed in
cpu/amd/mtrr.h to not have the build fail due to a non-identical
redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround
without reaming the defines isn't trivially possible, since the
stoneyridge romstage.c still ends up including both definitions which
can't be easily worked around. Now all non-vendorcode coreboot code uses
TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and
TOP_MEM2 to avoid this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-15 21:42:32 +00:00
Felix Held
c6889816d8 soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possible
Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)'
which is a helper function that does exactly the same, but slightly
simplifies the call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-15 21:41:59 +00:00
Yu-Ping Wu
078a5a0e7c commonlib/bsd/string: Fix pointer overflow for strnlen()
When `maxlen` is large (such as SIZE_MAX), the `end` pointer will
overflow, causing strnlen() to incorrectly return 0.

To not make the implementation over-complicated, fix the problem by
using a counter.

BUG=b:359951393
TEST=make unit-tests -j
BRANCH=none

Change-Id: Ic9d983b11391f5e05c2bceb262682aced5206f94
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83914
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2024-08-15 18:16:23 +00:00
Subrata Banik
0b2f9c9582 soc/intel/alderlake: Correct ISH partition availability check
The previous implementation incorrectly assumed that the presence of a
UFS device implied the availability of the ISH partition. This is not
always true, especially on Alder Lake platforms where ISH may be
enabled by default even without UFS.

This patch fixes the issue by directly checking for the presence of the
ISH device to determine if the ISH partition is available.

BUG=b:359440547
TEST=1. Able to dump the ISH version with UFS device:

```
tirwen-rev3 ~ # cbmem -c -1 | grep ISH
[DEBUG]  ISH version: 5.4.2.7780
```

2. Able to dump the ISH version with eMMC device:

```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG]  ISH version: 5.4.2.7780
```

Change-Id: I411e36606c0697f91050af40e0636f7c64810e95
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-15 06:28:33 +00:00
Matt DeVillier
7de2911589 mb/google/octopus/var/phaser: Update VBT
Extracted from coreboot-Google_Phaser.11297.296.0.bin.
Fixes display init on newer LASER14 boards.

TEST=build/boot google/phaser, observe display init successful.

Change-Id: Icb48edb4e74f147e3458f845d921a15a2d1906da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83897
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-14 16:46:35 +00:00
Felix Singer
a8b1260c7f util/liveiso/nixos/graphical: Preconfigure some Gnome settings
These settings are not a must, but nice to have. The most noteworthy
setting is `sleep-inactive-ac-type`, which is set to `nothing` so that
the target doesn't go into suspend when AC is used as power supply and
it's unused for a while.

Change-Id: I9a6e3eb88427f94f504a6b991a98b1b51e11bc19
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
2024-08-14 15:33:38 +00:00
Felix Held
9419820127 soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:

  Found overlapped clkreq assignment on clk req 0

Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file

Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-14 14:03:18 +00:00
David Wu
c4b7fad847 mb/google/nissa/var/riven: Disable external fivr
In next phase, riven will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.

BUG=b:359062365
TEST=build, boot to OS, suspend/resume work normally.

Change-Id: Id5f538b2eda7820a922b8d9ee14b2bae7df3726c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-14 14:02:46 +00:00
Karthikeyan Ramasubramanian
a4285f7366 mb/google/brox: Remove Mainboard Prepare to Sleep(MPTS) ACPI method
Brox does not have PCIe WWAN or discrete GPU. Hence no need to power
them off during suspend. Hence also remove the MPTS ACPI method.

BUG=None
TEST=Build Brox firmware and boot to OS.

Change-Id: Ia239c3f038ce31934efb0a391350fa0f786e3fcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83788
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-14 14:02:02 +00:00
Pablo Iranzo Gómez
bec449a14e Docs/getting-started/faq: Remove line break in URL breaking link
Change-Id: I3f950af4201486cd90e5fa61a4657ab7ae643825
Signed-off-by: Pablo Iranzo Gómez <Pablo.Iranzo@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83817
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-14 08:19:48 +00:00
Yu-Ping Wu
aff734bc42 commonlib/bsd: Add strcat() and strncat() functions
An upcoming vboot feature [1] will need strcat() to be defined in
string.h. Therefore, add strcat() and strncat() to commonlib/bsd. Remove
those functions from libpayload.

[1] https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_reference/+/5650810

Change-Id: If02fce0eafb4f6fa01d8bab17d87a32360f4ac83
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-14 03:09:20 +00:00
Yu-Ping Wu
0dcdc0347c commonlib/bsd: Add strlen() and strnlen() functions
Add strlen() and strnlen() to commonlib/bsd by rewriting them from
scratch, and remove the same functions from coreboot and libpayload.

Note that in the existing libpayload implementation, these functions
return 0 for NULL strings. Given that POSIX doesn't require the NULL
check and that other major libc implementations (e.g. glibc [1]) don't
seem to do that, the new functions also don't perform the NULL check.

[1] https://github.com/bminor/glibc/blob/master/sysdeps/i386/strlen.c

Change-Id: I1203ec9affabe493bd14b46662d212b08240cced
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-14 03:09:03 +00:00
Felix Singer
4ea4d82cec util/liveiso/nixos/graphical: Replace PulseAudio with PipeWire
PipeWire is the successor of PulseAudio. So use that instead.

Change-Id: Ib557925e481ab72a31a64c4bf353a261dff4296d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83851
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
2024-08-14 02:50:17 +00:00
Karthikeyan Ramasubramanian
7a9528b688 mb/google/brox: Do not override GPIO PM
Brox uses Ti50 which always supports long interrupt pulse. Hence no need
to override GPIO PM.

BUG=None
TEST=Build Brox firmware and boot to OS. Perform suspend/resume for 25
cycles.

Change-Id: I6a138c1953714bc29570db587594cab8f315a4ec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83856
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13 20:30:00 +00:00
Jayvik Desai
dfa830e530 soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
This patch updates the platform-specific Meteor Lake early
sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic
ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP
uGOP driver as an underlying technology for rendering eSOL screen.

This patch does not change the binary or the system behaviour.

BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.

Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13 14:51:11 +00:00
Jayvik Desai
95d03996d9 soc/intel/adl: update libgfx config to a generic eSOL config
This patch updates the early libgfx init config
(MAINBOARD_HAS_EARLY_LIBGFXINIT) used for Alder Lake SoC with a
generic CrOS/ChromeOS early sign of life config (CHROMEOS_ENABLE_ESOL)

This patch does not change the binary or the system behaviour and is
only meant to bind the early GFX initialization with a generic eSOL
config.

BUG=b:352651132
TEST=Able to build google/tivviks and checked the config in output

Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83841
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13 14:40:50 +00:00
Jayvik Desai
a0dbf25a22 vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch introduces a new early sign-of-life config option when
libgfx or uGOP is enabled for early graphics initialization.

BUG=b:352651132
TEST=Able to build google/rex and google/tivviks

Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83705
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13 14:40:33 +00:00
Pranava Y N
e8babf03ee mb/google/brya/var/nova: Enable TCSS XHCI setting
This patch enables the TCSS XHCI in the devicetree to solve the genesys
hub enumeration issue.

BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.

Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83845
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13 14:35:50 +00:00
Subrata Banik
1fac6b32ef commonlib/include: Include <stdint.h> to fix 'SIZE_MAX' undeclared error
This change includes the <stdint.h> header file to resolve the
compilation error "'SIZE_MAX' undeclared". This issue was introduced
by commit hash af0d4bce65 (region:
Introduce region_create() functions).

TEST=Able to build google/rex.

Change-Id: I0dbd839e3573d5c74375911903c8f9d6a66bbf28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83886
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13 14:35:16 +00:00
Leo Chou
994b7e9090 mb/google/nissa/var/pujjoga: Modify GPP_C1 setting
Confirm with EE, the GPP_C1 don't need PU 20K.
So modify GPP_C1 setting to remove PU 20k

Schematic version: 500E_GEN4S_ADL_N_MB_0418

BUG=b:358162951
TEST=Build and boot on pujjoga.

Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-13 13:26:22 +00:00
Leo Chou
87d9511741 mb/google/nissa/var/pujjoga: Modify P sensor setting
1. The P sensor need follow WWAN FW_CONFIG to enable/disable

2. Modify GPP_H19 setting to PAD_CFG_GPI_APIC to fix PLT test fail

Schematic version: 500E_GEN4S_ADL_N_MB_0418

BUG=b:357998089
TEST=1. Boot to OS and verify the P sensor devices is set based on
fw_config.
2. Confirm that the PLT test can pass successfully.

Change-Id: Ic3610180c8cf99eba9367e26bfc3666410af19f7
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13 13:25:57 +00:00
David Wu
e1e16e0cb9 mb/google/nissa/var/riven: Add elan touchscreen support
This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:348125053 b:348126380
TEST=emerge-nissa coreboot
     boot with elan TS, make sure elan TS is functional.

Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13 13:25:33 +00:00
Keith Hui
f7ed007298 mb/asus/p8z77-m: Light DRAM_LED during early boot
Turn on DRAM_LED on the mainboard in early bootblock, and turn it off
in ramstage. Primarily an indication if boot fails during raminit,
modeled after vendor firmware.

This LED is controlled by GPIO07 on the super I/O.

Boot tested on hardware.

Change-Id: I549b51375d1ef056d5fc01871bfe62d60b8a01cb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-13 13:25:23 +00:00
Jayvik Desai
0de60b2840 drivers/intel/fsp2: Add config for FSP uGOP eSOL
This patch introduces a new configuration option,
FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP
support using FSP-M for the early sign-of-life feature in SOC.

BUG=NA
TEST=Able to build google/rex and checked the config in output.

Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-12 13:13:36 +00:00
Elyes Haouas
259052f9db tree: Use boolean for pch_hda_sdi_enable[]
Change-Id: I27568d1205216f697b48ffb09ce5208505718978
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83863
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:36:58 +00:00
Gang Chen
1ea2a1c182 soc/intel/xeon_sp/gnr: Remove VPD from GNR Kconfig
Remove the unused config VPD from GNR Kconfig.

Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82975
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-08-11 17:36:26 +00:00
Saurabh Mishra
de56d38b07 soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:

1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
   and google/fatcat mainbaord.
5. Ref: Processor EDS documents
	vol0.51 #815002

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
     PTL using google/fatcat mainboard.

Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:35:27 +00:00
Morris Hsu
5bc6bd4c41 mb/google/brox/jubilant: update overridetree for dptf settings
Update dptf settings for EVT.

BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge

Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:34:31 +00:00
Morris Hsu
ffc1cbb8fc mb/google/brox/jubilant: update overridetree
Update touchpad settings.

BUG=b:342867386
TEST=ensure touchpad is working.

Change-Id: Ibf62470b7fd921065201894a63d7e2a83dad53ce
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-11 17:34:09 +00:00
zengqinghong
917f24018a mb/google/nissa/var/teliks: Configure TPM IRQ for teliks
Add TPM TIS ACPI interrupt configuration, set teliks's
`TPM_TIS_ACPI_INTERRUPT` to 13.

BUG=b:352263941
TEST=emerge-nissa coreboot

Change-Id: Iaed51e0bb8abac0ed0b35bfcf12e95fd34f92242
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83832
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-11 17:33:46 +00:00
zengqinghong
9d968c93da mb/google/nissa/var/teliks: Add DP AUX BIAS connect
Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.

BUG=b:352263941
TEST=DP function of MB and DB workable

Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:33:33 +00:00