Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- PCH asserts `SLP_S0#` during suspend (power LED blinks)
- `slp_s0_residency_usec` increases after suspend
Change-Id: I51eec89444cd0b7bc7834ee52c3b17ca0b3bf9ac
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The WD Black SN850X (WDS100T2XD0E) reports corrected RX errors on
suspend/resume.
Change-Id: I570ce0c392003f5514931272664bb4f9ec3c0803
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- PCH asserts `SLP_S0#` during suspend (power LED blinks)
- `slp_s0_residency_usec` increases after suspend
Change-Id: Ib94665f2504200388c093600e8b359fde092bd79
Signed-off-by: Tim Crawford <tcrawford@system76.com>
A previous CL ("Add missing ACPI device path names",
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors
from the Kernel on Brya devices (see Tim's comment on patchset 8):
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI
FSPI is defined in src/soc/intel/alderlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
TEST=Built and tested on brya by verifying the error is gone.
BUG=b:231582182
Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0#,
DevSlp blocks suspend entry. Disable it for now.
Change-Id: I3ac796f1fcdd201bcfc0bff4f02dca379b5b8234
Signed-off-by: Tim Crawford <tcrawford@system76.com>
galp6 only has one SSD slot connected to the CPU, which doesn't support
SATA.
Change-Id: If42b4b0c8d47d2205e1784bed98e45159ede6b8a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0#,
DevSlp blocks suspend entry. Disable it for now.
Change-Id: If1e1be78e36edaae74755686ec58772b122c41d1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add gfx register to System76 ADL boards so GMA ACPI data is generated.
Fixes backlight controls on Windows 10 and Linux 6.1.
Change-Id: I356e09350ee0f1412409509a2b1695642ae210b3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Tested by adding gfx register on system76/lemp11 and booting Windows.
Display settings has a brightness setting, and can change the brightness
level.
Change-Id: Ia29fb2adde1ec90ed8b0757a4d81e54240ee7575
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This has caused nothing but issues trying to get different drives to
behave correctly. Just remove it.
Change-Id: I5ed36c519fa7757034172f146fb5e03a15f40ede
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This has caused nothing but issues trying to get different drives to
behave correctly. Just remove it.
Change-Id: I72216960f9445e357b9c51faf3735f232adec78c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Other boards may have the S0ix issue. Always send PTS and let the EC
choose to apply the hack.
Change-Id: I0fc6e7ceac9fb79457a2ec35693c9d40afafae55
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Inform the EC to apply the PMC hack to allow the CPU to go to C10 during
suspend.
Change-Id: Id124b2e9249403cebf0038a172d2a324b81c433f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The RTD3 config is wrong, but the "correct" config uses BUF_PLT_RST#.
lemp11 still sometimes fails to reach C10, but plugging/removing AC
adapter still works to fix it.
Change-Id: I084bc4bf21d550822586092a4d1be384d2ca180b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
`gfx` got dropped during some rebase. Add them back.
Fixes brightness controls on Windows 10.
Change-Id: Ifd2553e3929962598185cc553c480dcb0087af5c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
- Enable early command training to fix FSP-M init of 8 GB DIMMs
- Preserve FSP-M default of 1 for LpDdrDqDqsReTraining
Change-Id: Iee6eccc6545f2920514018eff163e690f5ab6c01
Signed-off-by: Tim Crawford <tcrawford@system76.com>
oryp10 is nearly identical to the oryp9, with the differences being:
- Uses DDR5 RAM instead of DDR4 RAM
- Uses Realtek ALC1306 instead of TI TAS5825M
- Has an OLED display
Change-Id: If2617095e2ac1cb3ce7ccf27ebe35128e825b55b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This reverts commit 844dcb3725.
A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
BRANCH=firmware-brya-14505.B
BUG=b:240669428
TEST=verify that ETT is disabled
`iotools rdmsr 0 0x1fc'
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I96a72009aaf96d4237d57f4d5c8b1f41f87174d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66281
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now
function properly. Without this patch, only the top slot would work.
Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 884467a2b5.
Without these names, Windows fails with INTERNAL_POWER_ERROR (0xA0)
bugcheck with paramter 0x680. Linux reports errors for the devices, but
continues to work.
Change-Id: I5ced77f23929c39cc50276b17ac4b469c93fc250
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Device 0:01.1 does not exist on ADL-P. I assume this works because the
bridged device has function 1.
Fixes the following error in Linux:
pcieport 0000:00:01.0: can't derive routing for PCI INT B
snd_hda_intel 0000:01:00.1: PCI INT B: no GSI - using ISA IRQ 10
Which in turn resolves the conflict with the PCH HDA device...again:
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000bf549647>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: I9d9a0003764a1e031be578c1f406b2a5d7512de7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Intel rewrote the git history with the latest release. The following 2
commits no longer exist:
* 6c0c469 Merge pull request #59 from esyr-rh/microcode-20220510-releasenote-fixes
* 6ff5aa2 releasenote.md: changes summary fixes for microcode-20220510
Fixes building new checkouts of coreboot the require microcode blobs.
Change-Id: Id206bff57038178a362acf5ca2cdbe998381535d
Ref: commit 97144eee85 ("3rdparty/intel-microcode: Update submodule to recent main branch")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Correct the PCH PCIe RP indexes, which were copied from darp8.
Fixes using Ethernet and the SD card reader.
Change-Id: If14dea0492f6b7bea62d482ab970fe43e17c107b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This partial reverts commit d8d522884b.
These devices names cause ACPI errors in Linux as they are missing from
the DSDT.
ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.SRAM (20211217/dspkginit-438)
ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.HEC1 (20211217/dspkginit-438)
ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.FSPI (20211217/dspkginit-438)
Ref: https://review.coreboot.org/c/coreboot/+/63984
Change-Id: I644d2363d7e3c64af1d21e2a44bc3463819dd860
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Fixes the following warnings on Linux:
pcieport 0000:00:06.0: can't derive routing for PCI INT D
pcieport 0000:00:06.2: can't derive routing for PCI INT B
Change-Id: I49406e0db77cf2391972f6660729bd0a41a34f13
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Copy the constraints from ADL-S to ADL-P.
Fixes the following warning in Linux on System76 oryp9, which has an
NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack track on every boot.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000bf549647>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: I550c80105ff861d051170ed748149aeb25a545db
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for
ramstage to match other System76 boards.
Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Use the actual model name for the variant dir.
Change-Id: I199b8efb5c3cddb8943ba4b761546caa11c67a30
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Use the new "detect" method instead of "probed". Fixes an uncommon issue
where I2C HID fails to initialize the device in Linux.
Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Re-add FSP-S configs from the 4.13 branch, which were not included when
upstreamed.
Change-Id: I5f99d088190df07213c5b615f36fde29831aad86
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.
Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].
[1]: https://github.com/system76/smart-amp
Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
