Some tests have to be able to catch assertion errors.
Adding CMocka mock_assert() enables that.
Additionally fix test_imd_create_tiered_empty(),
test_full_stack() and test_incorrectly_initialized_stack()
by adding missing expect_assert_failure().
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
LANG LC_ALL TZ are required for reproducible builds. Those environment should
be always used for all builds in coreboot and for payloads.
By using COREBOOT_EXPORTS those would be removed in payload builds.
Change-Id: Iea965abbce23bf6ec408ef587da0a4c4ebc65a27
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, Depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
On Hayato Chromebook this can save ~100ms in total.
BUG=b:177389446
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51973
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The conversion to ASL 2.0 syntax in commit 81d55cf introduced a
regression triggering a BUG in Linux when reading the battery current.
Correct the wrongly-converted calculation.
Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0")
Tested-by: Andrew A. I. <aidron@yandex.ru>
Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected
the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the
corresponding SCI mapping register, but didn't set up the SCI level and
trigger type, so that couldn't have worked on most of the boards. The
only boards where I think this was actually tested are the google/zork
ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is
GPIO mode instead of the WAKE_L mode, but at least the SCI was
configured correctly. The new PAD_NF_SCI macro can configure both the
right GPIO mux setting and set up the SCI configuration correctly, so
use this new macro for the GPIO_2 pin. For test purposes I also added
the corresponding GPIO_2 configuration to amd/mandolin to see if the
affected registers end up having the expected value using the HDT
debugger to look at the registers, but didn't test the wake-up
functionality, since S3 resume isn't working on amd/mandolin yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit includes makefile cleanup to exclude common source file
compilation in each stage by using all-y flag.
BUG=b:182963902
TEST=trogdor validated on limozeen
Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
To train PCIe devices, the devices need to be enabled and taken out of
reset. This patch does the bare minimum needed to train PCIe. It is
not intended to handle timings, which will be addressed later.
Copy the enables for WWAN & WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.
Again, this patch is the minimum to let the FSP train the PCIe busses.
BUG=b:182202136
TEST=Boot guybrush from NVME.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.
Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.
The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.
BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.
Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
mb/google/guybrush: Update APCB - disable debug
mb/google/guybrush: Add APCB to get through memory training
soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode
soc/mediatek/mt8192: Update MCUPM firmware
soc/mediatek/mt8192: Add version info for SSPM
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I445d753c712670fe80efcdf29459736df2b76666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
