Some touchscreens need to adhere to certain timings during the power
off sequence as well as during the power on sequence. Adding
reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to
accommodate these devices.
BUG=b:78311818
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.
Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.
Tested with uImage payload on Cavium SoC.
Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Linux (4.16) assumes that the PIT interrupt is connected to the pin 0 of the
IOAPIC[0] and panics otherwise.
This might be a Linux bug. The MP Specification 1.4 does seem to mandate
sequential ordering for bus entries, but not for the I/O APICs.
Change-Id: Ibf823eb5b3a29e4590cba915069cdfe5f780edcd
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that assembly code isn't processing the idt gates there's
no need to ensure each vector entry is the same amount of code.
BUG=b:72728953
Change-Id: I2b248b26b9df36d6543163762c74622f79278961
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having
the interrupt handling code available to all stages. In order
to do this the idt setup is moved to a C module. The vecX
entries are made global so that a table of references to all
the interrupt vector entry points can be used to dynamically
initialize the idt. The ramification for ramstage is that
exceptions are initialized later (lib/hardwaremain.c). Not
all stages initialize exceptions when this Kconfig variable
is selected, but bootblock for the C, stages using
assembly_entry.S, and of course ramstage do. Anything left
out just needs a call to exception_init() at the right
location.
BUG=b:72728953
Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
CSRs are XLEN bits wide (i.e. the same width as general purpose
registers), so size_t seems a little more correct than int.
This change doesn't affect functionality because MSTATUS_MPRV already
fits in 31 bits.
Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Processors, such as glk, need to have paging enabled while
in cache-as-ram mode because the front end is agressive about
fetching lines into the L1I cache. If the line is dirty and in
the L1D then it writes it back to "memory". However, in this case
there is no backing store so the cache-as-ram data that was written
back transforms to all 0xff's when read back in causing corruption.
In order to mitigate the failure add x86 architecture support for
enabling paging while in cache-as-ram mode. A Kconfig variable,
NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
out for page tables within the cache-as-ram region. Additionally,
the page directory pointer table is also carved out of cache-as-ram.
Both areas are allocated from the persist-across-stages region
of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
the page tables.
The two paging-related areas are loaded by calling
paging_enable_for_car() with the names of cbfs files to load the
initial paging structures from.
BUG=b:72728953
Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram
is employed for that particular stage.
BUG=b:72728953
Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Certain platforms need to pass different stack pointer values to
postcar depending on S3 resume or not. Add comments to ease the
reader in understanding the point. If different stack values weren't
needed the program was already cached in stage cache with the correct
value.
Change-Id: I7202c62e6202a14416cb49ad5348740174747c7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Entry points from assembly to C need to have the stacks aligned
to 16 bytes with the newer compilers. This entry point was
missed. Correct it.
BUG=b:72728953
Change-Id: Idb29daf830c05fd5543c2194690364ce31b6a22c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently the idt setup and handling is only in ramstage. In
order to prepare having an exception handler in other stages
move the interrupt vector entry code to its own compilation
unit. vec0 and int_hand need to be global so c_start.S
references will resolve at link time.
BUG=b:72728953
Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.
This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.
There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
decoding the serial number into a byte array.
google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.
Testing this on grunt, dmidecode now shows the full serial number:
Serial Number: 00000000
BUG=b:65403853
TEST=tested on grunt
Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change f43adf0 (intel/common/block/cpu: Change post_cpus_init after
BS_DEV RESOURCES) moved post_cpus_init to BS_OS_RESUME for S3
path. This results in BSP timing out waiting for APs to be
parked. This change increases the time out value for APs to be parked
to 250ms. This value was chosen after running suspend-resume stress
test and capturing the maximum time taken for APs to be parked for
100 iterations. Typical values observed were ~150ms. Maximum value
observed was 152ms.
BUG=b:76442753
TEST=Verified for 100 iterations that suspend-resume does not run into
any AP park time out.
Change-Id: Id3e59db4fe7a5a2fb60357b05565bba89be1e00e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In case of all DMI Type 17 to be empty, the strip trailing whitespace
code will have a zero length Part Number entry, which will cause
exception when using (len - 1) where len is zero. Add extra code to
cover this corner case.
BUG=b:76452395
TEST=Boot up fine with meowth platform, without this patch system will
get stuck at "Create SMBIOS type 17".
Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
dmidecode used to print
'HMAA51S6AMR6N-UH '
it now prints
'HMAA51S6AMR6N-UH'
BUG=b:65403853
TEST=Verified using dmidecode
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia10ef434a2377e34ae7a8f733c6465c2f8ee8dfa
Reviewed-on: https://review.coreboot.org/25302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.
The following changes were done to coreboot and libpayload:
* Use page table lvl 0
* Increase VA bits to 48
* Enable 256TB in MMU controller
* Add additional asserts
Tested on Cavium SoC and two ARM64 Chromebooks.
Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some DIMMs have invalid strings when it comes to device part number
(bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused
space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ),
all others should be ASCII.
Create a test that detects invalid strings and replace invalid
characters with *. If a replacement was made the output string then must
be <Invalid (replaced string)>.
BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Use code to examine SMBIOS,
while testing different valid and invalid strings.
Remove string injection before committing.
Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update encoding.h to the version shipped with spike commit
0185d36 ("Merge pull request #165 from riscv/small_progbuf"),
and copy the license header from the LICENSE file.
Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.
As a first step, pass the bootrom-provided FDT to the payload,
unmodified.
Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Due to changes in the RISC-V Privileged Architecture specification,
Linux can now be started in physical memory and it will setup its own
page tables.
Thus we can delete most of virtual_memory.c.
Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.
NOTE: Spike does support RVC, but currently doesn't select
ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
support RVC.
Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.
Add the necessary alignment directive before trap_entry.
Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There are now a few architectural extensions available for ARMv8, some
of which introduce instructions or other features that may be useful.
This allows the user to select an extension implemented on their SoC
which will set the -march option passed into the compiler.
Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch changes the way coreboot builds ARM TF to pass the new
COREBOOT flag introduced with the following pull request:
https://github.com/ARM-software/arm-trusted-firmware/pull/1193
Since the new coreboot support code supports the CBMEM console, we need
to always enable LOG_LEVEL INFO. Supporting platforms will parse the
coreboot table to conditionally enable the serial console only if it was
enabled in coreboot as well.
Also remove explicit cache flushes of some BL31 parameters. Turns out we
never really needed these because we already flush the whole cache when
disabling the MMU, and we were already not doing it for most parameters.
Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some x86 platforms don't have a TSC that is invariant w.r.t.
rate to get accurate timestamps. As such a different timestamp
is required. Therefore, allow one to specify non-TSC timestamp
source and not compile in the default x86 TSC code.
BUG=b:72378235,b:72170796
Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830
Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000
Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The code dealing with the old config string isn't needed anymore,
because the config string has been deprecated in favor of
OpenFirmware-derived devicetrees.
Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
