7f8e2a6a4a
sb/intel: Use ACPI_COMMON_MADT_IOAPIC
...
i82801gx, i82801ix, i82801jx:
Maintain IRQ #0 to GSI #2 override as positive edge trigger.
ibexpeak, emulation/qemu-q35:
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-26 11:02:48 +00:00
10bdee1327
ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT
...
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.
Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.
Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-26 11:02:18 +00:00
e742b68f1a
arch/x86/ioapic: Promote ioapic_get_sci_pin()
...
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.
Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-26 10:53:16 +00:00
ae1b2d49cf
soc/intel: Introduce ioapic_get_sci_pin()
...
According to ACPI Release 6.5 systems supporting PIC (i8259)
interrupt mechanism need to report IRQ vector for the SCI_INT
field. In PIC mode only IRQ0..15 are allowed hardware vectors.
This change should cover section 5.2.9 to not pass SCI_INT
larger than IRQ15. Section 5.2.15.5 needs follow-up work.
Care should be taken that ioapic_get_sci_pin() is called
after platform code has potentially changed the routing
from the default.
It appears touched all platforms except siemens/mc_aplX
currently program SCI as IRQ9.
Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-26 10:52:21 +00:00
ddc37d69cb
ACPI: Add acpigen_write_PTC()
...
Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-26 10:51:35 +00:00
d48982acac
cpu/intel/speedstep: Separate single SSDT CPU entry
...
Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-26 10:51:12 +00:00
9368cf9025
acpi/acpi.c: Reduce scope of some functions
...
These functions are only used in one compilation unit.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756
Reviewed-by: Jan Samek <jan.samek@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com >
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-04-26 08:40:14 +00:00
323a0ae2b1
Documentation/mainboard/hp: Add more about internal flashing
...
Add a more detailed explanation of internal flashing
on the HP Compaq 8200 Elite SFF.
Signed-off-by: Václav Straka <venda.straka@gmail.com >
Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com >
2023-04-25 13:02:22 +00:00
a87da91719
util/docker/jenkins-node: Drop Zephyr SDK
...
The version of the Zephyr SDK that is used is quite old and Zephyr
hasn't been really used. Thus, drop it and also its dependencies from
u-boot.
Change-Id: Ie498d687e1566133adf650166117d8f68fcfdaf6
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Patrick Georgi <patrick@coreboot.org >
2023-04-25 05:36:13 +00:00
fa41fef557
util/docker/jenkins-node: Allow pip to install packages system-wide
...
Call pip3 with `--break-system-packages` allowing it to install packages
system-wide. This fixes building the Docker container.
Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-04-25 05:36:03 +00:00
98d7157a6d
util/docker/jenkins-node: Merge package installations into first step
...
It's not necessary to have multiple steps for installing packages and
requirements. Just merge the two install steps to one.
Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74245
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-04-25 05:35:57 +00:00
0197ddf20a
mb/google/nissa/var/yaviks: Update devicetree for UFC usb port
...
USB port 6 connects to a USB front camera, it should always probe.
Remove probe by rear camera fw_config.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Derek Huang <derekhuang@google.com >
2023-04-25 03:50:16 +00:00
fa945c8b1d
mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG
...
Update devicetree
-Enable USB2 port5 for WWAN
-Update OVTI8856 setting
-Update USB2/3 Type-A 0/1 port location
Probe devicetree based on FW_CONFIG
-pen garage
-rear mipi cam
-USB WWAN
BUG=b:273791621, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Derek Huang <derekhuang@google.com >
2023-04-25 03:50:13 +00:00
ec8f010a62
Documentation/releases/coreboot-4.20: Add toolchain updates section
...
Change-Id: I5fff8b97f6b85165a71aa2a86417f27986fd25fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
2023-04-25 01:23:38 +00:00
905768b8e2
mb/google/myst: Set system type to laptop
...
BUG=b:277294070
TEST=None
Change-Id: I0aa4e0bcfb06e5e5cb7e9d52f2d82b5818925267
Signed-off-by: Jon Murphy <jpmurphy@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74284
Reviewed-by: Tim Van Patten <timvp@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-24 16:05:52 +00:00
2c4a4d2cb4
mb/google/myst: Store XHCI PCI resources
...
Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.
BUG=b:277273428
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com >
Change-Id: I608d51f438681ac529323c23cc707845a3d609d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-24 16:03:56 +00:00
d40cecd00d
mb/google/myst: Enable gfx_hda
...
Enable gfx_hda to allow for audio over hdmi.
BUG=b:277219546
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com >
Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-24 15:42:51 +00:00
8f3f0cb0e7
mb/google/myst: Enable crypto in devicetree
...
Add the crypto device to the devicetree.
BUG=b:277214359
TEST=builds
Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2
Signed-off-by: Jon Murphy <jpmurphy@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-24 15:41:48 +00:00
137742225d
asus/p2b: Remove MADT LAPIC
...
Fix after 'commit 69a13964eakyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74472
Reviewed-by: Branden Waldner <scruffy99@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-04-24 14:25:18 +00:00
5a24d6491e
soc/mediatek/mt8183: Fix set but unused variable
...
This fixes a clang warning.
Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2023-04-24 13:58:13 +00:00
7277b26f05
vendorcode/mediatek/mt8192: Add or remove brackets
...
This fixes clang compilation warnings about logic problems and
superfluous brackets.
Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com >
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com >
Reviewed-by: Yidi Lin <yidilin@google.com >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2023-04-24 13:57:35 +00:00
77b590eed1
soc/mediatek/dptx.c: Remove set but unused variables
...
This fixes clang warning about set but unused variables.
Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74547
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com >
2023-04-24 13:55:25 +00:00
27af3e6b11
include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb
...
Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in
line with get_top_of_mem_below_4gb.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-04-23 21:41:29 +00:00
8c4a56a295
soc/amd/glinda: drop code for non-existing eMMC controller
...
Glinda doesn't have an eMMC controller and also doesn't have GPIO pins
that eMMC signals can be multiplexed on, so drop the eMMC related code
from Glinda.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I49ead01075780ea97dae99a36632f7659fd00587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74662
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-22 17:20:59 +00:00
d9d45be0e3
soc/amd/phoenix: drop defines for non-existing eMMC controller
...
Phoenix doesn't have an eMMC controller, so remove the remaining eMMC-
related defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I412c968479d23deb7f2e060b26b4a56ec9c764f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-04-22 17:20:48 +00:00
faa9fb6f7f
soc/amd/mendocino: drop code for non-existing eMMC controller
...
Mendocino and Rembrandt don't have an eMMC controller and also don't
have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC
related code from Mendocino.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-04-22 17:20:41 +00:00
d1128878e9
mb/google/octopus: Add EC_HOST_EVENT_PANIC to SCI mask
...
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:268342532
BRANCH=firmware-octopus-11297.B
TEST=Observe kernel ec panic handler run when ec panics
Signed-off-by: Rob Barnes <robbarnes@google.com >
Change-Id: I37e566e459f39f8bc2dafc3c3915260259730ca6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-04-22 16:28:55 +00:00
e279fe7070
mb/google/dedede/var/boxy: Generate SPD ID for supported memory part
...
Add boxy supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
3. Micron MT53E512M32D1NP-046 WT:B
BUG=b:278983561
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com >
Change-Id: I317f2b31774627706babdea10776af05ab692d1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Derek Huang <derekhuang@google.com >
2023-04-22 16:28:34 +00:00
aad8824741
mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks
...
Yavilla board memory id setting references to yaviks.
This CL aligen it with yaviks.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
H58G56BK7BX068 3 (0011)
MT62F1G32D2DS-026 WT:B 3 (0011)
K3KL8L80CM-MGCT 3 (0011)
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-04-22 16:26:53 +00:00
1c25808f0b
mb/google/brya/variants/hades: Swap LAN and SD Card PCIE Ports
...
To aid in layout, the PCI ports for LAN and SD card were swapped.
SD Card is now on RP3 (clksrc 4)
LAN is now on RP8 (clksrc 3)
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com >
Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-04-22 16:25:50 +00:00
dbf132cc1e
soc/intel/meteoerlake: set power limits dynamically
...
Set power limit values dynamically based on Meteor Lake
CPU TDP and PCI ID of SKU.
BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values for 15W SKU on Rex board
Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-04-22 16:24:41 +00:00
3810705ef0
mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating
...
The patch disables PCH USB2 PHY power gating to prevent possible
display flicker issue. Please refer Intel doc#723158 for more information.
BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Verify the build for marasov board
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com >
Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-22 16:23:45 +00:00
870eca2052
mb/google/corsola: Rename common config from STARMIE to STARYU
...
The STARYU is the mt8186 detachable reference design, and the STARMIE
is a variant of STARYU. Let's rename the common config from STARMIE
to STARYU, and we can select the STARYU config for the follow up
mt8186 detachable variant.
BRANCH=corsola
BUG=b:275470328
TEST=./utils/abuild/abuild -t google/corsola -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com >
Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74654
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Yidi Lin <yidilin@google.com >
2023-04-22 16:23:23 +00:00
7765b1019a
samsung/lumpy: Use APMC defines
...
Change-Id: I658596da1d84b486126d751b6066c3efd3f65290
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-04-22 16:22:09 +00:00
a9dd3c3fae
lib/version: Move board identification strings
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These strings are now only expanded in lib/identity.c.
This improves ccache hit rates slightly, as one built object file
lib/version.o is used for all variants of a board. Also one built
object file lib/identity.o can become a ccache hit for successive
builds of a variant, while the commit hash changes.
Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-04-22 16:20:49 +00:00
5cabc29013
soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I95916e409b3fbd4941a861054733a34100244da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-04-22 16:09:04 +00:00
e8a21e7a62
soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
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Since it's an internal bus, it's PCIE_ABC_C_DEVFN and not
PCIE_GPP_C_DEVFN. This also makes it consistent with the rest of the
internal PCI buses.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-04-22 16:08:53 +00:00
b5d8cf8d1c
soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63
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In the PPRs #57019 Rev 3.03 and #57396 Rev 3.04, SMITYPE_XHC3_PME,
SMITYPE_XHC4_PME and SMITYPE_CUR_TEMP_STATUS_5 are defined, so add those
defines. When doing the initial update for Phoenix, at least XHC3 and
XHC4 PME events were missing from the PPR. Those two are the PME events
of the two USB4 controllers. SMITYPE_XHC2_PME doesn't exist on this SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-04-22 16:08:39 +00:00
7c302cf208
cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c
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Now that the code is in a much better shape and uses native coreboot
functionality to perform the initialization, rename the file from
fixme.c to cpu_io_init.c to be more descriptive of what it does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I97d1ac2b12c624210c570f189f825409bd64f318
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74659
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-04-22 16:08:09 +00:00
044fc9f671
soc/intel/cmn/cse: Make cse_get_fpt_partition_info() function static
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The patch makes `cse_get_fpt_partition_info()` AP local/static as all
the references to this function are in local to the cse_lite.c file.
BUG=b:273661726
TEST=Able to build and boot google/marasov with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74388
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-04-22 05:38:35 +00:00
2e8df3784c
mb/google/brya: Enable CSE FPT Info config for Nissa
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Google Brya variants like Nissa family selects
`SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT
information.
BUG=b:273661726
TEST=Able to build and boot google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74387
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-04-22 05:38:20 +00:00
9bb2690609
soc/intel/alderlake: Implement soc_is_ish_partition_enabled override
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This patch implements `soc_is_ish_partition_enabled()` override to
uniquely identify the SKU type between UFS and non-UFS to conclude
if ISH partition is enabled and need to retrieve the ISH version from
CSE FPT by sending HECI command.
TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting
to google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-22 05:37:57 +00:00
3879334ca0
mb/google/rex: Enable asynchronous End-Of-Post
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Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about
100ms on google/rex.
TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-04-22 05:37:18 +00:00
534cc06d60
mb/google/myst: Expose SKU and board ID to Chrome OS
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Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:277293398
TEST=builds
Change-Id: I8e42ba23dada9771f335df34275e44e51d645596
Signed-off-by: Jon Murphy <jpmurphy@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74283
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-21 22:40:17 +00:00
e24d9d6b45
soc/intel/meteorlake: Don't offer D3Cold when it's disabled
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Use D3COLD_SUPPORT Kconfig option to adjust the maximum supported sleep
state in ACPI.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: Ifa55a19727e6adb6864158c2c323d08a0c22b996
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2023-04-21 21:30:36 +00:00
917261d11c
arch/riscv/trap_handler.c: Use new names for CSR
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sbadaddr and mbadaddr are deprecated names. This fixes compilation with clang.
Change-Id: I5c8fa82b6131dec10f55e8ebcf36b34e30b57bad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-04-21 20:12:42 +00:00
0d504c8c0f
arch/riscv: Fix compiler argument for clang
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The suffixes zicsr and zifencei are assumed by default for clang.
Change-Id: I75947f614c3600d5d9d461970159f0787fd6c3de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-04-21 20:12:25 +00:00
43c730f986
mb/intel/mtlrvp: Enable RTD3 root port mutex for WWAN
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This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN. The purpose of using this mutex is to prevent OSPM from
calling _ON and _OFF methods while WWAN kernel driver is calling _RST,
which accesses the GPIO pins.
BUG=NA
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com >
Change-Id: I5b53765453bac0fc96e9651ab347069c7c8bf058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73384
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com >
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
2023-04-21 18:49:14 +00:00
60703a81e2
mb/intel/adlrvp: Enable RTD3 root port mutex for WWAN
...
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN. The purpose of using this mutex is to prevent OSPM from
calling _ON and _OFF methods while WWAN kernel driver is calling _RST,
which accesses the GPIO pins.
BUG=NA
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com >
Change-Id: I809eb84cb1a09deb168040e83041b65237a1b576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73383
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com >
2023-04-21 18:48:59 +00:00
daeb781884
mb/google/brya: Enable RTD3 root port mutex for WWAN
...
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com >
Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com >
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
2023-04-21 18:48:43 +00:00
