The pspv2_mbox struct contained an unnamed union that covered the 32
bits of the command register of the PSP v2 mailbox. Since the pspv2_mbox
struct is mainly used for hardware register accesses and the union part
is mostly used to access the different bits before/after writing/reading
the command register, split this functionality. For the register access
a command field is added to the pspv2_mbox struct instead of the unnamed
union and for accessing the separate bits of the command register a new
named union is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3f00b6fd73c3f749154b77b940e6d5aa385ec49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The cmd_response field in the pspv2_mbox struct is the buffer used to
pass data to the PSP and back to the x86 side, so rename it to buffer.
This also aligns the code a bit more with the reference code. Also
rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for
heci1_disable(), once by caller (from various SoC) and again inside the
callee (heci1_disable) function.
As all callers of heci1_disable() function are doing
DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check
inside the callee can be dropped.
BUG=b:228789015
TEST=Able to build and boot google/redrix with this change. CSE PCI
device is getting function disabled upon selecting
DISABLE_HECI1_AT_PRE_BOOT from SoC config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.
BUG=b:228789015
TEST=Able to build google/redrix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.
Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.
Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The ITE EC used on Nereid can take a long time to update, and especially
too long to erase. There is a 1 second timeout enforced on the EC erase
command, but Nereid's IT81302 will typically take about 5 seconds to
complete erase, and could take as long as 30.
Since this affects any Nissa variant using an ITE EC and it's nice to
make the entire Nissa project consistent, this change disables early
sync for all Nissa boards.
BUG=b:222987250
TEST=EC software sync is no longer attempted (and thus does not fail) on
Nereid.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I55d36479e680c34a8bff65776e7e295e94291342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
To read data from an I2C EEPROM that uses 2 byte offsets or any other
I2C device that uses 2 byte offsets, first the two offset bytes are sent
to the device and then the data bytes are read from it. The main
difference to the existing i2c_read_bytes is that that function will
only send one offset byte to the I2C device.
TEST=Reading the contents of an EEPROM on the AMD Chausie board works
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.
This fixes building when some debug options are enabled.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()"
significantly reduced the size of the bootblock. This makes the space
saving options, required to make to bootblock fit in the 32K SOC
limit, unnecessary.
TESTED: with configs/config.google_octopus_spi_flash_console the .text
size is 0x29c8 bytes which is still well below the 0x8000 SOC limit.
Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
Additionally, this patch enforces SA lockdown configuration for SKL
and ICL as well.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit 211be9c03 (soc/intel/cmn/{block, pch}: Migrate GPMR driver)
drops `dmi` prefix from `lockdown_cfg` function name.
This patch adds the `gpmr` prefix to the lockdown_cfg function to make
it meaningful.
BUG=b:211954778
TEST=Able to build google/brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idaa0e089131ab125348e2430355041c4ee7971de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig
to skip FSP notify API (Post PCI Enumeration) and make use of native
coreboot driver to perform SoC recommended operations prior booting to
payload/OS.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.
[INFO ] coreboot skipped calling FSP notify phase: 00000020.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This area is used for storing AP RO verification data.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout
BRANCH=none
Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Camera LED flicker 3 times or so as sensor is being probed
during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot preventing camera LED flicker.
Corrects that by explicitly sequencing the reset GPIO and power GPIO
BUG=b:219644184
TEST=Build and boot on vell, observe whether camera LED flickers
Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
