Commit Graph

301 Commits

Author SHA1 Message Date
Shuo Liu
71814b0e5b acpi: Remove acpigen_write_OSC_pci_domain
For PCI domains, static _OSC will be used for better readability
and maintenance.

This reverts commit f4a12e1d39.

TEST=Build and boot on intel/archercity CRB

Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:48:06 +00:00
Jianeng Ceng
05ee5c21b4 acpi: Fix return value in acpi_device_write_dsd_gpio()
Fix ++ as suffix and * precedence. After modification, the gpio index
can be obtained correctly.
The error was introduced in the commit making it public:
commit 01344bce

BUG=None
TEST= Can get the correct index test on nissa.

Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82088
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-28 18:27:40 +00:00
Aseda Aboagye
b55000b2d5 acpigen_ps2_keybd: Add assistant key to linux,keymap
If the ChromiumOS EC indicates that the device has an assistant key,
we should also add it to the generated linux,keymap binding.  This
commit simply does so by examining the keyboard capabilities reported by
the EC.

BUG=b:333088656
TEST=With a device that has an assistant key, flash AP FW and verify
that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using
`evtest`.

Change-Id: I217220e89bce88e3045a4fc3b124954696276442
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-22 14:05:42 +00:00
Aseda Aboagye
fef07f2c3a acpigen_ps2_keybd: Add Fn key to linux,keymap
Some devices may generate scancodes for the Fn key if they have one.
If they do, we should add them to the linux,keymap binding.

BUG=b:333096023
TEST=Flash DUT that emits a scancode for the Fn key, verify that it is
mapped to KEY_FN in the Linux kernel using `evtest` when pressing the Fn
key.

Change-Id: Ie4daa64bc6b619392276d0b5f16e2d195d5bd68c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-19 17:22:48 +00:00
Jianeng Ceng
01344bce1a acpi: Make acpi_device_write_dsd_gpio() public
Make sure it can be used for other driver.
At present, i2c_generic_write_gpio() is not suitable for being called
by other drivers, so delete it, add acpi_device_write_dsd_gpio() to
replace it, and make it public.

BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.

Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-19 14:13:41 +00:00
Sergii Dmytruk
1a90314ac5 drivers/crb: use crb_tpm_ prefix instead of tpm2_
This prevents name clashes with drivers/spi/tpm and allows both to be
potentially compiled in at the same time.

Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-15 13:35:00 +00:00
Aseda Aboagye
f2782b8328 acpigen_ps2_keybd: Add support for dictation key
Some internal keyboards have a dictation key; this commit simply adds
support for this key by adding the mapping from the scancode to the
Linux keycode for use in the linux,physmap ACPI table.

BUG=b:333101631
TEST=Flash DUT that emits a scancode for a dictation key, verify that it
is mapped to KEY_DICTATE in the Linux kernel.

Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-04-15 13:32:48 +00:00
Elyes Haouas
9f1030feae tree: Drop duplicated <device/{path,resource}.h>
<device/device.h> is supposed to provide <device/{path,resource}.h>

Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12 04:24:20 +00:00
Shuo Liu
f4a12e1d39 acpi: Add acpigen_write_OSC_pci_domain
Add dynamic PCI domain _OSC ASL generation codes, supporting both
PCIe and CXL domains.

Dynamic SSDT generation is used to generate a list of ASL device
objects based on FSP outputs (e.g. the SoC/SKU configurations)
and _OSC is a method inside these objects (hence it would be
straightforward to be generated altogether, plus some C codes
managed boot configs could be referenced as well).

This usage is optional. It is helpful for cases where the same
code set supports multiple SKUs/SoCs (difficult to be handled by
one set of static SSDT), and the CPU performance is good enough
to run SSDT generation logics with minimal costs.

TEST=intel/archercity CRB

Tested with https://review.coreboot.org/c/coreboot/+/81377.

Change-Id: I711ce5350d718e47feb2912555108801ad7f918d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-01 08:06:46 +00:00
Elyes Haouas
58eddfc00c acpi: Remove blank lines before '}' and after '{'
Change-Id: I9ba061fe0b1396ccc1597e26685a6b4e312e3549
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:42:12 +00:00
Sergii Dmytruk
47e9e8cde1 security/tpm: replace CONFIG(TPMx) checks with runtime check
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2
during compilation, in which case actual TPM family in use can be
determined at runtime.

In some places both compile-time and runtime checks are necessary.
Yet in places like probe functions runtime state checks don't make sense
as runtime state is defined by results of probing.

Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28 15:18:04 +00:00
Felix Held
0ada3dafd0 acpi/acpigen_pci_root_resource_producer: zero-pad ranges
Print bus number, IO and MMIO ranges as fixed length zero-padded
hexadecimal numbers. The bus numbers are 1 byte long, the IO range
values are 2 bytes long and the MMIO range values can be up to 8 bytes
long, so use '%02x', '%04llx' and '%016llx' in the corresponding parts
of the format string.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-01 16:24:22 +00:00
Felix Held
e549ee093b soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt
implementation doesn't contain any AMD-specific code and can also be
used by other SoCs. So factor it out, move the implementation to
src/acpi/acpigen_pci_root_resource_producer.c, and rename it to
pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its
domain operation's acpi_fill_ssdt function pointer, the PCI domain
resource producer information will be added to the SSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 15:39:06 +00:00
Felix Held
0d19289e84 arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-23 15:13:37 +00:00
Patrick Rudolph
344ebf1f81 acpi/acpi: Pass struct device to acpi_create_srat_gia_pci
Instead of S:B:D:F numbers pass the struct device to
acpi_create_srat_gia_pci and let it extract the information needed.

This also adds support for PCI multi segment groups.

Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80258
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-09 13:47:00 +00:00
Arthur Heymans
7fcd4d58ec device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31 10:36:39 +00:00
Patrick Rudolph
f95dbcee71 device: Add inline method to identify PATH_ROOT
Add and use inline method to identify the root device.

Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-24 08:46:19 +00:00
Martin Roth
94de3255e5 acpi,arch,commonlib: Rename Makefiles from .inc to .mk
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice5dadd3eaadfa9962225520a3a75b05b44518ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80066
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24 08:32:11 +00:00
Arthur Heymans
8b036e1484 device/device.h: Drop acpi_inject_dsdt
This is now unused in the tree and filling SSDT should always be used.

TEST=intel/archercity CRB

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-22 13:54:41 +00:00
Felix Held
3b5b66d829 device: Add support for multiple PCI segment groups
Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.

Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-16 22:59:55 +00:00
Felix Held
75c4d44798 acpi/acpigen: add acpigen_write_SEG for segment group number method
Introduce acpigen_write_SEG to generate the ACPI method object that
returns the PCI segment group number for a PCI(e) host bridge.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-13 17:17:18 +00:00
Jeremy Compostella
ba757a71fe x86: Separate CPU and SoC physical address size
The physical address size of the System-on-Chip (SoC) can be different
from the CPU physical address size. These two different physical
address sizes should be used for settings of their respective field.

For instance, the physical address size related to the CPU should be
used for MTRR programming while the physical address size of the SoC
should be used for MMIO resource allocation.

Typically, on Meteor Lake, the CPUs physical address size is 46 if TME
is disabled and 42 if TME is enabled but Meteor Lake SoC physical
address size is always 42. As a result, MTRRs should reflect the TME
status while coreboot MMIO resource allocator should always use
42 bits.

This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the
physical address size of the SoC for those SoCs.

BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP

Change-Id: Icb76242718581357e5c62c2465690cf489cb1375
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22 12:26:59 +00:00
Sukumar Ghorai
9b3c5afc00 acpi: Reduce wait interval in delay loop for sleep
The optimization of sleep time in acpi code includes reducing the sleep
duration and increasing the polling frequency within the acpi _ON/_OFF
method. StorageD3Enable is activated in Google/Rex, and this
optimization results in a saving of approximately 25ms in D3cold resume
time, reducing it from around 160ms to 135ms.

BUG=b:296206467
BRANCH=firmware-rex-15709.B

TEST=boot test verified on google/rex
     verified _ON/_OFF Method in SSDT.
     verifid kernel log in s0ix test -
          0000:00:06.0: PM: pci_pm_resume_noirq

Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-12-20 04:28:27 +00:00
Marek Maslanka
017003cbd0 acpi: Add support for WDAT table
This commit lays the groundwork for implementing the ACPI WDAT (Watchdog
Action Table) table specification. The WDAT is a special ACPI table
introduced by Microsoft that describes the watchdog for the OS.

Platforms that need to implement the WDAT table must describe the
hardware watchdog management operations as described in the
specification. See “Links to ACPI-Related Documents”
(http://uefi.org/acpi) under the heading “Watchdog Action Table”.

BUG=b:314260167
TEST=Mock the acpi_soc_fill_wdat function for a specific platform/soc
and enable ACPI_WDAT_WDT in the kconfig. Check if the build passes
successfully.

Change-Id: Ieb82d1f69b2b7fffacfd2928bc71f8ff10498074
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-12-15 19:08:45 +00:00
Arthur Heymans
87837df807 acpi.c: Fix generating pointer to cb_tables located >4G
Use the generic resource_consumer method which works for memory both
above and below 4G.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1bc553b18d08cee502b765166227810f8e619631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76181
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-08 14:02:45 +00:00
Felix Held
4a9ed707c8 acpi: add missing device/device.h include
The device/device.h provides the definition for struct device used in
those files, so include this header file to make sure that it's not only
included indirectly via some other header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-07 13:19:47 +00:00
Naresh Solanki
1fe1904f38 acpi/acpi_gic: Add GIC ITS subtable
Add support for generating GIC subtable ITS (Interrupt Translator
Service).

Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06 13:07:27 +00:00
Naresh Solanki
6920c6f232 acpi: Add IO Remapping Table structures
Input Output Remapping Table (IORT) represents the IO topology of an Arm
based system.

Document number: ARM DEN 0049E.e, Sep 2022

Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06 13:06:22 +00:00
Felix Held
67b3c8f278 acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
While acpidump_print shouldn't be called with a NULL pointer as
table_ptr argument, better add a check to not end up dereferencing the
NULL pointer.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-05 18:36:15 +00:00
David Milosevic
d982274a4e acpi: Add PPTT support
This patch adds code to generate Processor Properties
Topology Tables (PPTT) compliant to the ACPI 6.4 specification.

 - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT
 is selected. Its purpose is to return a pointer to a topology tree,
 which describes the relationship between CPUs and caches. The hook
 can be provided by, for example, mainboard code.

Background: We are currently working on mainboard code for qemu-sbsa
and Neoverse N2. Both require a valid PPTT table. Patch was tested
against the qemu-sbsa board.

Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-02 19:16:26 +00:00
Zheng Bao
3ea3fbe4f2 soc/amd: Add DBG2 ACPI table
Dump the DBG2 table on Linux console.
$> acpidump -s
ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **)

$> acpidump > acpidump.bin
$> acpixtract -a acpidump.bin
$> iasl -d dbg2.dat
$> cat dbg2.dsl
/*
 * ACPI Data Table [DBG2]
 *
 * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
 */

[000h 0000 4]             Signature : "DBG2" [Debug Port table type 2]
[004h 0004 4]          Table Length : 00000054
[008h 0008 1]              Revision : 00
[009h 0009 1]              Checksum : FA
[00Ah 0010 6]                Oem ID : "COREv4"
[010h 0016 8]          Oem Table ID : "COREBOOT"
[018h 0024 4]          Oem Revision : 00000000
[01Ch 0028 4]       Asl Compiler ID : "CORE"
[020h 0032 4] Asl Compiler Revision : 20220331

[024h 0036 4]           Info Offset : 0000002C
[028h 0040 4]            Info Count : 00000001

[02Ch 0044 1]              Revision : 00
[02Dh 0045 2]                Length : 0028
[02Fh 0047 1]        Register Count : 01
[030h 0048 2]       Namepath Length : 0002
[032h 0050 2]       Namepath Offset : 0026
[034h 0052 2]       OEM Data Length : 0000 [Optional field not present]
[036h 0054 2]       OEM Data Offset : 0000 [Optional field not present]
[038h 0056 2]             Port Type : 8000
[03Ah 0058 2]          Port Subtype : 0012
[03Ch 0060 2]              Reserved : 0000
[03Eh 0062 2]   Base Address Offset : 0016
[040h 0064 2]   Address Size Offset : 0022

[042h 006612] Base Address Register : [Generic Address Structure]
[042h 0066 1]              Space ID : 00 [SystemMemory]
[043h 0067 1]             Bit Width : 00
[044h 0068 1]            Bit Offset : 00
[045h 0069 1]  Encoded Access Width : 03 [DWord Access:32]
[046h 0070 8]               Address : 00000000FEDC9000

[04Eh 0078 4]          Address Size : 00000100

[052h 0082 2]              Namepath : "."

Raw Table Data: Length 84 (0x54)

 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4
 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE
 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(..
 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&.............
 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "...............
 50: 00 00 2E 00                                     // ....

BUG=b:303689867

Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02 17:51:42 +00:00
Naresh Solanki
1d6eeff171 acpi: Enable 64bit ECAM resource
Adjust ACPI DSDT to support ECAM resource above 4GB by modifying the PCI
ECAM Resource Consumption settings. The changes include specifying a
QWordMemory resource template, accommodating non-cacheable, read-write
attributes, and adjusting the address range.

Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-27 21:10:41 +00:00
Arthur Heymans
62f788e244 acpigen.c: Add resource consumer functions for mmio
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id9e4adcd976e1f56ef7f502d9df16dbefce95c3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79217
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23 14:42:59 +00:00
CoolStar
42be899b65 acpi/device: Only return dev->ops->acpi_name if non-NULL
Returning a NULL device name can cause issues if something else does
handle it.

E.g. UART and GNA devices on Intel Alder Lake-N cause
INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid
packages being created from a NULL name

Test: build/boot google/nissa (craaskvin) to Win11

Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-16 22:18:25 +00:00
Felix Held
09b7dc51ce acpi/acpigen: drop len assert in acpigen_pop_len
This is already handled as a separate case in the code below, so there's
no need for this assert any more.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15 13:53:09 +00:00
Felix Held
575ee135d1 acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTES
Use a define instead of magic numbers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15 13:52:59 +00:00
Felix Held
a6f7459f38 acpi/acpigen: rework acpigen_pop_len for different size PkgLength
Previously acpigen_pop_len always wrote a 3 byte PkgLength to the 3
bytes reserved by acpigen_write_len_f. After this patch acpigen_pop_len
encodes PkgLength in 1-3 bytes depending on the PkgLength. When less
than the 3 bytes that were previously reserved in the corresponding
acpigen_write_len_f call are needed for PkgLength, the payload data will
be moved back by the number of reserved bytes that aren't needed for the
PkgLength.

This fixes the problem that the Windows AML parser doesn't like a 3 byte
PkgLength being used for the size of the buffer containing UTF-16
strings when the length could be encoded in a single PkgLength byte. In
that case, Windows previously ignored the whole SSDT containing this
larger than necessary PkgLength encoding. It should however be noted
that the ACPI 6.4 spec doesn't specify if it's required to always use
the most compact possible encoding of the PkgLength or not. Since iasl
generates the shortest possible PkgLength encoding, it's also a good
idea to make coreboot's acpigen do the same although it's not required
by the specification.

With this patch applied, Windows still boots on Mandolin and the time it
takes to write the tables doesn't change. To measure the times, the log
level in bs_sample_time was increased to BIOS_CRIT and the console log
level was increased to BIOS_CRIT too to only get those times as output.

BS: BS_WRITE_TABLES run times (exec / console): 8 / 0 ms

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib897b08a05a7cdc52902d51364246c260ea1f206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-15 13:52:44 +00:00
Felix Held
6ac6f6a6d0 acpi/acpigen: point out what acpigen_write_len_f does
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf2f54f2f428f4438ef22b7f9d205db10e144db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79001
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13 14:10:33 +00:00
Matt DeVillier
d4d40c64e1 acpi/acpigen: Fix buffer length in acpigen_write_name_unicode()
The buffer length is in bytes, and since we are converting from ASCII
to UTF-16, the value written needs to be 2x the string length + null
terminator.

TEST=build/boot google skyrim (frostflow), dump acpi and check bytecode
for correct buffer length preceding unicode strings.

Change-Id: Id322e3ff457ca1c92c55125224ca6cfab8762a84
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-11 15:12:21 +00:00
Paweł Anikiel
ed3b688e76 acpi/acpigen: Allow general namestring in write mutex functions
BUG=b:301150499
TEST=Compiled and tested on google/redrix - PERST# goes low when wwan
modem goes into runtime suspend.

Change-Id: Ib09d5a6091cedfce24da49390cf980414f97a2c9
Signed-off-by: Paweł Anikiel <panikiel@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-10-16 07:59:21 +00:00
Jonathon Hall
b63017fb71 acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punct
Librem 11's volume keys act as a PS/2 keyboard with only those two
keys.  Reduce the minimum number of top-row keys to 2.  Make the
"rest of keys" (alphanumerics, punctuation, etc.) optional.

Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-02 16:24:54 +00:00
Naresh Solanki
75f0b607fa acpi: Fix typos
Change-Id: Ie986c1cbbc9bcc7817dfeb04a4be86898b302987
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-27 15:28:26 +00:00
Arthur Heymans
3df6cc9de6 acpi: Add functions to declare ARM GIC V3 hardware
For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.

For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18 13:34:47 +00:00
Arthur Heymans
fca612497d acpi/Makefile.inc: Move code inclusion
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I63bbac225662377693ad5f29cc8911494c49b422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-18 13:29:10 +00:00
Arthur Heymans
f3aa88a51c arch/arm64: Hook up ACPI table generation
Linux v6.3.5 is able to detect and use ACPI tables on an out of tree
target using hacked version of u-boot to pass ACPI through UEFI.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-09-18 13:26:37 +00:00
Cliff Huang
95e4ffe848 acpi: Comply with ACPI specification by making _STR unicode strings
_STR should return Unicode string. From ACPI spec:
6.1.10 _STR (String)
The _STR object evaluates to an Unicode string that describes the
device or thermal zone.

BUG=NA
TEST=Check the changed _STR in SSDT to see if Unicode() macro is used

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1f4b55a268c1dadbae456afe5821ae161b8e15a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77695
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-14 12:03:32 +00:00
Arthur Heymans
c2830c9661 acpi.c: Add XSDT on QEMU
Since d8f2dce "acpi.c: Swap XSDT and RSDT for adding/finding tables"
XSDT is primarily used to add new tables or to find the S3 resume vector.
However with QEMU coreboot does not generate most ACPI tables but takes
them from whatever QEMU provides. Qemu only creates an RSDT and lacks an
XSDT.

To keep the codebase simple with the assumption that XSDT is always
present, create an XSDT based on the existing RSDT and update the
address in RSDP.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia9b7f090f55e436de98afad6f23597c3d426bb88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77385
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14 10:37:33 +00:00
Martin Roth
22e16db4c5 acpi/soundwire.[ch]: Fix dpn entry array overrun
In soundwire.h, SOUNDWIRE_DPN MIN  & MAX are set to 1 and 14. When
creating the dpn array, the length was set to MAX - MIN or 13, numbered
0 to 12.

When accessing the array, the code was bailing out if a value greater
than MAX was trying to be accessed, so the array was able to be overrun
by two structure lengths.

Fix this problem by:
1) Not subtracting the MIN value when creating the array, which does
waste a little space. If anyone wants to refactor the code to fix that,
please feel free.
2) Breaking out of the loop when the port is equal to the MAX port
number instead of just when it's greater than the max port number.

Reported-by: Coverity (CID:1429766 & CID:1429771)
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-09-13 15:26:01 +00:00
Naresh Solanki
4d0b18480d acpi/acpi.c: Accomodate 64bit MMCONF base in MCFG table
Allow the use of 64bit MMCONF base in MCFG table.
Previously only 32 bits were utilized for MMCONF base, while the
remaining 32bits were reserved & held value of zero as evident from MCFG
table disassembly. This commit entails updating the 'base_address' field
in the 'mmconfig' structure to 64 bits and removing the 'base_reserved'
field.

TEST=Confirmed the functionality of the 64bit MMCONF base in the MCFG
table disassembly below

            Signature : "MCFG"
         Table Length : 0000003C
             Revision : 01
             Checksum : BD
               Oem ID : "COREv4"
         Oem Table ID : "COREBOOT"
         Oem Revision : 00000000
      Asl Compiler ID : "CORE"
Asl Compiler Revision : 20230628

             Reserved : 0000000000000000

         Base Address : 0000001010000000
 Segment Group Number : 0000
     Start Bus Number : 00
       End Bus Number : FF
             Reserved : 00000000

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77539
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01 21:13:09 +00:00
Arthur Heymans
736d4d25df acpi: Add function to add ARM PL011 to ACPI DBG2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24 13:20:06 +00:00