While the SoC-level defaults for VGA_BIOS_ID are the expected correctly
remapped PCI VID/PID of the GPU which matches the PCI VID/DID inside the
VBIOS file, some mainboards override the VGA_BIOS_ID setting to the
non-remapped PCI ID. This resulted in coreboot not finding the VBIOS
file after commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping
in pci_rom_probe"). The proper solution would be to not override this
SoC-level config in neither the mainboard code nor some external config
file. This however requires adding/using some mechanism to tell SeaBIOS
which VBIOS image to use for the GPU device. Once this is implemented,
the SoC default for VGA_BIOS_ID shouldn't be overridden any more and
this patch can be reverted again.
This sort-of reverts parts of commit 42f0396a1028 ("device/pci_rom:
rework PCI ID remapping in pci_rom_probe"), but it still tries to find
the VBIOS image with the expected remapped PCI ID and only adds trying
the non-remapped PCI ID as a fallback when the file with the remapped
PCI ID doesn't exist and prints a notice in that case. Before the patch
referenced above, using the correct remapped PCI VID/DID resulted in a
warning about the CBFS file with the non-remapped name not being found,
but first checking the remapped version solves that problem.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This adds the Authors from the 24.02 tag to the 24.05 tag.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icb53c62c9a122ccdf2548cc2eebc8b0316a844ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82617
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pre-release notes never capture everything, so we need to do an
update to finalize them after the release is tagged.
This captures on additional SoC added right before the release and
updates the statistics.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3efcd15597e4fee0bdbca76e474974ae32d3263
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82613
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Integrate head.S directly into libc and remove all instances of head.o.
* Drop 'separate class' entry for head.S.
* Drop special treament for head.o inside lpgcc.
* Change the .text in `x86/head.S` to `.section .text._entry`.
* Drop arch/mock/head.c, initially added as a dummy file.
Change-Id: I156d781908fcc38d455bbf9f2c29e5ab95c7775a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This moves the multiboot header into its own include file, simplifying
head.S and making it easier to include/exclude the multiboot header
based on config options.
BUG=b:242829490
TEST=Able to build and boot google/rex.
Change-Id: I59a22dfe36044b4dd64a5b028a134be7a7d02a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch tries to simplify the baseboard/variant GPIO programming
for Google/Trulo. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.
With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.
BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant)
TEST=Able to build google/orisa.
Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* Introduce a null check before calling `gpio_padbased_override`
in `variant_configure_pads`.
* This prevents potential errors in cases where the
`variant_gpio_override_table` function returns a null pointer,
indicating that there are no override pads to configure.
BUG=b:334826281
TEST=Able to avoid hang incase there is no GPIO override.
Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the
problem of the PCI VID/DID combination of the Picasso iGPU not being
sufficient information to know which VGA BIOS file to run, so a new
function that additionally checks the PCI revision of that device was
introduced. Later it turned out that there might be a case where even
that isn't sufficient, so the soc_is_raven2() function is used in the
remap function to always use the correct VBIOS file.
Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME
Kconfig option, so all other SoCs are unaffected by this change.
Now that we use the VBIOS images with only the PCI VID and DID in the
CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID
as the iGPU in CBFS and we don't need the workaround to add a third
VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects.
This will result in SeaBIOS now running the VBIOS that has the same PCI
VID/DID as the hardware which will be the wrong one in the RV2 silicon
showing the PCO silicon PCI VID/DID, but that was also the case with the
VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one
of the two possible images during build time and hoped that it was the
correct one for that actual hardware. The only board where this patch
might cause a regression compared to the old behavior is the AMD Cereme
reference board with Pollock APU, but I'm not even sure if any coreboot
developer still has one of those boards, so I'm willing to accept that.
To properly solve the problem with SeaBIOS using the correct VBIOS file
in all cases, we'd need to generate that info during coreboot runtime
and somehow pass it to SeaBIOS, but that's out of scope for this patch.
TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS
and Ubuntu still works. Booting Windows 10 via the pre-built EDK2
payload that I'm using also resulted in the display output working.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6de533c536044698d85404427719b8f534870fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Type-C kernel driver no longer programs the AP mux, as of
https://review.coreboot.org/c/coreboot/+/82077. So remove device
references to the TCSS Mux control device from the Type-C port driver.
This eliminates the following kernel error which was observed as a
result of the kernel trying to program muxes it no longer has control
over:
[ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95
[ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95
BUG=b:341331428
TEST=Run system reboot; configure mux kernel errors no longer seen.
Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1) Add all changes needed for early graphics
2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa
The InnoLux (N156HCN-EBA C7) panel is used for the device tree.
BUG=b:296433986
TEST=On-screen text message seen during MRC training on Craask
Logs:
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
[SPEW ] bootmode is set to: 0
[0.171409] DP PHY mode status not complete
[0.175509] DP PHY mode status not complete
[0.179799] DP PHY mode status not complete
[0.184087] DP PHY mode status not complete
[0.188376] DP PHY mode status not complete
[0.192665] DP PHY mode status not complete
[0.196954] DP PHY mode status not complete
[0.201243] DP PHY mode status not complete
[0.205532] DP PHY mode status not complete
[0.209821] DP PHY mode status not complete
[0.214110] DP PHY mode status not complete
[0.218397] DP PHY mode status not complete
[INFO ] Informing user on-display of memory training.
Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE
ports, similar boards are available in other port configurations. As a
low cost, relatively high performance board with 4 NICs, it is well
suited for networking or 'homelab' tasks.
CPU: Intel N100 or N350
Memory: DDR5-4800 SODIMM (max 16 GB)
NIC: 4x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 4x Ethernet
- Display Port
- HDMI
- 4x USB 2.0
- Micro SD
Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- DisplayPort / HDMI
- 4x Intel I226 2.5 GbE NICs
- M.2 ports
- Micro SD slot
- ACPI S3
Not working / not tested:
- Fan (ITE IT8613E)
- Audio
- S0ix
- Internal USB ports
VBT extracted from vendor UEFI firmware version ADLN 0.01 x64
(04/04/2023 11:42:38).
Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some proximity domain info are type specifics, e.g. base/size/dev
are effective for PD_TYPE_GENERIC_INITIATOR, but not for
PD_TYPE_PROCESSOR. Dump info per their type.
TEST=Build and boot on intel/archercity
Change-Id: I7e722a0577bba954efba3e91cc152c758c001d68
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Move proximity domain setting up to ahead of attach_iio_stacks()
so that proximity domain info could be ready before
attach_iio_stacks()/create_xeonsp_domains().
For example in SPR, is_iio_cxl_stack_res() refers to proximity
domain info, and it will be called in create_xeonsp_domains().
TEST=Build and boot on intel/archercity
No significant boot log difference except for proximity domain
dump info display are moved ahead (with correct contents).
Change-Id: I594f0ec0c23e3b62c3bdd917ebf6e45be6e4069e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82267
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:337178014
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the `AZALIA_PIN_CFG_NC(0)` macro instead of `0x411111f0` and tidy up
some comments (align them and be consistent with capitalisation).
Tested with BUILD_TIMELESS=1, prodrive/hermes remains identical.
Change-Id: I1ff1197b1309fc0e5b978d6d36867a3f1a68c67c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Now that we also have the devicetree registers for the USB PHY config
in the openSIL case, add the USB PHY config setting from the Phoenix
with FSP devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a0acbf1b9d705dbf09f4480eb35e71e587ddd44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Add the USB PHY configuration structs for the openSIL case, so that
those can be configured in the devicetree like in the FSP case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied25e90859c4b1bc9b876bed3f3c46358ca36d32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82584
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the now common get_ddi1_type function to update the connector type
of the DDI1 port to match the display output extension card plugged into
the reference board.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82583
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both port descriptor files used in the FSP case contain an identical
get_ddi1_type implementation, so factor it out into a separate file.
This will also allow using the same function in the openSIL case in a
following patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82582
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a static DDI port configuration to the devicetree used in the
Phoenix with openSIL case. The configuration is taken from the
birman_ddi_descriptors array in port_descriptor_phoenix.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the FSP case, the DDI descriptors aren't part of the devicetree and
are instead retrieved in romstage by calling the mainboard's
mainboard_get_dxio_ddi_descriptors function which allows updating the
descriptors during romstage where the devicetree is static. In the
openSIL case, the DDI configuration is first needed in ramstage, so we
can put this info into the devicetree and update it if needed in
ramstage.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de12ff6af42e38751a3016efa313613677fa87a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82580
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Remove the unexpected '<' char at the end of the comment about the PSPP
policy config.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82579
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Remove the TODO to update the chipset devicetree for Phoenix, since this
has already been done.
When re-checking the chipset devicetree, I found conflicting information
about the existence of the PCI bridge to an external PCIe port on bus 0
device 1 function 5, but after looking into this, I'm reasonably certain
that it either doesn't exist or at least wouldn't be usable, so I won't
add that one to the chipset devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
This reverts commit f867c9c5473156617691d78350c362cd993bfcdd.
The new verb table breaks external mic detection on brox.
Revert and use old verb tables instead.
BUG=b:330433089
BRANCH=main
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.
Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82273
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nova will use SOLDERDOWN. Add memory.c to override baseboard.
Update dram id table for correct platform parameter.
BUG=b:328711879
Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256)
Update to Realtek provided verb table for ALC236 audio codec.
BUG=b:336967284
TEST=Verified headset and audio workable on DUT with "rec" and
"aplay" command.
Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds some helper functions for FDT, since more and more mainboards
seem to need FDT nowadays. For example our QEMU boards need it in order
to know how much RAM is available. Also all RISC-V boards in our tree
need FDT.
This also adds some tests in order to test said functions.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81081
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Debian sid is too unstable at this point, and frequently ends up having
issues that cause the coreboot-sdk docker image to fail to build. Using
stable also better reflects what users will typically be running.
Also remove the parameters to quiet the apt-get install command so that
if something does break, we can see what happened more easily.
Fixes bug 536
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41b6464b024df89c114db2cdb9367c0526eb0297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82411
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the `get_port_b_vref_cfg()` function to only return the
variable bits of the value. The NID itself is not connected, and
the `misc` field in the verb conveys the Vref value.
Change-Id: I5108f5339c5b002403a4e5339da6d52046c8bcbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit renames the variable _ARCH to _ARCHDIR in the libpayload
build script (lpgcc) to align with the naming convention of other
variables used in this file.
This change improves code readability and maintainability.
Change-Id: Iea4af68e49ab1cd7ec8156a14f8215244e9c0622
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82479
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The cr50.c file currently prints "cr50" in debug messages no
matter the system is using Cr50 or Ti50. This can be confusing
for developers.
This patch replaces "cr50" with "GSC" in debug messages. Using
"GSC" makes the messages more clear and easier to search via
`grep`.
BUG=none
TEST=Build and test on karis
Change-Id: I21f66cf8b608ca4e4dc82d7a55a851ec996c8bb3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82420
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/beechnutcity CRB
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
