This patch refactors RAMTOP MTRR type selection to address a critical
NEM logic bug on SoCs with non-power-of-two cache sets. This bug can
cause runtime hangs when Write Back (WB) caching is enabled.
Workaround: Force MTRR type to WC (Write Combining) on affected SoCs
when the cache set count is not a power of two.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a function to determine whether the number of cache sets is
a power of two. This aligns with common cache design practices that
favor power-of-two counts for efficient indexing and addressing.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified functionality on google/ovis and google/rex (including
a non-power-of-two Ovis configuration).
Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe using clk_src[0] and clk_req[1] mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=0,clk_req=1 in mFIT.
BUG=b:328318578
TEST=build firmware and veirfy suspend function on NVMe SKU DUT.
Cq-Depend: chrome-internal:7063434
Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since
all code is BSD licensed anyway.
It also moves some code from libpayloads stdlib.h to
commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is
useful for a subsequent commit that adds devicetree.c into commonlib.
Also we don't support DMA on arm platforms in coreboot (only libpayload)
therefore `dma_malloc()` has been removed and `dma_coherent()` has been
moved to architecture specific functions. Any architecture that tries to
use `dma_coherent()` now will get a compile time error. In order to not
break current platforms like mb/google/herobrine which make use of the
commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a
stub has been added to arch/arm64/dma.c.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rewrite the function by iterating IOMMU (Input/Output Memory
Management Unit) devices instead of iterating socket and stacks,
which is more aligned to coreboot infrastructure.
TEST=intel/archercity CRB
coreboot DRHD generation is compared, the order of sections are
changed as expected but the content is kept equvalient.
Change-Id: I700513e05181303cf3f4effc793a872eb23340cb
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81228
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Obtain IOMMU (Input/Output Memory Management Unit) info and
enumerate devices using device utils instead of FSP HOB interface,
which might change across SoC generations and no ambiguity across
multiple PCIe segments.
TEST=intel/archercity CRB
coreboot DRHD generation log no changes before and after
Change-Id: Ic5c404899172a0e4fba2721b8e8ca6c1f0856698
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81227
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1
and dw2. dw0, dw1 and dw2 are uninitialized before calling
soc_get_gpi_gpe_configs. This is error prone for some soc
implementations where soc_get_gpi_gpe_configs does nothing.
This patch is simple, just to assign zero values to dw0, dw1 and
dw0, to enhance the code robustness.
TEST=intel/archercity CRB
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMP (Physical Memory Protection) is a feature of the RISC-V
Privileged Architecture spec, that allows defining region(s) of
the address space to be protected in a variety of ways: ranges
for M mode can be protected against access from lower privilege
levels, and M mode can be locked out of accessig to memory
reserved for lower privilege levels. Limits on Read, Write, and
Execute are allowed. In coreboot, we protect against Write and
Execute of PMP code from lower levels, but allow Reading, so as
to ease data structure access. PMP is not a security boundary,
it is an accident prevention device.
PMP is used here to protect persistent ramstage code that is
used to support SBI, e.g. printk and some data structures. It
also protects the SBI stacks. Note that there is one stack per
hart. There are 512- and 1024-hart SoC's being built today, so
the stack should be kept small.
PMP is not a general purpose protection mechanism and it is easy
to get around it. For example, S mode can stage a DMA that
overwrites all the M mode code. PMP is, rather, a way to avoid
simple accidents. It is understood that PMP depends on proper OS
behavior to implement true SBI security (personal conversation
with a RISC-V architect). Think of PMP as "Protection Minus
Protection".
PMP is also a very limited resource, as defined in the
architecture. This language is instructive: "PMP entries are
described by an 8-bit configuration register and one XLEN-bit
address register. Some PMP settings additionally use the address
register associated with the preceding PMP entry. Up to 16 PMP
entries are supported. If any PMP entries are implemented, then
all PMP CSRs must be implemented, but all PMP CSR fields are
WARL and may be hardwired to zero. PMP CSRs are only accessible
to M-mode."
In other words if you implement PMP even a little, you have to
impelement it all; but you can implement it in part by simply
returning 0 for a pmpcfg. Also, PMP address registers (pmpaddr)
don't have to implement all the bits. On a SiFive FU740, for
example, PMP only implements bits 33:0, i.e. a 34 bit address.
PMPs are just packed with all kinds of special cases. There are
no requirements that you read back what you wrote to the pmpaddr
registers. The earlier PMP code would die if the read did not
match the write, but, since pmpaddr are WARL, that was not
correct. An SoC can just decide it only does 4096-byte
granularity, on TOR PMP types, and that is your problem if you
wanted finer granulatiry. SoC's don't have to implement all the
high order bits either.
And, to reiterate, there is no requirement about which of the pmpcfg
are implemented. Implementing just pmpcfg15 is allowed.
The coreboot SBI code was written before PMP existed. In order
for coreboot SBI code to work, this patch is necessary.
With this change, a simple S-mode payload that calls SBI putchar
works:
1:
li a7, 1
li a0, 48
ecall
j 1b
Without this change, it will not work.
Getting this to build on RV32 required changes to the API,
as it was incorrect. In RV32, PMP entries are 34 bits.
Hence, the setup_pmp needed to accept u64. So,
uinptr_t can not be used, as on 32 bits they are
only 32 bit numbers. The internal API uses uintptr_t,
but the exported API uses u64, so external code
does not have to think about right shifts on base
and size.
Errors are detected: an error in base and size will result
in a BIOS_EMERG print, but not a panic.
Boots not bricks if possible.
There are small changes to the internal API to reduce
stack pressure: there's no need to have two pmpcfg_t
on the stack when one will do.
TEST: Linux now boots partly on the SiFive unmatched. There are
changes in flight on the coreboot SBI that will allow Linux to
boot further, but they are out of scope for this patch.
Currently, clk_ignore_unused is required, this requires a
separate patch.
Change-Id: I6edce139d340783148cbb446cde004ba96e67944
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
In Xeon-SP, the domain0, which is located at stack0, usually needs
special handling due to the compatible devices on it (HEPT, IO-APIC
and legacy IOs). This patch adds util function detect whether a
give domain or stack is with such a role.
TEST=intel/archercity CRB
Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
For Xeon-SP, there are 4 main domain roles (PCIe/CXL/IOAT/UBOX).
This patch adds util function to check whether a given domain
belongs to one of these roles, or a give device belongs to
a domain of the specific role.
TEST=intel/archercity CRB
Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This also does some light cleaning up:
- Place spaces in function names to make it easier to read.
- Adds a newline to a console message.
TEST=Tested to work on HP ProBook 450 G3
Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81204
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define SSFC bit 0-1 in coreboot for add 2nd BOE G7500 touchscreen.
BUG=b:329339069
BRANCH=firmware-nissa-15217.B
TEST=Check touchscreen can detect and function work.
[INFO ] input: GTCH7503:00 2A94:A804 as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-GTCH7503:00/0014
Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Now that EC software sync has been verified to work on Brox, we can
enable it by default.
BUG=b:326152804
BRANCH=None
TEST=Verify that SW sync occurs
Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PAYLOAD_INFO is a very old feature that can add a key/value information
section to a payload file. It seems to have only ever been generated by
coreinfo and never really read by anything.
Since CB:1721 in 2012, the feature has been inadvertently broken in
practice since the `.note.pinfo` sections that contain the information
get discarded from the payload before cbfstool gets to see them. Since
CB:28647 in 2018, support for the section in the SELF loader was
(inadvertently?) dropped, so if someone actually fed cbfstool a payload
ELF that did have a `.note.pinfo` section, modern coreboot would refuse
to boot the payload entirely (which is probably not a good state to
leave things in).
This patch removes the code to generate PAYLOAD_INFO entries entirely,
but leaves the support to parse and extract those sections from old
payloads in place in cbfstool.
Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Pull down USI_REPORT_EN(GPP_C6) in romstage to solve
an abnormal peek pull high before BL_EN.
Because power sequence no meet spec, pre #comment36,
it may have ghost touch.
BUG=b:326337003
TEST=FW_NAME=omnigul emerge-brya coreboot, measurement of HW and test
touch detection by evtest
Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80769
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rewrite the function by iterating IOMMU (Input/Output Memory
Management Unit) devices instead of iterating socket and stacks,
which is more aligned to coreboot infrastructure.
TEST=intel/archercity CRB
coreboot DRHD generation is compared, the order of sections are
changed as expected but the content is kept equvalient.
Change-Id: I4c1cbf8d8fc93f746640efc3a82c539dcb3fdee2
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Obtain IOMMU (Input/Output Memory Management Unit) info and
enumerate devices using device utils instead of FSP HOB interface,
which might change across SoC generations and no ambiguity across
multiple PCIe segments.
TEST=intel/archercity CRB
coreboot DRHD generation log no changes before and after
Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81048
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Xeon-SP, it's common pattern to find devices under specific
socket, stack and domain. This patch adds util function for
these operations.
TEST=intel/archercity CRB
Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Implement watchdog for intel based platform by filling ACPI Watchdog
Action Table (WDAT) table.
The WDAT ACPI table encompasses essential watchdog functions, including:
- Setting and retrieving countdown/timeout values
- Starting and stopping the watchdog
- Pinging the watchdog
- Retrieving the cause of the last reboot, whether it was triggered by
the watchdog or another reason
The general purpose register TCO_MESSAGE1 stores the reason for the most
recent reboot rather than the original register TCO2_STS. This is
because the firmware must clear TCO2_STS, and it can't be reused for
storing this information for the operating system.
The watchdog is designed for use by the OS through certain defined
actions in the WDAT table. It relies on the ACPI Power Management Timer,
which may result in an increase in power consumption.
BUG=b:314260167
TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the
config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy
both firmware and kernel to the device. Trigger the watchdog by
performing the command: “cat > /dev/watchdog”. Wait approximately 30
seconds for the watchdog to reset the device.
Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
SATC is for RCiEPs (Root Complex Integrated EndPoints) but not
limited to IOAT domains. Rewrite the func by iterating all domains
and its RCiEPs. Currently the codes only support 1 PCIe segment.
TEST=intel/archercity CRB
coreboot SATC generation logs are unchanged before and after.
Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81049
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain
is a PCI domain with single bus number and PCIe RCiEPs (Root
Complex Integrated End Points) on it. The 2nd domain is a CXL
domain with remaining buses for CXL 1.0/1.1 end points and
possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual
Function) if any.
TEST=intel/archercity CRB
P.S. The SUT is not with CXL cards however we hope this refactor
could be integrated first as an improvement of the design.
Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the nova variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:328711879
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOVA
Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Add a stub MPIO chip driver to the openSIL stub code, so that the
devicetree entries needed for the MPIO chip can already be added to the
mainboard's devicetree files. This driver won't do anything, but still
allows the register settings in the devicetree to be set to make
switching over to the actual openSIL code and the corresponding glue
code easier.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
FSP can also make use of Multi-Processor services during its
multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot
take MP ownership as FSP-S may still use EDK2 MP services
concurrently.
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80691
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 829e8e65b9 ("soc/intel: Use common codeflow for MP init")
brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function
static. This function needs to be accessible from
src/drivers/intel/fsp2_0/fsp_mpinit.c.
TEST=Verified on Meteor Lake rex board
Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
With this patch, all domain creation logics are moved into the scope
of attach_iio_stack/chip_common.c for the ease of maintenance
and future SoC integration where the domain creation process for
specific stack types might be overridden.
TEST=intel/archercity CRB
1. Boot to CentOS 9 Stream Cloud.
2. Compare PCIe enumeration and ACPI table generation logs before and
and after this patch, no changes.
Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81098
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Acoustic noise mitigation for xol. The setting values are from
internal power team.
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=None
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL.
Update gpio config and corresponding ACPI for WoWLAN.
BUG=b:327379404
BRANCH=None
TEST=Boot image on SKU1 and check Wake on WLAN from S0ix.
Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
