7ffbe0a04e
soc/qualcomm/ipq40xx: Do resource transition
...
Change-Id: I93c16b563c7a4f4c653d2ebfd001170cb0fca82e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2022-07-06 12:50:48 +00:00
02a0d5c1a6
mb/google/nissa/var/joxer: Add lock gpio pins
...
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: Ia087b62904fd515bf73960a188b225f1d49197dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65646
Reviewed-by: Reka Norman <rekanorman@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-06 01:44:01 +00:00
7bc711743d
mb/google/nissa: Select Kconfig to perform CSE FW update in ramstage
...
Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW
Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform
CSE FW sync in ramstage.
BRANCH=firmware-brya-14505.B
TEST=Perform CSE FW upgrade/downgrade on nivviks.
Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368
Reviewed-by: Reka Norman <rekanorman@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-06 01:43:44 +00:00
e3178a16e0
common/intel/cse: Add function to perform CSE FW update in ramstage
...
When compressed ME RW blobs are used for CSE FW update, it has to be
loaded into memory to decompress. So perform CSE FW update in ramstage.
Alder Lake-N based nissa boards use compressed ME RW blobs to save on
SPI flash size. Enable CSE FW update in ramstage.
BRANCH=firmware-brya-14505.B
TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade
works.
Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-06 01:43:26 +00:00
7195cee17f
soc/intel/alderlake: Add check for CSE FW sync in romstage
...
Some Alder Lake-N boards will use compressed ME RW blobs to obtain
savings on the SPI size (1916KB before compression, ~1132KB after
compression). So add an additional check before calling
cse_fw_sync() from romstage. When compressed blobs are used, the call to
CSE firmware update has to be in post-RAM stages.
BRANCH=firmware-brya-14505.B
Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760
Reviewed-by: Kangheui Won <khwon@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-06 01:43:03 +00:00
0a87c10f96
mb/google/nissa/var/pujjo: Add lock gpio pins
...
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I9f0fcf52b6b7d622e4fd182e007de6401856c7fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65645
Reviewed-by: Reka Norman <rekanorman@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-06 01:42:41 +00:00
878574df94
Makefile.inc: Update submodules only when git is present
...
Instead of trying to update the submodules, then skipping each update if
git is not present, just don't try to update the submodules at all.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: I83ef48a21820c0983e38823331c9ba0fe0fc277f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-07-06 00:35:01 +00:00
553787bd32
.gitignore: Ignore .cache directory & compile_commands.json
...
To configure the clangd plugin for various editors, The command
'bear -- make' is used to generate the compile_commands.json.
The clangd plugin creates a .cache directory under inside coreboot.
Just ignore both of these.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: Ic844f807ab48597b8aae29bb64ab16d6c8dff217
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-07-06 00:33:48 +00:00
a6710d01d4
Makefile.inc: Notify about updating submodules
...
There is no longer any information printed when updating submodules, so
on the initial build, this can lead to a long delay without explaining
what's going on.
Just add an information line that the submodules are being updated so
that the user can see what's happening.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: I987e50b99e39b976bc8367525549153e1eba69cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-07-06 00:33:03 +00:00
0a18d64d00
nb,soc/intel: Handle upper RAM boundary
...
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2022-07-05 13:08:34 +00:00
e0ddbbb0d2
soc/intel/meteorlake: Enable X2APIC
...
This patch enables X2APIC to avoid hang-ups due to
`Switching from X2APIC to XAPIC mode is not implemented.`
BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP)
TEST=Able to enable X2APIC on rex.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2022-07-05 13:07:29 +00:00
5c3cbcd8cc
soc/intel/baytrail,braswell,quark: Drop RES_IN_KIB
...
Change-Id: I2360a1a79f07ff8466ed01aa7f180d410e019292
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2022-07-05 13:07:08 +00:00
772ca3cc00
mb/google/brask/variants/moli: set tcc_offset to 0℃
...
Set tcc_offset value to 0 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com >
Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
2022-07-05 13:06:45 +00:00
fa7970aa81
mb/starlabs/labtop/tgl: Nit - minor format change
...
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-05 13:06:32 +00:00
2eb2dcebc7
mb/starlabs/labtop: Define CCD Port in Kconfig
...
Define the CCD (aka "Webcam") USB port in the devicetree as
it is used in multiple places. It is used in devtree to
disable it based on the CMOS setting "webcam", and in the
devicetree to configure the port tuning.
This also corrects the port that is disabled on CML, from
usb2_port[6] to usb2_port[3].
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I16e368fc7965f978f2302633122ba63038603c1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64704
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-05 13:06:21 +00:00
2e21725fd5
mb/starlabs/labtop/tgl: Organise USB ports by hardware port
...
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
This also removes usb3_port[2] as it is not connected and fixes the labelling of usb3_port[0] and usb3_port[1].
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I7923fc00c36687a7f89d863eb0ea4e01a036502d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-07-05 13:05:22 +00:00
a6accb580c
mb/starlabs/lite/glk: Update Vbt
...
Update the Vbt to disable the fixed mode feature, to allow for
bootloader resolutions higher than 1920x1080.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-07-05 00:40:09 +00:00
f777cad791
mb/google/nissa: Lock gpio pins in fw config for nissa variants
...
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: Ieed2d40b0222d8c8c193e0590131f83a5d96add9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Reka Norman <rekanorman@chromium.org >
2022-07-05 00:39:41 +00:00
cd4264fbe7
mb/google/nissa: Lock gpio pins for nissa variants
...
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Reka Norman <rekanorman@chromium.org >
2022-07-05 00:39:14 +00:00
1b44c81d3d
soc/intel/alderlake: RPL-P power limits and VR settings
...
This patch sets the Power Limits and Voltage Regulator settings for
three RaptorLake SKUs (45W, 28W and 15W) following the guidance from
document 686872 (June 7th edition).
BUG=b:237809660
TEST=Power Limit and VR serial logs review + debug instrumentation
SKUs successfully booted
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com >
Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Cliff Huang <cliff.huang@intel.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2022-07-04 14:13:15 +00:00
7c60068b23
mb/qemu-i440fx,soc/nvidia: Fix coverity reported defects
...
In reality the expression should not overflow as the value
fits in 32 bits.
Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2022-07-04 14:11:06 +00:00
cb08c7937d
soc/intel/alderlake: remove unnecessary test condition
...
mch_id is set to zero and then unnecessarily tested.
TEST=build and boot image on ADL RVP board
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com >
Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-07-04 14:09:13 +00:00
97074645b3
soc/intel/alderlake/fsp_params.c: Handle CnviWifiCore parameter
...
Platform with public FSP hooked-up have an additional parameter
to control CNVi WiFi with CnviWifiCore UPD.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-07-04 14:08:24 +00:00
073779b5ef
soc/intel/alderlake: Hook up ADL-P and ADL-S public FSP
...
Update 3rdparty/fsp submodule to include AlderLake FSP.
Hook up the Kconfig settings to point to Fsp.fd and headers for
ADL-S and ADL-P platforms which the FSP has been published for.
The FSP binaries are compliant with the specification revision 2.3
so update these settings accordingly.
Although FSP header is v2.3 compliant, the features set of the FSP
v2.3 is not being met.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-04 14:07:44 +00:00
23ddcb0bc4
mb/google/brya: Disable PCH USB2 phy power gating for crota
...
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237725329
TEST=Verify the build for crota board
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com >
Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-07-04 14:06:16 +00:00
bc8ab7bf6e
mb/google/brya/var/kinox: Change HDMI port form DDPC to DDP2
...
Modify GPIOs according to SOC_GPIO_Table_0629.xlsx.
- GPP_A21 from TCP_DP1_CTRLCLK to NC
- GPP_A22 from TCP_DP1_CTRLDATA to NC
- GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1)
- GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1)
BUG=b:237468533
TEST=emerge-brask coreboot
Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Ricky Chang <rickytlchang@google.com >
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
2022-07-04 14:04:38 +00:00
42dae32e6c
mb/google/nissa: Lock PLT_RST_L pin
...
There is a requirement that the TPM RST signal cannot be asserted by
software. On nissa this is PLT_RST_L, so lock this pin to prevent it
being reconfigured as a GPIO.
BUG=b:216671701
TEST=Try to change GPP_B13 from the kernel:
$ echo 677 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/gpio677/direction
$ echo 0 > /sys/class/gpio/gpio677/value
$ echo 1 > /sys/class/gpio/gpio677/value
GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED"
Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688
Signed-off-by: Reka Norman <rekanorman@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
2022-07-04 14:04:18 +00:00
5d9b8a9632
mb/google/nissa/var/craask: Enable G2 touchscreen
...
Add G2 touchscreen support for craaskvin.
BUG=b:235919755
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com >
Change-Id: I7ade3ac1d135b8b21b09ef335ab7b30ae7a5e2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Reka Norman <rekanorman@chromium.org >
2022-07-04 14:03:59 +00:00
36f655456b
mb/google/nissa/var/joxer: set up gpio
...
Set the GPIO configuration of joxer
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com >
Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Reka Norman <rekanorman@chromium.org >
2022-07-04 14:03:46 +00:00
d3f859d5e5
soc/qualcomm/sc7180: Update hardware watchdog logging
...
Move watchdog functionality to common folder.
BUG=b:221393157
TEST=None
Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com >
Change-Id: Ib2f7f21ce991fd8193329e7b8260e58e47bf39c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2022-07-04 14:03:21 +00:00
05d135e6b0
mb/google/brask/var/kuldax: Add ACPI _PLD custom values
...
This patch uses ACPI _PLD macros to add custom values for USB ports.
C0 A2 A3
+----------------+
| REAR |
| |
| |
| |
| FRONT |
+----------------+
A1 A0
BUG=b:232419500
TEST=emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I5ada4e9b25102a9cfd3b02a2abcd956f6cbc5619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Won Chung <wonchung@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-07-04 14:02:38 +00:00
c4e90454f4
treewide: Unify Google branding
...
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-07-04 14:02:26 +00:00
dc86804a7d
src/driver/intel/mipi_camera: Update ACPI entry to provide silicon info
...
CPUID_RAPTORLAKE_P_Q0 is ES. Add it to generate is_es = 1 in ACPI
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon
Signed-off-by: zhixingma <zhixing.ma@intel.com >
Change-Id: I67d70dc7e916a4818869aef86e7e642b66ea5dae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2022-07-04 14:02:08 +00:00
50786cc2c8
mb/amd/bilby: Add PSP NVRAM and RPMC NVRAM region to flash map
...
Create PSP NVRAM and RPMC NVRAM region with size 128K & 64K
respectively, which are supported region by the PSP.
moved CBFS up due to build error, CBFS need not to be at the end the flash for amd Zen cpu.
Change-Id: Ide778c61a755697c1bef1eaa87f2976d8ff12eb6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-07-04 14:01:48 +00:00
d3dae3deb6
soc/amd/sabrina: Add support for Rembrandt SoC as base SoC
...
This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.
Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-07-04 14:00:55 +00:00
c6d0a4c1a8
mb/google/brya/var/kano: Disable PCH USB2 phy power gating
...
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for kano board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I19430a68e1e847e71382781563200a4c88f37a59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com >
2022-07-04 13:59:59 +00:00
d69158d17a
mb/google/brya/var/pujjo: Add GPIO table
...
Fill GPIO table for Pujjo.
BUG=b:235774770
TEST=emerge-nissa coreboot
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com >
Change-Id: I307b8460632f1feae9591200057c0e6471cbab24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65104
Reviewed-by: Reka Norman <rekanorman@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-04 13:59:44 +00:00
8dcc651806
mb/google/brya/var/ghost4adl: Update Type-C locations
...
This updates the ACPI locations of Type-C ports.
BUG=b:232806406
TEST=none
Change-Id: Ia15e09a58c731a1364a994fadf8df39115fbe7c4
Signed-off-by: Caveh Jalali <caveh@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-07-04 13:59:32 +00:00
db8442b10a
mb/google/geralt: Add MediaTek MT8188 reference board
...
Add mainboard folder and drivers for new reference board 'Geralt'.
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com >
Change-Id: I5e437d46097369bef535ff64e6a693b7cf67f2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65586
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yidi Lin <yidilin@chromium.org >
2022-07-04 08:36:02 +00:00
3f83c6ff85
soc/mediatek/mt8188: Add a stub implementation of the MT8188 SoC
...
Add new folder and basic drivers for Mediatek SoC 'MT8188'.
Difference of modules including in this patch between MT8188 and
existing SoCs:
Timer:
Similar to MT8195 and MT8186, MT8188 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
The implementation is based on these files:
MT8188G_Application Processor Technical Brief_v0.4.pdf
MT8188G_Functional Specification v0.4.pdf
MT8188 Application Processor Registers-1.pdf
MT8188 Application Processor Registers-2.pdf
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com >
Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yidi Lin <yidilin@chromium.org >
2022-07-04 08:35:53 +00:00
e88bee7219
soc/intel/meteorlake: Use coreboot native event handler for FSP-M/S
...
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-03 04:57:58 +00:00
8206741a06
vc/intel/fsp2_0: Add UPDs into the FSP partial header version 2222
...
This patch adds below UPDs into the existing FSP partial header v2222.1
FSP-M UPD:
DisableMc0Ch0
DisableMc0Ch1
DisableMc0Ch2
DisableMc0Ch3
DisableMc1Ch0
DisableMc1Ch1
DisableMc1Ch2
DisableMc1Ch3
DdrFreqLimit
GpioOverride
SerialIoUartDebugMode
SerialDebugMrcLevel
SmbusDynamicPowerGating
WdtDisableAndLock
SaIpuEnable
SkipCpuReplacementCheck
TcssDma0En
TcssDma1En
VtdBaseAddress
CpuCrashLogDevice
CpuCrashLogEnable
LCT
TdcEnable
TdcTimeWindow
Lp5CccConfig
RMTBIT
RmtPerTask
RMTLoopCount
MrcFastBoot
EnCmdRate
SaGvGear
TAT
PchHdaVcType
BdatTestType
RdEnergyMc0Ch0Dimm1
RdEnergyMc0Ch0Dimm0
CorePllVoltageOffset
RdEnergyMc1Ch1Dimm1
RdEnergyMc1Ch1Dimm0
DciEn
PchPort80Route
ActEnergyMc0Ch1Dimm1
ActEnergyMc0Ch1Dimm0
HeciCommunication2
PcdSerialDebugBaudRate
HeciTimeouts
ThrtCkeMinDefeatLpddr
PchPcieHsioRxSetCtle
BdatEnable
DisableCpuReplacedPolling
PchSataHsioRxGen1EqBoostMagEnable
CoreVoltageOffset
PchPcieHsioTxGen1DownscaleAmp
PchHdaDspUaaCompliance
VddVoltage
WRVC1D
PreBootDmaMask
tWR
RingVoltageAdaptive
PchSataHsioTxGen3DeEmphEnable
PchPcieHsioRxSetCtleEnable
RingPllVoltageOffset
OcSupport
WrEnergyMc0Ch0Dimm1
PdEnergyMc1Ch1Dimm1
PdEnergyMc1Ch1Dimm0
DmiGen3ProgramStaticEq
SmramMask
tRAS
PerCoreHtDisable
IdleEnergyMc1Ch0Dimm0
IdleEnergyMc1Ch0Dimm1
Gen3LtcoEnable
tWTR
RCVET
DmiGen3UsPresetEnable
tCWL
PwdwnIdleCounter
WRTC1D
CLKTCO
PrimaryDisplay
DisableMessageCheck
tFAW
PchSataHsioTxGen2DeEmphEnable
SerialIoUartDebugRtsPinMux
GtExtraTurboVoltage
TXTCO
PchSataHsioTxGen3DownscaleAmp
CpuRatioOverride
PostCodeOutputPort
DmiHweq
CoreVfPointCount
NModeSupport
Ddr4DdpSharedZq
RdEnergyMc1Ch0Dimm0
RdEnergyMc1Ch0Dimm1
PchSataHsioTxGen2DownscaleAmp
DebugInterfaceEnable
WrEnergyMc0Ch1Dimm0
WrEnergyMc0Ch1Dimm1
SaPllVoltageOffset
DmiGen3EndPointPreset
PchSataHsioRxGen2EqBoostMag
VDDQT
PvdRatioThreshold
CoreVfPointOffsetMode
DmiGen3DsPortRxPreset
BclkRfiFreq
SmbusArpEnable
PowerDownMode
DebugInterfaceLockEnable
RingVoltageOffset
EnableExtts
SerialIoUartDebugCtsPinMux
PchPcieHsioTxGen2DownscaleAmpEnable
Avx2VoltageScaleFactor
GearRatio
GtVoltageOverride
EccSupport
RingMaxOcRatio
TrainTrace
EnablePwrDn
IsTPMPresence
OcLock
DmaBufferSize
SOT
CoreVfPointRatio
PchPcieHsioTxGen2DownscaleAmp
TjMaxOffset
CoreMaxOcRatio
RingDownBin
PchSataHsioRxGen1EqBoostMag
BiosAcmSize
tRFC
PchPcieHsioTxGen1DownscaleAmpEnable
PdEnergyMc0Ch1Dimm0
PdEnergyMc0Ch1Dimm1
RDMPRT
TxtLcpPdBase
CMDVC
SerialIoUartDebugBaudRate
PchTraceHubMemReg1Size
CoreVoltageOverride
McPllVoltageOffset
PdEnergyMc1Ch0Dimm0
PdEnergyMc1Ch0Dimm1
GttMmAdr
PchPcieHsioTxGen1DeEmphEnable
ApStartupBase
CoreVoltageAdaptive
GtVoltageMode
PcieImrRpSelection
TxtLcpPdSize
PchPcieHsioTxGen2DeEmph3p5
ThrtCkeMinTmr
RealtimeMemoryTiming
UserBudgetEnable
PchPcieHsioTxGen3DownscaleAmpEnable
GmAdr
PchSataHsioTxGen1DeEmphEnable
CrashLogGprs
tRTP
RMC
PchSataHsioTxGen3DownscaleAmpEnable
RDODTT
RDVREFDC
PerCoreRatio
IdleEnergyMc0Ch1Dimm1
tRCDtRP
DidInitStat
SerialIoUartDebugRxPinMux
SerialIoUartDebugMmioBase
BiosSize
MmioSizeAdjustment
PchTraceHubMode
DmiGen3Ltcpre
CoreVoltageMode
DmiGen3UsPortTxPreset
Gen3EqPhase3Bypass
BclkSource
KtDeviceEnable
DciUsb3TypecUfpDbg
CoreVfPointOffset
Gen3RtcoRtpoEnable
TotalFlashSize
BclkAdaptiveVoltage
TvbRatioClipping
EnablePwrDnLpddr
WRTC2D
RankInterleave
PchSataHsioRxGen3EqBoostMag
IdleEnergyMc0Ch0Dimm1
IdleEnergyMc0Ch0Dimm0
Ratio
JWRL
Avx3RatioOffset
Avx2RatioOffset
RDVC1D
DCC
PchSataHsioTxGen2DeEmph
ExitOnFailure
IdleEnergyMc1Ch1Dimm1
IdleEnergyMc1Ch1Dimm0
RingVoltageOverride
SpdProfileSelected
ScramblerSupport
SaGvFreq
WRVC2D
DmiGen3EqPh3Method
CMDSR
RdEnergyMc0Ch1Dimm0
RdEnergyMc0Ch1Dimm1
UserThresholdEnable
ThrtCkeMinDefeat
DmiGen3EqPh2Enable
tRRD
ChHashEnable
BistOnReset
ChHashInterleaveBit
RemapEnable
RDVC2D
DIMMRONT
WrEnergyMc0Ch0Dimm0
DmiAspm
PchPcieHsioTxGen2DeEmph6p0Enable
PchSataHsioTxGen1DeEmph
RDEQT
TxtDprMemoryBase
WrEnergyMc1Ch0Dimm1
WrEnergyMc1Ch0Dimm0
DmiGen3EndPointHint
CleanMemory
PchSmbAlertEnable
SaOcSupport
PchSataHsioTxGen3DeEmph
TxtImplemented
CoreVfPointOffsetPrefix
PchHdaTestPowerClockGating
DmaControlGuarantee
DIMMODTT
ERDMPRTC2D
RootPortIndex
SkipStopPbet
VtdIopEnable
DmiGen3DsPortTxPreset
ActiveCoreCount
PchLpcEnhancePort8xhDecoding
GtVoltageOffset
DisPgCloseIdleTimeout
ActEnergyMc1Ch0Dimm1
ActEnergyMc1Ch0Dimm0
Idd3n
Idd3p
PchSataHsioTxGen1DownscaleAmpEnable
BClkFrequency
ActEnergyMc0Ch0Dimm0
ActEnergyMc0Ch0Dimm1
DdrFreqLimit
Gen3EqPhase23Bypass
WrEnergyMc1Ch1Dimm0
DmiGen3DsPresetEnable
PcieImrSize
EWRTC2D
IbeccOperationMode
VtdBaseAddress
TvbVoltageOptimization
DciDbcMode
HobBufferSize
PchHdaSdiEnable
PcieImrEnabled
IdleEnergyMc0Ch1Dimm0
SerialIoUartDebugAutoFlow
tCL
PdEnergyMc0Ch0Dimm1
PdEnergyMc0Ch0Dimm0
RDTC2D
ERDTC2D
SerialIoUartDebugParity
PchPcieHsioTxGen2DeEmph3p5Enable
PchPcieHsioTxGen1DeEmph
DmiGen3Ltcpo
PchSmbusIoBase
RaplPwrFlCh1
RaplPwrFlCh0
EnhancedInterleave
PchPcieHsioTxGen2DeEmph6p0
MemTestOnWarmBoot
Ibecc
PanelPowerEnable
BiosAcmBase
DmiGen3UsPortRxPreset
DmiAspmL1ExitLatency
CmdMirror
PchSataHsioTxGen2DownscaleAmpEnable
tREFI
CpuBclkOcFrequency
CridEnable
EpgEnable
SmbusSpdWriteDisable
DdrSpeedControl
PchSataHsioRxGen2EqBoostMagEnable
GtMaxOcRatio
DmiMaxLinkSpeed
PchSataHsioRxGen3EqBoostMagEnable
PcieImrRpLocation
CmdRanksTerminated
SkipMbpHob
SerialIoUartDebugTxPinMux
PchSataHsioTxGen1DownscaleAmp
PchPcieHsioTxGen3DownscaleAmp
PerCoreRatioOverride
PchHdaAudioLinkDmicClockSelect
SerialIoUartDebugDataBits
SrefCfgEna
Avx512VoltageScaleFactor
MmioSize
SaVoltageOffset
SaIpuEnable
ActEnergyMc1Ch1Dimm0
ActEnergyMc1Ch1Dimm1
ProbelessTrace
VtdIgdEnable
ALIASCHK
PchTraceHubMemReg0Size
DIMMODTCA
TgaSize
EWRDSEQ
SerialIoUartDebugStopBits
RDTC1D
CMDNORM
RingVoltageMode
EnableAbove4GBMmio
WrEnergyMc1Ch1Dimm1
Txt
PcieMultipleSegmentEnabled
CnviDdrRfim
FSP-S UPD:
CpuMpPpi
LidStatus
ITbtConnectTopologyTimeoutInMs
D3HotEnable
D3ColdEnable
PchLockDownGlobalSmi
PchLockDownBiosInterface
PchUnlockGpioPads
RtcMemoryLock
SkipPamLock
EndOfPostMessage
CpuUsb3OverCurrentPin
PcieRpHotPlug
SerialIoUartAutoFlow
TccActivationOffset
VmdEnable
Enable8254ClockGating
Enable8254ClockGatingOnS3
HybridStorageMode
PcieRpHotPlug
Hwp
Cx
PsOnEnable
EnergyEfficientTurbo
PchPmDisableEnergyReport
UfsEnable
FspEventHandler
GnaEnable
VbtSize
PcieComplianceTestMode
CStatePreWake
SerialIoUartDataBits
SataPortsExternal
CstateLatencyControl0TimeUnit
SataP0Tinact
PmcV1p05PhyExtFetControlEn
ApIdleManner
SataPortsSpinUp
DisableProcHotOut
ITbtPcieTunnelingForUsb4
SerialIoUartDmaEnable
SaPcieItbtRpNonSnoopLatencyOverrideMode
SaPcieItbtRpSnoopLatencyOverrideMode
MlcSpatialPrefetcher
PchXhciOcLock
PmcPowerButtonDebounce
TccOffsetClamp
LogoPixelWidth
AvxDisable
Custom1PowerLimit1
Custom1PowerLimit2
PmcCpuC10GatePinEnable
PchPmSlpStrchSusUp
IshI2cSdaPadTermination
Custom2PowerLimit1Time
RtcBiosInterfaceLock
WatchDogTimerBios
SataP1TDisp
PchPciePort8xhDecodePortIndex
PcieRpImrSelection
TcCstateLimit
PchS0ixAutoDemotion
PchFivrExtV1p05RailEnabledStates
PcieRpSlotPowerLimitScale
IshUartCtsPinMuxing
PcieRpSnoopLatencyOverrideMode
TTCrossThrottling
PsysPowerLimit1
SataRstInterrupt
IshSpiClkPadTermination
PcieEnablePeerMemoryWrite
SataP1T2M
ChipsetInitBinPtr
LogoPixelHeight
PsysPowerLimit1Time
HwpInterruptControl
DevIntConfigPtr
IshUartRtsPadTermination
PsysPowerLimit1Power
EnergyEfficientTurbo
Custom3TurboActivationRatio
PcieDpc
TurboMode
PchFivrExtVnnRailSupportedVoltageStates
ITbtDmaLtr
IshSpiClkPinMuxing
PchSbAccessUnlock
PcieRpSystemErrorOnCorrectableError
PcieRpSlotPowerLimitValue
SendEcCmd
SataSpeedLimit
SataRstPcieEnable
PchUsb3HsioCtrlAdaptOffsetCfg
SataP0T2M
PchHdaVerbTableEntryNum
DmiTS1TW
DmiTS2TW
PcieRpImrEnabled
GpioIrqRoute
SataPortsSolidStateDrive
RaceToHalt
PcieRpNonSnoopLatencyOverrideMultiplier
PcieRpUnsupportedRequestReport
AesEnable
PchFivrExtVnnRailSxVoltage
SataP1Tinact
PkgCStateUnDemotion
SataPortsZpOdd
PchSerialIoI2cPadsTermination
PchFivrExtV1p05RailSupportedVoltageStates
PchUsbLtrLowIdleTimeOverride
IshSpiMosiPinMuxing
PchProtectedRangeLimit
SaPcieItbtRpNonSnoopLatencyOverrideValue
SataP1T3M
PchPmWoWlanEnable
IshUartRtsPinMuxing
SataLedEnable
VmdGlobalMapping
PcieRpEnableCpm
IshGpGpioPadTermination
PchDmiCwbEnable
ForcMebxSyncUp
FspEventHandler
PchFivrExtVnnRailIccMax
PchPmMeWakeSts
DisableD0I3SettingForHeci
PcieRpNonSnoopLatencyOverrideMode
PmgCstCfgCtrlLock
PchUsbLtrHighIdleTimeOverride
Usb3HsioTxRate2UniqTran
SiNumberOfSsidTableEntry
IshSpiMisoPadTermination
IshUartRxPadTermination
PcieRpSlotImplemented
PchUsbOverCurrentEnable
EndOfPostMessage
SaPcieItbtRpSnoopLatencyOverrideValue
EnableHwpAutoEppGrouping
SerialIoUartDbg2
ConfigTdpLock
EsataSpeedLimit
PchTsnEnable
PowerLimit3DutyCycle
TTSuggestedSetting
PchEnableDbcObs
IehMode
VmdPort
PchFivrExtVnnRailCtrlRampTmr
PchPmSlpAMinAssert
CstateLatencyControl5TimeUnit
ProcessorTraceEnable
ChipsetInitBinLen
PchTemperatureHotLevel
Usb3HsioTxRate3UniqTranEnable
NumberOfEntries
Custom2ConfigTdpControl
PowerLimit3Lock
SiCustomizedSsid
PchUsb3HsioFilterSelP
DisableVrThermalAlert
PchIoApicEntry24_119
SmbiosType4MaxSpeedOverride
PowerLimit3Time
C1StateUnDemotion
PchDmiAspmCtrl
PchUsb3HsioFilterSelN
PchTTEnable
PcieRpNoFatalErrorReport
Custom1ConfigTdpControl
PmcC10DynamicThresholdAdjustment
PchFivrVccinAuxRetToLowCurModeVolTranTime
BiProcHot
VmdPortFunc
PchUsb3HsioFilterSelNEnable
PchHdaVerbTablePtr
TurboPowerLimitLock
PcieRpSystemErrorOnNonFatalError
PmcUsb2PhySusPgEnable
PcieRpSystemErrorOnFatalError
PchProtectedRangeBase
VccSt
PchFivrExtVnnRailSxEnabledStates
EnableHwpAutoPerCorePstate
CstateLatencyControl1TimeUnit
SaPcieItbtRpSnoopLatencyOverrideMultiplier
PchPmSlpS4MinAssert
PcieRpTransmitterHalfSwing
Usb3HsioTxRate3UniqTran
RenderStandby
ProcessorTraceOutputScheme
SkipFspGop
PchHdaPme
EcCmdProvisionEav
BgpdtHash
Usb3HsioTxRate0UniqTran
UsbOverride
PkgCStateDemotion
EnableAllThermalFunctions
PchPmWolEnableOverride
IshSpiCsPinMuxing
PchIshSpiCsEnable
IshUartCtsPadTermination
PmcV1p05IsExtFetControlEn
MaxRingRatioLimit
PchIshPdtUnlock
IshUartTxPinMuxing
PchFivrExtV1p05RailIccMax
BiosGuardAttr
LogoPtr
CpuBistData
ShowSpiController
PchPmWolOvrWkSts
SataP0T1M
CstCfgCtrIoMwaitRedirection
TcoIrqEnable
PchHdaLinkFrequency
ITbtForcePowerOnTimeoutInMs
SerialIoSpiCsEnable
VmdMemBar2Base
TStates
SiSkipSsidProgramming
TccOffsetTimeWindowForRatl
AmtSolEnabled
PchUsb3HsioCtrlAdaptOffsetCfgEnable
PchFivrExtVnnRailIccMaximum
PchEspiLgmrEnable
SkipPamLock
IshGpGpioPinMuxing
PchUsb3HsioFilterSelPEnable
PchFivrExtVnnRailVoltage
SataPortsDevSlpResetConfig
ProcHotLock
PchDmiTsawEn
SerialIoSpiCsPolarity
PkgCStateLimit
EnableRsr
PmcDbgMsgEn
PchPmPwrCycDur
NumOfDevIntConfig
SerialIoSpiDefaultCsOutput
PchPmPciePllSsc
PxRcConfig
CstateLatencyControl4TimeUnit
PcieRpPmSci
ConfigTdpBios
PmcPdEnable
PchT1Level
PmcModPhySusPgEnable
DisableTurboGt
EnableTcoTimer
IshSpiMisoPinMuxing
IshI2cSclPinMuxing
PcieRpCorrectableErrorReport
C1StateAutoDemotion
PchEspiLockLinkConfiguration
PchFivrExtV1p05RailCtrlRampTmr
SataRstPcieStoragePort
PchFivrExtV1p05RailVoltage
PchPmSlpSusMinAssert
PchHotEnable
PcieRpNonSnoopLatencyOverrideValue
TcoIrqSelect
PcieRpCompletionTimeout
FwProgress
StateRatioMax16
ConfigTdpLevel
IshI2cSdaPinMuxing
PcieRpPhysicalSlotNumber
SerialIoUartParity
TxtEnable
PchLegacyIoLowLatency
PchUsbLtrMediumIdleTimeOverride
PchPmPmeB0S5Dis
SerialIoUartPowerGating
PcieRpSnoopLatencyOverrideValue
PchPmSlpLanLowDc
PchT2Level
CstateLatencyControl2TimeUnit
PchPmSlpS3MinAssert
PchUsb3HsioOlfpsCfgPullUpDwnResEnable
MonitorMwaitEnable
Usb3HsioTxRate1UniqTran
Eist
IshSpiMosiPadTermination
PowerLimit4Lock
Custom3PowerLimit1Time
PcieEnablePort8xhDecode
DualTauBoost
WatchDogEnabled
MaxRatio
Custom2TurboActivationRatio
PchFivrExtVnnRailEnabledStates
ApplyConfigTdp
IshI2cSclPadTermination
PowerLimit2Power
ThermalMonitor
CpuUsb3OverCurrentPin
PchTTLock
Custom1PowerLimit1Time
PchEspiHostC10ReportEnable
Usb3HsioTxRate2UniqTranEnable
SataPortsInterlockSw
EnablePerCorePState
PsysPowerLimit2Power
UfsEnable
PchPmDisableNativePowerButton
VmdVariablePtr
Custom3PowerLimit2
PchPmDisableEnergyReport
Custom3PowerLimit1
DmiTS3TW
EnforceEDebugMode
CstateLatencyControl3TimeUnit
VmdCfgBarBase
DmiSuggestedSetting
SataPortsEnableDitoConfig
SerialIoUartBaudRate
Usb3HsioTxRate1UniqTranEnable
SataPortsHotPlug
MachineCheckEnable
Custom1TurboActivationRatio
Custom2PowerLimit1
Custom2PowerLimit2
VmdMemBar1Base
SaPcieItbtRpLtrConfigLock
SataP0TDispFinit
PchFivrExtVnnRailSxIccMaximum
PchTsnLinkSpeed
SataThermalSuggestedSetting
SaPcieItbtRpLtrEnable
TimedMwait
PchTsnMultiVcEnable
PcieRpFunctionSwap
PcieEqOverrideDefault
SataP1T1M
PsysPowerLimit2
PchLanLtrEnable
SerialIoUartStopBits
SciIrqSelect
C1e
PchFivrExtVnnRailSxIccMax
PowerLimit3
PowerLimit2
PowerLimit1
MeUnconfigOnRtcClear
PcieRpPcieSpeed
PchUsbLtrOverrideEnable
UsbPdoProgramming
Custom3ConfigTdpControl
SataP1TDispFinit
PchFivrDynPm
VmdPortDev
EnableItbm
MinRingRatioLimit
PcieRpFatalErrorReport
MctpBroadcastCycle
EcCmdLock
StateRatio
PchPmVrAlert
DmiTS0TW
LogoSize
PchIoApicId
SaPcieItbtRpForceLtrOverride
PcieRpSnoopLatencyOverrideMultiplier
IshUartTxPadTermination
PchCrid
SataRstPcieDeviceResetDelay
ProcHotResponse
BltBufferSize
MlcStreamerPrefetcher
PcieRpLtrConfigLock
SiSsidTablePtr
SataP0TDisp
PchUsb3HsioOlfpsCfgPullUpDwnRes
BltBufferAddress
PcieRpDetectTimeoutMs
PpinSupport
SataRstRaidDeviceId
PchPmLatchEventsC10Exit
IshUartRxPinMuxing
PpmIrmSetting
EnergyEfficientPState
PchFivrExtV1p05RailIccMaximum
PortResetMessageEnable
PchReadProtectionEnable
BiosGuardModulePtr
PchWriteProtectionEnable
AmtEnabled
PchHdaCodecSxWakeCapability
SiCustomizedSvid
PcieEdpc
TccOffsetLock
PchPmPwrBtnOverridePeriod
SaPcieItbtRpNonSnoopLatencyOverrideMultiplier
WatchDogTimerOs
PchTTState13Enable
PowerLimit1Time
PchT0Level
IshSpiCsPadTermination
SataP0T3M
Usb3HsioTxRate0UniqTranEnable
SataTestMode
PmcOsIdleEnable
PowerLimit4
PcieRpAcsEnabled
PavpEnable
UsbTcPortEn
Additionally, optimize the `reserved` fields across header files.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I976a5762701711fbf000c43c5ff05f9bd93f688f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-03 04:57:33 +00:00
abc59fb6fc
mb/google/rex: Redirect AP UART over LPSS UART 0
...
This patch ensures AP UART messages are coming over LPSS UART 0 hence,
select required kconfig and program both early and late UART
RX/TX GPIOs accroding to the rex schematics dated 06/27.
BUG=b:224325352
TEST=Able to see AP UART log over LPSS UART0.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:24:55 +00:00
a26760c047
mb/google/rex: Generate LP5 RAM ID
...
Add the support LP5 RAM parts for rex:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:224325352
TEST=emerge-rex coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Ibcd25ae80d625b623b9a78ff2cd4447e85831cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65476
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:24:34 +00:00
67219f7331
mb/google/rex: Add memory init
...
Add memory init with placeholder to fill in required memory
configuration parameters. DQ map and Rcomp can be auto probed by
the FSP-M hence, kept it as default.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Able to boot till FSP-M/MRC using MTL simics.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:24:16 +00:00
8481056a53
mb/google/rex: Add EC smihandler
...
Add SMI handler implementation to manage power cycle,
power state transition and Chrome EC events.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I10aab8257fce92aaf913a53c0c9fb6c1a4f5dea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64623
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:24:07 +00:00
366fba27a8
mb/google/rex: Enable building for Chrome OS
...
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:23:58 +00:00
7c304f8d34
mb/google/rex: Enable EC
...
Perform EC initialization in bootblock and ramstages. Add associated
ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:23:45 +00:00
7a294be356
mb/google/rex: Enable ACPI and add ACPI table
...
Enable ACPI configuration and add DSDT ACPI table.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:23:38 +00:00
5c02779ec8
mb/google/rex: Add GPIO stubs
...
Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock, romstage and ramstage.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-07-01 07:23:27 +00:00
