<device/mmio.h> is supposed to chain-include <arch/mmio.h>. See
`Documentation/contributing/coding_style.md` section `Headers and includes`
Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
`gpio_calc_eint_pos_bit`.
- Implement `gpio_get_eint_reg` to obtain EINT base address.
This change is prepared for the driver change in MT8196.
BUG=b:334723688
TEST=EINT works on Geralt
Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
and Stoneyridge which don't use/support this.
If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file,
the start and length of it in the flash will be passed to amdfwtool
which then adds the base and length to the corresponding type 0x54 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83815
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Devicetree for lenovo/520 is missing USB ports config, hence they
don't work. This change introduces USB port config.
Tests performed:
- Can select a boot media using a USB keyboard from any port.
- Can boot from each port except usb@1:1.1.
- Measured read speed from a thumb drive on each port 24.5-28.9 MiB/s.
Change-Id: I96dba153a563e0e290b96b837fdca39d7598ef17
Signed-off-by: PuFF1k <exopuf@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the tracehub driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is
reserved.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since a generic ITE GPIO driver is available and in use, the existence
of chips-specific drivers no longer make sense. Remove the dead code
in favor of generic GPIO driver.
Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:350844195
TEST=emerge-nissa coreboot
boot with G2 TS, make sure G2 TS is functional.
Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.
* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
as before.
Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.
BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:
1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""
Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.
Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.
* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
* `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
* `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.
BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.
Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This change enables storing the ISH firmware version on the Trulo
baseboard by selecting the `SOC_INTEL_STORE_ISH_FW_VERSION` config
option.
BUG=b:354607924
TEST=Able to dump ISH version on trulo.
> cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.7780
Change-Id: I69a7fa19c53f435ef1f6306b259f703c7b196137
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83820
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC
PMC IPC Command to read and print Intel SoC QDF information using PMC
interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is
supported from Panther Lake SoC.
QDF is a four digit code that can be used to identify enabled features
and capabilities. This information will be useful to debug issues
found during the development phase and in the field as well.
Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83784
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Official EDK2 repository has VARIABLE_SUPPORT defaulting to EMU in
UefiPayloadPkg, switch it to SMMSTORE if coreboot is built with
SMMSTOREv2.
This removes custom default of EDK2_CUSTOM_BUILD_PARAMS for
EDK2_REPO_MRCHROMEBOX which is unnecessary now.
Change-Id: Ic59f89c0f708f9b144bd35cd18870d0e1c65677d
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83737
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
which doesn't use/support this. This was previously only implemented for
Picasso, but not for the SoCs that support this, so add the support to
those other SoCs as well.
If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the
start and length of it in the flash will be passed to amdfwtool which
then adds the base and length to the corresponding type 0x04 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83814
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Currently a warning is printed even if the maximum amount of nodes is
not exceeded.
Remove the warning, since in most cases the maximum amount of nodes
for a given prefix is usually well known. For example the /cpu nodes
always have a maximum of CONFIG_MAX_CPUS.
One may also just want to read the first X amount of nodes matching a
given prefix.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic1111e8acb72ea1e9159da0d8386f40cbbdbc63f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Before 'handle_psp_command' calls any of the functions in this file, it
make sure that the 'size' field in the command buffer's header doesn't
indicate that the command buffer is larger than the SMM memory region
reserved for it.
The read/write command buffer has a 'num_bytes' field to indicate how
many bytes should be read from the SPI flash and put into the data
buffer within the command buffer or how many bytes from this buffer
should be written to the flash. While we should be able to assume that
the PSP won't send us malformed command buffer, we should still better
check this just to be sure.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e8514eedc3ad154a705c8a1e85d367e452dbed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83778
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use coreboot's SPI flash access infrastructure to do the flash read,
write, or erase operations as requested from the PSP.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I4957a6d316015cc7037acf52facb6cc69188d446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Detect the block size of the SPI flash and number of flash blocks
reserved for the flash region corresponding to the 'target_nv_id' field
in the command buffer. This information is then written to the
corresponding fields in the command buffer. Since detecting the flash
chip still might result in accesses to it, make sure that it's available
for use and not currently used by an OS driver. Since this code is
inside the SMI handler, we don't have to worry about this code to be
interrupted, so we don't need to set some bit to tell other code that
we're currently using the SPI controller in the SMI handler.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83776
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI_SEMAPHORE_DRIVER_LOCKED bit in the SPI_MISC_CNTRL register
doesn't affect the hardware, but it re-used by AMD as a semaphore to
synchronize the access to the SPI controller between SMM and non-SMM
software like an OS-level driver. Since it doesn't affect the hardware,
it's marked as reserved in the PPRs. Add the 'spi_controller_available'
helper function to check this bit to see if some software or driver
outside of SMM is currently using the SPI flash controller to avoid
interfering with that operation.
This patch is a slightly reworked version of parts of CB:65523.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83775
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 'find_psp_spi_flash_device_region' to get a pointer to the spi_flash
struct of the SPI flash used in the system and the region_device struct
for the target FMAP region specified by the target NV ID from the PSP
to x86 mailbox command. In order to have small patches, the newly added
static 'find_psp_spi_flash_device_region' function is marked as inline;
that inline will be removed in a following patch that calls this new
function.
This patch is a slightly reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I64b8fba2392de46ecd4c786cef0d5b6acdbd865a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83774
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add and use functions to validate the target non-volatile storage ID in
the different command buffer structs.
This patch is a slightly reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: Idda0166c862d41d380b2ed21345eead5e0a1c135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83758
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the PSP wants to access the SPI flash during runtime, but isn't the
owner of the SPI flash controller, it sends an SMI to the x86 side. The
corresponding SMI handler then checks the P2C (PSP to core) mailbox for
the command and data, processes the command, and if needed puts the
requested data into the P2C buffer.
The P2C mailbox is a memory region in TSEG aka SMM memory. Both location
and size are communicated to the PSP via the PSP SMM info mailbox
command which is sent right after mpinit is done.
This commit adds the code to access the P2C mailbox to the PSP SMI
handler code, but the handling of the actual mailbox commands the PSP
sends to the SMI handler is added in later patches to keep the patch
size manageable.
This patch is a heavily reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I50479bed2332addae652026c6818460eeb6403af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83740
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Adjust Touchpad I2C fall time configuration such that it meets the
I2C fast mode specification(<= 400KHz).
BUG=b:328670295
TEST=Build Brox firmware and boot to OS. Confirm the I2C bus
frequency(375 KHz), rise(650 ns) and fall(330 ns) times meet the
specification.
Change-Id: I0006bfb9bb5839ffa1248d9f2ea055160ed0936e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83755
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Clean up the devicetree by removing settings set to 0, which are
initialized with 0 anyway, remove superfluous disabled devices and also
remove comments duplicating the device alias names.
Change-Id: I07005ae1db7d92fd50e72351031a5eb491768d3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
