This change adds a sku_id() function that returns a static value to
differentiate the sarien and arcada boards.
Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kabylake RVP11 uses FSPT to support Intel security features like
bootguard verify boot and measured boot.
This patch add FSP CAR support for kabylake by programming tempraminit
parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is
selected in order to relocate FSPT binary while adding it in CBFS so that
it can be executed in place.
BUG=None
TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified
for successful FSP CAR setup.
Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build AMD Bettong.
Change-Id: I4167c7eeb9339937b064e81e615ceb65f4689082
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A very common pattern in drivers is that we need to wait for a condition
to become true (e.g. for a lock bit in a PLL status register to become
set), but we still want to have a maximum timeout before we treat it as
an error. coreboot uses the stopwatch API for this, but it's still a
little verbose for the most simple cases. This patch introduces two new
helper macros that wrap this common application of the stopwatch API in
a single line: wait_ms(XXX, YYY) waits for up to XXX milliseconds to see
if the C condition 'if (YYY)' becomes true. The return value is 0 on
failure (i.e. timeout expires without the condition becoming true) and
the amount of elapsed time on success, so it can be used both in a
boolean context and to log the amount of time waited.
Replace the custom version used in an MTK ADC driver with this new
generic version.
Change-Id: I6de38ee00673c46332ae92b8a11099485de5327a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If remaining charge is more than x% of the full capacity, the
remaining charge is raised to the full capacity before it's
reported to the rest of the system.
Some batteries don't update full capacity timely or don't update it
at all. On such systems, compensation is required to guarantee
the remaining charge will be equal to the full capacity eventually.
On some systems, Rohm charger generates audio noise when the battery
is fully charged and AC is plugged. A workaround is to do charge-
discharge cycles between 93 and 100%. On such systems, compensation
was also applied to mask this cycle from users.
This used to be done in ACPI, thus, all software components except EC
was able to see the compensated charge. This patch is part of the
effort of moving the logic to EC. With this and the EC changes, EC
can see what the rest of the system sees, thus, can control LEDs
synchronously (to the display percentage).
Another rationale of this move is EC can perform more granular and
precise compensation than ACPI since it has more knowledge about the
battery and the charger.
CQ-DEPEND=CL:1312204
BUG=b:109954565,b:80270446,chromium:899120
BRANCH=none
TEST=Verify charge LED changes to white (full) on Sona synchronously
to the display percentage.
TEST=Verify charge LED changes to blinking white (low) on Sona
within 30 seconds synchronously to the display percentage.
Change-Id: I0b51911b90dc2e7fcf5c730c54d9fda1fea76aa9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Since S3 resume sometimes breaks when trying to find the wakeup vector,
it is useful to log whether it errors or not. Since it is an error,
print it as such.
Change-Id: Ib006c4a213c0da180018e5fbf7a47d6af66f8bc4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some variants of nami will have a fingerprint MCU.
BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)
Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TEST=Make the printk reachable, check with
`strings build/cbfs/fallback/romstage.elf | grep lowest`
that this patch changes "MHzas" to "MHz as".
Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build and boot grunt.
Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high more than 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.
BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use GPIO_134 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BRANCH=none
BUG=crbug:896347, b:118443377
CQ-DEPEND=CL:1298699
TEST=verify sensor events coming in on a reworked board
with companion EC and kernel patches
Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/29278
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each stage performs some basic initialization (stack, HLS etc) and then
call smp_pause to enter the single-threaded state. The main work of each
stage is executed in a single-threaded state, and the multi-threaded
state is restored by call smp_resume while booting the next stage.
Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
There are some small mistakes in these recently-added mainboards:
- board_info.txt: Lists board socket incorrectly.
- cmos.default: Loglevel was decreased some time ago.
- devicetree.cb: Spelling mistake.
- Kconfig: Mainboard name does not have a hyphen.
Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Get board id from AUXIN4 and RAM code from AUXIN3.
BUG=b:80501386
BRANCH=none
TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0.
AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1.
Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We plan to get board id and RAM code from AUXADC on Kukui. Add AUXADC
driver to support it.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I121a6a0240f9c517c0cbc07e0c18b09167849ff1
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/29061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
