mb/system76/bonw14: Enable TAS5825M smart amp

The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>

Documentation/releases/coreboot-24.08-relnotes.md

@@ -0,0 +1,100 @@
+Upcoming release - coreboot 24.08
+========================================================================
+
+The 24.08 release is scheduled for Mid Aug, 2024
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+* Upgrade ACPICA from 20230628 to 20240321
+* Upgrade CMake from 3.28.3 to 3.29.3
+* Upgrade nasm from 2.16.01 to 2.16.03
+* Upgrade LLVM from 17.0.6 to 18.1.6
+* Upgrade GCC from 13.2 to 14.1.0
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 24.05 to the 24.08 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: https://www.coreboot.org
+* Downloads: https://coreboot.org/downloads.html
+* Source control: https://review.coreboot.org
+* Documentation: https://doc.coreboot.org
+* Issue tracker: https://ticket.coreboot.org/projects/coreboot
+* Donations: https://coreboot.org/donate.html

Documentation/releases/index.md

@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-24.05 - May 2024 <coreboot-24.05-relnotes.md>
+24.08 - August 2024 <coreboot-24.08-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+24.05  - May 2024 <coreboot-24.05-relnotes.md>
 24.02  - February 2024 <coreboot-24.02-relnotes.md>
 4.22   - November 2023 <coreboot-4.22-relnotes.md>
 4.21   - August 2023 <coreboot-4.21-relnotes.md>

configs/builder/config.intel.crb.avc

@@ -0,0 +1,50 @@
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc
+
+#
+# [RO] Board Configurations
+#
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_AVENUECITY_CRB=y
+
+CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
+CONFIG_CONFIGURABLE_RAMSTAGE=y
+
+CONFIG_NO_GFX_INIT=y
+
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_PAYLOAD_LINUX=y
+
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_CONSOLE_SERIAL_115200=y
+
+#
+# [RW] IFWI Ingredients
+#
+CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
+CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb"
+CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
+CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/"
+
+CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage"
+CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
+
+#
+# [RW] Debug Settings
+#
+CONFIG_CONSOLE_POST=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+
+CONFIG_VERIFY_HOBS=y
+CONFIG_DISPLAY_MTRRS=y
+
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+
+CONFIG_HAVE_DEBUG_GPIO=y
+CONFIG_DEBUG_GPIO=y

configs/builder/config.intel.crb.bnc

@@ -0,0 +1,50 @@
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc
+
+#
+# [RO] Board Configurations
+#
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y
+
+CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
+CONFIG_CONFIGURABLE_RAMSTAGE=y
+
+CONFIG_NO_GFX_INIT=y
+
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_PAYLOAD_LINUX=y
+
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_CONSOLE_SERIAL_115200=y
+
+#
+# [RW] IFWI Ingredients
+#
+CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
+CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb"
+CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
+CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
+
+CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage"
+CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
+
+#
+# [RW] Debug Settings
+#
+CONFIG_CONSOLE_POST=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+
+CONFIG_VERIFY_HOBS=y
+CONFIG_DISPLAY_MTRRS=y
+
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+
+CONFIG_HAVE_DEBUG_GPIO=y
+CONFIG_DEBUG_GPIO=y

payloads/external/edk2/Makefile

@@ -37,6 +37,8 @@ BUILD_STR += -s
 endif
 endif
 
+BUILD_STR += -D BUILD_ARCH=X64
+
 #
 # EDK II (edk2/master) has the following build options relevant to coreboot:
 #

payloads/libpayload/bin/lpgcc

@@ -74,34 +74,30 @@ else
 fi
 
 if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/arm
-  _ARCHLIBDIR=$_LIBDIR/arm
+  _ARCHDIR=arm
   _ARCHEXTRA=""
-  _ARCH=arm
+
 fi
 if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/arm64
-  _ARCHLIBDIR=$_LIBDIR/arm64
+  _ARCHDIR=arm64
   _ARCHEXTRA=""
-  _ARCH=arm64
 fi
 if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/x86
-  _ARCHLIBDIR=$_LIBDIR/x86
+  _ARCHDIR=x86
   _ARCHEXTRA="-m32 "
-  _ARCH=x86
 fi
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/mock
-  _ARCHLIBDIR=$_LIBDIR/mock
+  _ARCHDIR=mock
   _ARCHEXTRA=""
-  _ARCH=mock
 fi
 
+_ARCHINCDIR=$_INCDIR/$_ARCHDIR
+_ARCHLIBDIR=$_LIBDIR/$_ARCHDIR
+
 if [ -f $_LIBDIR/libpayload.ldscript ]; then
 	_LDDIR=$_LIBDIR
-elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then
-	_LDDIR=$BASE/../arch/$_ARCH
+elif [ -f $BASE/../arch/$_ARCHDIR/libpayload.ldscript ]; then
+	_LDDIR=$BASE/../arch/$_ARCHDIR
 fi
 # Host arch should youse default linker script
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then

src/cpu/x86/pae/pgtbl.c

@@ -277,177 +277,3 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name)
 
 	return 0;
 }
-
-static void *get_pdpt_addr(void)
-{
-	if (preram_symbols_available())
-		return _pdpt;
-	return (void *)(uintptr_t)read_cr3();
-}
-
-static uint64_t pde_pat_flags(int pat)
-{
-	switch (pat) {
-	case PAT_UC:
-		return 0 | PDE_PCD | PDE_PWT;
-	case PAT_WC:
-		return 0 | 0 | PDE_PWT;
-	case PAT_WT:
-		return PDE_PAT | PDE_PCD | PDE_PWT;
-	case PAT_WP:
-		return PDE_PAT | 0 | PDE_PWT;
-	case PAT_WB:
-		return 0 | 0 | 0;
-	case PAT_UC_MINUS:
-		return 0 | PDE_PCD | 0;
-	default:
-		printk(BIOS_ERR, "PDE PAT defaulting to WB: %x\n", pat);
-		return pde_pat_flags(PAT_WB);
-	}
-}
-
-static uint64_t pde_page_flags(int pat)
-{
-	uint64_t flags = PDE_PS | PDE_PRES | PDE_RW | PDE_A | PDE_D;
-
-	return flags | pde_pat_flags(pat);
-}
-
-static uint64_t pte_pat_flags(int pat)
-{
-	switch (pat) {
-	case PAT_UC:
-		return 0 | PTE_PCD | PTE_PWT;
-	case PAT_WC:
-		return 0 | 0 | PTE_PWT;
-	case PAT_WT:
-		return PTE_PAT | PTE_PCD | PTE_PWT;
-	case PAT_WP:
-		return PTE_PAT | 0 | PTE_PWT;
-	case PAT_WB:
-		return 0 | 0 | 0;
-	case PAT_UC_MINUS:
-		return 0 | PTE_PCD | 0;
-	default:
-		printk(BIOS_ERR, "PTE PAT defaulting to WB: %x\n", pat);
-		return pte_pat_flags(PAT_WB);
-	}
-}
-
-static uint64_t pte_page_flags(int pat)
-{
-	uint64_t flags = PTE_PRES | PTE_RW | PTE_A | PTE_D;
-	return flags | pte_pat_flags(pat);
-}
-
-/* Identity map an address. This function does not handle splitting or adding
- * new pages to the page tables. It's assumed all the page tables are already
- * seeded with the correct amount and topology. */
-static int identity_map_one_page(uintptr_t base, size_t size, int pat,
-				int commit)
-{
-	uint64_t (*pdpt)[4];
-	uint64_t pdpte;
-	uint64_t (*pd)[512];
-	uint64_t pde;
-
-	pdpt = get_pdpt_addr();
-
-	pdpte = (*pdpt)[(base >> PDPTE_IDX_SHIFT) & PDPTE_IDX_MASK];
-
-	/* No page table page allocation. */
-	if (!(pdpte & PDPTE_PRES))
-		return -1;
-
-	pd = (void *)(uintptr_t)(pdpte & PDPTE_ADDR_MASK);
-
-	/* Map in a 2MiB page. */
-	if (size == s2MiB) {
-		if (!commit)
-			return 0;
-		pde = base;
-		pde |= pde_page_flags(pat);
-		(*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK] = pde;
-		return 0;
-	}
-
-	if (size == s4KiB) {
-		uint64_t (*pt)[512];
-		uint64_t pte;
-
-		pde = (*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK];
-
-		/* No page table page allocation. */
-		if (!(pde & PDE_PRES)) {
-			printk(BIOS_ERR, "Cannot allocate page table for pde %p\n",
-				(void *)base);
-			return -1;
-		}
-
-		/* No splitting pages */
-		if (pde & PDE_PS) {
-			printk(BIOS_ERR, "Cannot split pde %p\n", (void *)base);
-			return -1;
-		}
-
-		if (!commit)
-			return 0;
-
-		pt = (void *)(uintptr_t)(pde & PDE_ADDR_MASK);
-		pte = base;
-		pte |= pte_page_flags(pat);
-		(*pt)[(base >> PTE_IDX_SHIFT) & PTE_IDX_MASK] = pte;
-
-		return 0;
-	}
-
-	return -1;
-}
-
-static int _paging_identity_map_addr(uintptr_t base, size_t size, int pat,
-					int commit)
-{
-	while (size != 0) {
-		size_t map_size;
-
-		map_size = IS_ALIGNED(base, s2MiB) ? s2MiB : s4KiB;
-		map_size = MIN(size, map_size);
-
-		if (identity_map_one_page(base, map_size, pat, commit) < 0)
-			return -1;
-
-		base += map_size;
-		size -= map_size;
-	}
-
-	return 0;
-}
-
-static int paging_is_enabled(void)
-{
-	return !!(read_cr0() & CR0_PG);
-}
-
-int paging_identity_map_addr(uintptr_t base, size_t size, int pat)
-{
-	if (!paging_is_enabled()) {
-		printk(BIOS_ERR, "Paging is not enabled.\n");
-		return -1;
-	}
-
-	if (!IS_ALIGNED(base, s2MiB) && !IS_ALIGNED(base, s4KiB)) {
-		printk(BIOS_ERR, "base %p is not aligned.\n", (void *)base);
-		return -1;
-	}
-
-	if (!IS_ALIGNED(size, s2MiB) && !IS_ALIGNED(size, s4KiB)) {
-		printk(BIOS_ERR, "size %zx is not aligned.\n", size);
-		return -1;
-	}
-
-	/* First try without committing. If success commit. */
-	if (_paging_identity_map_addr(base, size, pat, 0))
-		return -1;
-
-	return _paging_identity_map_addr(base, size, pat, 1);
-}

src/drivers/i2c/tpm/cr50.c

@@ -498,7 +498,7 @@ tpm_result_t tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t d
 	if (rc)
 		return rc;
 
-	printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id %#x)\n",
+	printk(BIOS_DEBUG, "GSC TPM 2.0 (i2c %u:0x%02x id %#x)\n",
 	       bus, dev_addr, did_vid >> 16);
 
 	if (tpm_first_access_this_boot()) {

src/ec/google/chromeec/ec_acpi.c

@@ -233,6 +233,7 @@ static const enum ps2_action_key ps2_enum_val[] = {
 	[TK_KBD_BKLIGHT_TOGGLE] = PS2_KEY_KBD_BKLIGHT_TOGGLE,
 	[TK_MICMUTE] = PS2_KEY_MICMUTE,
 	[TK_MENU] = PS2_KEY_MENU,
+	[TK_DICTATE] = PS2_KEY_DICTATE,
 };
 
 static void fill_ssdt_ps2_keyboard(const struct device *dev)

src/include/cpu/x86/pae.h

@@ -35,11 +35,6 @@ void paging_set_default_pat(void);
  * failure. */
 int paging_enable_for_car(const char *pdpt_name, const char *pt_name);
 
-/* Identity map the region indicated by 'base' and 'size'. Both 'base' and
- * 'size' need to be 4KiB or 2 MiB aligned. 'pat' should be one of the
- * PAT defines above. 0 is returned on success, < 0 on failure. */
-int paging_identity_map_addr(uintptr_t base, size_t size, int pat);
-
 /* To be used with memset_pae */
 #define MEMSET_PAE_VMEM_ALIGN (2 * MiB)
 #define MEMSET_PAE_VMEM_SIZE (2 * MiB)

src/include/device/pci_ids.h

@@ -4182,8 +4182,8 @@
 #define PCI_DID_INTEL_RPL_U_GT4				0xa7ac
 #define PCI_DID_INTEL_RPL_U_GT5				0xa7ad
 #define PCI_DID_INTEL_LNL_M_GT2				0x64a0
-#define PCI_DID_INTEL_TWL_GT1_1				0x46D3
-#define PCI_DID_INTEL_TWL_GT1_2				0x46D4
+#define PCI_DID_INTEL_TWL_GT1_1				0x46d3
+#define PCI_DID_INTEL_TWL_GT1_2				0x46d4
 #define PCI_DID_INTEL_PTL_GT2				0x64a0
 
 /* Intel Northbridge Ids */

src/include/device_tree.h

@@ -4,6 +4,7 @@
 #ifndef __DEVICE_TREE_H__
 #define __DEVICE_TREE_H__
 
+#include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <commonlib/list.h>
@@ -33,6 +34,7 @@ struct fdt_header {
 #define FDT_TOKEN_BEGIN_NODE	1
 #define FDT_TOKEN_END_NODE	2
 #define FDT_TOKEN_PROPERTY	3
+#define FDT_TOKEN_NOP		4
 #define FDT_TOKEN_END		9
 #define FDT_PHANDLE_ILLEGAL	0xdeadbeef
 
@@ -47,6 +49,11 @@ struct fdt_property
  * Unflattened device tree structures.
  */
 
+struct device_tree_region {
+	u64 addr;
+	u64 size;
+};
+
 struct device_tree_property
 {
 	struct fdt_property prop;
@@ -91,6 +98,8 @@ struct device_tree
  * which were consumed reading the requested value.
  */
 
+/* Checks if blob points to a valid FDT */
+bool fdt_is_valid(const void *blob);
 /* Read the property at offset, if any exists. */
 int fdt_next_property(const void *blob, uint32_t offset,
 		      struct fdt_property *prop);
@@ -100,6 +109,26 @@ int fdt_node_name(const void *blob, uint32_t offset, const char **name);
 void fdt_print_node(const void *blob, uint32_t offset);
 int fdt_skip_node(const void *blob, uint32_t offset);
 
+/* Read property and put into fdt_prop. Returns offset to property */
+u32 fdt_read_prop(const void *blob, u32 node_offset, const char *prop_name,
+		  struct fdt_property *fdt_prop);
+/* Read reg property and save regions inside 'regions'. Returns number of regions read */
+u32 fdt_read_reg_prop(const void *blob, u32 node_offset, u32 addr_cells, u32 size_cells,
+		      struct device_tree_region regions[], size_t regions_count);
+/* Find a node by a given path and return the offset */
+u32 fdt_find_node_by_path(const void *blob, const char *path, u32 *addrcp, u32 *sizecp);
+/* Find multiple nodes matching a given pattern. Returns number of nodes found */
+size_t fdt_find_subnodes_by_prefix(const void *blob, u32 node_offset, const char *prefix,
+				   u32 *addrcp, u32 *sizecp, u32 results[], size_t results_len);
+/* Find a node by a given alias and return its offset */
+u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
+			   u32 *addr_cells, u32 *size_cells);
+/*
+ * Read the node name into 'name' of the node behind 'node_offset'
+ * and return total bytes used for name
+ */
+int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
+
 /* Read a flattened device tree into a hierarchical structure which refers to
    the contents of the flattened tree in place. Modifying the flat tree
    invalidates the unflattened one. */

src/lib/device_tree.c

@@ -6,21 +6,39 @@
 #include <ctype.h>
 #include <device_tree.h>
 #include <endian.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
 #include <stddef.h>
 #include <stdlib.h>
 
+#define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound
+#define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound
+
 /*
  * Functions for picking apart flattened trees.
  */
 
+static int fdt_skip_nops(const void *blob, uint32_t offset)
+{
+	uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
+
+	int index = 0;
+	while (be32toh(ptr[index]) == FDT_TOKEN_NOP)
+		index++;
+
+	return index * sizeof(uint32_t);
+}
+
 int fdt_next_property(const void *blob, uint32_t offset,
 		      struct fdt_property *prop)
 {
 	struct fdt_header *header = (struct fdt_header *)blob;
 	uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
 
+	// skip NOP tokens
+	offset += fdt_skip_nops(blob, offset);
+
 	int index = 0;
 	if (be32toh(ptr[index++]) != FDT_TOKEN_PROPERTY)
 		return 0;
@@ -40,24 +58,369 @@ int fdt_next_property(const void *blob, uint32_t offset,
 	return index * sizeof(uint32_t);
 }
 
-int fdt_node_name(const void *blob, uint32_t offset, const char **name)
+/*
+ * fdt_next_node_name  reads a node name
+ *
+ * @params blob    address of FDT
+ * @params offset  offset to the node to read the name from
+ * @params name    parameter to hold the name that has been read or NULL
+ *
+ * @returns  Either 0 on error or offset to the properties that come after the node name
+ */
+int fdt_next_node_name(const void *blob, uint32_t offset, const char **name)
 {
-	uint8_t *ptr = ((uint8_t *)blob) + offset;
+	// skip NOP tokens
+	offset += fdt_skip_nops(blob, offset);
+
+	char *ptr = ((char *)blob) + offset;
 	if (be32dec(ptr) != FDT_TOKEN_BEGIN_NODE)
 		return 0;
 
 	ptr += 4;
 	if (name)
-		*name = (char *)ptr;
-	return ALIGN_UP(strlen((char *)ptr) + 1, sizeof(uint32_t)) + 4;
+		*name = ptr;
+
+	return ALIGN_UP(strlen(ptr) + 1, 4) + 4;
 }
 
-static int dt_prop_is_phandle(struct device_tree_property *prop)
+/*
+ * A utility function to skip past nodes in flattened trees.
+ */
+int fdt_skip_node(const void *blob, uint32_t start_offset)
 {
-	return !(strcmp("phandle", prop->prop.name) &&
-		 strcmp("linux,phandle", prop->prop.name));
+	uint32_t offset = start_offset;
+
+	const char *name;
+	int size = fdt_next_node_name(blob, offset, &name);
+	if (!size)
+		return 0;
+	offset += size;
+
+	while ((size = fdt_next_property(blob, offset, NULL)))
+		offset += size;
+
+	while ((size = fdt_skip_node(blob, offset)))
+		offset += size;
+
+	// skip NOP tokens
+	offset += fdt_skip_nops(blob, offset);
+
+	return offset - start_offset + sizeof(uint32_t);
 }
 
+/*
+ * fdt_read_prop reads a property inside a node
+ *
+ * @params blob         address of FDT
+ * @params node_offset  offset to the node to read the property from
+ * @params prop_name    name of the property to read
+ * @params fdt_prop     property is saved inside this parameter
+ *
+ * @returns  Either 0 if no property has been found or an offset that points to the location
+ *           of the property
+ */
+u32 fdt_read_prop(const void *blob, u32 node_offset, const char *prop_name,
+		  struct fdt_property *fdt_prop)
+{
+	u32 offset = node_offset;
+
+	offset += fdt_next_node_name(blob, offset, NULL); // skip node name
+
+	size_t size;
+	while ((size = fdt_next_property(blob, offset, fdt_prop))) {
+		if (strcmp(fdt_prop->name, prop_name) == 0)
+			return offset;
+		offset += size;
+	}
+	return 0; // property not found
+}
+
+/*
+ * fdt_read_reg_prop reads the reg property inside a node
+ *
+ * @params blob           address of FDT
+ * @params node_offset    offset to the node to read the reg property from
+ * @params addr_cells     number of cells used for one address
+ * @params size_cells     number of cells used for one size
+ * @params regions        all regions that are read inside the reg property are saved inside
+ *                        this array
+ * @params regions_count  maximum number of entries that can be saved inside the regions array.
+ *
+ * Returns: Either 0 on error or returns the number of regions put into the regions array.
+ */
+u32 fdt_read_reg_prop(const void *blob, u32 node_offset, u32 addr_cells, u32 size_cells,
+		      struct device_tree_region regions[], size_t regions_count)
+{
+	struct fdt_property prop;
+	u32 offset = fdt_read_prop(blob, node_offset, "reg", &prop);
+
+	if (!offset) {
+		printk(BIOS_DEBUG, "no reg property found in node_offset: %x\n", node_offset);
+		return 0;
+	}
+
+	// we found the reg property, now need to parse all regions in 'reg'
+	size_t count = prop.size / (4 * addr_cells + 4 * size_cells);
+	if (count > regions_count) {
+		printk(BIOS_ERR, "reg property at node_offset: %x has more entries (%zd) than regions array can hold (%zd)\n", node_offset, count, regions_count);
+		count = regions_count;
+	}
+	if (addr_cells > 2 || size_cells > 2) {
+		printk(BIOS_ERR, "addr_cells (%d) or size_cells (%d) bigger than 2\n",
+				  addr_cells, size_cells);
+		return 0;
+	}
+	uint32_t *ptr = prop.data;
+	for (int i = 0; i < count; i++) {
+		if (addr_cells == 1)
+			regions[i].addr = be32dec(ptr);
+		else if (addr_cells == 2)
+			regions[i].addr = be64dec(ptr);
+		ptr += addr_cells;
+		if (size_cells == 1)
+			regions[i].size = be32dec(ptr);
+		else if (size_cells == 2)
+			regions[i].size = be64dec(ptr);
+		ptr += size_cells;
+	}
+
+	return count; // return the number of regions found in the reg property
+}
+
+static u32 fdt_read_cell_props(const void *blob, u32 node_offset, u32 *addrcp, u32 *sizecp)
+{
+	struct fdt_property prop;
+	u32 offset = node_offset;
+	size_t size;
+	while ((size = fdt_next_property(blob, offset, &prop))) {
+		if (addrcp && !strcmp(prop.name, "#address-cells"))
+			*addrcp = be32dec(prop.data);
+		if (sizecp && !strcmp(prop.name, "#size-cells"))
+			*sizecp = be32dec(prop.data);
+		offset += size;
+	}
+	return offset;
+}
+
+/*
+ * fdt_find_node searches for a node relative to another node
+ *
+ * @params blob  address of FDT
+ *
+ * @params parent_node_offset  offset to node from which to traverse the tree
+ *
+ * @params path  null terminated array of node names specifying a
+ *               relative path (e.g: { "cpus", "cpu0", NULL })
+ *
+ * @params addrcp/sizecp  If any address-cells and size-cells properties are found that are
+ *                        part of the parent node of the node we are looking, addrcp and sizecp
+ *                        are set to these respectively.
+ *
+ * @returns: Either 0 if no node has been found or the offset to the node found
+ */
+static u32 fdt_find_node(const void *blob, u32 parent_node_offset, char **path,
+			 u32 *addrcp, u32 *sizecp)
+{
+	if (*path == NULL)
+		return parent_node_offset; // node found
+
+	size_t size = fdt_next_node_name(blob, parent_node_offset, NULL); // skip node name
+
+	/*
+	 * get address-cells and size-cells properties while skipping the others.
+	 * According to spec address-cells and size-cells are not inherited, but we
+	 * intentionally follow the Linux implementation here and treat them as inheritable.
+	 */
+	u32 node_offset = fdt_read_cell_props(blob, parent_node_offset + size, addrcp, sizecp);
+
+	const char *node_name;
+	// walk all children nodes
+	while ((size = fdt_next_node_name(blob, node_offset, &node_name))) {
+		if (!strcmp(*path, node_name)) {
+			// traverse one level deeper into the path
+			return fdt_find_node(blob, node_offset, path + 1, addrcp, sizecp);
+		}
+		// node is not the correct one. skip current node
+		node_offset += fdt_skip_node(blob, node_offset);
+	}
+
+	// we have searched everything and could not find a fitting node
+	return 0;
+}
+
+/*
+ * fdt_find_node_by_path finds a node behind a given node path
+ *
+ * @params blob  address of FDT
+ * @params path  absolute path to the node that should be searched for
+ *
+ * @params addrcp/sizecp  Pointer that will be updated with any #address-cells and #size-cells
+ *                        value found in the node of the node specified by node_offset. Either
+ *                        may be NULL to ignore. If no #address-cells and #size-cells is found
+ *                        default values of #address-cells=2 and #size-cells=1 are returned.
+ *
+ * @returns Either 0 on error or the offset to the node found behind the path
+ */
+u32 fdt_find_node_by_path(const void *blob, const char *path, u32 *addrcp, u32 *sizecp)
+{
+	// sanity check
+	if (path[0] != '/') {
+		printk(BIOS_ERR, "devicetree path must start with a /\n");
+		return 0;
+	}
+	if (!blob) {
+		printk(BIOS_ERR, "devicetree blob is NULL\n");
+		return 0;
+	}
+
+	if (addrcp)
+		*addrcp = 2;
+	if (sizecp)
+		*sizecp = 1;
+
+	struct fdt_header *fdt_hdr = (struct fdt_header *)blob;
+
+	/*
+	 * split path into separate nodes
+	 * e.g: "/cpus/cpu0" -> { "cpus", "cpu0" }
+	 */
+	char *path_array[FDT_PATH_MAX_DEPTH];
+	size_t path_size = strlen(path);
+	assert(path_size < FDT_PATH_MAX_LEN);
+	char path_copy[FDT_PATH_MAX_LEN];
+	memcpy(path_copy, path, path_size + 1);
+	char *cur = path_copy;
+	int i;
+	for (i = 0; i < FDT_PATH_MAX_DEPTH; i++) {
+		path_array[i] = strtok_r(NULL, "/", &cur);
+		if (!path_array[i])
+			break;
+	}
+	assert(i < FDT_PATH_MAX_DEPTH);
+
+	return fdt_find_node(blob, be32toh(fdt_hdr->structure_offset), path_array, addrcp, sizecp);
+}
+
+/*
+ * fdt_find_subnodes_by_prefix finds a node with a given prefix relative to a parent node
+ *
+ * @params blob  The FDT to search.
+ *
+ * @params node_offset  offset to the node of which the children should be searched
+ *
+ * @params prefix  A string to search for a node with a given prefix. This can for example
+ *                 be 'cpu' to look for all nodes matching this prefix. Only children of
+ *                 node_offset are searched. Therefore in order to search all nodes matching
+ *                 the 'cpu' prefix, node_offset should probably point to the 'cpus' node.
+ *                 An empty prefix ("") searches for all children nodes of node_offset.
+ *
+ * @params addrcp/sizecp  Pointer that will be updated with any #address-cells and #size-cells
+ *                        value found in the node of the node specified by node_offset. Either
+ *                        may be NULL to ignore. If no #address-cells and #size-cells is found
+ *                        addrcp and sizecp are left untouched.
+ *
+ * @params results      Array of offsets pointing to each node matching the given prefix.
+ * @params results_len  Number of entries allocated for the 'results' array
+ *
+ * @returns  offset to last node found behind path or 0 if no node has been found
+ */
+size_t fdt_find_subnodes_by_prefix(const void *blob, u32 node_offset, const char *prefix,
+				   u32 *addrcp, u32 *sizecp, u32 *results, size_t results_len)
+{
+	// sanity checks
+	if (!blob || !results || !prefix) {
+		printk(BIOS_ERR, "%s: input parameter cannot be null/\n", __func__);
+		return 0;
+	}
+
+	u32 offset = node_offset;
+
+	// we don't care about the name of the current node
+	u32 size = fdt_next_node_name(blob, offset, NULL);
+	if (!size) {
+		printk(BIOS_ERR, "%s: node_offset: %x does not point to a node\n",
+		       __func__, node_offset);
+		return 0;
+	}
+	offset += size;
+
+	/*
+	 * update addrcp and sizecp if the node contains an address-cells and size-cells
+	 * property. Otherwise use addrcp and sizecp provided by caller.
+	 */
+	offset = fdt_read_cell_props(blob, offset, addrcp, sizecp);
+
+	size_t count_results = 0;
+	int prefix_len = strlen(prefix);
+	const char *node_name;
+	// walk all children nodes of offset
+	while ((size = fdt_next_node_name(blob, offset, &node_name))) {
+
+		if (count_results >= results_len) {
+			printk(BIOS_WARNING,
+				"%s: results_len (%zd) smaller than count_results (%zd)\n",
+				__func__, results_len, count_results);
+			break;
+		}
+
+		if (!strncmp(prefix, node_name, prefix_len)) {
+			// we found a node that matches the prefix
+			results[count_results++] = offset;
+		}
+
+		// node does not match the prefix. skip current node
+		offset += fdt_skip_node(blob, offset);
+	}
+
+	// return last occurrence
+	return count_results;
+}
+
+static const char *fdt_read_alias_prop(const void *blob, const char *alias_name)
+{
+	u32 node_offset =  fdt_find_node_by_path(blob, "/aliases", NULL, NULL);
+	if (!node_offset) {
+		printk(BIOS_DEBUG, "no /aliases node found\n");
+		return NULL;
+	}
+	struct fdt_property alias_prop;
+	if (!fdt_read_prop(blob, node_offset, alias_name, &alias_prop)) {
+		printk(BIOS_DEBUG, "property %s in /aliases node not found\n", alias_name);
+		return NULL;
+	}
+	return (const char *)alias_prop.data;
+}
+
+/*
+ * Find a node in the tree from a string device tree path.
+ *
+ * @params blob           Address to the FDT
+ * @params alias_name     node name alias that should be searched for.
+ * @params addrcp/sizecp  Pointer that will be updated with any #address-cells and #size-cells
+ *                        value found in the node of the node specified by node_offset. Either
+ *                        may be NULL to ignore. If no #address-cells and #size-cells is found
+ *                        default values of #address-cells=2 and #size-cells=1 are returned.
+ *
+ * @returns  offset to last node found behind path or 0 if no node has been found
+ */
+u32 fdt_find_node_by_alias(const void *blob, const char *alias_name, u32 *addrcp, u32 *sizecp)
+{
+	const char *node_name = fdt_read_alias_prop(blob, alias_name);
+	if (!node_name)  {
+		printk(BIOS_DEBUG, "alias %s not found\n", alias_name);
+		return 0;
+	}
+
+	u32 node_offset = fdt_find_node_by_path(blob, node_name, addrcp, sizecp);
+	if (!node_offset) {
+		// This should not happen (invalid devicetree)
+		printk(BIOS_WARNING,
+		       "Could not find node '%s', which alias was referring to '%s'\n",
+		       node_name, alias_name);
+		return 0;
+	}
+	return node_offset;
+}
 
 
 /*
@@ -108,7 +471,7 @@ static int print_flat_node(const void *blob, uint32_t start_offset, int depth)
 	const char *name;
 	int size;
 
-	size = fdt_node_name(blob, offset, &name);
+	size = fdt_next_node_name(blob, offset, &name);
 	if (!size)
 		return 0;
 	offset += size;
@@ -139,38 +502,16 @@ void fdt_print_node(const void *blob, uint32_t offset)
 	print_flat_node(blob, offset, 0);
 }
 
-
-
-/*
- * A utility function to skip past nodes in flattened trees.
- */
-
-int fdt_skip_node(const void *blob, uint32_t start_offset)
-{
-	int offset = start_offset;
-	int size;
-
-	const char *name;
-	size = fdt_node_name(blob, offset, &name);
-	if (!size)
-		return 0;
-	offset += size;
-
-	while ((size = fdt_next_property(blob, offset, NULL)))
-		offset += size;
-
-	while ((size = fdt_skip_node(blob, offset)))
-		offset += size;
-
-	return offset - start_offset + sizeof(uint32_t);
-}
-
-
-
 /*
  * Functions to turn a flattened tree into an unflattened one.
  */
 
+static int dt_prop_is_phandle(struct device_tree_property *prop)
+{
+	return !(strcmp("phandle", prop->prop.name) &&
+		 strcmp("linux,phandle", prop->prop.name));
+}
+
 static int fdt_unflatten_node(const void *blob, uint32_t start_offset,
 			      struct device_tree *tree,
 			      struct device_tree_node **new_node)
@@ -180,7 +521,7 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset,
 	const char *name;
 	int size;
 
-	size = fdt_node_name(blob, offset, &name);
+	size = fdt_next_node_name(blob, offset, &name);
 	if (!size)
 		return 0;
 	offset += size;
@@ -237,30 +578,37 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset,
 	return sizeof(uint64_t) * 2;
 }
 
-struct device_tree *fdt_unflatten(const void *blob)
+bool fdt_is_valid(const void *blob)
 {
-	struct device_tree *tree = xzalloc(sizeof(*tree));
 	const struct fdt_header *header = (const struct fdt_header *)blob;
-	tree->header = header;
 
 	uint32_t magic = be32toh(header->magic);
 	uint32_t version = be32toh(header->version);
 	uint32_t last_comp_version = be32toh(header->last_comp_version);
 
 	if (magic != FDT_HEADER_MAGIC) {
-		printk(BIOS_DEBUG, "Invalid device tree magic %#.8x!\n", magic);
-		free(tree);
-		return NULL;
+		printk(BIOS_ERR, "Invalid device tree magic %#.8x!\n", magic);
+		return false;
 	}
 	if (last_comp_version > FDT_SUPPORTED_VERSION) {
-		printk(BIOS_DEBUG, "Unsupported device tree version %u(>=%u)\n",
+		printk(BIOS_ERR, "Unsupported device tree version %u(>=%u)\n",
 		       version, last_comp_version);
-		free(tree);
-		return NULL;
+		return false;
 	}
 	if (version > FDT_SUPPORTED_VERSION)
 		printk(BIOS_NOTICE, "FDT version %u too new, should add support!\n",
 		       version);
+	return true;
+}
+
+struct device_tree *fdt_unflatten(const void *blob)
+{
+	struct device_tree *tree = xzalloc(sizeof(*tree));
+	const struct fdt_header *header = (const struct fdt_header *)blob;
+	tree->header = header;
+
+	if (fdt_is_valid(blob))
+		return NULL;
 
 	uint32_t struct_offset = be32toh(header->structure_offset);
 	uint32_t strings_offset = be32toh(header->strings_offset);
@@ -981,7 +1329,7 @@ void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val)
  * Add a 'reg' address list property to a node, or update it if it exists.
  *
  * @param node		The device tree node to add to.
- * @param addrs		Array of address values to be stored in the property.
+ * @param regions       Array of address values to be stored in the property.
  * @param sizes		Array of corresponding size values to 'addrs'.
  * @param count		Number of values in 'addrs' and 'sizes' (must be equal).
  * @param addr_cells	Value of #address-cells property valid for this node.

src/mainboard/amd/birman/Makefile.mk

@@ -9,6 +9,7 @@ romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c
 
 ramstage-y += chromeos.c
 ramstage-y += gpio.c
+ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL) += update_devicetree_phoenix_opensil.c
 ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c
 ramstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c
 

src/mainboard/amd/birman/devicetree_phoenix_opensil.cb

@@ -43,25 +43,75 @@ chip soc/amd/phoenix
 
 	device domain 0 on
 		device ref iommu on end
-		device ref gpp_bridge_1_1 on end # MXM
-		device ref gpp_bridge_1_2 on
-			# Required so the NVMe gets placed into D3 when entering S0i3.
-			chip drivers/pcie/rtd3/device
-				register "name" = ""NVME""
-				device pci 00.0 on end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "0"
+			register "end_lane" = "7"
+			register "aspm" = "ASPM_L1"
+			register "clk_req" = "CLK_REQ0"
+			# register "gpio_group" is currently not used
+			device ref gpp_bridge_1_1 on end # MXM
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "8"
+			register "end_lane" = "11"
+			register "aspm" = "ASPM_L1"
+			register "clk_req" = "CLK_REQ1"
+			device ref gpp_bridge_1_2 on # NVMe SSD1
+				# Required so the NVMe gets placed into D3 when entering S0i3.
+				chip drivers/pcie/rtd3/device
+					register "name" = ""NVME""
+					device pci 00.0 on end
+				end
 			end
-		end # NVMe SSD1
-		device ref gpp_bridge_1_3 on end # GBE
-		device ref gpp_bridge_2_1 on end # SD
-		device ref gpp_bridge_2_2 on end # WWAN
-		device ref gpp_bridge_2_3 on end # WIFI
-		device ref gpp_bridge_2_4 on
-			# Required so the NVMe gets placed into D3 when entering S0i3.
-			chip drivers/pcie/rtd3/device
-				register "name" = ""NVME""
-				device pci 00.0 on end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "12"
+			register "end_lane" = "12"
+			register "aspm" = "ASPM_DISABLED"
+			register "clk_req" = "CLK_REQ6"
+			device ref gpp_bridge_1_3 on end # GBE
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "13"
+			register "end_lane" = "13"
+			register "aspm" = "ASPM_DISABLED"
+			register "clk_req" = "CLK_REQ5"
+			device ref gpp_bridge_2_1 on end # SD
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "14"
+			register "end_lane" = "14"
+			register "aspm" = "ASPM_DISABLED"
+			register "clk_req" = "CLK_REQ4"
+			device ref gpp_bridge_2_2 on end # WWAN
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "15"
+			register "end_lane" = "15"
+			register "aspm" = "ASPM_DISABLED"
+			register "clk_req" = "CLK_REQ3"
+			device ref gpp_bridge_2_3 on end # WIFI
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "16"
+			register "end_lane" = "19"
+			register "aspm" = "ASPM_DISABLED"
+			register "clk_req" = "CLK_REQ2"
+			device ref gpp_bridge_2_4 on # NVMe SSD0
+				# Required so the NVMe gets placed into D3 when entering S0i3.
+				chip drivers/pcie/rtd3/device
+					register "name" = ""NVME""
+					device pci 00.0 on end
+				end
 			end
-		end # NVMe SSD0
+		end
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref gfx on end # Internal GPU (GFX)
 			device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)

src/mainboard/amd/birman/mainboard.c

@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <types.h>
 #include "gpio.h"
+#include "update_devicetree.h"
 
 /* TODO: Update for birman */
 
@@ -58,6 +59,9 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
 static void mainboard_init(void *chip_info)
 {
 	mainboard_program_gpios();
+
+	if (CONFIG(BOARD_AMD_BIRMAN_PHOENIX_OPENSIL))
+		mainboard_update_devicetree_opensil();
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/amd/birman/update_devicetree.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_UPDATE_DEVICETREE_H
+#define MAINBOARD_UPDATE_DEVICETREE_H
+
+void mainboard_update_devicetree_opensil(void);
+
+#endif  /* MAINBOARD_UPDATE_DEVICETREE_H */

src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/soc_util.h>
+#include <vendorcode/amd/opensil/chip/mpio/chip.h>
+#include "update_devicetree.h"
+
+static void mainboard_update_mpio(void)
+{
+	struct device *mxm_bridge = DEV_PTR(gpp_bridge_1_1);
+	struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2);
+	struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2);
+	struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3);
+	struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge);
+	struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge);
+	struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge);
+	struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge);
+
+	/* Phoenix 2 has less PCIe lanes than Phoenix */
+	if (get_soc_type() == SOC_PHOENIX2) {
+		mxm_bridge_cfg->end_lane = 3;
+		ssd1_bridge_cfg->end_lane = 9;
+	}
+	if (!CONFIG(ENABLE_EVAL_CARD)) {
+		mxm_bridge->enabled = false;
+	}
+	if (CONFIG(DISABLE_DT_M2)) {
+		ssd1_bridge->enabled = false;
+	}
+	/* When the WLAN card uses 2 lanes, the WWAN card can't be used */
+	if (CONFIG(WLAN01)) {
+		wwan_bridge->enabled = false;
+		wlan_bridge_cfg->end_lane = 14;
+	}
+	/* When the WWAN card uses 2 lanes, the WLAN card can't be used */
+	if (CONFIG(WWAN01)) {
+		wlan_bridge->enabled = false;
+		wwan_bridge_cfg->end_lane = 15;
+	}
+}
+
+void mainboard_update_devicetree_opensil(void)
+{
+	mainboard_update_mpio();
+}

src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h

@@ -7,13 +7,13 @@
 
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
-	0x10ec0256,	// Codec Vendor / Device ID: Realtek ALC256
-	0x10ec12ac,	// Subsystem ID
+	0x10ec0236,	// Codec Vendor / Device ID: Realtek ALC236
+	0x103C8C60,	// Subsystem ID
 	0x00000013,	// Number of jacks (NID entries)
 
 	AZALIA_RESET(0x1),
 	/* NID 0x01, HDA Codec Subsystem ID Verb table */
-	AZALIA_SUBVENDOR(0, 0x10ec12ac),
+	AZALIA_SUBVENDOR(0, 0x103C8C60),
 
 	/* Pin Widget Verb Table */
 
@@ -30,41 +30,56 @@ const u32 cim_verb_data[] = {
 	/* Pin widget 0x18 - NPC */
 	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
 	/* Pin widget 0x19 - MIC2 (Port-F) */
-	AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x03A11020),
 	/* Pin widget 0x1A - LINE1 (Port-C) */
 	AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
 	/* Pin widget 0x1B - NPC */
 	AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
 	/* Pin widget 0x1D - BEEP-IN */
-	AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40600001),
 	/* Pin widget 0x1E - NPC */
 	AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
 	/* Pin widget 0x21 - HP1-OUT (Port-I) */
-	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+	AZALIA_PIN_CFG(0, 0x21, 0x03211040),
+
+	/*
+	 * ;Pin widget 0x19 - MIC2 (Port-F)
+	 */
+	0x01971C20,
+	0x01971D10,
+	0x01971EA1,
+	0x01971F03,
+	/*
+	 * Pin widget 0x21 - HP1-OUT (Port-I)
+	 */
+	0x02171C40,
+	0x02171D10,
+	0x02171E21,
+	0x02171F03,
 	/*
 	 * Widget node 0x20 - 1
 	 * Codec hidden reset and speaker power 2W/4ohm
 	 */
-	0x0205001A,
-	0x0204C003,
-	0x02050038,
-	0x02047901,
-	/*
-	 * Widget node 0x20 - 2
-	 * Class D power on Reset
-	 */
 	0x0205003C,
 	0x02040354,
 	0x0205003C,
 	0x02040314,
+	/*
+	 * Widget node 0x20 - 2
+	 * Class D power on Reset
+	 */
+	0x0205001B,
+	0x02040A4B,
+	0x0205000B,
+	0x02047778,
 	/*
 	 * Widget node 0x20 - 3
 	 * Disable AGC and set AGC limit to -1.5dB
 	 */
-	0x02050016,
-	0x02040C50,
-	0x02050012,
-	0x0204EBC1,
+	0x02050046,
+	0x02040004,
+	0x05750003,
+	0x057409A3,
 	/*
 	 * Widget node 0x20 - 4
 	 * Set AGC Post gain +1.5dB then Enable AGC

src/mainboard/google/brya/Kconfig

@@ -67,7 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
 	select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG
 	select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
 	select HAVE_SLP_S0_GATE
-	select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION
+	select MEMORY_SODIMM if !(BOARD_GOOGLE_CONSTITUTION || BOARD_GOOGLE_NOVA)
 	select RT8168_GEN_ACPI_POWER_RESOURCE
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
@@ -362,6 +362,7 @@ config BOARD_GOOGLE_NOKRIS
 config BOARD_GOOGLE_NOVA
 	select BOARD_GOOGLE_BASEBOARD_BRASK
 	select SOC_INTEL_RAPTORLAKE
+	select MEMORY_SOLDERDOWN
 
 config BOARD_GOOGLE_OMNIGUL
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -370,6 +371,9 @@ config BOARD_GOOGLE_OMNIGUL
 	select SOC_INTEL_RAPTORLAKE
 	select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
 
+config BOARD_GOOGLE_ORISA
+	select BOARD_GOOGLE_BASEBOARD_TRULO
+
 config BOARD_GOOGLE_OSIRIS
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -644,6 +648,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_NIVVIKS
 	default 0x1 if BOARD_GOOGLE_NOVA
 	default 0x1 if BOARD_GOOGLE_OMNIGUL
+	default 0x0 if BOARD_GOOGLE_ORISA
 	default 0x1 if BOARD_GOOGLE_OSIRIS
 	default 0x0 if BOARD_GOOGLE_PIRRHA
 	default 0x1 if BOARD_GOOGLE_PRIMUS
@@ -733,6 +738,7 @@ config MAINBOARD_PART_NUMBER
 	default "Nokris" if BOARD_GOOGLE_NOKRIS
 	default "Nova" if BOARD_GOOGLE_NOVA
 	default "Omnigul" if BOARD_GOOGLE_OMNIGUL
+	default "Orisa" if BOARD_GOOGLE_ORISA
 	default "Osiris" if BOARD_GOOGLE_OSIRIS
 	default "Pirrha" if BOARD_GOOGLE_PIRRHA
 	default "Primus" if BOARD_GOOGLE_PRIMUS
@@ -797,6 +803,7 @@ config VARIANT_DIR
 	default "nokris" if BOARD_GOOGLE_NOKRIS
 	default "nova" if BOARD_GOOGLE_NOVA
 	default "omnigul" if BOARD_GOOGLE_OMNIGUL
+	default "orisa" if BOARD_GOOGLE_ORISA
 	default "osiris" if BOARD_GOOGLE_OSIRIS
 	default "pirrha" if BOARD_GOOGLE_PIRRHA
 	default "primus" if BOARD_GOOGLE_PRIMUS

src/mainboard/google/brya/Kconfig.name

@@ -184,3 +184,6 @@ config BOARD_GOOGLE_SUNDANCE
 
 config BOARD_GOOGLE_PUJJOGA
 	bool "->  Pujjoga"
+
+config BOARD_GOOGLE_ORISA
+	bool "->  Orisa"

src/mainboard/google/brya/variants/bujia/Makefile.mk

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c

src/mainboard/google/brya/variants/bujia/gpio.c

@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A14 : USB_OC1# ==> NC */
+	PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG),
+	/* A15 : USB_OC2# ==> NC */
+	PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG),
+	/* A18 : DDSP_HPDB ==> HDMIB_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19 : DDSP_HPD1 ==> NC */
+	PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG),
+	/* A20 : DDSP_HPD2 ==> NC */
+	PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
+	/* A21 : DDPC_CTRCLK ==> NC */
+	PAD_NC(GPP_A21, NONE),
+	/* A22 : DDPC_CTRLDATA ==> NC */
+	PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
+
+	/* B2  : VRALERT# ==> M2_SSD_PLA_L */
+	PAD_NC(GPP_B2, NONE),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
+	PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
+	/* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
+	PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
+
+	/* D0  : ISH_GP0 ==> NC */
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
+	/* D1  : ISH_GP1 ==> NC */
+	PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
+	/* D2  : ISH_GP2 ==> NC */
+	PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
+	/* D3  : ISH_GP3 ==> NC */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D8  : SRCCLKREQ3# ==> NC */
+	PAD_NC(GPP_D8, NONE),
+	/* D9  : ISH_SPI_CS# ==> NC */
+	PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
+	/* D10 : ISH_SPI_CLK ==> GPI */
+	PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG),
+	/* D17 : UART1_RXD */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* D18 : UART1_TXD */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+
+	/* E14 : DDSP_HPDA ==> HDMIA_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* F11 : THC1_SPI2_CLK ==> NC */
+	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
+	/* F12 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* F13 : GSXDOUT ==> NC */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : GSXSRESET# ==> NC */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+	/* F16 : GSXCLK ==> NC */
+	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
+
+	/* H12 : I2C7_SDA ==> NC */
+	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
+	/* H13 : I2C7_SCL ==> NC */
+	PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
+
+	/* R4 : HDA_RST# ==> NC */
+	PAD_NC(GPP_R4, NONE),
+	/* R5 : HDA_SDI1 ==> NC */
+	PAD_NC(GPP_R5, NONE),
+	/* R6 : I2S2_TXD ==> NC */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : I2S2_RXD ==> NC */
+	PAD_NC(GPP_R7, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F14 : GSXDIN ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}

src/mainboard/google/brya/variants/bujia/overridetree.cb

@@ -1,6 +1,318 @@
 chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
 
-        device domain 0 on
-        end
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field	     |	Value			 |
+	#+-------------------+---------------------------+
+	#| GSPI1	     | NC			 |
+	#| I2C0		     | Audio			 |
+	#| I2C1		     | cr50 TPM. Early init is	 |
+	#|		     | required to set up a BAR  |
+	#|		     | for TPM communication	 |
+	#| I2C3		     | NC			 |
+	#| I2C5		     | NC			 |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+		.i2c[1] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+	}"
 
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A3
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Port 3 - Port 5 for OPS interface
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Disable Port 6
+
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY "		# Disable Port 2
+	# USB3 Port 3 for OPS interface
+
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"		# Disable Port1
+	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"		# Disable Port2
+
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+	}"
+
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		[DDI_PORT_1] = DDI_ENABLE_HPD,
+		[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM""
+				register "options.tsr[1].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,		CPU,	       95, 5000),
+					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,	       105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,	85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,	85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,	0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end #NVME
+		device ref tbt_pcie_rp1 off end
+		device ref tbt_pcie_rp2 off end
+
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 off end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5650""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5650""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-mode""
+				register "property_list[0].integer" = "2"
+				device i2c 1a on end
+			end
+		end # I2C0
+		device ref i2c1 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+				device i2c 50 on end
+			end
+		end # I2C1
+		device ref pcie_rp7 on
+			chip drivers/net
+				register "wake" = "GPE0_DW0_07"
+				register "customized_leds" = "0x060f"
+				register "enable_aspm_l1_2" = "1"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end # RTL8111 Ethernet NIC
+		device ref pcie_rp8 off end # disable SD reader
+		device ref gspi1 off end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A3 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A2 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 OPS interface TX25A""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 OPS interface TX25A""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 OPS interface TX25A""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 OPS interface TX25A""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+	end
 end

src/mainboard/google/brya/variants/nova/Makefile.mk

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c

src/mainboard/google/brya/variants/nova/memory.c

@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map as per doc #573387 */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  3,  0,  2,  1,  4,  6,  5,  7, },
+			.dq1 = {  12, 13, 14, 15, 8,  9,  10, 11, },
+		},
+		.ddr1 = {
+			.dq0 = { 13, 14, 11, 12,  10, 8, 15,  9, },
+			.dq1 = {  5,  2,  4,  3,  1,  6,  0,  7, },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  7,  6,  5,  4, },
+			.dq1 = { 12,  13, 14, 15, 8,  9, 10, 11, },
+		},
+		.ddr3 = {
+			.dq0 = { 13, 14, 12, 15, 11,  9,  8, 10, },
+			.dq1 = {  5,  2,  1,  4,  7,  0,  3,  6, },
+		},
+		.ddr4 = {
+			.dq0 = { 11, 10,  8,  9, 14, 15, 13, 12, },
+			.dq1 = {  3,  0,  2,  1,  5,  4,  6,  7, },
+		},
+		.ddr5 = {
+			.dq0 = { 11, 15, 13, 12, 10,  9, 14,  8, },
+			.dq1 = {  3,  0,  2,  1,  6,  7,  5,  4, },
+		},
+		.ddr6 = {
+			.dq0 = { 11, 13, 10, 12, 15,  9, 14,  8, },
+			.dq1 = {  4,  3,  5,  2,  7,  0,  1,  6, },
+		},
+		.ddr7 = {
+			.dq0 = { 12, 13, 15, 14, 11,  9, 10,  8, },
+			.dq1 = {  4,  5,  1,  2,  6,  3,  0,  7, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map as per doc #573387 */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_F16
+	 * GPIO_MEM_CONFIG_1	GPP_F12
+	 * GPIO_MEM_CONFIG_2	GPP_F13
+	 * GPIO_MEM_CONFIG_3	GPP_F15
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_F16,
+		GPP_F12,
+		GPP_F13,
+		GPP_F15,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_F11 */
+	return gpio_get(GPP_F11);
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}

src/mainboard/google/brya/variants/nova/memory/Makefile.mk

@@ -1,8 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE

src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt

@@ -1,10 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 K4U6E3S4AB-MGCL                0 (0000)
 H9HCNNNBKMMLXR-NEE             0 (0000)
-MT53E1G32D2NP-046 WT:B         1 (0001)
-K4UBE3D4AB-MGCL                1 (0001)

src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt

@@ -1,4 +1,2 @@
 K4U6E3S4AB-MGCL
 H9HCNNNBKMMLXR-NEE
-MT53E1G32D2NP-046 WT:B
-K4UBE3D4AB-MGCL

src/mainboard/google/brya/variants/nova/overridetree.cb

@@ -178,13 +178,6 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end
-		device ref tcss_dma0 on
-			chip drivers/intel/usb4/retimer
-				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
-				use tcss_usb3_port1 as dfp[0].typec_port
-				device generic 0 on end
-			end
-		end
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"

src/mainboard/google/brya/variants/orisa/include/variant/ec.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/brya/variants/orisa/include/variant/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif

src/mainboard/google/brya/variants/orisa/memory/Makefile.mk

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder

src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt

@@ -0,0 +1 @@
+DRAM Part Name                 ID to assign

src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt

@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name

src/mainboard/google/brya/variants/orisa/overridetree.cb

@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+        device domain 0 on
+        end
+
+end

src/mainboard/google/dedede/variants/kracko/overridetree.cb

@@ -133,6 +133,15 @@ chip soc/intel/jasperlake
 							probe DB_PORTS DB_PORTS_1C_LTE
 						end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device usb 2.1 on
+							probe DB_PORTS DB_PORTS_1C_1A
+							probe DB_PORTS DB_PORTS_1C_LTE
+						end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""Right Type-A Port""
 						register "type" = "UPC_TYPE_A"
@@ -151,6 +160,15 @@ chip soc/intel/jasperlake
 						register "type" = "UPC_TYPE_INTERNAL"
 						device usb 2.6 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device usb 3.1 on
+							probe DB_PORTS DB_PORTS_1C_1A
+							probe DB_PORTS DB_PORTS_1C_LTE
+						end
+					end
 					chip drivers/usb/acpi
 						register "desc" = ""LTE""
 						register "type" = "UPC_TYPE_INTERNAL"

src/mainboard/google/dedede/variants/kracko/ramstage.c

@@ -11,7 +11,23 @@ static void ext_vr_update(void)
 		cfg->disable_external_bypass_vr = 1;
 }
 
+static void usb_port_update(void)
+{
+	struct soc_intel_jasperlake_config *cfg = config_of_soc();
+
+	if (fw_config_is_provisioned() &&
+	   fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_NONE))) {
+		/* Disable USB C1 port */
+		cfg->usb2_ports[1].enable = 0;
+		cfg->usb3_ports[1].enable = 0;
+		/* Disable USB A1 port */
+		cfg->usb2_ports[3].enable = 0;
+		cfg->usb3_ports[3].enable = 0;
+	}
+}
+
 void variant_devtree_update(void)
 {
 	ext_vr_update();
+	usb_port_update();
 }

src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h

@@ -24,6 +24,9 @@ int variant_memory_sku(void);
 bool variant_is_half_populated(void);
 void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config);
 
+/* Get soc power limit config struct for current CPU sku */
+struct soc_power_limits_config *variant_get_soc_power_limit_config(void);
+
 enum s0ix_entry {
 	S0IX_EXIT,
 	S0IX_ENTRY,

src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb

@@ -86,6 +86,7 @@ chip soc/intel/meteorlake
 	device domain 0 on
 		device ref igpu on end
 		device ref dtt on end
+		device ref vpu on end
 		device ref ioe_shared_sram on end
 		device ref xhci on end
 		device ref pmc_shared_sram on end

src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c

@@ -1,8 +1,35 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <console/console.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <intelblocks/power_limit.h>
+#include <soc/pci_devs.h>
+
+struct soc_power_limits_config *variant_get_soc_power_limit_config(void)
+{
+	config_t *config = config_of_soc();
+	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+	u8 tdp = get_cpu_tdp();
+	size_t i = 0;
+
+	if (mchid == 0xffff)
+		return NULL;
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) {
+		if (mchid == cpuid_to_mtl[i].cpu_id && tdp == cpuid_to_mtl[i].cpu_tdp) {
+			return &config->power_limits_config[cpuid_to_mtl[i].limits];
+		}
+	}
+
+	if (i == ARRAY_SIZE(cpuid_to_mtl)) {
+		printk(BIOS_ERR, "Cannot find correct ovis sku index.\n");
+		return NULL;
+	}
+
+	return NULL;
+}
 
 /*
  * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),

src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb

@@ -97,6 +97,7 @@ chip soc/intel/meteorlake
 	device domain 0 on
 		device ref igpu on end
 		device ref dtt on end
+		device ref vpu on end
 		device ref ioe_shared_sram on end
 		device ref xhci on end
 		device ref pmc_shared_sram on end

src/mainboard/google/rex/variants/karis/overridetree.cb

@@ -34,10 +34,6 @@ fw_config
 		option DISABLE			0
 		option ENABLE			1
 	end
-	field VPU 22
-		option VPU_DIS			0
-		option VPU_EN			1
-	end
 end
 
 chip soc/intel/meteorlake
@@ -585,8 +581,5 @@ chip soc/intel/meteorlake
 			end
 		end
 		device ref hda on end
-		device ref vpu on
-			probe VPU VPU_EN
-		end
 	end
 end

src/mainboard/google/rex/variants/rex0/overridetree.cb

@@ -52,10 +52,6 @@ fw_config
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1
 	end
-	field VPU 22
-		option VPU_DIS			0
-		option VPU_EN			1
-	end
 end
 
 chip soc/intel/meteorlake
@@ -323,9 +319,6 @@ chip soc/intel/meteorlake
 		end
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp2 on end
-		device ref vpu on
-			probe VPU VPU_EN
-		end
 		device ref tcss_xhci on
 			chip drivers/usb/acpi
 				device ref tcss_root_hub on

src/mainboard/google/rex/variants/screebo/overridetree.cb

@@ -30,10 +30,6 @@ fw_config
 		option WIFI_SAR_ID_0		0
 		option WIFI_SAR_ID_1		1
 	end
-	field VPU 22
-		option VPU_DIS			0
-		option VPU_EN			1
-	end
 end
 
 chip soc/intel/meteorlake
@@ -602,8 +598,5 @@ chip soc/intel/meteorlake
 				end
 			end
 		end
-		device ref vpu on
-			probe VPU VPU_EN
-		end
 	end
 end

src/mainboard/intel/avenuecity_crb/Kconfig

@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_INTEL_AVENUECITY_CRB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select SOC_INTEL_GRANITERAPIDS
+	select SUPERIO_ASPEED_AST2400
+	select HAVE_ACPI_TABLES
+	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
+	select VPD
+	select OCP_VPD
+	select MEMORY_MAPPED_TPM
+
+config CARDBUS_PLUGIN_SUPPORT
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default "intel/avenuecity_crb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Avenue City CRB"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config DIMM_MAX
+	int
+	default 1
+
+endif

src/mainboard/intel/avenuecity_crb/Kconfig.name

@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_INTEL_AVENUECITY_CRB
+	bool "Avenue City CRB"

src/mainboard/intel/avenuecity_crb/Makefile.mk

@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+romstage-y += config/iio.c
+ramstage-y += ramstage.c

src/mainboard/intel/avenuecity_crb/board.fmd

@@ -0,0 +1,12 @@
+FLASH@0xfc000000 64M {
+	SI_ALL 48M {
+		SI_DESC@0x0 0x1000
+	}
+	SI_BIOS 16M {
+		RW_MRC_CACHE 0x10000
+		FMAP 0x800
+		RW_VPD(PRESERVE) 0x4000
+		RO_VPD(PRESERVE) 0x4000
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/intel/avenuecity_crb/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Avenue City CRB
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y

src/mainboard/intel/avenuecity_crb/bootblock.c

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <intelblocks/lpc_lib.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+	lpc_io_setup_comm_a_b();
+	lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F);
+
+	if (CONFIG_UART_FOR_CONSOLE == 0) {
+		/* Setup superio com1 */
+		const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+		aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+	} else
+		die("COMs other than COM1 not supported\n");
+}

src/mainboard/intel/avenuecity_crb/config/iio.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/iio.h>
+
+static const struct iio_pe_config iio_config_table[] = {
+	/*
+	 * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated
+	 * then port settings are listed accordingly. The minimal port elements are x2.
+	 * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be
+	 * disabled.
+	 */
+	{_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5),
+	}},
+};
+
+const struct iio_pe_config *get_iio_config_table(int *size)
+{
+	*size = ARRAY_SIZE(iio_config_table);
+	return iio_config_table;
+}

src/mainboard/intel/avenuecity_crb/devicetree.cb

@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/gnr
+
+	# configure LPC generic IO decode ranges
+	# 	[bits 31..24: reserved]
+	# 	[bits 23..18: io decode address mask <7..2>]
+	# 	[bits 17..16: reserved]
+	# 	[bits 15..2 : io decode dword aligned address <15..2>]
+	#	[bit 1      : reserved]
+	#	[bit 0      : enabled]
+	register "gen1_dec" = "0x00000CA1" # IPMI KCS
+
+	# configure FSP debug settings
+	register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE
+
+	device domain 0 on
+		device pci 1f.0 on
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on # SUART1
+							io 0x60 = 0x3f8 # PNP_IDX_IO0
+							irq 0x70 = 4 # PNP_IDX_IRQ0
+						end
+					end
+				end
+			end
+			chip drivers/ipmi
+				device pnp ca2.0 on end # BMC KCS
+				register "wait_for_bmc" = "1"
+				register "bmc_boot_timeout" = "60"
+			end
+		end
+	end
+end

src/mainboard/intel/avenuecity_crb/dsdt.asl

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+	#include <commonlib/include/commonlib/console/post_codes.h>
+	#include <arch/x86/acpi/post.asl>
+	#include <arch/x86/acpi/debug.asl>
+}

src/mainboard/intel/avenuecity_crb/ramstage.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+
+}

src/mainboard/intel/avenuecity_crb/romstage.c

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <drivers/ipmi/ipmi_if.h>
+#include <drivers/ocp/include/vpd.h>
+#include <drivers/vpd/vpd.h>
+#include <fmap_config.h>
+#include <device/device.h>
+#include <soc/ddr.h>
+#include <soc/iio.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+#include "chip.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	/* FSP log outputs */
+	const config_t *config = config_of_soc();
+	m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base;
+	m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT);
+	m_cfg->DebugPrintLevel = config->debug_print_level;
+	m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL,
+		FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
+
+	/* Early connect BMC, e.g. to query configuration parameters */
+	if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS)
+		printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n",
+			CONFIG_BMC_KCS_BASE);
+
+	/* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */
+	m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
+	m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
+	printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
+	printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);
+
+	/* IIO init */
+	int size;
+	const struct iio_pe_config *iio_config_table = get_iio_config_table(&size);
+	soc_config_iio_pe_ports(mupd, iio_config_table, size);
+}
+
+bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
+{
+	//TODO: not implemented yet
+	return false;
+}

src/mainboard/intel/beechnutcity_crb/Kconfig

@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_INTEL_BEECHNUTCITY_CRB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select SOC_INTEL_GRANITERAPIDS
+	select SUPERIO_ASPEED_AST2400
+	select HAVE_ACPI_TABLES
+	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
+	select VPD
+	select OCP_VPD
+	select MEMORY_MAPPED_TPM
+
+config CARDBUS_PLUGIN_SUPPORT
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default "intel/beechnutcity_crb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Beechnut City CRB"
+
+config FMDFILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config DIMM_MAX
+	int
+	default 1
+
+endif

src/mainboard/intel/beechnutcity_crb/Kconfig.name

@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_INTEL_BEECHNUTCITY_CRB
+	bool "Beechnut City CRB"

src/mainboard/intel/beechnutcity_crb/Makefile.mk

@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+romstage-y += config/iio.c
+ramstage-y += ramstage.c

src/mainboard/intel/beechnutcity_crb/board.fmd

@@ -0,0 +1,12 @@
+FLASH@0xfc000000 64M {
+	SI_ALL 48M {
+		SI_DESC@0x0 0x1000
+	}
+	SI_BIOS 16M {
+		RW_MRC_CACHE 0x10000
+		FMAP 0x800
+		RW_VPD(PRESERVE) 0x4000
+		RO_VPD(PRESERVE) 0x4000
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/intel/beechnutcity_crb/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Beechnut City CRB
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y

src/mainboard/intel/beechnutcity_crb/bootblock.c

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <intelblocks/lpc_lib.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+	lpc_io_setup_comm_a_b();
+	lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F);
+
+	if (CONFIG_UART_FOR_CONSOLE == 0) {
+		/* Setup superio com1 */
+		const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+		aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+	} else
+		die("COMs other than COM1 not supported\n");
+}

src/mainboard/intel/beechnutcity_crb/config/iio.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/iio.h>
+
+static const struct iio_pe_config iio_config_table[] = {
+	/*
+	 * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated
+	 * then port settings are listed accordingly. The minimal port elements are x2.
+	 * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be
+	 * disabled.
+	 */
+	{_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) {
+		/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
+		_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1),
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_DISABLED,
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4),
+		_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5),
+	}},
+};
+
+const struct iio_pe_config *get_iio_config_table(int *size)
+{
+	*size = ARRAY_SIZE(iio_config_table);
+	return iio_config_table;
+}

src/mainboard/intel/beechnutcity_crb/devicetree.cb

@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/gnr
+
+	# configure LPC generic IO decode ranges
+	# 	[bits 31..24: reserved]
+	# 	[bits 23..18: io decode address mask <7..2>]
+	# 	[bits 17..16: reserved]
+	# 	[bits 15..2 : io decode dword aligned address <15..2>]
+	#	[bit 1      : reserved]
+	#	[bit 0      : enabled]
+	register "gen1_dec" = "0x00000CA1" # IPMI KCS
+
+	# configure FSP debug settings
+	register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE
+
+	device domain 0 on
+		device pci 1f.0 on
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on # SUART1
+							io 0x60 = 0x3f8 # PNP_IDX_IO0
+							irq 0x70 = 4 # PNP_IDX_IRQ0
+						end
+					end
+				end
+			end
+			chip drivers/ipmi
+				device pnp ca2.0 on end # BMC KCS
+				register "wait_for_bmc" = "1"
+				register "bmc_boot_timeout" = "60"
+			end
+		end
+	end
+end

src/mainboard/intel/beechnutcity_crb/dsdt.asl

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+	#include <commonlib/include/commonlib/console/post_codes.h>
+	#include <arch/x86/acpi/post.asl>
+	#include <arch/x86/acpi/debug.asl>
+}

src/mainboard/intel/beechnutcity_crb/ramstage.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+
+}

src/mainboard/intel/beechnutcity_crb/romstage.c

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <drivers/ipmi/ipmi_if.h>
+#include <drivers/ocp/include/vpd.h>
+#include <drivers/vpd/vpd.h>
+#include <fmap_config.h>
+#include <device/device.h>
+#include <soc/ddr.h>
+#include <soc/iio.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+#include "chip.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	/* FSP log outputs */
+	const config_t *config = config_of_soc();
+	m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base;
+	m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT);
+	m_cfg->DebugPrintLevel = config->debug_print_level;
+	m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL,
+		FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
+
+	/* Early connect BMC, e.g. to query configuration parameters */
+	if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS)
+		printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n",
+			CONFIG_BMC_KCS_BASE);
+
+	/* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */
+	m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
+	m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
+	printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
+	printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);
+
+	/* IIO init */
+	int size;
+	const struct iio_pe_config *iio_config_table = get_iio_config_table(&size);
+	soc_config_iio_pe_ports(mupd, iio_config_table, size);
+}
+
+bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
+{
+	//TODO: not implemented yet
+	return false;
+}

src/mainboard/prodrive/hermes/hda_verb.c

@@ -95,15 +95,15 @@ static u32 get_port_b_vref_cfg(uint8_t pink_rear_vref)
 	switch (pink_rear_vref) {
 	default:
 	case 0:
-		return 0x411110f0; /* Disabled (Hi-Z) */
+		return 0; /* Disabled (Hi-Z) */
 	case 1:
-		return 0x411111f0; /* 50% of LDO out */
+		return 1; /* 50% of LDO out */
 	case 2:
-		return 0x411114f0; /* 80% of LDO out */
+		return 4; /* 80% of LDO out */
 	case 3:
-		return 0x411115f0; /* 100% of LDO out */
+		return 5; /* 100% of LDO out */
 	case 4:
-		return 0x411112f0; /* Ground */
+		return 2; /* Ground */
 	}
 }
 
@@ -145,7 +145,7 @@ static void mainboard_r0x_configure_alc888(u8 *base, u32 viddid)
 		 * persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
 		 * to restore port B Vref after resetting the codec.
 		 */
-		AZALIA_PIN_CFG(0, 0x12, port_b_vref_cfg),
+		AZALIA_PIN_CFG(0, 0x12, 0x411110f0 | port_b_vref_cfg << 8),
 		AZALIA_PIN_CFG(0, 0x19, front_mic_cfg),
 		AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg),
 		0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */

src/mainboard/system76/bonw14/Kconfig

@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/bonw14/Makefile.mk

@@ -10,3 +10,4 @@ romstage-y += romstage.c
 ramstage-y += ramstage.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/bonw14/devicetree.cb

@@ -219,7 +219,16 @@ chip soc/intel/cannonlake
 		device pci 1f.3 on      # Intel HDA
 			register "PchHdaAudioLinkHda" = "1"
 		end
-		device pci 1f.4 on  end # SMBus
+		device pci 1f.4 on      # SMBus
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+			chip drivers/i2c/tas5825m
+				register "id" = "1"
+				device i2c 4f on end # (8bit address: 0x9e)
+			end
+		end
 		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 off end # GbE
 	end

src/mainboard/system76/bonw14/tas5825m.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+#include "tas5825m-normal.c"
+#include "tas5825m-sub.c"
+
+int tas5825m_setup(struct device *dev, int id)
+{
+	if (id == 0)
+		return tas5825m_setup_normal(dev);
+	if (id == 1)
+		return tas5825m_setup_sub(dev);
+	return -1;
+}

src/security/tpm/tss/vendor/cr50/cr50.c

@@ -14,7 +14,7 @@ tpm_result_t tlcl_cr50_enable_nvcommits(void)
 	uint16_t sub_command = TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS;
 	struct tpm2_response *response;
 
-	printk(BIOS_INFO, "Enabling cr50 nvmem commits\n");
+	printk(BIOS_INFO, "Enabling GSC nvmem commits\n");
 
 	response = tlcl2_process_command(TPM2_CR50_VENDOR_COMMAND, &sub_command);
 
@@ -37,7 +37,7 @@ tpm_result_t tlcl_cr50_enable_update(uint16_t timeout_ms,
 		TPM2_CR50_SUB_CMD_TURN_UPDATE_ON, timeout_ms
 	};
 
-	printk(BIOS_INFO, "Checking cr50 for pending updates\n");
+	printk(BIOS_INFO, "Checking GSC for pending updates\n");
 
 	response = tlcl2_process_command(TPM2_CR50_VENDOR_COMMAND, command_body);
 
@@ -53,7 +53,7 @@ tpm_result_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state)
 	struct tpm2_response *response;
 	uint16_t sub_command = TPM2_CR50_SUB_CMD_GET_REC_BTN;
 
-	printk(BIOS_INFO, "Checking cr50 for recovery request\n");
+	printk(BIOS_INFO, "Checking GSC for recovery request\n");
 
 	response = tlcl2_process_command(TPM2_CR50_VENDOR_COMMAND, &sub_command);
 
@@ -70,7 +70,7 @@ tpm_result_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode)
 	uint16_t mode_command = TPM2_CR50_SUB_CMD_TPM_MODE;
 	*tpm_mode = TPM_MODE_INVALID;
 
-	printk(BIOS_INFO, "Reading cr50 TPM mode\n");
+	printk(BIOS_INFO, "Reading GSC TPM mode\n");
 
 	response = tlcl2_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command);
 
@@ -110,7 +110,7 @@ tpm_result_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode)
 	struct tpm2_response *response;
 	uint16_t mode_command = TPM2_CR50_SUB_CMD_GET_BOOT_MODE;
 
-	printk(BIOS_DEBUG, "Reading cr50 boot mode\n");
+	printk(BIOS_DEBUG, "Reading GSC boot mode\n");
 
 	response = tlcl2_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command);
 
@@ -140,7 +140,7 @@ tpm_result_t tlcl_cr50_immediate_reset(uint16_t timeout_ms)
 	/*
 	 * Issue an immediate reset to the Cr50.
 	 */
-	printk(BIOS_INFO, "Issuing cr50 reset\n");
+	printk(BIOS_INFO, "Issuing GSC reset\n");
 	response = tlcl2_process_command(TPM2_CR50_VENDOR_COMMAND, &reset_command_body);
 
 	if (!response)

src/soc/amd/phoenix/Kconfig

@@ -109,7 +109,8 @@ if SOC_AMD_PHOENIX_BASE
 
 config CHIPSET_DEVICETREE
 	string
-	default "soc/amd/phoenix/chipset.cb"
+	default "soc/amd/phoenix/chipset_fsp.cb" if SOC_AMD_PHOENIX_FSP
+	default "soc/amd/phoenix/chipset_opensil.cb"
 
 config EARLY_RESERVED_DRAM_BASE
 	hex

src/soc/amd/phoenix/chipset_opensil.cb

@@ -0,0 +1,170 @@
+# TODO: Update for Phoenix
+
+chip soc/amd/phoenix
+	device cpu_cluster 0 on
+		ops amd_cpu_bus_ops
+	end
+	device domain 0 on
+		ops phoenix_pci_domain_ops
+		device pci 00.0 alias gnb on ops phoenix_root_complex_operations end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
+
+		device pci 01.0 on end # Dummy device function, do not disable
+		# The PCIe GPP aliases in this SoC match the device and function numbers
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end
+		end
+
+		device pci 02.0 on end # Dummy device function, do not disable
+		# The PCIe GPP aliases in this SoC match the device and function numbers
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end
+		end
+		chip vendorcode/amd/opensil/chip/mpio
+			device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end
+		end
+
+		device pci 03.0 on end # Dummy device function, do not disable
+		device pci 03.1 alias usb4_pcie_bridge_0 off end
+
+		device pci 04.0 on end # Dummy device function, do not disable
+		device pci 04.1 alias usb4_pcie_bridge_1 off end
+
+		device pci 08.0 on end # Dummy device function, do not disable
+		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+			ops amd_internal_pcie_gpp_ops
+			device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
+			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
+			device pci 0.2 alias crypto off end # Crypto Coprocessor
+			device pci 0.3 alias xhci_0 off
+				ops xhci_pci_ops
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias xhci_0_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port2 off end
+						end
+						chip drivers/usb/acpi
+							device usb 3.1 alias usb3_port3 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port2 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.1 alias usb2_port3 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.2 alias usb2_port4 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.3 alias usb2_port5 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.4 alias usb2_port6 off end
+						end
+					end
+				end
+			end
+			device pci 0.4 alias xhci_1 off
+				ops xhci_pci_ops
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias xhci_1_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port7 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port7 off end
+						end
+					end
+				end
+			end
+			device pci 0.5 alias acp off ops amd_acp_ops end # Audio Processor (ACP)
+			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
+			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
+		end
+		device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+			ops amd_internal_pcie_gpp_ops
+			device pci 0.0 on end # dummy, do not disable
+			device pci 0.1 alias ipu off end
+		end
+
+		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+			ops amd_internal_pcie_gpp_ops
+			device pci 0.0 on end # dummy, do not disable
+			device pci 0.3 alias usb4_xhci_0 off
+				ops xhci_pci_ops
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias usb4_xhci_0_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port0 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port0 off end
+						end
+					end
+				end
+			end
+			device pci 0.4 alias usb4_xhci_1 off
+				ops xhci_pci_ops
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias usb4_xhci_1_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port1 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port1 off end
+						end
+					end
+				end
+			end
+			device pci 0.5 alias usb4_router_0 off end
+			device pci 0.6 alias usb4_router_1 off end
+		end
+
+		device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function
+		device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
+
+		device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end
+		device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end
+		device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end
+		device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end
+		device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end
+		device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end
+		device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end
+		device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end
+	end
+
+	device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
+	device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end
+	device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end
+	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
+	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+end

src/soc/intel/meteorlake/chip.h

@@ -515,6 +515,9 @@ struct soc_intel_meteorlake_config {
 	/* Platform Power Pmax in Watts. Zero means automatic. */
 	uint16_t psys_pmax_watts;
 
+	/* Platform Power Limit 2 in Watts. */
+	uint16_t psys_pl2_watts;
+
 	/* Enable or Disable Acoustic Noise Mitigation feature */
 	uint8_t enable_acoustic_noise_mitigation;
 	/* Disable Fast Slew Rate for Deep Package C States for VR domains */

src/soc/intel/xeon_sp/gnr/Makefile.mk

@@ -11,6 +11,7 @@ subdirs-y += ../../../../cpu/intel/microcode
 
 romstage-y += romstage.c
 romstage-y += soc_util.c
+romstage-y += soc_iio.c
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 
 ramstage-y += chip.c

src/soc/intel/xeon_sp/gnr/include/soc/iio.h

@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_IIO_H_
+#define _SOC_IIO_H_
+
+#include <soc/soc_util.h>
+
+#include <fsp/util.h>
+#include <FspmUpd.h>
+#include <IioPcieConfigUpd.h>
+
+#define CB_IIO_BIFURCATE_xxxxxxxx		IIO_BIFURCATE_xxxxxxxx
+#define CB_IIO_BIFURCATE_x4x4x4x4		IIO_BIFURCATE_x4x4x4x4
+#define CB_IIO_BIFURCATE_x8xxx4x4		IIO_BIFURCATE_x4x4xxx8
+#define CB_IIO_BIFURCATE_x4x4x8xx		IIO_BIFURCATE_xxx8x4x4
+#define CB_IIO_BIFURCATE_x8xxx8xx		IIO_BIFURCATE_xxx8xxx8
+#define CB_IIO_BIFURCATE_x16xxxxx		IIO_BIFURCATE_xxxxxx16
+#define CB_IIO_BIFURCATE_x8x4x2x2		IIO_BIFURCATE_x2x2x4x8
+#define CB_IIO_BIFURCATE_x8x2x2x4		IIO_BIFURCATE_x4x2x2x8
+#define CB_IIO_BIFURCATE_x4x2x2x8		IIO_BIFURCATE_x8x2x2x4
+#define CB_IIO_BIFURCATE_x2x2x4x8		IIO_BIFURCATE_x8x4x2x2
+#define CB_IIO_BIFURCATE_x4x4x4x2x2		IIO_BIFURCATE_x2x2x4x4x4
+#define CB_IIO_BIFURCATE_x4x4x2x2x4		IIO_BIFURCATE_x4x2x2x4x4
+#define CB_IIO_BIFURCATE_x4x2x2x4x4		IIO_BIFURCATE_x4x4x2x2x4
+#define CB_IIO_BIFURCATE_x2x2x4x4x4		IIO_BIFURCATE_x4x4x4x2x2
+#define CB_IIO_BIFURCATE_x8x2x2x2x2		IIO_BIFURCATE_x2x2x2x2x8
+#define CB_IIO_BIFURCATE_x2x2x2x2x8		IIO_BIFURCATE_x8x2x2x2x2
+#define CB_IIO_BIFURCATE_x4x4x2x2x2x2		IIO_BIFURCATE_x2x2x2x2x4x4
+#define CB_IIO_BIFURCATE_x4x2x2x4x2x2		IIO_BIFURCATE_x2x2x4x2x2x4
+#define CB_IIO_BIFURCATE_x2x2x4x4x2x2		IIO_BIFURCATE_x2x2x4x4x2x2
+#define CB_IIO_BIFURCATE_x4x2x2x2x2x4		IIO_BIFURCATE_x4x2x2x2x2x4
+#define CB_IIO_BIFURCATE_x2x2x4x2x2x4		IIO_BIFURCATE_x4x2x2x4x2x2
+#define CB_IIO_BIFURCATE_x2x2x2x2x4x4		IIO_BIFURCATE_x4x4x2x2x2x2
+#define CB_IIO_BIFURCATE_x4x2x2x2x2x2x2		IIO_BIFURCATE_x2x2x2x2x2x2x4
+#define CB_IIO_BIFURCATE_x2x2x4x2x2x2x2		IIO_BIFURCATE_x2x2x2x2x4x2x2
+#define CB_IIO_BIFURCATE_x2x2x2x2x4x2x2		IIO_BIFURCATE_x2x2x4x2x2x2x2
+#define CB_IIO_BIFURCATE_x2x2x2x2x2x2x4		IIO_BIFURCATE_x4x2x2x2x2x2x2
+#define CB_IIO_BIFURCATE_x2x2x2x2x2x2x2x2	IIO_BIFURCATE_x2x2x2x2x2x2x2x2
+#define CB_IIO_BIFURCATE_AUTO			IIO_BIFURCATE_AUTO
+
+struct iio_port_config {
+	uint8_t	vpp_address;			// SMBUS address of IO expander which provides VPP register
+	uint8_t	vpp_port;			// Port or bank on IoExpander which provides VPP register
+	uint8_t	vpp_mux_address;		// SMBUS address of MUX used to access VPP
+	uint8_t	vpp_mux_channel;		// Channel of the MUX used to access VPP
+
+	uint8_t	slot_eip:1;			// Electromechanical Interlock Present -
+						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+	uint8_t	slot_hps:1;			// Hot Plug surprise supported -
+						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+	uint8_t	slot_pind:1;			// Power Indicator Present -
+						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+	uint8_t	slot_aind:1;			// Attention Inductor Present -
+						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+	uint8_t	slot_pctl:1;			// Power Controller Present -
+						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
+	uint8_t	slot_abtn:1;			// Attention Button Present -
+						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+	uint8_t	slot_rsvd:2;			// Reserved
+
+	uint8_t	vpp_enabled:1;			// If VPP is supported on given port
+	uint8_t	vpp_exp_type:1;			// IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
+						//   for values definitions)
+
+	uint8_t	slot_implemented:1;
+	uint8_t	reserved:4;
+
+	uint16_t hot_plug:1;			// If hotplug is supported on slot connected to this port
+	uint16_t mrl_sensor_present:1;		// If MRL is present on slot connected to this port
+	uint16_t slot_power_limit_scale:2;	// Slot Power Scale for slot connected to this port
+	uint16_t slot_power_limit_value:12;	// Slot Power Value for slot connected to this port
+
+	uint16_t physical_slot_number;		// Slot number for slot connected to this port
+};
+
+struct iio_pe_config {
+	uint8_t			socket;
+	IIO_PACKAGE_PE		pe;
+	IIO_BIFURCATION		bifurcation;
+	uint8_t			cxl_support:1;
+	uint8_t			reserved:7;
+	struct iio_port_config	port_config[MAX_IIO_PORTS_PER_STACK];
+};
+
+/*
+ * {_IIO_PE_CFG_STRUCT(socket, pe, bif, cxl) {
+ *    _IIO_PORT_CFG_STRUCT(vppen vppex vaddr vport vmuxa vmuxc ...),
+ *    _IIO_PORT_CFG_STRUCT(..),
+ *    ...
+ *    _IIO_PORT_CFG_STRUCT(..) //MAX_IIO_PORTS_PER_STACK port configs
+ * }}
+ */
+
+#define PE_TYPE_CXL  1
+#define PE_TYPE_PCIE 0
+
+#define _IIO_PE_CFG_STRUCT(s, p, bif, cxl) \
+	.socket			= (s),\
+	.pe			= (p),\
+	.bifurcation		= (bif),\
+	.cxl_support		= (cxl),\
+	.reserved		= 0,\
+	.port_config		=
+
+/* TODO: to update rsv1 - rsv5 after SoC launch */
+#define _IIO_PORT_CFG_STRUCT(vppen, vppex, vaddr, vport, vmuxa, vmuxc,\
+		slteip, slthps, sltpind, sltaind, sltpctl, sltabtn, hotp, mrlsp,\
+		sltimpl, sltpls, sltplv, psn,\
+		rsv1, rsv2, rsv3, rsv4, rsv5) {\
+	.vpp_enabled		= (vppen),\
+	.vpp_exp_type		= (vppex),\
+	.vpp_address		= (vaddr),\
+	.vpp_port		= (vport),\
+	.vpp_mux_address	= (vmuxa),\
+	.vpp_mux_channel	= (vmuxc),\
+	.slot_eip		= (slteip),\
+	.slot_hps		= (slthps),\
+	.slot_pind		= (sltpind),\
+	.slot_aind		= (sltaind),\
+	.slot_pctl		= (sltpctl),\
+	.slot_abtn		= (sltabtn),\
+	.slot_rsvd		= 0,\
+	.slot_implemented	= (sltimpl),\
+	.reserved		= 0,\
+	.hot_plug		= (hotp),\
+	.mrl_sensor_present	= (mrlsp),\
+	.slot_power_limit_scale	= (sltpls),\
+	.slot_power_limit_value	= (sltplv),\
+	.physical_slot_number	= (psn)\
+}
+
+#define _IIO_PORT_CFG_STRUCT_DISABLED \
+	_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0)
+
+#define _IIO_PORT_CFG_STRUCT_X8 _IIO_PORT_CFG_STRUCT
+#define _IIO_PORT_CFG_STRUCT_X4 _IIO_PORT_CFG_STRUCT
+#define _IIO_PORT_CFG_STRUCT_X2 _IIO_PORT_CFG_STRUCT
+
+#define _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn)\
+	_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x1, sltpls, sltplv, psn, 0x0, 0x0, 0x0, 0x0, 0x0)
+
+#define _IIO_PORT_CFG_STRUCT_BASIC_X8 _IIO_PORT_CFG_STRUCT_BASIC
+#define _IIO_PORT_CFG_STRUCT_BASIC_X4 _IIO_PORT_CFG_STRUCT_BASIC
+#define _IIO_PORT_CFG_STRUCT_BASIC_X2 _IIO_PORT_CFG_STRUCT_BASIC
+
+void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_table,
+				unsigned int num_entries);
+
+const struct iio_pe_config *get_iio_config_table(int *size);
+
+#endif /* _SOC_IIO_H_ */

src/soc/intel/xeon_sp/gnr/soc_iio.c

@@ -0,0 +1,66 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/iio.h>
+#include <string.h>
+
+#include <fsp/util.h>
+#include <IioPcieConfigUpd.h>
+
+static IIO_BOARD_SETTINGS_HOB iio_upd_hob;
+
+void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_table,
+				unsigned int num_entries)
+{
+	int i;
+	uint8_t socket, pe, port;
+
+	const struct iio_pe_config *board_pe_config;
+	const struct iio_port_config *board_port_config;
+
+	IIO_BOARD_SETTINGS_PER_PE *upd_pe_config;
+	IIO_BOARD_SETTINGS_PER_PORT *upd_port_config;
+
+	for (i = 0; i < num_entries; i++) {
+		board_pe_config = &config_table[i];
+		socket = board_pe_config->socket;
+		pe = board_pe_config->pe;
+
+		upd_pe_config = &(iio_upd_hob.Socket[socket].Pe[pe]);
+
+		if ((socket >= MAX_SOCKET) || (pe >= MAX_IIO_PCIE_PER_SOCKET))
+			continue;
+
+		for (port = 0; port < MAX_IIO_PORTS_PER_STACK; port++) {
+			upd_port_config = &(upd_pe_config->Port[port]);
+			board_port_config = &(board_pe_config->port_config[port]);
+
+			upd_pe_config->Bifurcation = board_pe_config->bifurcation;
+			upd_pe_config->CxlSupportInUba = board_pe_config->cxl_support;
+
+			upd_port_config->Vpp.Address = board_port_config->vpp_address;
+			upd_port_config->Vpp.Port = board_port_config->vpp_port;
+			upd_port_config->Vpp.MuxAddress	= board_port_config->vpp_mux_address;
+			upd_port_config->Vpp.MuxChannel	= board_port_config->vpp_mux_channel;
+
+			upd_port_config->Slot.Eip = board_port_config->slot_eip;
+			upd_port_config->Slot.HotPlugSurprise = board_port_config->slot_hps;
+			upd_port_config->Slot.PowerInd = board_port_config->slot_pind;
+			upd_port_config->Slot.AttentionInd = board_port_config->slot_aind;
+			upd_port_config->Slot.PowerCtrl = board_port_config->slot_pctl;
+			upd_port_config->Slot.AttentionBtn = board_port_config->slot_abtn;
+
+			upd_port_config->VppEnabled = board_port_config->vpp_enabled;
+			upd_port_config->VppExpType = board_port_config->vpp_exp_type;
+
+			upd_port_config->SlotImplemented = board_port_config->slot_implemented;
+			upd_port_config->HotPlug = board_port_config->hot_plug;
+			upd_port_config->MrlSensorPresent = board_port_config->mrl_sensor_present;
+			upd_port_config->SlotPowerLimitScale = board_port_config->slot_power_limit_scale;
+			upd_port_config->SlotPowerLimitValue = board_port_config->slot_power_limit_value;
+			upd_port_config->PhysicalSlotNumber = board_port_config->physical_slot_number;
+		}
+	}
+
+	mupd->FspmConfig.IioBoardSettingsHobPtr = (UINT32)&iio_upd_hob;
+	mupd->FspmConfig.IioBoardSettingsHobLength = sizeof(iio_upd_hob);
+}

tests/Makefile.common

@@ -60,6 +60,7 @@ TEST_CFLAGS += -Os
 endif
 
 TEST_CFLAGS += -D__TEST__ -D__COREBOOT__
+TEST_CFLAGS += -D__TEST_DATA_DIR__=\"$(testsrc)/data\"
 
 ifneq ($(filter-out 0,$(TEST_PRINT)),)
 TEST_CFLAGS += -DTEST_PRINT=1
@@ -121,7 +122,6 @@ $$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER)
 $($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \
 	-D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ \
 	-D__TEST_NAME__=\"$(subst /,_,$(1))\" \
-	-D__TEST_DATA_DIR__=\"$(testsrc)/data\"
 
 # Give us a way to distinguish between coreboot source files and test files in code.
 $($(1)-srcobjs): TEST_CFLAGS += -D__TEST_SRCOBJ__

tests/helpers/file.c

@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fcntl.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+/*
+ * Get the file size of a given file
+ *
+ * @params fname  name of the file relative to the __TEST_DATA_DIR__ directory
+ *
+ * @return  On success file size in bytes is returned. On failure -1 is returned.
+ */
+int test_get_file_size(const char *fname)
+{
+	char path[strlen(__TEST_DATA_DIR__) + strlen(fname) + 2];
+	sprintf(path, "%s/%s", __TEST_DATA_DIR__, fname);
+
+	struct stat st;
+	if (stat(path, &st) == -1)
+		return -1;
+	return st.st_size;
+}
+
+/*
+ * Read a file and write its contents into a buffer
+ *
+ * @params fname  name of the file relative to the __TEST_DATA_DIR__ directory
+ * @params buf    buffer to write file contents into
+ * @params size   size of buf
+ *
+ * @return  On success number of bytes read is returned. On failure -1 is returned.
+ */
+int test_read_file(const char *fname, uint8_t *buf, size_t size)
+{
+	char path[strlen(__TEST_DATA_DIR__) + strlen(fname) + 2];
+	sprintf(path, "%s/%s", __TEST_DATA_DIR__, fname);
+
+	int f = open(path, O_RDONLY);
+	if (f == -1)
+		return -1;
+
+	int read_size = read(f, buf, size);
+
+	close(f);
+	return read_size;
+}

tests/include/helpers/file.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _TESTS_HELPERS_FILE_H
+#define _TESTS_HELPERS_FILE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+int test_get_file_size(const char *fname);
+int test_read_file(const char *fname, uint8_t *buf, size_t size);
+
+#endif

tests/lib/Makefile.mk

@@ -39,9 +39,15 @@ tests-y += cbfs-lookup-no-mcache-test
 tests-y += cbfs-lookup-has-mcache-test
 tests-y += lzma-test
 tests-y += ux_locales-test
+tests-y += device_tree-test
 
 lib-test-srcs += tests/lib/lib-test.c
 
+device_tree-test-srcs += tests/lib/device_tree-test.c
+device_tree-test-srcs += tests/stubs/console.c
+device_tree-test-srcs += src/lib/device_tree.c
+device_tree-test-syssrcs += tests/helpers/file.c
+
 string-test-srcs += tests/lib/string-test.c
 string-test-srcs += src/lib/string.c
 
@@ -234,6 +240,7 @@ lzma-test-srcs += tests/lib/lzma-test.c
 lzma-test-srcs += tests/stubs/console.c
 lzma-test-srcs += src/lib/lzma.c
 lzma-test-srcs += src/lib/lzmadecode.c
+lzma-test-syssrcs += tests/helpers/file.c
 
 ux_locales-test-srcs += tests/lib/ux_locales-test.c
 ux_locales-test-srcs += tests/stubs/console.c

tests/lib/device_tree-test.c

@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device_tree.h>
+#include <helpers/file.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <tests/test.h>
+
+static int setup_device_tree_test_group(void **state)
+{
+	/*
+	 * fattest FDT I could find from Linux Kernel to test the worst cases
+	 * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/nvidia/tegra30-ouya.dts?id=443b349019f2d946
+	 */
+	const char dtb_path[] = "lib/devicetree-test/tegra30-ouya.dtb";
+	int file_size = test_get_file_size(dtb_path);
+	assert_int_not_equal(file_size, -1);
+
+	void *big_fat_dtb = test_malloc(file_size);
+	assert_int_not_equal(big_fat_dtb, NULL);
+	assert_int_equal(test_read_file(dtb_path, big_fat_dtb, file_size), file_size);
+	*state = big_fat_dtb;
+
+	return 0;
+}
+
+static int teardown_device_tree_test_group(void **state)
+{
+	test_free(*state);
+	return 0;
+}
+
+static void test_fdt_find_node_by_path(void **state)
+{
+	uint32_t addrcp, sizecp;
+	assert_int_equal(0, fdt_find_node_by_path(*state, "test", &addrcp, &sizecp));
+	assert_int_equal(56, fdt_find_node_by_path(*state, "/", &addrcp, &sizecp));
+	assert_int_equal(2, addrcp);
+	assert_int_equal(1, sizecp);
+	assert_int_equal(0, fdt_find_node_by_path(*state, "/test", &addrcp, &sizecp));
+	assert_int_equal(0x181f4, fdt_find_node_by_path(*state, "/chosen", &addrcp, &sizecp));
+	assert_int_equal(1, addrcp);
+	assert_int_equal(1, sizecp);
+	assert_int_equal(0x156d4, fdt_find_node_by_path(*state, "/cpus", &addrcp, &sizecp));
+	assert_int_equal(1, addrcp);
+	assert_int_equal(1, sizecp);
+	assert_int_equal(0x1517c, fdt_find_node_by_path(*state, "/usb@7d004000/ethernet@2", &addrcp, &sizecp));
+	assert_int_equal(1, addrcp);
+	assert_int_equal(0, sizecp);
+	assert_int_equal(0x1517c, fdt_find_node_by_path(*state, "/usb@7d004000/ethernet@2/", &addrcp, &sizecp));
+	assert_int_equal(1, addrcp);
+	assert_int_equal(0, sizecp);
+
+	assert_int_equal(0xee08, fdt_find_node_by_path(*state, "/pinmux@70000868/pinmux/drive_groups",
+						       &addrcp, &sizecp));
+}
+
+static void test_fdt_find_subnodes_by_prefix(void **state)
+{
+	uint32_t offset = fdt_find_node_by_path(*state, "/cpus", NULL, NULL);
+	uint32_t results[3] = { 0 };
+	uint32_t addrcp, sizecp;
+	size_t count_results = fdt_find_subnodes_by_prefix(*state, offset, "cpu@",
+							   &addrcp, &sizecp, results, 3);
+	assert_int_equal(3, count_results);
+	assert_int_equal(0x15700, results[0]);
+	assert_int_equal(0x157a0, results[1]);
+	assert_int_equal(0x15840, results[2]);
+
+	results[1] = 0xDEADBEEF;
+	results[2] = 0xDEADBEEF;
+	count_results = fdt_find_subnodes_by_prefix(*state, offset, "cpu@",
+							   &addrcp, &sizecp, results, 1);
+	assert_int_equal(1, count_results);
+	assert_int_equal(0x15700, results[0]);
+	assert_int_equal(0xDEADBEEF, results[1]);
+	assert_int_equal(0xDEADBEEF, results[2]);
+}
+
+static void test_fdt_find_node_by_alias(void **state)
+{
+	assert_int_equal(0xf298, fdt_find_node_by_alias(*state, "serial0", NULL, NULL));
+	assert_int_equal(0, fdt_find_node_by_alias(*state, "mmc2", NULL, NULL));
+}
+
+static void test_fdt_find_prop_in_node(void **state)
+{
+	uintptr_t cnode_offset = fdt_find_node_by_path(*state, "/clock", NULL, NULL);
+	uintptr_t mnode_offset = fdt_find_node_by_path(*state, "/memory@80000000", NULL, NULL);
+	assert_int_equal(0x18400, cnode_offset);
+
+	struct fdt_property fdt_prop;
+	assert_int_equal(0x1840c, fdt_read_prop(*state, cnode_offset, "compatible", &fdt_prop));
+	assert_string_equal("fixed-clock", (char *)fdt_prop.data);
+	assert_int_equal(0x6094, fdt_read_prop(*state, mnode_offset, "reg", &fdt_prop));
+	assert_int_equal(0x0, fdt_read_prop(*state, cnode_offset, "notfound", &fdt_prop));
+}
+
+static void test_fdt_read_reg_prop(void **state)
+{
+	uint32_t addrcp1, sizecp1, addrcp2, sizecp2;
+	uint64_t node_offset1 = fdt_find_node_by_path(*state, "/memory@80000000", &addrcp1, &sizecp1);
+	uint64_t node_offset2 = fdt_find_node_by_path(*state, "/reserved-memory/ramoops@bfdf0000", &addrcp2, &sizecp2);
+
+	struct device_tree_region regions[3];
+	regions[0].addr = 0xDEADBEEF;
+	regions[0].size = 0xDEADBEEF;
+	fdt_read_reg_prop(*state, node_offset1, addrcp1, sizecp1, regions, 0);
+	assert_int_equal(0xDEADBEEF, regions[0].addr);
+	assert_int_equal(0xDEADBEEF, regions[0].size);
+	fdt_read_reg_prop(*state, node_offset2, addrcp2, sizecp2, regions, 1);
+	assert_int_equal(0xbfdf0000, regions[0].addr);
+	assert_int_equal(0x00010000, regions[0].size);
+}
+
+int main(void)
+{
+	const struct CMUnitTest tests[] = {
+		cmocka_unit_test(test_fdt_find_node_by_path),
+		cmocka_unit_test(test_fdt_find_subnodes_by_prefix),
+		cmocka_unit_test(test_fdt_find_node_by_alias),
+		cmocka_unit_test(test_fdt_find_prop_in_node),
+		cmocka_unit_test(test_fdt_read_reg_prop),
+	};
+
+	return cb_run_group_tests(tests, setup_device_tree_test_group,
+			teardown_device_tree_test_group);
+}

tests/lib/lzma-test.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <fcntl.h>
+#include <helpers/file.h>
 #include <lib.h>
 #include <lib/lzmadecode.h>
 #include <stdlib.h>
@@ -10,7 +11,6 @@
 #include <tests/test.h>
 #include <unistd.h>
 
-
 struct lzma_test_state {
 	char *raw_filename;
 	size_t raw_file_sz;
@@ -18,14 +18,6 @@ struct lzma_test_state {
 	size_t comp_file_sz;
 };
 
-static int get_file_size(const char *fname)
-{
-	struct stat st;
-	if (stat(fname, &st) == -1)
-		return -1;
-	return st.st_size;
-}
-
 static int teardown_ulzman_file(void **state)
 {
 	struct lzma_test_state *s = *state;
@@ -42,7 +34,7 @@ static int setup_ulzman_file(void **state)
 {
 	int ret = 0;
 	const char *fname_base = *state;
-	const char path_prefix[] = __TEST_DATA_DIR__ "/lib/lzma-test/%s%s";
+	const char path_prefix[] = "lib/lzma-test/%s%s";
 	const char raw_file_suffix[] = ".bin";
 	const char comp_file_suffix[] = ".lzma.bin";
 	struct lzma_test_state *s = test_malloc(sizeof(*s));
@@ -69,8 +61,8 @@ static int setup_ulzman_file(void **state)
 	snprintf(s->comp_filename, comp_filename_size, path_prefix, fname_base,
 		 comp_file_suffix);
 
-	s->raw_file_sz = get_file_size(s->raw_filename);
-	s->comp_file_sz = get_file_size(s->comp_filename);
+	s->raw_file_sz = test_get_file_size(s->raw_filename);
+	s->comp_file_sz = test_get_file_size(s->comp_filename);
 
 	if (s->raw_file_sz == -1) {
 		print_error("Unable to open file: %s\n", s->raw_filename);
@@ -91,20 +83,6 @@ error:
 	return ret;
 }
 
-static int read_file(const char *fname, uint8_t *buf, size_t sz)
-{
-	int f = open(fname, O_RDONLY);
-	int read_sz = 0;
-
-	if (f == -1)
-		return -1;
-
-	read_sz = read(f, buf, sz);
-
-	close(f);
-	return read_sz;
-}
-
 static void test_ulzman_correct_file(void **state)
 {
 	struct lzma_test_state *s = *state;
@@ -115,9 +93,10 @@ static void test_ulzman_correct_file(void **state)
 	assert_non_null(raw_buf);
 	assert_non_null(decomp_buf);
 	assert_non_null(comp_buf);
-	assert_int_equal(s->raw_file_sz, read_file(s->raw_filename, raw_buf, s->raw_file_sz));
+	assert_int_equal(s->raw_file_sz,
+			 test_read_file(s->raw_filename, raw_buf, s->raw_file_sz));
 	assert_int_equal(s->comp_file_sz,
-			 read_file(s->comp_filename, comp_buf, s->comp_file_sz));
+			 test_read_file(s->comp_filename, comp_buf, s->comp_file_sz));
 
 	assert_int_equal(s->raw_file_sz,
 			 ulzman(comp_buf, s->comp_file_sz, decomp_buf, s->raw_file_sz));

util/crossgcc/buildgcc

@@ -38,13 +38,13 @@ COREBOOT_MIRROR_URL="https://www.coreboot.org/releases/crossgcc-sources"
 GMP_VERSION=6.3.0
 MPFR_VERSION=4.2.1
 MPC_VERSION=1.3.1
-GCC_VERSION=13.2.0
+GCC_VERSION=14.1.0
 BINUTILS_VERSION=2.42
-IASL_VERSION="20230628"
+IASL_VERSION=20240321
 # CLANG version number
-CLANG_VERSION=17.0.6
-CMAKE_VERSION=3.28.3
-NASM_VERSION=2.16.01
+CLANG_VERSION=18.1.6
+CMAKE_VERSION=3.29.3
+NASM_VERSION=2.16.03
 
 # Filename for each package
 GMP_ARCHIVE="gmp-${GMP_VERSION}.tar.xz"
@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
 MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
 GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
 BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://downloadmirror.intel.com/783534"
+IASL_BASE_URL="https://downloadmirror.intel.com/819451"
 # CLANG toolchain archive locations
 LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
 CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"

util/crossgcc/patches/gcc-14.1.0_musl_poisoned_calloc.patch

@@ -23,26 +23,19 @@ included first.
  
  /* glibc versions earlier than 2.7 do not define the routines to handle
     dynamically allocated CPU sets. For these targets, we use the static
---- gcc-13.2.0/gcc/ada/argv.c
-+++ gcc-13.2.0.musl/gcc/ada/argv.c
-@@ -42,6 +42,8 @@
-    main program, and these routines are accessed from the
-    Ada.Command_Line.Environment package.  */
- 
-+#include "adaint.h"
-+
- #ifdef IN_RTS
- #include "runtime.h"
- #include <stdlib.h>
-@@ -50,8 +52,6 @@
- #include "config.h"
+--- gcc-14-20240211/gcc/ada/argv.c
++++ gcc-14-20240211.musl/gcc/ada/argv.c
+@@ -51,10 +51,6 @@
  #include "system.h"
  #endif
--
--#include "adaint.h"
  
+-#ifndef LIGHT_RUNTIME
+-#include "adaint.h"
+-#endif
+-
  #ifdef __cplusplus
  extern "C" {
+ #endif
 --- gcc-13.2.0/gcc/ada/cio.c
 +++ gcc-13.2.0.musl/gcc/ada/cio.c
 @@ -29,6 +29,8 @@

util/crossgcc/patches/nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch

@@ -1,231 +0,0 @@
-From 7e80d6b834cd792dbbd7a99fbff98e46cdd5789f Mon Sep 17 00:00:00 2001
-From: "H. Peter Anvin" <hpa@zytor.com>
-Date: Tue, 17 Jan 2023 13:05:55 -0800
-Subject: [PATCH] Make: handle warning files while building in a directory
-
-The dependency on the warning files breaks when we are building in a
-directory *and* the files already exist from being shipped with the
-distribution tarballs. The make VPATH simply isn't sophisticated
-enough to deal with it, so let the C compiler handle it by #including
-the generated file from a dummy C file.
-
-Reported-by: Rudi Heitbaum <rudi@heitbaum.com>
-Signed-off-by: H. Peter Anvin <hpa@zytor.com>
----
- Makefile.in          | 38 ++++++++++++++++++++------------------
- Mkfiles/msvc.mak     | 14 +++++++-------
- Mkfiles/openwcom.mak | 14 +++++++-------
- doc/Makefile.in      |  2 +-
- 6 files changed, 37 insertions(+), 34 deletions(-)
-
-diff --git a/Makefile.in b/Makefile.in
-index 148fcb50..95268fd2 100644
---- a/Makefile.in
-+++ b/Makefile.in
-@@ -37,8 +37,10 @@ AR		= @AR@
- RANLIB		= @RANLIB@
- STRIP		= @STRIP@
- 
-+tools		= $(top_srcdir)/tools
-+
- PERL		= perl
--PERLFLAGS	= -I$(srcdir)/perllib -I$(srcdir)
-+PERLFLAGS	= -I$(top_srcdir)/perllib -I$(srcdir)
- RUNPERL         = $(PERL) $(PERLFLAGS)
- 
- PYTHON3		= python3
-@@ -65,8 +67,8 @@ LN_S		= @LN_S@
- FIND		= find
- 
- # Binary suffixes
--O              	= @OBJEXT@
--X              	= @EXEEXT@
-+O		= @OBJEXT@
-+X		= @EXEEXT@
- A		= @LIBEXT@
- 
- # Debug stuff
-@@ -194,14 +196,14 @@ PERLREQ = config/unconfig.h \
- 	  x86/iflag.c x86/iflaggen.h \
- 	  macros/macros.c \
- 	  asm/pptok.ph asm/directbl.c asm/directiv.h \
--	  asm/warnings.c include/warnings.h doc/warnings.src \
-+	  $(WARNFILES) \
- 	  misc/nasmtok.el \
- 	  version.h version.mac version.mak nsis/version.nsh
- 
- INSDEP = x86/insns.dat x86/insns.pl x86/insns-iflags.ph x86/iflags.ph
- 
- config/unconfig.h: config/config.h.in
--	$(RUNPERL) $(srcdir)/tools/unconfig.pl \
-+	$(RUNPERL) $(tools)/unconfig.pl \
- 		'$(srcdir)' config/config.h.in config/unconfig.h
- 
- x86/iflag.c: $(INSDEP)
-@@ -273,7 +275,7 @@ x86/regs.h: x86/regs.dat x86/regs.pl
- # reasonable, but doesn't update the time stamp if the files aren't
- # changed, to avoid rebuilding everything every time. Track the actual
- # dependency by the empty file asm/warnings.time.
--WARNFILES = asm/warnings.c include/warnings.h doc/warnings.src
-+WARNFILES = asm/warnings_c.h include/warnings.h doc/warnings.src
- 
- warnings:
- 	$(RM_F) $(WARNFILES) $(WARNFILES:=.time)
-@@ -283,11 +285,11 @@ asm/warnings.time: $(ALLOBJ_NW:.$(O)=.c)
- 	: > asm/warnings.time
- 	$(MAKE) $(WARNFILES:=.time)
- 
--asm/warnings.c.time: asm/warnings.pl asm/warnings.time
--	$(RUNPERL) $(srcdir)/asm/warnings.pl c asm/warnings.c $(srcdir)
--	: > asm/warnings.c.time
-+asm/warnings_c.h.time: asm/warnings.pl asm/warnings.time
-+	$(RUNPERL) $(srcdir)/asm/warnings.pl c asm/warnings_c.h $(srcdir)
-+	: > asm/warnings_c.h.time
- 
--asm/warnings.c: asm/warnings.c.time
-+asm/warnings_c.h: asm/warnings_c.h.time
- 	@: Side effect
- 
- include/warnings.h.time: asm/warnings.pl asm/warnings.time
-@@ -506,8 +508,8 @@ EXTERNAL_DEPENDENCIES = 1
- # the dependency information will remain external, so it doesn't
- # pollute the git logs.
- #
--Makefile.dep: $(PERLREQ) tools/mkdep.pl config.status
--	$(RUNPERL) tools/mkdep.pl -M Makefile.in -- $(DEPDIRS)
-+Makefile.dep: $(PERLREQ) $(tools)/mkdep.pl config.status
-+	$(RUNPERL) $(tools)/mkdep.pl -M Makefile.in -- $(DEPDIRS)
- 
- dep: Makefile.dep
- 
-@@ -517,9 +519,9 @@ dep: Makefile.dep
- # be invoked manually or via "make dist".  It should be run before
- # creating release archives.
- #
--alldeps: $(PERLREQ) tools/syncfiles.pl tools/mkdep.pl
--	$(RUNPERL) tools/syncfiles.pl Makefile.in Mkfiles/*.mak
--	$(RUNPERL) tools/mkdep.pl -i -M Makefile.in Mkfiles/*.mak -- \
-+alldeps: $(PERLREQ) $(tools)/syncfiles.pl $(tools)/mkdep.pl
-+	$(RUNPERL) $(tools)/syncfiles.pl Makefile.in Mkfiles/*.mak
-+	$(RUNPERL) $(tools)/mkdep.pl -i -M Makefile.in Mkfiles/*.mak -- \
- 		$(DEPDIRS)
- 	$(RM_F) *.dep
- 	if [ -f config.status ]; then \
-@@ -528,9 +530,9 @@ alldeps: $(PERLREQ) tools/syncfiles.pl tools/mkdep.pl
- 
- # Strip internal dependency information from all Makefiles; this makes
- # the output good for git checkin
--cleandeps: $(PERLREQ) tools/syncfiles.pl tools/mkdep.pl
--	$(RUNPERL) tools/syncfiles.pl Makefile.in Mkfiles/*.mak
--	$(RUNPERL) tools/mkdep.pl -e -M Makefile.in Mkfiles/*.mak -- \
-+cleandeps: $(PERLREQ) $(tools)/syncfiles.pl $(tools)/mkdep.pl
-+	$(RUNPERL) $(tools)/syncfiles.pl Makefile.in Mkfiles/*.mak
-+	$(RUNPERL) $(tools)/mkdep.pl -e -M Makefile.in Mkfiles/*.mak -- \
- 		$(DEPDIRS)
- 	$(RM_F) *.dep
- 	if [ -f config.status ]; then \
-diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak
-index cf71fffc..da71c5c6 100644
---- a/Mkfiles/msvc.mak
-+++ b/Mkfiles/msvc.mak
-@@ -153,14 +153,14 @@ PERLREQ = config\unconfig.h \
- 	  x86\iflag.c x86\iflaggen.h \
- 	  macros\macros.c \
- 	  asm\pptok.ph asm\directbl.c asm\directiv.h \
--	  asm\warnings.c include\warnings.h doc\warnings.src \
-+	  $(WARNFILES) \
- 	  misc\nasmtok.el \
- 	  version.h version.mac version.mak nsis\version.nsh
- 
- INSDEP = x86\insns.dat x86\insns.pl x86\insns-iflags.ph x86\iflags.ph
- 
- config\unconfig.h: config\config.h.in
--	$(RUNPERL) $(srcdir)\tools\unconfig.pl \
-+	$(RUNPERL) $(tools)\unconfig.pl \
- 		'$(srcdir)' config\config.h.in config\unconfig.h
- 
- x86\iflag.c: $(INSDEP)
-@@ -232,7 +232,7 @@ x86\regs.h: x86\regs.dat x86\regs.pl
- # reasonable, but doesn't update the time stamp if the files aren't
- # changed, to avoid rebuilding everything every time. Track the actual
- # dependency by the empty file asm\warnings.time.
--WARNFILES = asm\warnings.c include\warnings.h doc\warnings.src
-+WARNFILES = asm\warnings_c.h include\warnings.h doc\warnings.src
- 
- warnings:
- 	$(RM_F) $(WARNFILES) $(WARNFILES:=.time)
-@@ -242,11 +242,11 @@ asm\warnings.time: $(ALLOBJ_NW:.$(O)=.c)
- 	: > asm\warnings.time
- 	$(MAKE) $(WARNFILES:=.time)
- 
--asm\warnings.c.time: asm\warnings.pl asm\warnings.time
--	$(RUNPERL) $(srcdir)\asm\warnings.pl c asm\warnings.c $(srcdir)
--	: > asm\warnings.c.time
-+asm\warnings_c.h.time: asm\warnings.pl asm\warnings.time
-+	$(RUNPERL) $(srcdir)\asm\warnings.pl c asm\warnings_c.h $(srcdir)
-+	: > asm\warnings_c.h.time
- 
--asm\warnings.c: asm\warnings.c.time
-+asm\warnings_c.h: asm\warnings_c.h.time
- 	@: Side effect
- 
- include\warnings.h.time: asm\warnings.pl asm\warnings.time
-diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak
-index 5394d85d..605f9afe 100644
---- a/Mkfiles/openwcom.mak
-+++ b/Mkfiles/openwcom.mak
-@@ -166,14 +166,14 @@ PERLREQ = config\unconfig.h &
- 	  x86\iflag.c x86\iflaggen.h &
- 	  macros\macros.c &
- 	  asm\pptok.ph asm\directbl.c asm\directiv.h &
--	  asm\warnings.c include\warnings.h doc\warnings.src &
-+	  $(WARNFILES) &
- 	  misc\nasmtok.el &
- 	  version.h version.mac version.mak nsis\version.nsh
- 
- INSDEP = x86\insns.dat x86\insns.pl x86\insns-iflags.ph x86\iflags.ph
- 
- config\unconfig.h: config\config.h.in
--	$(RUNPERL) $(srcdir)\tools\unconfig.pl &
-+	$(RUNPERL) $(tools)\unconfig.pl &
- 		'$(srcdir)' config\config.h.in config\unconfig.h
- 
- x86\iflag.c: $(INSDEP)
-@@ -245,7 +245,7 @@ x86\regs.h: x86\regs.dat x86\regs.pl
- # reasonable, but doesn't update the time stamp if the files aren't
- # changed, to avoid rebuilding everything every time. Track the actual
- # dependency by the empty file asm\warnings.time.
--WARNFILES = asm\warnings.c include\warnings.h doc\warnings.src
-+WARNFILES = asm\warnings_c.h include\warnings.h doc\warnings.src
- 
- warnings:
- 	$(RM_F) $(WARNFILES) $(WARNFILES:=.time)
-@@ -255,11 +255,11 @@ asm\warnings.time: $(ALLOBJ_NW:.$(O)=.c)
- 	: > asm\warnings.time
- 	$(MAKE) $(WARNFILES:=.time)
- 
--asm\warnings.c.time: asm\warnings.pl asm\warnings.time
--	$(RUNPERL) $(srcdir)\asm\warnings.pl c asm\warnings.c $(srcdir)
--	: > asm\warnings.c.time
-+asm\warnings_c.h.time: asm\warnings.pl asm\warnings.time
-+	$(RUNPERL) $(srcdir)\asm\warnings.pl c asm\warnings_c.h $(srcdir)
-+	: > asm\warnings_c.h.time
- 
--asm\warnings.c: asm\warnings.c.time
-+asm\warnings_c.h: asm\warnings_c.h.time
- 	@: Side effect
- 
- include\warnings.h.time: asm\warnings.pl asm\warnings.time
-diff --git a/doc/Makefile.in b/doc/Makefile.in
-index e92437a0..1c8393c5 100644
---- a/doc/Makefile.in
-+++ b/doc/Makefile.in
-@@ -20,7 +20,7 @@ INSTALL		= @INSTALL@
- INSTALL_PROGRAM	= @INSTALL_PROGRAM@
- INSTALL_DATA	= @INSTALL_DATA@
- 
--PERL		= perl -I$(srcdir)
-+PERL		= perl -I$(top_srcdir)/perllib -I$(srcdir)
- 
- PDFOPT		= @PDFOPT@
- 

util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum

@@ -1 +0,0 @@
-3b893fb771cf3fbd3531de3036e1a5bfc624c9d2  tarballs/acpica-unix-20230628.tar.gz