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80 Commits

Author SHA1 Message Date
Tim Crawford
af37b54564 mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-05-22 13:30:20 -06:00
Kenneth Chan
6a3ff9ce68 mb/google/brya/var/nova: Add SOLDERDOWN support
Nova will use SOLDERDOWN. Add memory.c to override baseboard.
Update dram id table for correct platform parameter.

BUG=b:328711879

Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21 13:46:17 +00:00
Wu Garen
7dcb3d9c72 mb/google/brox/var/greenbayupoc: Update verb table from ALC256 to ALC236
On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256)
Update to Realtek provided verb table for ALC236 audio codec.

BUG=b:336967284
TEST=Verified headset and audio workable on DUT with "rec" and
"aplay" command.

Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21 13:45:49 +00:00
Maximilian Brune
33079b8174 lib/device_tree: Add some FDT helper functions
This adds some helper functions for FDT, since more and more mainboards
seem to need FDT nowadays. For example our QEMU boards need it in order
to know how much RAM is available. Also all RISC-V boards in our tree
need FDT.

This also adds some tests in order to test said functions.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81081
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21 13:44:47 +00:00
Maximilian Brune
25c737d403 tests/lib: Factor out file related functions
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5c22913b35848c5ea32d6805ea081abefd3380bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82237
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-05-21 13:44:39 +00:00
Tony Huang
62a6188da5 soc/intel/meteorlake: Add PsysPL2 configuration
psys_pl2_watts is configured in SoC node of devicetree.
Value represents Watts.

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot

Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-21 13:37:09 +00:00
Shon Wang
0da12e0f2a mb/google/brya/var/bujia: Add devicetree based on schematics
Add devicetree settings per the schematic.
Differences to gladios:
1. remove SD reader
2. remove EMMC setting
3. modify USB port distribution

FRONT
-------------------------------------------------------
|                                        A3   A1      |
|               C0                       A2   A0      |
-------------------------------------------------------

BACK
-------------------------------------------------------
|                    ---------------                  |
|                    |    TX25A    |                  |
-------------------------------------------------------

BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-21 13:36:33 +00:00
Elyes Haouas
b4949d3de5 crossgcc: Update LLVM from 18.1.5 to 18.1.6
Change-Id: Ie087f43e6f60df7b97d7d7b402d3540c3a0a2461
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-20 20:33:20 +00:00
Martin Roth
c3086b12a4 util/docker: Change Debian suite from Sid to stable
Debian sid is too unstable at this point, and frequently ends up having
issues that cause the coreboot-sdk docker image to fail to build. Using
stable also better reflects what users will typically be running.

Also remove the parameters to quiet the apt-get install command so that
if something does break, we can see what happened more easily.

Fixes bug 536

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41b6464b024df89c114db2cdb9367c0526eb0297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82411
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-20 19:30:33 +00:00
Angel Pons
455538d3ae 3rdparty/libgfxinit: Update submodule pointer
Update the submodule pointer to current main. This brings in 5 commits:

* e096913 connector_info: Fix HDMI/DVI default bytes per color setting
* 87469f2 gma config: Add new device IDs for Raptor Lake
* 4be2e75 gma: Update transcoder setup for TGL
* 4b991bf gfxtest: Drop unnecessary with of ancestor
* 17cfc92 tgl plls: Disable warnings about unused variable

Change-Id: Ic40edc773ba11ab9a0f9e92057bd687d10b95069
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82554
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-20 13:24:36 +00:00
Angel Pons
78a26aca8b mb/prodrive/hermes/hda_verb.c: Refactor port B Vref cfg
Refactor the `get_port_b_vref_cfg()` function to only return the
variable bits of the value. The NID itself is not connected, and
the `misc` field in the verb conveys the Vref value.

Change-Id: I5108f5339c5b002403a4e5339da6d52046c8bcbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-20 12:58:07 +00:00
Subrata Banik
f2d260d988 Libpayload: Rename arch variable _ARCH to _ARCHDIR for consistency
This commit renames the variable _ARCH to _ARCHDIR in the libpayload
build script (lpgcc) to align with the naming convention of other
variables used in this file.

This change improves code readability and maintainability.

Change-Id: Iea4af68e49ab1cd7ec8156a14f8215244e9c0622
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82479
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-18 18:27:53 +00:00
Robert Chen
67a96902d5 mb/google/dedede/var/kracko: Disable un-used C1 port by daughterboard
Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.

BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.

Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-17 17:48:59 +00:00
Kenneth Chan
917bdbffd3 mb/google/brask/var/nova: Remove unused retimer
Remove unused setting for retimer.

BUG=b:328711879
Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-17 13:17:37 +00:00
Tyler Wang
557aad1df9 cr50: Replace "cr50" to "GSC" in debug messages
The cr50.c file currently prints "cr50" in debug messages no
matter the system is using Cr50 or Ti50. This can be confusing
for developers.

This patch replaces "cr50" with "GSC" in debug messages. Using
"GSC" makes the messages more clear and easier to search via
`grep`.

BUG=none
TEST=Build and test on karis

Change-Id: I21f66cf8b608ca4e4dc82d7a55a851ec996c8bb3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82420
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2024-05-17 12:50:28 +00:00
Shuo Liu
43a54184b0 mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).

This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).

TEST=Build on intel/beechnutcity CRB

Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 21:05:28 +00:00
Gang Chen
921ddba69e mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).

This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).

TEST=Build on intel/avenuecity CRB

Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 20:55:05 +00:00
Gang Chen
6258093575 soc/intel/xeon_sp/gnr: Add IIO config utils
Add IIO configuration utils shared in GNR boards to handle the
complex IIO configuration settings.

Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 20:52:20 +00:00
Aseda Aboagye
cc82f74605 chromeec/ec_acpi: Convert TK_DICTATE to ps2_action_key
When support for the dictation key was added in commit f2782b8328
(acpigen_ps2_keybd: Add support for dictation key), I had failed to
include this portion of the change in that commit. The top row key of
`TK_DICTATE` needs to be converted to the ps2_action_key.  This commit
simply adds that mapping so that it can be translated.

BUG=b:333101631
TEST=Flash DUT that emits a scancode for a dictation key, verify that it
is mapped to KEY_DICTATE in the Linux kernel using `evtest`.

Change-Id: I1be8c0a96931cca36e6bbbfa0be7d36c4cd93768
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82274
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 17:08:56 +00:00
Felix Held
e189043aec mb/amd/birman/update_devicetree_phoenix_opensil: use common header file
Instead of including stub/mpio/chip.h, include chip/mpio/chip.h that
will include the correct implementation to be able to use the same file
with both the openSIL stub and the actual openSIL implementation glue
code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaae26a0dfe0ba96842e72582c06f1b0b3f29871c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82472
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 15:47:15 +00:00
Subrata Banik
c61b35b696 mb/google/rex: Remove redundant VPU enablement code
This patch removes VPU enablement code that is no longer needed because
the VPU is already enabled by default in the baseboard devicetree.

BUG=b:332488817
TEST=Able to see VPU PCI device in lspci list after booting
google/screebo to OS

Change-Id: I94de92e970be1548068ed4e19309a95129f041ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-16 13:03:31 +00:00
Subrata Banik
a0426b6d93 mb/google/rex: Enable VPU device for Rex/Ovis baseboard
This patch enables the Versatile Processing Unit (VPU) by default for
Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in
the 14th generation "Meteor Lake" Core processors.

The VPU is designed to efficiently run AI models directly on the
system on chip (SoC). There is no power regression observed while
keeping the VPU default enabled to run AI models natively hence, this
patch enables the VPU by default.

BUG=b:332488817
TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting
google/screebo to OS.

Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16 13:03:24 +00:00
Saurabh Mishra
1b2fe88a04 include/device/pci_ids.h: Update TWL device IDs
Set lowercase hex format for IGD DIDs.

BUG=b:326901448
TEST=Build tivviks and verify the IGD IDs.

Change-Id: I1299512d1c48eba854fea2ec394cef40d44a87d7
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82414
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16 11:29:40 +00:00
Tony Huang
3d4128299f mb/google/rex/var/baseboard/ovis: Support CPU power limits per variant
There is no direct way to override CPU default power_limits for
different SKUs.

This CL add structure variant_get_soc_power_limit_config() for
variants to define and configure the values of soc_power_limits_config
for current CPU SKU.

Variants can override these values i.e. pl1, pl2, psyspl2
in variant_devtree_update().

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
     check overrides setting

Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 11:28:58 +00:00
Shon Wang
ff79993e95 mb/google/brask/var/bujia: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 11:28:00 +00:00
Krystian Hebel
a8fdafa427 cpu/x86/pae/pgtbl.c: remove dead paging_identity_map_addr()
This function had roughly the same use (except PAT) as part of
memset_pae(), however the latter is able to make use of PAE and map
physical memory located above 4 GB. Remove paging_identity_map_addr()
to avoid semi-duplicated code.

The function has been unused since CB:26745.

Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15 16:53:50 +00:00
Elyes Haouas
07913736e0 Doc/releases: List toolchain updates in coreboot-24.08-relnotes
Report upgraded version for ACPICA, CMake, nasm, LLVM and GCC.

Change-Id: I93a9ae4a2f4c3403a6e8c9a8b7aca74b996e7db8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82410
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-15 16:51:31 +00:00
Nicholas Sudsgaard
744e389800 payload/external/edk2: Explicitly define the build arch as X64
Upstream commit 11ad164bce (UefiPayloadPkg: Make UPL build script arch
agnostic, 2024-02-22) changes the build script's behavior to not assume
the arch. Without defining BUILD_ARCH, the build script will not
function properly and results in the payload failing to build.

Both UefiPayload and Universal Payload can only be built in X64.

Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-05-15 16:49:26 +00:00
Jason Glenesk
ab42a64d99 Add 24.08 release notes template
In preparation for the upcoming release, add the template for the
24.05 release and update index.md.

Change-Id: I733f541a2d6e556c82aff1656fe7f79ae3673ba7
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82400
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-15 15:16:52 +00:00
Felix Held
b43accd233 mb/amd/birman: add function to update MPIO config in devicetree
Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end
numbers need to be adjusted to take that into account. When the Kconfig
options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses
both PICe lanes that are available for those two devices, so the MPIO
descriptor information the devicetree needs to be updated accordingly
and the bridge to the PCIe port that doesn't have any lane left needs to
be disabled. Two other PCIe devices will be disabled when the
corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have
the value that results in the device being disabled via some GPIO driven
by the EC. Since the code is specific to the openSIL case, only include
it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-15 15:01:55 +00:00
Felix Held
d7158c8149 mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
Add the stub MPIO chips that contain the PCIe engine configuration for
the external PCIe interfaces to the devicetree. Birman's
port_descriptors_phoenix.c was used as a reference. The static
configuration in the devicetree assumes that the default WLAN0_WWAN0 is
selected; for the other cases we'll still need to fix up things
accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still
need to be handled in a follow-up patch. Since openSIL currently doesn't
use the info from the gpio_group struct element, but deasserts both PCIe
reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip
configuration in the devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-15 15:01:05 +00:00
EricKY Cheng
7728ed3ea2 mb/google/brya: Create orisa variant
Create the orisa variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:337178014
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ORISA

Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-15 12:08:23 +00:00
Felix Singer
acdd8dd14d util/crossgcc: Update GCC from 13.2 to 14.1.0
Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81683
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-05-15 01:53:34 +00:00
Lennart Eichhorn
e885aa5a05 util/crossgcc: Update LLVM from 17.0.6 to 18.1.5
Change-Id: I03a44e0c23a925396f614f282882405dc886ba58
Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-05-15 01:53:22 +00:00
Elyes Haouas
0090039bbd crossgcc: upgrade nasm from 2.16.01 to 2.16.03
Remove the patch since it was picked from master before and thus it's
included in the new release.

Change-Id: I70408b189b974f8abaadc66f0c809a1dbe10504b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81900
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15 01:53:10 +00:00
Felix Singer
41fdb882f1 util/crossgcc: Update ACPICA from 20230628 to 20240321
Change-Id: I41f56ba58af51b1ec1d7554fb35a49ccf9e778f6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-14 23:35:39 +00:00
Felix Singer
6b4036ee9e util/crossgcc: Update CMake from 3.28.3 to 3.29.3
Change-Id: Iaf2d4f579d987fbfd4187ae41c1be5cec55e0e8e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14 23:34:36 +00:00
Martin Roth
5a0207e56a Documentation: Finalize 24.05 release notes
These are the final release notes for the 24.05 release before the tree
is marked with a tag, completing the release. We will update the notes
with final numbers and anything else after the release is tagged.

The 24.05 release will be announced a week later, barring any issues
that require an updated release tag.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I00be0127351f8641116b4bc523c266628b084e69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82407
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14 22:13:50 +00:00
Shuo Liu
a5487ba17a soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.

This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).

1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.

2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.

Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14 20:49:04 +00:00
Jason Glenesk
ed366c07bb Documentation/vboot: Update vboot supported boards list
Auto-generated by util/vboot_list/vboot_list.sh.

Change-Id: I5e1a7046b03687d15e8ceae2074ec25aa72a6f28
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82399
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14 20:33:35 +00:00
Ashish Kumar Mishra
5a86707417 soc/intel/common: Add RPL tracehub support
Add PCI ID for RPL tracehub and update the PCI ID in the
pci_device_ids[] in tracehub.c.

Reference:
Raptor Lake External Design Specification Volume 1 (640555)

BUG=None
TEST=Verified on brox

Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14 19:48:55 +00:00
Angel Pons
f1e4067a90 util/autoport: Remove incorrect comment
Yes, the DSDT revision is the OEM revision. But most certainly not that
of the board being ported. Because no one seems to care about the value
(newer boards inexplicably use lower values even though this represents
a date in 0xYYYYMMDD format), simply drop the incorrect comment. Should
save a bit of effort when reviewing mainboard ports: no longer will one
have to ask authors to drop the comment.

Change-Id: I9c425573e4fcb0f670a780e7821e815eadc8a2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-14 19:48:31 +00:00
Angel Pons
ff0f6dcba3 util/autoport/.gitignore: Ignore logs folder
The README suggests using `logs` as the folder name where autoport puts
the generated logs. Thus, add this folder to .gitignore for the sake of
convenience. Yes, people can use other folder names, but `logs` is most
commonly used.

Change-Id: I37906b43ba3e132de616184e4a5082ce00f4b230
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82398
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-14 19:48:17 +00:00
Saurabh Mishra
2e532b19d5 soc/intel/common: Add Panther Lake DIDs
Reference:
Panther Lake External Design Specification Volume 0.51 (815002)

BUG=b:329787286
TEST=verified on Panther Lake Simics Platform.

Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:12:00 +00:00
Saurabh Mishra
1057865a89 soc/intel: Add Panther Lake PCIE device IDs
Add Panther Lake specific CPU and PCIE device IDs

Reference:
Panther Lake External Design Specification Volume 0.51 (815002)

BUG=b:329787286
TEST=verified on Panther Lake Simics Platform.

Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:11:04 +00:00
Saurabh Mishra
47e7240ffc soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDs
Reference:
Lunar Lake External Design Specification Volume 1 (734362)

BUG=b:329787286
TEST=verified on Lunar Lake RVP board (lnlrvp).

Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:10:34 +00:00
Frank Chu
e3b1a9d7a1 mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 A
Iccmax of VccIn_Aux is 25A with MBVR design.

BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:10:10 +00:00
Robert Chen
e7e717b3a6 mb/google/nissa/var/quandiso: Add stop pin for G2 touchscreen
Add stop pin control for G2 touchscreen refer to
G7500_Datasheet_Ver.1.2.

BUG=b:335803573
TEST=build and verified touchscreen works normally

Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:09:43 +00:00
Eren Peng
d2f810ed9f mb/google/brox/var/greenbayupoc: Add vbt from brox
Copy the data.vbt from brox to greenbayupoc

BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT

Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:09:29 +00:00
Eren Peng
bb616ca483 mb/google/brox/var/greenbayupoc: Update devicetree and gpio settings
Based on latest schematics GREENBAY_0412.SCH update the gpio and
devicetree settings.

BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT

Cq-Depend:chrome-internal:7218819
Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-14 13:08:30 +00:00
Subrata Banik
d05611d264 arch/x86: Remove unused protected_mode_jump API
This patch removes all instances of the `protected_mode_jump` API and
its associated header file.

The API is no longer used by any code within the tree.

BUG=b:332759882
TEST=Built and booted 64-bit coreboot with 32-bit payload successfully.

Change-Id: I3eb31b09c92512338ccc540f60289960bd6bf439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82372
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:08:04 +00:00
Subrata Banik
06b25c26a1 x86: Switch to protected_mode_call_1arg for correct argument passing
The payload execution process has been updated to utilize
protected_mode_call_1arg in order to guarantee proper handling of
function parameters.

The previous use of protected_mode_jump with a "jmp" instruction did
not allow for proper stack setup for argument passing, as the calling
convention was not aligned with the System V ABI calling convention.

This patch ensures that calling into the libpayload entry point using
protected mode is now aligned with the System V ABI calling convention.

This resolves an issue where retrieving the "pointer to coreboot tables"
from within the libpayload entry point was failing due to incorrect
argument passing.

BUG=b:332759882
TEST=Built and booted 64-bit coreboot with 32-bit payload successfully.

Change-Id: Ibd522544ad1e9deed6a11015b0c0e95265bda8eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82294
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-05-14 13:07:28 +00:00
Leo Chou
94d50bbe2a mb/google/nissa/var/sundance: Update HID offset to 0x01 for Focal touchpad
Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01.

BUG=b:339756281
TEST=Build and check Focal touchpad can work.

Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14 13:06:12 +00:00
Daniel_Peng
958d29fd83 mb/google/dedede/var/pirika: Add SPD IDs for two new memory parts
Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix
H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these
parts.

DRAM Part Name                 ID to assign
MT53E512M32D1NP-046 WT:B       0 (0000)
H54G46CYRBX267                 0 (0000)

BUG=b:337173071
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
     ./util/spd_tools/src/part_id_gen/part_id_gen.go \
     JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
     src/mainboard/google/dedede/variants/pirika/memory/\
     mem_parts_used.txt"

Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14 13:05:49 +00:00
Lennart Eichhorn
fbc4f699bc doc/release/24.05: Add git submodule updates
Change-Id: I136905d60de14749cfa325b24de3df204f0135ec
Signed-off-by: Lennart Eichhorn <lennart@zebre.us>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82116
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 20:18:52 +00:00
Keith Hui
8869414105 mb/asus/p8z77-m: Support AC97 front audio panel
Add a nvram option for front audio panel type.

If it is set to AC97, reprogram front line out and microphone
pins to match vendor firmware under same configuration.

TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97
front audio panel, front panel line out port is now available as
headphone port in Fedora 39 with this patch applied and option
set correctly. And it works. Without the patch (or with this option
set to HD Audio), front audio ports are completely inoperable.

Change-Id: I39ccf066d87c5744a697599861719182768e0728
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-13 17:18:22 +00:00
Elyes Haouas
ca3764ab18 nb/intel/haswell: Use <device/dram/ddr3.h>
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 17:12:45 +00:00
Elyes Haouas
200075ba2d mb/google/rambi: Use <device/dram/ddr3.h>
Change-Id: I3aa669042908b92d7b270df077a352e197071780
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 17:12:30 +00:00
Elyes Haouas
c2837e70b9 soc/intel/xeon_sp: Use <spd.h>
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-13 17:12:19 +00:00
Elyes Haouas
27becf5da6 mb/intel/{harcuvar,kunimitsu}: Use <spd.h> and <dram/ddr{3,4}.h>
Change-Id: I2d73f7815e83e8bf0c6d0a402d32bc99c32c7d90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82243
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 17:11:35 +00:00
Elyes Haouas
7809eb8db6 mb/google/{eve,glados}: Use <spd.h> and <dram/ddr3.h>
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-13 17:10:25 +00:00
Fabian Meyer
a8a4a39adc util/inteltool: Fix Emmitsburg GPIO Group J pad names
Pad names now matching soc/intel/xeon_sp/ebg/soc_gpio.c.

Test: Generated pad names for ASRock Rack SPC741D8 now compile.

Change-Id: Ied53b654f905add86a05bce8c2e366dea9ccf4d3
Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 15:09:45 +00:00
Elyes Haouas
6fe35343b1 soc/amd/common/block/psp: Comment unused symbol
This adds a comment for unused AMD_FWM_POSITION_20000_DEFAULT.

Change-Id: Id8369f488893e7e5b2e7e7126d1b53199ed1aa77
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-13 14:30:54 +00:00
David Wu
de7492e942 mb/google/brya/var/riven: Copy VBT data file from nivviks
Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT
for riven as it has a VBT file now.
The VBT file is copied from the nivviks reference board.

BUG=b:337169542
TEST=build pass

Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 12:32:17 +00:00
Krystian Hebel
33192a3752 cpu/x86/pae/pgtbl.c: remove dead map_2M_page()
This function isn't used anywhere. It probably wouldn't work with
current coreboot anyway, as it identity mapped lower 2GB of RAM, while
ramstage is run from CBMEM, which is usually just below top of memory.

It was last used in K8 code that is long gone.

Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-05-13 12:31:32 +00:00
Ashish Kumar Mishra
7e7e569db4 mb/google/brox: Disable c1 state auto-demotion
Disable c1 state auto-demotion support for brox

BUG=None
BRANCH=None
TEST=Boot brox and verify in fsp debug logs

Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 12:30:40 +00:00
Saurabh Mishra
254a4b9072 soc/intel/lunarlake: Support stepping A0_2
Details:
- Add support for new Lunar Lake MCH ID 0x6410
- Add new CPU id 0xb06d1

Reference:
Lunar Lake External Design Specification Volume 1 (734362)

TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage.
	Below prints verified on Lunar Lake RVP board (lnlrvp).
	[DEBUG]  MCH: device id 6410 (rev 02) is LunarLake M

Change-Id: I976d7f269485633d835d204afa224736d71baaa8
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12 18:57:39 +00:00
Saurabh Mishra
7f2020b712 soc/intel/common: Add Lunar Lake CNVI device IDs
Without this patch, ACPI SSDT does not supports and lists CNVW.

With this patch, verified "CNVW" in ACPI SSDT listing.

Scope (\_SB.PCI0)
    {
        Device (CNVW)
        {
            Name (_ADR, 0x0000000000140003)  // _ADR: Address
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }
        }
    }

Reference:
Lunar Lake External Design Specification Volume 1 (734362)

BUG=b:329787286
TEST=verified on Lunar Lake RVP board (lnlrvp).

Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12 18:57:05 +00:00
Tony Huang
83fd2d8a28 mb/google/rex/var/deku: Correct FVM Itrip for GT VR domain
Previous CL misspelling VR domain to IA not GT which cause
FVM Itrip(GT) not set correctly.

This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT)
has set to 54.

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
      check overrides setting
      IccLimit[1] = 216 ( 1/4 A)

Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12 18:55:47 +00:00
Felix Held
0fc69141e5 vc/amd/opensil: introduce common mpio/chip.h header file
The chip drivers in the devicetree use the path where the corresponding
chip.h file resides both to include this chip.h file in the static.c
generated by util/sconfig from the devicetree and also for the names of
the chip config and chip ops struct. To be able to build a SoC using
either the MPIO chip driver from the openSIL stub or from the actual
openSIL glue code without needing different devicetree files for the
different cases, introduce a common MPIO chip.h file that then includes
the correct MPIO header file. The chip config and ops structures also
need to be renamed to take this change into account.

Thanks to Matt for pointing out how to make the path to the actual MPIO
chip.h file configurable via a Kconfig setting. This allows overriding
this path from site-local without the need to have any reference to
site-local in the upstream code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12 18:54:50 +00:00
Felix Held
444edcba5d vc/amd/opensil/*/mpio/chip.h: add missing include guards
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idef3b661b1cf3008373e61e0760a7dd3b9e9fede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82261
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12 18:53:48 +00:00
Filip Lewiński
7898594b7c util/intelp2m: add Meteor Lake support
Enables parsing Meteor Lake inteltool output into gpio.h pad macros.

Change-Id: Iaebd51d587507e68c6f263b92dc61cb6c0411bf8
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81916
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-05-12 18:53:31 +00:00
Michał Kopeć
c42e28f077 mb/protectli/vault_cml: use combo v1/v2 FSP
Also switch configs to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.

Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81963
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-12 18:52:41 +00:00
Eren Peng
1a395728df mb/google/brox/var/greenbayupoc: Configure board for SODIMM use
Configure SODIMM settings for greenbayupoc. The SODIMM settings are
copied from mainboard/google/brya/variants/baseboard/brask/memory.c.

BUG=b:336955026, b:332230842
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS
using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM.

Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-12 18:51:46 +00:00
David Wu
a56baa1d50 mb/google/brya/var/riven: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

1. MT62F1G32D4DR-031 WT:B (Mircon)
2. MT62F512M32D2DR-031 WT:B (Mircon)
3. H9JCNNNBK3MLYR-N6E (Hynix)
4. K3LKLKL0EM-MGCN (Samsung)
5. K3LKBKB0BM-MGCP (Samsung)
6. H9JCNNNCP3MLYR-N6E (Hynix)

BUG=b:337169542
TEST=build pass

Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-12 18:50:39 +00:00
Filip Lewiński
eacc1c7ea9 util/inteltool: add Meteor Lake support
Based on:
Intel Core Ultra Processor External Design Specification
Meteor Lake SOC IO Registers
Meteor Lake-U/H/U Type4 and Arrow Lake-U/H GPIO Implementation Summary

Change-Id: I7473119fa97c57cd2a1303f08f964abd0ca96270
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-05-12 18:50:10 +00:00
Frans Hendriks
6d5cc39a78 LinuxBoot/Makefile: initramfs not build for bzImage
initramfs is not build when bzImage is selected

Add build/initramfs dependency to build/bzImage

BUG = N/A
TEST = Built and boot facebook monolith

Change-Id: I002202a0340347e78ce22024761d997605bd3f72
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77606
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11 18:28:30 +00:00
Subrata Banik
cf5fc2312a include/efi: Override EFIAPI macro for x86_64
This commit overrides the EFIAPI macro definition when using FSP on
x86_64 to ensure the correct calling convention is used.

On i386, there is no side-effect since the C calling convention used
by coreboot and FSP are the same. However, on x86_64, FSP/UEFI uses
the Microsoft x64 calling convention while coreboot uses the System
V AMD64 ABI.

This change resolves this incompatibility by setting EFIAPI to
attribute((ms_abi)) on x86_64 when using FSP.

TEST=Able to build google/rex0 in 32-bit and 64-bit mode.

Change-Id: Ifae910be66d550af04cce5136d186a7e9dd085b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82266
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11 08:28:17 +00:00
Subrata Banik
f5be5e4999 driver/intel/fsp2_0: Update soc_binding.h for coreboot compatibility
Included <efi/efi_datatype.h> to address coreboot style header
definitions rather using EDK2 header <Base.h>.

TEST=Able to build google/rex0.

Change-Id: I66559872c8d137d1baef5860fb98cad2a5214368
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82265
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11 08:28:11 +00:00
Zhongtian Wu
3a3804f458 drivers/mipi: Update init code for IVO_T109NW41 panel
1. VCOM OTP burning, initial code Settings can be deleted, B6h
2. Fine-tune VGH, VGL, VGHO, VGLO voltage, B1h PA6
3. Boot CLK performance change: add E9h, C7h, E9h
4. Extend TFT life: D5h PA25~PA32,D3h PA1~PA5;
5. Gamma optimization: E0h
6. Improve picture quality, add EQ: D2h to CLK
7. Press mura to improve and modify B1h PA4 and PA5

BUG=b:320892589
TEST=boot ciri with IVO_T109NW41 panel and see firmware screen

Change-Id: I13421660faba9ef8e33a51c5ab28aeb1388aff40
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82240
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-05-10 09:25:59 +00:00
259 changed files with 8039 additions and 1061 deletions

View File

@@ -1,37 +1,76 @@
Upcoming release - coreboot 24.05
coreboot 24.05 release
========================================================================
The 24.05 release is scheduled for Mid May, 2024
The coreboot project is pleased to announce the release of coreboot version
24.05. This update represents three months of hard work and commitment from our
community. With over 20 new members and contributions from more than a hundred
fifty other people in coding, reviewing patches, and other areas, this release
showcases the strength of our collaborative efforts.
With this release, coreboot has expanded its support, adding 25 new platforms or
variants and 2 new processors, further demonstrating our dedication to offering
flexible and adaptable firmware solutions. From laptops and servers to embedded
devices, coreboot 24.05 is designed to enhance a variety of hardware platforms
with its strong features.
Update this document with changes that should be in the release notes.
We are grateful to all the contributors who have made this release possible.
Your expertise and collaborative efforts continue to propel the coreboot project
forward. We value the participation of everyone in the community, from long-time
developers to those new to the project, and encourage you to explore the new
opportunities that coreboot 24.05 offers.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
Our next release will be 24.08, scheduled for mid-August.
Significant or interesting changes
----------------------------------
* Add changes that need a full description here
### Mark 64-bit support as stable
* This section should have full descriptions and can or should have
a link to the referenced commits.
A significant amount of work has gone into fully supporting 64-bit coreboot
builds. There are still additional pieces that are happening, but with SMM
holding page tables itself, we can consider SMM support stable and safe enough
for general use.
### security/tpm: support compiling in multiple TPM drivers
Previously, boards could only be built with code supporting TPM 1.x or TPM 2.x
specifications. This has been updated with code allowing both to be built in
simultaneously, allowing the system to query the TPM. For systems with
soldered-down TPMs or firmware TPM solutions, its still possible to specify a
single TPM version so that the code for the other version isnt included.
### arch/arm64: Add EL1/EL2/EL3 support for arm64
Previously, arch/arm64 required coreboot to run on EL3 due to EL3 register
access. This might be an issue when, for example, one boots into TF-A first and
drops into EL2 for coreboot afterwards.
This patch aims at making arch/arm64 more versatile by removing the current EL3
constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3.
The strategy is to add a Kconfig option (ARM64_CURRENT_EL) which allows us to
specify coreboot's EL upon entry. Based on that, we access the appropriate ELx
registers. So, for example, when running coreboot on EL1, we would not access
vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults
when accessing higher-EL registers.
Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
* util/smmstoretool: support processing ROMs
* cpu/x86: Link page tables in stage if possible
* lib/lzmadecode: Allow for 8 byte reads on 64bit to speed up decompression
* mb/lenovo/*: Set VR12 PSI to fix crash
* Numerous fixes for clang support
* Ongoing code cleanup
* Docs: Replace Recommonmark with MyST Parser. For changes, see the commit
message in https://review.coreboot.org/73158
@@ -40,11 +79,29 @@ Changes to external resources
### Toolchain updates
* util/kconfig: Uprev to Linux 6.8's kconfig
* crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
* util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
* crossgcc: Upgrade binutils from 2.41 to 2.42
* util/crossgcc/buildgcc: Use Intel mirror for ACPICA
### Git submodule pointers
- amd_blobs: Update from commit id 64cdd7c8ef to ae5fc7d277 (1 commits)
- arm-trusted-firmware: Update from commit id 17bef2248d to 48f1bc9f52 (517
commits)
- cmocka: Update from commit id 8931845c35 to 8be3737209 (32 commits)
- fsp: Update from commit id 507ef01cce to cc6399e8c7 (14 commits)
- intel-microcode: Update from commit id ece0d294a2 to 41af345005 (1 commit)
- vboot: Update from commit id 3d37d2aafe to 09fcd2184f (27 commits)
### External payloads
#### External payloads
* payloads/U-Boot: Upgrade from U-Boot v2023.07 to v2024.4
* payloads/edk2: Add Kconfig options for LAPIC timer & UFS support
* payloads/Kconfig: Add flat binary as payload option
@@ -52,42 +109,154 @@ Platform Updates
----------------
### Added mainboards:
* To be filled in immediately before the release by the release team
* AMD BirmanPlus for Glinda SoC
* AMD BirmanPlus for Phoenix SoC
* ASROCK Z97 Extreme6
* Dell OptiPlex 7020/9020 MT
* Dell OptiPlex 7020/9020 SFF
* Framework Azalea (Framework 13 AMD 7040)
* Google Brox EC ISH
* Google Bujia
* Google Glassway
* Google Greenbayupoc
* Google Kyogre
* Google Lotso
* Google Nova
* Google Pujjoga
* Google Riven
* Google Skitty
* Google Squirtle
* Google Sundance
* Google Tivviks
* Google Trulo
* Google Veluza
* Google Wugtrio
* Google Yavista
* HP Pro 3500 Series
* Lenovo ThinkCentre M700 / M900 Tiny
* Lenovo ThinkCentre M710s
* Raptor Computing Systems Talos II
* SiFive HiFive Unmatched
### Removed Mainboards
* To be filled in immediately before the release by the release team
* Intel Alderlake-M RVP
* Intel Alderlake-M RVP with Chrome EC
### Updated SoCs
* To be filled in immediately before the release by the release team
* Added src/soc/ibm/power9
* Added src/soc/sifive/fu740
Plans to move platform support to a branch
------------------------------------------
* To be filled in immediately before the release by the release team
Statistics from the 4.22 to the 24.02 release
Statistics from the 24.02 to the 24.05 release
--------------------------------------------
* To be filled in immediately before the release by the release team
* Total Commits: 722
* Average Commits per day: 8.55
* Total lines added: 302523
* Average lines added per commit: 419.01
* Number of patches adding more than 100 lines: 57
* Average lines added per small commit: 37.80
* Total lines removed: 16089
* Average lines removed per commit: 22.28
* Total difference between added and removed: 286434
* Total authors: 131
* New authors: 23
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
* To be filled in immediately before the release by the release team
## coreboot-wide or architecture-wide issues
```{eval-rst}
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 522 | 'region_overlap()' issues due to an integer overflow. |
+-----+-----------------------------------------------------------------+
| 519 | make gconfig - could not find glade file |
+-----+-----------------------------------------------------------------+
| 518 | make xconfig - g++: fatal error: no input files |
+-----+-----------------------------------------------------------------+
```
## Payload-specific issues
```{eval-rst}
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 496 | Missing malloc check in libpayload |
+-----+-----------------------------------------------------------------+
| 484 | No USB keyboard support with secondary payloads |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
```
## Platform-specific issues
```{eval-rst}
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx |
+-----+-----------------------------------------------------------------+
| 517 | lenovo x230 boot stuck with connected external monitor |
+-----+-----------------------------------------------------------------+
| 509 | SD Card hotplug not working on Apollo Lake |
+-----+-----------------------------------------------------------------+
| 507 | Windows GPU driver fails on Google guybrush & skyrim boards |
+-----+-----------------------------------------------------------------+
| 506 | APL/GML don't boot OS when CPU microcode included "from tree" |
+-----+-----------------------------------------------------------------+
| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system |
+-----+-----------------------------------------------------------------+
| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 495 | Stoney Chromebooks not booting PSPSecureOS |
+-----+-----------------------------------------------------------------+
| 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
```
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* Main Website: https://www.coreboot.org
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org

View File

@@ -0,0 +1,100 @@
Upcoming release - coreboot 24.08
========================================================================
The 24.08 release is scheduled for Mid Aug, 2024
Update this document with changes that should be in the release notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
Significant or interesting changes
----------------------------------
* Add changes that need a full description here
* This section should have full descriptions and can or should have
a link to the referenced commits.
Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
Changes to external resources
-----------------------------
### Toolchain updates
* Upgrade ACPICA from 20230628 to 20240321
* Upgrade CMake from 3.28.3 to 3.29.3
* Upgrade nasm from 2.16.01 to 2.16.03
* Upgrade LLVM from 17.0.6 to 18.1.6
* Upgrade GCC from 13.2 to 14.1.0
### Git submodule pointers
### External payloads
Platform Updates
----------------
### Added mainboards:
* To be filled in immediately before the release by the release team
### Removed Mainboards
* To be filled in immediately before the release by the release team
### Updated SoCs
* To be filled in immediately before the release by the release team
Plans to move platform support to a branch
------------------------------------------
* To be filled in immediately before the release by the release team
Statistics from the 24.05 to the 24.08 release
--------------------------------------------
* To be filled in immediately before the release by the release team
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
* To be filled in immediately before the release by the release team
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

View File

@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
```{toctree}
:maxdepth: 1
24.05 - May 2024 <coreboot-24.05-relnotes.md>
24.08 - August 2024 <coreboot-24.08-relnotes.md>
```
The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
```{toctree}
:maxdepth: 1
24.05 - May 2024 <coreboot-24.05-relnotes.md>
24.02 - February 2024 <coreboot-24.02-relnotes.md>
4.22 - November 2023 <coreboot-4.22-relnotes.md>
4.21 - August 2023 <coreboot-4.21-relnotes.md>

View File

@@ -4,6 +4,8 @@
- Birman for Phoenix SoC using FSP
- Birman for Phoenix SoC using openSIL
- Birman for Glinda SoC
- BirmanPlus for Phoenix SoC
- BirmanPlus for Glinda SoC
- Chausie
- Majolica
- Mayan for Phoenix SoC
@@ -35,6 +37,9 @@
- Tricky (Dell Chromebox 3010)
- Zako (HP Chromebox G1)
- Brox
- Brox EC ISH
- Lotso
- Greenbayupoc
- Agah
- Anahera
- Anahera4ES
@@ -53,6 +58,7 @@
- Gimble
- Gimble4ES
- Gladios
- Glassway
- Gothrax
- Hades
- Kano
@@ -74,11 +80,14 @@
- Quandiso
- Redrix
- Redrix4ES
- Riven
- Skolas
- Skolas4ES
- Taeko
- Taeko4ES
- Taniks
- Tivviks
- Trulo
- Uldren
- Vell
- Volmar
@@ -87,19 +96,29 @@
- Yavilla
- Zydron
- Xol
- Nova
- Bujia
- Yavista
- Sundance
- Pujjoga
- Butterfly (HP Pavilion Chromebook 14)
- Cherry
- Dojo
- Tomato
- Kingler
- Kyogre
- Ponyta
- Squirtle
- Steelix
- Voltorb
- Ponyta
- Krabby
- Tentacruel
- Magikarp
- Chinchou
- Krabby
- Magikarp
- Skitty
- Tentacruel
- Veluza
- Starmie
- Wugtrio
- Banon (Acer Chromebook 15 (CB3-532))
- Celes (Samsung Chromebook 3)
- Cyan (Acer Chromebook R11 (C738T))
@@ -305,8 +324,6 @@
- Alderlake-P RVP
- Alderlake-P RVP with Chrome EC
- Alderlake-P RVP with Microchip EC
- Alderlake-M RVP
- Alderlake-M RVP with Chrome EC
- Alderlake-N RVP
- Alderlake-N RVP with Chrome EC
- Raptorlake silicon with Alderlake-P RVP
@@ -365,6 +382,7 @@
- ThinkPad X230
- ThinkPad X230t
- ThinkPad X230s
- ThinkPad X230 eDP Mod (2K/FHD)
- ThinkPad X60 / X60s / X60t
## MSI

View File

@@ -0,0 +1,50 @@
# Type this in coreboot root directory to get a working .config:
# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc
#
# [RO] Board Configurations
#
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_AVENUECITY_CRB=y
CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
CONFIG_CONFIGURABLE_RAMSTAGE=y
CONFIG_NO_GFX_INIT=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_PAYLOAD_LINUX=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_CONSOLE_SERIAL_115200=y
#
# [RW] IFWI Ingredients
#
CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb"
CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/"
CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage"
CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
#
# [RW] Debug Settings
#
CONFIG_CONSOLE_POST=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
CONFIG_VERIFY_HOBS=y
CONFIG_DISPLAY_MTRRS=y
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y
CONFIG_HAVE_DEBUG_GPIO=y
CONFIG_DEBUG_GPIO=y

View File

@@ -0,0 +1,50 @@
# Type this in coreboot root directory to get a working .config:
# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc
#
# [RO] Board Configurations
#
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y
CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
CONFIG_CONFIGURABLE_RAMSTAGE=y
CONFIG_NO_GFX_INIT=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_PAYLOAD_LINUX=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_CONSOLE_SERIAL_115200=y
#
# [RW] IFWI Ingredients
#
CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb"
CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage"
CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
#
# [RW] Debug Settings
#
CONFIG_CONSOLE_POST=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
CONFIG_VERIFY_HOBS=y
CONFIG_DISPLAY_MTRRS=y
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y
CONFIG_HAVE_DEBUG_GPIO=y
CONFIG_DEBUG_GPIO=y

View File

@@ -1,5 +1,5 @@
CONFIG_VENDOR_PROTECTLI=y
CONFIG_BOARD_PROTECTLI_VP4670=y
CONFIG_BOARD_PROTECTLI_VP46XX=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_SMMSTORE_SIZE=0x40000
CONFIG_TPM2=y

View File

@@ -1,13 +0,0 @@
CONFIG_VENDOR_PROTECTLI=y
CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_SMMSTORE_SIZE=0x40000
CONFIG_TPM2=y
CONFIG_POST_IO_PORT=0x80
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
CONFIG_EDK2_BOOT_TIMEOUT=6
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
CONFIG_EDK2_SD_MMC_TIMEOUT=10
CONFIG_EDK2_SERIAL_SUPPORT=y

View File

@@ -33,7 +33,7 @@ endif
ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build
build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage build/initramfs | build
cp $< $@
else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)

View File

@@ -37,6 +37,8 @@ BUILD_STR += -s
endif
endif
BUILD_STR += -D BUILD_ARCH=X64
#
# EDK II (edk2/master) has the following build options relevant to coreboot:
#

View File

@@ -74,34 +74,30 @@ else
fi
if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
_ARCHINCDIR=$_INCDIR/arm
_ARCHLIBDIR=$_LIBDIR/arm
_ARCHDIR=arm
_ARCHEXTRA=""
_ARCH=arm
fi
if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
_ARCHINCDIR=$_INCDIR/arm64
_ARCHLIBDIR=$_LIBDIR/arm64
_ARCHDIR=arm64
_ARCHEXTRA=""
_ARCH=arm64
fi
if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
_ARCHINCDIR=$_INCDIR/x86
_ARCHLIBDIR=$_LIBDIR/x86
_ARCHDIR=x86
_ARCHEXTRA="-m32 "
_ARCH=x86
fi
if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
_ARCHINCDIR=$_INCDIR/mock
_ARCHLIBDIR=$_LIBDIR/mock
_ARCHDIR=mock
_ARCHEXTRA=""
_ARCH=mock
fi
_ARCHINCDIR=$_INCDIR/$_ARCHDIR
_ARCHLIBDIR=$_LIBDIR/$_ARCHDIR
if [ -f $_LIBDIR/libpayload.ldscript ]; then
_LDDIR=$_LIBDIR
elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then
_LDDIR=$BASE/../arch/$_ARCH
elif [ -f $BASE/../arch/$_ARCHDIR/libpayload.ldscript ]; then
_LDDIR=$BASE/../arch/$_ARCHDIR
fi
# Host arch should youse default linker script
if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then

View File

@@ -253,7 +253,6 @@ ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c
ramstage-y += boot.c
ramstage-y += post.c
ramstage-y += c_start.S
ramstage-y += c_exit.S
ramstage-y += cpu.c
ramstage-y += cpu_common.c
ramstage-$(CONFIG_DEBUG_HW_BREAKPOINTS) += breakpoint.c

View File

@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/boot/boot.h>
#include <arch/cpu.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <mode_switch.h>
#include <program_loading.h>
#include <symbols.h>
#include <assert.h>
@@ -26,7 +26,7 @@ void arch_prog_run(struct prog *prog)
const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog));
/* On x86 coreboot payloads expect to be called in protected mode */
protected_mode_jump(entry, arg);
protected_mode_call_1arg((void *)(uintptr_t)entry, arg);
#else
#if ENV_X86_64
void (*doit)(void *arg);

View File

@@ -1,36 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ram_segs.h>
#include <cpu/x86/cr.h>
#if ENV_X86_64
/*
* Functions to handle mode switches from long mode to protected
* mode.
*/
.text
.code64
.section ".text.protected_mode_jump", "ax", @progbits
.globl protected_mode_jump
protected_mode_jump:
push %rbp
mov %rsp, %rbp
/* Arguments to stack */
push %rdi
push %rsi
#include <cpu/x86/64bit/exit32.inc>
movl -8(%ebp), %eax /* Function to call */
movl -16(%ebp), %ebx /* Argument 0 */
/* Align the stack */
andl $0xFFFFFFF0, %esp
subl $12, %esp
pushl %ebx /* Argument 0 */
jmp *%eax
#endif

View File

@@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef X86_BOOT_H
#define X86_BOOT_H
#include <types.h>
/*
* Jump to function in protected mode.
* @arg func_ptr Function to jump to in protected mode
* @arg Argument to pass to called function
*
* @noreturn
*/
void protected_mode_jump(uint32_t func_ptr, uint32_t argument);
#endif /* X86_BOOT_H */

View File

@@ -213,69 +213,6 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
return 0;
}
#if ENV_RAMSTAGE
void *map_2M_page(unsigned long page)
{
struct pde {
uint32_t addr_lo;
uint32_t addr_hi;
} __packed;
struct pg_table {
struct pde pd[2048];
struct pde pdp[512];
} __packed;
static struct pg_table pgtbl[CONFIG_MAX_CPUS]
__attribute__((aligned(4096)));
static unsigned long mapped_window[CONFIG_MAX_CPUS];
int index;
unsigned long window;
void *result;
int i;
index = cpu_index();
if (index < 0)
return MAPPING_ERROR;
window = page >> 10;
if (window != mapped_window[index]) {
paging_disable_pae();
if (window > 1) {
struct pde *pd, *pdp;
/* Point the page directory pointers at the page
* directories
*/
memset(&pgtbl[index].pdp, 0, sizeof(pgtbl[index].pdp));
pd = pgtbl[index].pd;
pdp = pgtbl[index].pdp;
pdp[0].addr_lo = ((uintptr_t)&pd[512*0])|1;
pdp[1].addr_lo = ((uintptr_t)&pd[512*1])|1;
pdp[2].addr_lo = ((uintptr_t)&pd[512*2])|1;
pdp[3].addr_lo = ((uintptr_t)&pd[512*3])|1;
/* The first half of the page table is identity mapped
*/
for (i = 0; i < 1024; i++) {
pd[i].addr_lo = ((i & 0x3ff) << 21) | 0xE3;
pd[i].addr_hi = 0;
}
/* The second half of the page table holds the mapped
* page
*/
for (i = 1024; i < 2048; i++) {
pd[i].addr_lo = ((window & 1) << 31)
| ((i & 0x3ff) << 21) | 0xE3;
pd[i].addr_hi = (window >> 1);
}
paging_enable_pae_cr3((uintptr_t)pdp);
}
mapped_window[index] = window;
}
if (window == 0)
result = (void *)(page << 21);
else
result = (void *)(0x80000000 | ((page & 0x3ff) << 21));
return result;
}
#endif
void paging_set_nxe(int enable)
{
msr_t msr = rdmsr(IA32_EFER);
@@ -340,177 +277,3 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name)
return 0;
}
static void *get_pdpt_addr(void)
{
if (preram_symbols_available())
return _pdpt;
return (void *)(uintptr_t)read_cr3();
}
static uint64_t pde_pat_flags(int pat)
{
switch (pat) {
case PAT_UC:
return 0 | PDE_PCD | PDE_PWT;
case PAT_WC:
return 0 | 0 | PDE_PWT;
case PAT_WT:
return PDE_PAT | PDE_PCD | PDE_PWT;
case PAT_WP:
return PDE_PAT | 0 | PDE_PWT;
case PAT_WB:
return 0 | 0 | 0;
case PAT_UC_MINUS:
return 0 | PDE_PCD | 0;
default:
printk(BIOS_ERR, "PDE PAT defaulting to WB: %x\n", pat);
return pde_pat_flags(PAT_WB);
}
}
static uint64_t pde_page_flags(int pat)
{
uint64_t flags = PDE_PS | PDE_PRES | PDE_RW | PDE_A | PDE_D;
return flags | pde_pat_flags(pat);
}
static uint64_t pte_pat_flags(int pat)
{
switch (pat) {
case PAT_UC:
return 0 | PTE_PCD | PTE_PWT;
case PAT_WC:
return 0 | 0 | PTE_PWT;
case PAT_WT:
return PTE_PAT | PTE_PCD | PTE_PWT;
case PAT_WP:
return PTE_PAT | 0 | PTE_PWT;
case PAT_WB:
return 0 | 0 | 0;
case PAT_UC_MINUS:
return 0 | PTE_PCD | 0;
default:
printk(BIOS_ERR, "PTE PAT defaulting to WB: %x\n", pat);
return pte_pat_flags(PAT_WB);
}
}
static uint64_t pte_page_flags(int pat)
{
uint64_t flags = PTE_PRES | PTE_RW | PTE_A | PTE_D;
return flags | pte_pat_flags(pat);
}
/* Identity map an address. This function does not handle splitting or adding
* new pages to the page tables. It's assumed all the page tables are already
* seeded with the correct amount and topology. */
static int identity_map_one_page(uintptr_t base, size_t size, int pat,
int commit)
{
uint64_t (*pdpt)[4];
uint64_t pdpte;
uint64_t (*pd)[512];
uint64_t pde;
pdpt = get_pdpt_addr();
pdpte = (*pdpt)[(base >> PDPTE_IDX_SHIFT) & PDPTE_IDX_MASK];
/* No page table page allocation. */
if (!(pdpte & PDPTE_PRES))
return -1;
pd = (void *)(uintptr_t)(pdpte & PDPTE_ADDR_MASK);
/* Map in a 2MiB page. */
if (size == s2MiB) {
if (!commit)
return 0;
pde = base;
pde |= pde_page_flags(pat);
(*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK] = pde;
return 0;
}
if (size == s4KiB) {
uint64_t (*pt)[512];
uint64_t pte;
pde = (*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK];
/* No page table page allocation. */
if (!(pde & PDE_PRES)) {
printk(BIOS_ERR, "Cannot allocate page table for pde %p\n",
(void *)base);
return -1;
}
/* No splitting pages */
if (pde & PDE_PS) {
printk(BIOS_ERR, "Cannot split pde %p\n", (void *)base);
return -1;
}
if (!commit)
return 0;
pt = (void *)(uintptr_t)(pde & PDE_ADDR_MASK);
pte = base;
pte |= pte_page_flags(pat);
(*pt)[(base >> PTE_IDX_SHIFT) & PTE_IDX_MASK] = pte;
return 0;
}
return -1;
}
static int _paging_identity_map_addr(uintptr_t base, size_t size, int pat,
int commit)
{
while (size != 0) {
size_t map_size;
map_size = IS_ALIGNED(base, s2MiB) ? s2MiB : s4KiB;
map_size = MIN(size, map_size);
if (identity_map_one_page(base, map_size, pat, commit) < 0)
return -1;
base += map_size;
size -= map_size;
}
return 0;
}
static int paging_is_enabled(void)
{
return !!(read_cr0() & CR0_PG);
}
int paging_identity_map_addr(uintptr_t base, size_t size, int pat)
{
if (!paging_is_enabled()) {
printk(BIOS_ERR, "Paging is not enabled.\n");
return -1;
}
if (!IS_ALIGNED(base, s2MiB) && !IS_ALIGNED(base, s4KiB)) {
printk(BIOS_ERR, "base %p is not aligned.\n", (void *)base);
return -1;
}
if (!IS_ALIGNED(size, s2MiB) && !IS_ALIGNED(size, s4KiB)) {
printk(BIOS_ERR, "size %zx is not aligned.\n", size);
return -1;
}
/* First try without committing. If success commit. */
if (_paging_identity_map_addr(base, size, pat, 0))
return -1;
return _paging_identity_map_addr(base, size, pat, 1);
}

View File

@@ -498,7 +498,7 @@ tpm_result_t tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t d
if (rc)
return rc;
printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id %#x)\n",
printk(BIOS_DEBUG, "GSC TPM 2.0 (i2c %u:0x%02x id %#x)\n",
bus, dev_addr, did_vid >> 16);
if (tpm_first_access_this_boot()) {

View File

@@ -7,6 +7,8 @@
#pragma pack(push)
#include <efi/efi_datatype.h>
/**
* These includes are required to include headers that are missing in
* the FSP headers. Import order matter for the correct PiHob definition
@@ -24,7 +26,6 @@
* This file is a implementation specific header. i.e. different
* FSP implementations for different chipsets.
*/
#include <Base.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
#if CONFIG(MRC_CACHE_USING_MRC_VERSION)

View File

@@ -79,6 +79,7 @@ static const struct device_operations pci_ish_device_ops = {
};
static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_PTL_ISHB,
PCI_DID_INTEL_LNL_ISHB,
PCI_DID_INTEL_MTL_ISHB,
PCI_DID_INTEL_CNL_ISHB,

View File

@@ -21,14 +21,13 @@ struct panel_serializable_data IVO_T109NW41 = {
.init = {
PANEL_DELAY(60),
PANEL_DCS(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x27, 0xE7, 0x42, 0xF5, 0x39,
PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x0F, 0xCF, 0x42, 0xF5, 0x39,
0x36, 0x36, 0x36, 0x36, 0x32, 0x8B, 0x11, 0x65, 0x00, 0x88,
0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0xD6, 0x33),
PANEL_DCS(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x71, 0x3C,
0xA3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01),
PANEL_DCS(0xB4, 0x35, 0x35, 0x43, 0x43, 0x35, 0x35, 0x30, 0x7A,
0x30, 0x7A, 0x01, 0x9D),
PANEL_DCS(0xB6, 0x34, 0x34, 0x03),
PANEL_DCS(0xE9, 0xCD),
PANEL_DCS(0xBA, 0x84),
PANEL_DCS(0xE9, 0x3F),
@@ -40,6 +39,9 @@ struct panel_serializable_data IVO_T109NW41 = {
PANEL_DCS(0xE9, 0xCC),
PANEL_DCS(0xC7, 0x80),
PANEL_DCS(0xE9, 0x3F),
PANEL_DCS(0xE9, 0xD3),
PANEL_DCS(0xC7, 0x22),
PANEL_DCS(0xE9, 0x3F),
PANEL_DCS(0xE9, 0xC6),
PANEL_DCS(0xC8, 0x97),
PANEL_DCS(0xE9, 0x3F),
@@ -56,19 +58,25 @@ struct panel_serializable_data IVO_T109NW41 = {
0x00, 0x02, 0x00, 0x02, 0x00, 0x00),
PANEL_DCS(0xD5, 0x25, 0x24, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18,
0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02,
0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0xA8, 0xA8, 0xA8, 0xA8,
0x29, 0x29, 0x29, 0x29, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18,
0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x1E, 0x1E, 0x1E, 0x1E,
0x1F, 0x1F, 0x1F, 0x1F, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
PANEL_DCS(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
PANEL_DCS(0xE0, 0x04, 0X04, 0X06, 0X0A, 0X0A, 0X05, 0X12, 0X14,
0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C, 0X56, 0X61, 0X78,
0X7A, 0X41, 0X50, 0X68, 0X73, 0X04, 0X04, 0X06, 0X0A, 0X0A,
0X05, 0X12, 0X14, 0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C,
0X56, 0X61, 0X78, 0X7A, 0X41, 0X50, 0X68, 0X73),
PANEL_DCS(0xE7, 0x07, 0x10, 0x10, 0x1A, 0x26, 0x9E, 0x00, 0x4F,
0xA0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0A, 0x02,
0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01),
PANEL_DCS(0xBD, 0x01),
PANEL_DCS(0xB1, 0x01, 0x7F, 0x11, 0xFD),
PANEL_DCS(0xCB, 0x86),
PANEL_DCS(0xD3, 0x00, 0X00, 0X04, 0X00, 0X00),
PANEL_DCS(0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0,
0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00,
@@ -94,6 +102,7 @@ struct panel_serializable_data IVO_T109NW41 = {
PANEL_DCS(0xE9, 0x3F),
PANEL_DCS(0xE1, 0x00),
PANEL_DCS(0xBD, 0x00),
PANEL_DCS(0xD2, 0xFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
PANEL_DCS(0xE9, 0xC4),
PANEL_DCS(0xBA, 0x96),
PANEL_DCS(0xE9, 0x3F),

View File

@@ -233,6 +233,7 @@ static const enum ps2_action_key ps2_enum_val[] = {
[TK_KBD_BKLIGHT_TOGGLE] = PS2_KEY_KBD_BKLIGHT_TOGGLE,
[TK_MICMUTE] = PS2_KEY_MICMUTE,
[TK_MENU] = PS2_KEY_MENU,
[TK_DICTATE] = PS2_KEY_DICTATE,
};
static void fill_ssdt_ps2_keyboard(const struct device *dev)

View File

@@ -81,5 +81,7 @@
#define CPUID_RAPTORLAKE_J0 0xb06a2
#define CPUID_RAPTORLAKE_Q0 0xb06a3
#define CPUID_LUNARLAKE_A0_1 0xb06d0
#define CPUID_LUNARLAKE_A0_2 0xb06d1
#define CPUID_PANTHERLAKE_A0 0xc06c0
#endif /* CPU_INTEL_CPU_IDS_H */

View File

@@ -35,14 +35,6 @@ void paging_set_default_pat(void);
* failure. */
int paging_enable_for_car(const char *pdpt_name, const char *pt_name);
/* Identity map the region indicated by 'base' and 'size'. Both 'base' and
* 'size' need to be 4KiB or 2 MiB aligned. 'pat' should be one of the
* PAT defines above. 0 is returned on success, < 0 on failure. */
int paging_identity_map_addr(uintptr_t base, size_t size, int pat);
#define MAPPING_ERROR ((void *)0xffffffffUL)
void *map_2M_page(unsigned long page);
/* To be used with memset_pae */
#define MEMSET_PAE_VMEM_ALIGN (2 * MiB)
#define MEMSET_PAE_VMEM_SIZE (2 * MiB)

View File

@@ -2185,6 +2185,7 @@
#define PCI_DID_INTEL_ADL_N_ISHB 0x54fc
#define PCI_DID_INTEL_ADL_P_ISHB 0x51fc
#define PCI_DID_INTEL_LNL_ISHB 0xa845
#define PCI_DID_INTEL_PTL_ISHB 0xe445
/* Intel 82371FB (PIIX) */
#define PCI_DID_INTEL_82371FB_ISA 0x122e
@@ -3166,6 +3167,14 @@
#define PCI_DID_INTEL_LNL_ESPI_5 0xa805
#define PCI_DID_INTEL_LNL_ESPI_6 0xa806
#define PCI_DID_INTEL_LNL_ESPI_7 0xa807
#define PCI_DID_INTEL_PTL_ESPI_0 0xe400
#define PCI_DID_INTEL_PTL_ESPI_1 0xe401
#define PCI_DID_INTEL_PTL_ESPI_2 0xe402
#define PCI_DID_INTEL_PTL_ESPI_3 0xe403
#define PCI_DID_INTEL_PTL_ESPI_4 0xe404
#define PCI_DID_INTEL_PTL_ESPI_5 0xe405
#define PCI_DID_INTEL_PTL_ESPI_6 0xe406
#define PCI_DID_INTEL_PTL_ESPI_7 0xe407
/* Intel PCIE device ids */
#define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10
@@ -3528,6 +3537,14 @@
#define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d
#define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e
#define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f
#define PCI_DID_INTEL_PTL_PCIE_RP1 0xe438
#define PCI_DID_INTEL_PTL_PCIE_RP2 0xe439
#define PCI_DID_INTEL_PTL_PCIE_RP3 0xe43a
#define PCI_DID_INTEL_PTL_PCIE_RP4 0xe43b
#define PCI_DID_INTEL_PTL_PCIE_RP5 0xe43c
#define PCI_DID_INTEL_PTL_PCIE_RP6 0xe43d
#define PCI_DID_INTEL_PTL_PCIE_RP7 0xe43e
#define PCI_DID_INTEL_PTL_PCIE_RP8 0xe43f
#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38
#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39
@@ -3672,6 +3689,7 @@
#define PCI_DID_INTEL_RPP_P_PMC 0x51a1
#define PCI_DID_INTEL_RPP_S_PMC 0x7a21
#define PCI_DID_INTEL_LNL_PMC 0xa821
#define PCI_DID_INTEL_PTL_PMC 0xe421
/* Intel I2C device Ids */
#define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61
@@ -3803,6 +3821,13 @@
#define PCI_DID_INTEL_LNL_I2C4 0xa850
#define PCI_DID_INTEL_LNL_I2C5 0xa851
#define PCI_DID_INTEL_PTL_I2C0 0xe478
#define PCI_DID_INTEL_PTL_I2C1 0xe479
#define PCI_DID_INTEL_PTL_I2C2 0xe47a
#define PCI_DID_INTEL_PTL_I2C3 0xe47b
#define PCI_DID_INTEL_PTL_I2C4 0xe450
#define PCI_DID_INTEL_PTL_I2C5 0xe451
/* Intel UART device Ids */
#define PCI_DID_INTEL_LPT_LP_UART0 0x9c63
#define PCI_DID_INTEL_LPT_LP_UART1 0x9c64
@@ -3886,6 +3911,10 @@
#define PCI_DID_INTEL_LNL_UART1 0xa826
#define PCI_DID_INTEL_LNL_UART2 0xa852
#define PCI_DID_INTEL_PTL_UART0 0xe425
#define PCI_DID_INTEL_PTL_UART1 0xe426
#define PCI_DID_INTEL_PTL_UART2 0xe452
/* Intel SPI device Ids */
#define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65
#define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66
@@ -3985,6 +4014,11 @@
#define PCI_DID_INTEL_LNL_GSPI1 0xa830
#define PCI_DID_INTEL_LNL_GSPI2 0xa846
#define PCI_DID_INTEL_PTL_HWSEQ_SPI 0xe423
#define PCI_DID_INTEL_PTL_SPI0 0xe427
#define PCI_DID_INTEL_PTL_SPI1 0xe430
#define PCI_DID_INTEL_PTL_SPI2 0xe446
/* Intel IGD device Ids */
#define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902
#define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906
@@ -4148,8 +4182,9 @@
#define PCI_DID_INTEL_RPL_U_GT4 0xa7ac
#define PCI_DID_INTEL_RPL_U_GT5 0xa7ad
#define PCI_DID_INTEL_LNL_M_GT2 0x64a0
#define PCI_DID_INTEL_TWL_GT1_1 0x46D3
#define PCI_DID_INTEL_TWL_GT1_2 0x46D4
#define PCI_DID_INTEL_TWL_GT1_1 0x46d3
#define PCI_DID_INTEL_TWL_GT1_2 0x46d4
#define PCI_DID_INTEL_PTL_GT2 0x64a0
/* Intel Northbridge Ids */
#define PCI_DID_INTEL_APL_NB 0x5af0
@@ -4292,6 +4327,8 @@
#define PCI_DID_INTEL_RPL_P_ID_7 0xa70a
#define PCI_DID_INTEL_RPL_P_ID_8 0xa716
#define PCI_DID_INTEL_LNL_M_ID 0x6400
#define PCI_DID_INTEL_LNL_M_ID_1 0x6410
#define PCI_DID_INTEL_PTL_ID 0xb001
/* Intel SMBUS device Ids */
#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
@@ -4321,6 +4358,7 @@
#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
#define PCI_DID_INTEL_LNL_SMBUS 0xa822
#define PCI_DID_INTEL_PTL_SMBUS 0xe422
/* Intel EHCI device IDs */
#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
@@ -4363,6 +4401,8 @@
#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
#define PCI_DID_INTEL_LNL_XHCI 0xa87d
#define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831
#define PCI_DID_INTEL_PTL_XHCI 0xe47d
#define PCI_DID_INTEL_PTL_TCSS_XHCI 0xe431
/* Intel P2SB device Ids */
#define PCI_DID_INTEL_APL_P2SB 0x5a92
@@ -4391,6 +4431,8 @@
#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
#define PCI_DID_INTEL_LNL_P2SB 0xa820
#define PCI_DID_INTEL_LNL_P2SB2 0xa84c
#define PCI_DID_INTEL_PTL_P2SB 0xe420
#define PCI_DID_INTEL_PTL_P2SB2 0xe44c
/* Intel SRAM device Ids */
#define PCI_DID_INTEL_APL_SRAM 0x5aec
@@ -4406,6 +4448,7 @@
#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf
#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf
#define PCI_DID_INTEL_LNL_SRAM 0xa87f
#define PCI_DID_INTEL_PTL_SRAM 0xe47f
/* Intel AUDIO device Ids */
#define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20
@@ -4472,6 +4515,15 @@
#define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e
#define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f
#define PCI_DID_INTEL_PTL_AUDIO_1 0xe428
#define PCI_DID_INTEL_PTL_AUDIO_2 0xe429
#define PCI_DID_INTEL_PTL_AUDIO_3 0xe42a
#define PCI_DID_INTEL_PTL_AUDIO_4 0xe42b
#define PCI_DID_INTEL_PTL_AUDIO_5 0xe42c
#define PCI_DID_INTEL_PTL_AUDIO_6 0xe42d
#define PCI_DID_INTEL_PTL_AUDIO_7 0xe42e
#define PCI_DID_INTEL_PTL_AUDIO_8 0xe42f
/* Intel HECI/ME device Ids */
#define PCI_DID_INTEL_LPT_H_MEI 0x8c3a
#define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba
@@ -4517,6 +4569,10 @@
#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
#define PCI_DID_INTEL_MTL_CSE0 0x7e70
#define PCI_DID_INTEL_LNL_CSE0 0xa870
#define PCI_DID_INTEL_PTL_CSE0 0xe470
#define PCI_DID_INTEL_PTL_CSE1 0xe471
#define PCI_DID_INTEL_PTL_CSE2 0xe474
#define PCI_DID_INTEL_PTL_CSE3 0xe475
/* Intel XDCI device Ids */
#define PCI_DID_INTEL_APL_XDCI 0x5aaa
@@ -4540,6 +4596,7 @@
#define PCI_DID_INTEL_MTL_XDCI 0x7e7e
#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1
#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1
#define PCI_DID_INTEL_PTL_TCSS_XDCI 0xe432
/* Intel SD device Ids */
#define PCI_DID_INTEL_LPT_LP_SD 0x9c35
@@ -4561,6 +4618,7 @@
/* Intel UFS device Ids */
#define PCI_DID_INTEL_LNL_UFS 0xa847
#define PCI_DID_INTEL_PTL_UFS 0xe447
/* Intel Thunderbolt device Ids */
#define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23
@@ -4598,8 +4656,11 @@
#define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e
#define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f
#define PCI_DID_INTEL_LNL_TBT_RP2 0xa860
#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837
#define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833
#define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834
#define PCI_DID_INTEL_PTL_TBT_DMA0 0xe433
#define PCI_DID_INTEL_PTL_TBT_DMA1 0xe434
/* Intel WIFI Ids */
#define PCI_DID_1000_SERIES_WIFI 0x0084
@@ -4632,6 +4693,7 @@
#define PCI_DID_TP_6SERIES_WIFI 0x2725
#define PCI_DID_MP_7SERIES_WIFI 0x272b
/* Intel IPU device IDs */
#define PCI_DID_INTEL_TGL_IPU 0x9a19
#define PCI_DID_INTEL_TGL_H_IPU 0x9a39
#define PCI_DID_INTEL_JSL_IPU 0x4e19
@@ -4640,6 +4702,7 @@
#define PCI_DID_INTEL_MTL_IPU 0x7d19
#define PCI_DID_INTEL_RPL_IPU 0xa75d
#define PCI_DID_INTEL_LNL_IPU 0x645d
#define PCI_DID_INTEL_PTL_IPU 0xb05d
/* Intel Dynamic Tuning Technology Device */
#define PCI_DID_INTEL_CML_DTT 0x1903
@@ -4699,12 +4762,20 @@
#define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842
#define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843
#define PCI_DID_INTEL_LNL_CNVI_BT 0xa876
#define PCI_DID_INTEL_PTL_CNVI_WIFI_0 0xe440
#define PCI_DID_INTEL_PTL_CNVI_WIFI_1 0xe441
#define PCI_DID_INTEL_PTL_CNVI_WIFI_2 0xe442
#define PCI_DID_INTEL_PTL_CNVI_WIFI_3 0xe443
#define PCI_DID_INTEL_PTL_CNVI_BT 0xe476
/* Platform Security Engine */
#define PCI_DID_INTEL_LNL_PSE0 0xa862
#define PCI_DID_INTEL_LNL_PSE1 0xa863
#define PCI_DID_INTEL_LNL_PSE2 0xa864
/* In-memory Analytics Accelerator device IDs */
#define PCI_DID_INTEL_LNL_IAA 0x642d
/* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d
#define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d
@@ -4718,6 +4789,7 @@
/* Intel Trace Hub */
#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24
#define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f
/* Intel Ethernet Controller device Ids */
#define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32

View File

@@ -4,6 +4,7 @@
#ifndef __DEVICE_TREE_H__
#define __DEVICE_TREE_H__
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <commonlib/list.h>
@@ -33,6 +34,7 @@ struct fdt_header {
#define FDT_TOKEN_BEGIN_NODE 1
#define FDT_TOKEN_END_NODE 2
#define FDT_TOKEN_PROPERTY 3
#define FDT_TOKEN_NOP 4
#define FDT_TOKEN_END 9
#define FDT_PHANDLE_ILLEGAL 0xdeadbeef
@@ -47,6 +49,11 @@ struct fdt_property
* Unflattened device tree structures.
*/
struct device_tree_region {
u64 addr;
u64 size;
};
struct device_tree_property
{
struct fdt_property prop;
@@ -91,6 +98,8 @@ struct device_tree
* which were consumed reading the requested value.
*/
/* Checks if blob points to a valid FDT */
bool fdt_is_valid(const void *blob);
/* Read the property at offset, if any exists. */
int fdt_next_property(const void *blob, uint32_t offset,
struct fdt_property *prop);
@@ -100,6 +109,26 @@ int fdt_node_name(const void *blob, uint32_t offset, const char **name);
void fdt_print_node(const void *blob, uint32_t offset);
int fdt_skip_node(const void *blob, uint32_t offset);
/* Read property and put into fdt_prop. Returns offset to property */
u32 fdt_read_prop(const void *blob, u32 node_offset, const char *prop_name,
struct fdt_property *fdt_prop);
/* Read reg property and save regions inside 'regions'. Returns number of regions read */
u32 fdt_read_reg_prop(const void *blob, u32 node_offset, u32 addr_cells, u32 size_cells,
struct device_tree_region regions[], size_t regions_count);
/* Find a node by a given path and return the offset */
u32 fdt_find_node_by_path(const void *blob, const char *path, u32 *addrcp, u32 *sizecp);
/* Find multiple nodes matching a given pattern. Returns number of nodes found */
size_t fdt_find_subnodes_by_prefix(const void *blob, u32 node_offset, const char *prefix,
u32 *addrcp, u32 *sizecp, u32 results[], size_t results_len);
/* Find a node by a given alias and return its offset */
u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
u32 *addr_cells, u32 *size_cells);
/*
* Read the node name into 'name' of the node behind 'node_offset'
* and return total bytes used for name
*/
int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
/* Read a flattened device tree into a hierarchical structure which refers to
the contents of the flattened tree in place. Modifying the flat tree
invalidates the unflattened one. */

View File

@@ -3,6 +3,22 @@
/* Create EFI equivalent datatype in coreboot based on UEFI specification */
#ifndef __EFI_DATATYPE_H__
#define __EFI_DATATYPE_H__
/*
* EDK2 EFIAPI macro definition relies on compiler flags such as __GNUC__ which
* is not working well when included by coreboot. While it has no side-effect on
* i386 because the C calling convention used by coreboot and FSP are the same,
* it breaks on x86_64 because FSP/UEFI uses the Microsoft x64 calling
* convention while coreboot uses the System V AMD64 ABI.
*
* Fortunately, EDK2 header allows to override EFIAPI.
*/
#if CONFIG(PLATFORM_USES_FSP2_X86_32)
#define EFIAPI __attribute__((regparm(0)))
#else
#define EFIAPI __attribute__((__ms_abi__))
#endif
#include <Base.h>
#include <Uefi/UefiBaseType.h>

View File

@@ -6,21 +6,39 @@
#include <ctype.h>
#include <device_tree.h>
#include <endian.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stddef.h>
#include <stdlib.h>
#define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound
#define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound
/*
* Functions for picking apart flattened trees.
*/
static int fdt_skip_nops(const void *blob, uint32_t offset)
{
uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
int index = 0;
while (be32toh(ptr[index]) == FDT_TOKEN_NOP)
index++;
return index * sizeof(uint32_t);
}
int fdt_next_property(const void *blob, uint32_t offset,
struct fdt_property *prop)
{
struct fdt_header *header = (struct fdt_header *)blob;
uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
// skip NOP tokens
offset += fdt_skip_nops(blob, offset);
int index = 0;
if (be32toh(ptr[index++]) != FDT_TOKEN_PROPERTY)
return 0;
@@ -40,24 +58,369 @@ int fdt_next_property(const void *blob, uint32_t offset,
return index * sizeof(uint32_t);
}
int fdt_node_name(const void *blob, uint32_t offset, const char **name)
/*
* fdt_next_node_name reads a node name
*
* @params blob address of FDT
* @params offset offset to the node to read the name from
* @params name parameter to hold the name that has been read or NULL
*
* @returns Either 0 on error or offset to the properties that come after the node name
*/
int fdt_next_node_name(const void *blob, uint32_t offset, const char **name)
{
uint8_t *ptr = ((uint8_t *)blob) + offset;
// skip NOP tokens
offset += fdt_skip_nops(blob, offset);
char *ptr = ((char *)blob) + offset;
if (be32dec(ptr) != FDT_TOKEN_BEGIN_NODE)
return 0;
ptr += 4;
if (name)
*name = (char *)ptr;
return ALIGN_UP(strlen((char *)ptr) + 1, sizeof(uint32_t)) + 4;
*name = ptr;
return ALIGN_UP(strlen(ptr) + 1, 4) + 4;
}
static int dt_prop_is_phandle(struct device_tree_property *prop)
/*
* A utility function to skip past nodes in flattened trees.
*/
int fdt_skip_node(const void *blob, uint32_t start_offset)
{
return !(strcmp("phandle", prop->prop.name) &&
strcmp("linux,phandle", prop->prop.name));
uint32_t offset = start_offset;
const char *name;
int size = fdt_next_node_name(blob, offset, &name);
if (!size)
return 0;
offset += size;
while ((size = fdt_next_property(blob, offset, NULL)))
offset += size;
while ((size = fdt_skip_node(blob, offset)))
offset += size;
// skip NOP tokens
offset += fdt_skip_nops(blob, offset);
return offset - start_offset + sizeof(uint32_t);
}
/*
* fdt_read_prop reads a property inside a node
*
* @params blob address of FDT
* @params node_offset offset to the node to read the property from
* @params prop_name name of the property to read
* @params fdt_prop property is saved inside this parameter
*
* @returns Either 0 if no property has been found or an offset that points to the location
* of the property
*/
u32 fdt_read_prop(const void *blob, u32 node_offset, const char *prop_name,
struct fdt_property *fdt_prop)
{
u32 offset = node_offset;
offset += fdt_next_node_name(blob, offset, NULL); // skip node name
size_t size;
while ((size = fdt_next_property(blob, offset, fdt_prop))) {
if (strcmp(fdt_prop->name, prop_name) == 0)
return offset;
offset += size;
}
return 0; // property not found
}
/*
* fdt_read_reg_prop reads the reg property inside a node
*
* @params blob address of FDT
* @params node_offset offset to the node to read the reg property from
* @params addr_cells number of cells used for one address
* @params size_cells number of cells used for one size
* @params regions all regions that are read inside the reg property are saved inside
* this array
* @params regions_count maximum number of entries that can be saved inside the regions array.
*
* Returns: Either 0 on error or returns the number of regions put into the regions array.
*/
u32 fdt_read_reg_prop(const void *blob, u32 node_offset, u32 addr_cells, u32 size_cells,
struct device_tree_region regions[], size_t regions_count)
{
struct fdt_property prop;
u32 offset = fdt_read_prop(blob, node_offset, "reg", &prop);
if (!offset) {
printk(BIOS_DEBUG, "no reg property found in node_offset: %x\n", node_offset);
return 0;
}
// we found the reg property, now need to parse all regions in 'reg'
size_t count = prop.size / (4 * addr_cells + 4 * size_cells);
if (count > regions_count) {
printk(BIOS_ERR, "reg property at node_offset: %x has more entries (%zd) than regions array can hold (%zd)\n", node_offset, count, regions_count);
count = regions_count;
}
if (addr_cells > 2 || size_cells > 2) {
printk(BIOS_ERR, "addr_cells (%d) or size_cells (%d) bigger than 2\n",
addr_cells, size_cells);
return 0;
}
uint32_t *ptr = prop.data;
for (int i = 0; i < count; i++) {
if (addr_cells == 1)
regions[i].addr = be32dec(ptr);
else if (addr_cells == 2)
regions[i].addr = be64dec(ptr);
ptr += addr_cells;
if (size_cells == 1)
regions[i].size = be32dec(ptr);
else if (size_cells == 2)
regions[i].size = be64dec(ptr);
ptr += size_cells;
}
return count; // return the number of regions found in the reg property
}
static u32 fdt_read_cell_props(const void *blob, u32 node_offset, u32 *addrcp, u32 *sizecp)
{
struct fdt_property prop;
u32 offset = node_offset;
size_t size;
while ((size = fdt_next_property(blob, offset, &prop))) {
if (addrcp && !strcmp(prop.name, "#address-cells"))
*addrcp = be32dec(prop.data);
if (sizecp && !strcmp(prop.name, "#size-cells"))
*sizecp = be32dec(prop.data);
offset += size;
}
return offset;
}
/*
* fdt_find_node searches for a node relative to another node
*
* @params blob address of FDT
*
* @params parent_node_offset offset to node from which to traverse the tree
*
* @params path null terminated array of node names specifying a
* relative path (e.g: { "cpus", "cpu0", NULL })
*
* @params addrcp/sizecp If any address-cells and size-cells properties are found that are
* part of the parent node of the node we are looking, addrcp and sizecp
* are set to these respectively.
*
* @returns: Either 0 if no node has been found or the offset to the node found
*/
static u32 fdt_find_node(const void *blob, u32 parent_node_offset, char **path,
u32 *addrcp, u32 *sizecp)
{
if (*path == NULL)
return parent_node_offset; // node found
size_t size = fdt_next_node_name(blob, parent_node_offset, NULL); // skip node name
/*
* get address-cells and size-cells properties while skipping the others.
* According to spec address-cells and size-cells are not inherited, but we
* intentionally follow the Linux implementation here and treat them as inheritable.
*/
u32 node_offset = fdt_read_cell_props(blob, parent_node_offset + size, addrcp, sizecp);
const char *node_name;
// walk all children nodes
while ((size = fdt_next_node_name(blob, node_offset, &node_name))) {
if (!strcmp(*path, node_name)) {
// traverse one level deeper into the path
return fdt_find_node(blob, node_offset, path + 1, addrcp, sizecp);
}
// node is not the correct one. skip current node
node_offset += fdt_skip_node(blob, node_offset);
}
// we have searched everything and could not find a fitting node
return 0;
}
/*
* fdt_find_node_by_path finds a node behind a given node path
*
* @params blob address of FDT
* @params path absolute path to the node that should be searched for
*
* @params addrcp/sizecp Pointer that will be updated with any #address-cells and #size-cells
* value found in the node of the node specified by node_offset. Either
* may be NULL to ignore. If no #address-cells and #size-cells is found
* default values of #address-cells=2 and #size-cells=1 are returned.
*
* @returns Either 0 on error or the offset to the node found behind the path
*/
u32 fdt_find_node_by_path(const void *blob, const char *path, u32 *addrcp, u32 *sizecp)
{
// sanity check
if (path[0] != '/') {
printk(BIOS_ERR, "devicetree path must start with a /\n");
return 0;
}
if (!blob) {
printk(BIOS_ERR, "devicetree blob is NULL\n");
return 0;
}
if (addrcp)
*addrcp = 2;
if (sizecp)
*sizecp = 1;
struct fdt_header *fdt_hdr = (struct fdt_header *)blob;
/*
* split path into separate nodes
* e.g: "/cpus/cpu0" -> { "cpus", "cpu0" }
*/
char *path_array[FDT_PATH_MAX_DEPTH];
size_t path_size = strlen(path);
assert(path_size < FDT_PATH_MAX_LEN);
char path_copy[FDT_PATH_MAX_LEN];
memcpy(path_copy, path, path_size + 1);
char *cur = path_copy;
int i;
for (i = 0; i < FDT_PATH_MAX_DEPTH; i++) {
path_array[i] = strtok_r(NULL, "/", &cur);
if (!path_array[i])
break;
}
assert(i < FDT_PATH_MAX_DEPTH);
return fdt_find_node(blob, be32toh(fdt_hdr->structure_offset), path_array, addrcp, sizecp);
}
/*
* fdt_find_subnodes_by_prefix finds a node with a given prefix relative to a parent node
*
* @params blob The FDT to search.
*
* @params node_offset offset to the node of which the children should be searched
*
* @params prefix A string to search for a node with a given prefix. This can for example
* be 'cpu' to look for all nodes matching this prefix. Only children of
* node_offset are searched. Therefore in order to search all nodes matching
* the 'cpu' prefix, node_offset should probably point to the 'cpus' node.
* An empty prefix ("") searches for all children nodes of node_offset.
*
* @params addrcp/sizecp Pointer that will be updated with any #address-cells and #size-cells
* value found in the node of the node specified by node_offset. Either
* may be NULL to ignore. If no #address-cells and #size-cells is found
* addrcp and sizecp are left untouched.
*
* @params results Array of offsets pointing to each node matching the given prefix.
* @params results_len Number of entries allocated for the 'results' array
*
* @returns offset to last node found behind path or 0 if no node has been found
*/
size_t fdt_find_subnodes_by_prefix(const void *blob, u32 node_offset, const char *prefix,
u32 *addrcp, u32 *sizecp, u32 *results, size_t results_len)
{
// sanity checks
if (!blob || !results || !prefix) {
printk(BIOS_ERR, "%s: input parameter cannot be null/\n", __func__);
return 0;
}
u32 offset = node_offset;
// we don't care about the name of the current node
u32 size = fdt_next_node_name(blob, offset, NULL);
if (!size) {
printk(BIOS_ERR, "%s: node_offset: %x does not point to a node\n",
__func__, node_offset);
return 0;
}
offset += size;
/*
* update addrcp and sizecp if the node contains an address-cells and size-cells
* property. Otherwise use addrcp and sizecp provided by caller.
*/
offset = fdt_read_cell_props(blob, offset, addrcp, sizecp);
size_t count_results = 0;
int prefix_len = strlen(prefix);
const char *node_name;
// walk all children nodes of offset
while ((size = fdt_next_node_name(blob, offset, &node_name))) {
if (count_results >= results_len) {
printk(BIOS_WARNING,
"%s: results_len (%zd) smaller than count_results (%zd)\n",
__func__, results_len, count_results);
break;
}
if (!strncmp(prefix, node_name, prefix_len)) {
// we found a node that matches the prefix
results[count_results++] = offset;
}
// node does not match the prefix. skip current node
offset += fdt_skip_node(blob, offset);
}
// return last occurrence
return count_results;
}
static const char *fdt_read_alias_prop(const void *blob, const char *alias_name)
{
u32 node_offset = fdt_find_node_by_path(blob, "/aliases", NULL, NULL);
if (!node_offset) {
printk(BIOS_DEBUG, "no /aliases node found\n");
return NULL;
}
struct fdt_property alias_prop;
if (!fdt_read_prop(blob, node_offset, alias_name, &alias_prop)) {
printk(BIOS_DEBUG, "property %s in /aliases node not found\n", alias_name);
return NULL;
}
return (const char *)alias_prop.data;
}
/*
* Find a node in the tree from a string device tree path.
*
* @params blob Address to the FDT
* @params alias_name node name alias that should be searched for.
* @params addrcp/sizecp Pointer that will be updated with any #address-cells and #size-cells
* value found in the node of the node specified by node_offset. Either
* may be NULL to ignore. If no #address-cells and #size-cells is found
* default values of #address-cells=2 and #size-cells=1 are returned.
*
* @returns offset to last node found behind path or 0 if no node has been found
*/
u32 fdt_find_node_by_alias(const void *blob, const char *alias_name, u32 *addrcp, u32 *sizecp)
{
const char *node_name = fdt_read_alias_prop(blob, alias_name);
if (!node_name) {
printk(BIOS_DEBUG, "alias %s not found\n", alias_name);
return 0;
}
u32 node_offset = fdt_find_node_by_path(blob, node_name, addrcp, sizecp);
if (!node_offset) {
// This should not happen (invalid devicetree)
printk(BIOS_WARNING,
"Could not find node '%s', which alias was referring to '%s'\n",
node_name, alias_name);
return 0;
}
return node_offset;
}
/*
@@ -108,7 +471,7 @@ static int print_flat_node(const void *blob, uint32_t start_offset, int depth)
const char *name;
int size;
size = fdt_node_name(blob, offset, &name);
size = fdt_next_node_name(blob, offset, &name);
if (!size)
return 0;
offset += size;
@@ -139,38 +502,16 @@ void fdt_print_node(const void *blob, uint32_t offset)
print_flat_node(blob, offset, 0);
}
/*
* A utility function to skip past nodes in flattened trees.
*/
int fdt_skip_node(const void *blob, uint32_t start_offset)
{
int offset = start_offset;
int size;
const char *name;
size = fdt_node_name(blob, offset, &name);
if (!size)
return 0;
offset += size;
while ((size = fdt_next_property(blob, offset, NULL)))
offset += size;
while ((size = fdt_skip_node(blob, offset)))
offset += size;
return offset - start_offset + sizeof(uint32_t);
}
/*
* Functions to turn a flattened tree into an unflattened one.
*/
static int dt_prop_is_phandle(struct device_tree_property *prop)
{
return !(strcmp("phandle", prop->prop.name) &&
strcmp("linux,phandle", prop->prop.name));
}
static int fdt_unflatten_node(const void *blob, uint32_t start_offset,
struct device_tree *tree,
struct device_tree_node **new_node)
@@ -180,7 +521,7 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset,
const char *name;
int size;
size = fdt_node_name(blob, offset, &name);
size = fdt_next_node_name(blob, offset, &name);
if (!size)
return 0;
offset += size;
@@ -237,30 +578,37 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset,
return sizeof(uint64_t) * 2;
}
struct device_tree *fdt_unflatten(const void *blob)
bool fdt_is_valid(const void *blob)
{
struct device_tree *tree = xzalloc(sizeof(*tree));
const struct fdt_header *header = (const struct fdt_header *)blob;
tree->header = header;
uint32_t magic = be32toh(header->magic);
uint32_t version = be32toh(header->version);
uint32_t last_comp_version = be32toh(header->last_comp_version);
if (magic != FDT_HEADER_MAGIC) {
printk(BIOS_DEBUG, "Invalid device tree magic %#.8x!\n", magic);
free(tree);
return NULL;
printk(BIOS_ERR, "Invalid device tree magic %#.8x!\n", magic);
return false;
}
if (last_comp_version > FDT_SUPPORTED_VERSION) {
printk(BIOS_DEBUG, "Unsupported device tree version %u(>=%u)\n",
printk(BIOS_ERR, "Unsupported device tree version %u(>=%u)\n",
version, last_comp_version);
free(tree);
return NULL;
return false;
}
if (version > FDT_SUPPORTED_VERSION)
printk(BIOS_NOTICE, "FDT version %u too new, should add support!\n",
version);
return true;
}
struct device_tree *fdt_unflatten(const void *blob)
{
struct device_tree *tree = xzalloc(sizeof(*tree));
const struct fdt_header *header = (const struct fdt_header *)blob;
tree->header = header;
if (fdt_is_valid(blob))
return NULL;
uint32_t struct_offset = be32toh(header->structure_offset);
uint32_t strings_offset = be32toh(header->strings_offset);
@@ -981,7 +1329,7 @@ void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val)
* Add a 'reg' address list property to a node, or update it if it exists.
*
* @param node The device tree node to add to.
* @param addrs Array of address values to be stored in the property.
* @param regions Array of address values to be stored in the property.
* @param sizes Array of corresponding size values to 'addrs'.
* @param count Number of values in 'addrs' and 'sizes' (must be equal).
* @param addr_cells Value of #address-cells property valid for this node.

View File

@@ -9,6 +9,7 @@ romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c
ramstage-y += chromeos.c
ramstage-y += gpio.c
ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL) += update_devicetree_phoenix_opensil.c
ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c
ramstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c

View File

@@ -43,25 +43,75 @@ chip soc/amd/phoenix
device domain 0 on
device ref iommu on end
device ref gpp_bridge_1_1 on end # MXM
device ref gpp_bridge_1_2 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "0"
register "end_lane" = "7"
register "aspm" = "ASPM_L1"
register "clk_req" = "CLK_REQ0"
# register "gpio_group" is currently not used
device ref gpp_bridge_1_1 on end # MXM
end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "8"
register "end_lane" = "11"
register "aspm" = "ASPM_L1"
register "clk_req" = "CLK_REQ1"
device ref gpp_bridge_1_2 on # NVMe SSD1
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end
end # NVMe SSD1
device ref gpp_bridge_1_3 on end # GBE
device ref gpp_bridge_2_1 on end # SD
device ref gpp_bridge_2_2 on end # WWAN
device ref gpp_bridge_2_3 on end # WIFI
device ref gpp_bridge_2_4 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "12"
register "end_lane" = "12"
register "aspm" = "ASPM_DISABLED"
register "clk_req" = "CLK_REQ6"
device ref gpp_bridge_1_3 on end # GBE
end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "13"
register "end_lane" = "13"
register "aspm" = "ASPM_DISABLED"
register "clk_req" = "CLK_REQ5"
device ref gpp_bridge_2_1 on end # SD
end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "14"
register "end_lane" = "14"
register "aspm" = "ASPM_DISABLED"
register "clk_req" = "CLK_REQ4"
device ref gpp_bridge_2_2 on end # WWAN
end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "15"
register "end_lane" = "15"
register "aspm" = "ASPM_DISABLED"
register "clk_req" = "CLK_REQ3"
device ref gpp_bridge_2_3 on end # WIFI
end
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "16"
register "end_lane" = "19"
register "aspm" = "ASPM_DISABLED"
register "clk_req" = "CLK_REQ2"
device ref gpp_bridge_2_4 on # NVMe SSD0
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end
end # NVMe SSD0
end
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)

View File

@@ -6,6 +6,7 @@
#include <device/device.h>
#include <types.h>
#include "gpio.h"
#include "update_devicetree.h"
/* TODO: Update for birman */
@@ -58,6 +59,9 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
static void mainboard_init(void *chip_info)
{
mainboard_program_gpios();
if (CONFIG(BOARD_AMD_BIRMAN_PHOENIX_OPENSIL))
mainboard_update_devicetree_opensil();
}
struct chip_operations mainboard_ops = {

View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_UPDATE_DEVICETREE_H
#define MAINBOARD_UPDATE_DEVICETREE_H
void mainboard_update_devicetree_opensil(void);
#endif /* MAINBOARD_UPDATE_DEVICETREE_H */

View File

@@ -0,0 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <soc/soc_util.h>
#include <vendorcode/amd/opensil/chip/mpio/chip.h>
#include "update_devicetree.h"
static void mainboard_update_mpio(void)
{
struct device *mxm_bridge = DEV_PTR(gpp_bridge_1_1);
struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2);
struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2);
struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3);
struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge);
struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge);
struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge);
struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge);
/* Phoenix 2 has less PCIe lanes than Phoenix */
if (get_soc_type() == SOC_PHOENIX2) {
mxm_bridge_cfg->end_lane = 3;
ssd1_bridge_cfg->end_lane = 9;
}
if (!CONFIG(ENABLE_EVAL_CARD)) {
mxm_bridge->enabled = false;
}
if (CONFIG(DISABLE_DT_M2)) {
ssd1_bridge->enabled = false;
}
/* When the WLAN card uses 2 lanes, the WWAN card can't be used */
if (CONFIG(WLAN01)) {
wwan_bridge->enabled = false;
wlan_bridge_cfg->end_lane = 14;
}
/* When the WWAN card uses 2 lanes, the WLAN card can't be used */
if (CONFIG(WWAN01)) {
wlan_bridge->enabled = false;
wwan_bridge_cfg->end_lane = 15;
}
}
void mainboard_update_devicetree_opensil(void)
{
mainboard_update_mpio();
}

View File

@@ -55,7 +55,7 @@ chip soc/amd/genoa_poc
device domain 0 on
device ref iommu_0 on end
device ref rcec_0 on end
chip vendorcode/amd/opensil/genoa_poc/mpio # P2
chip vendorcode/amd/opensil/chip/mpio # P2
register "type" = "IFTYPE_PCIE"
register "start_lane" = "48"
register "end_lane" = "63"
@@ -63,7 +63,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_0_0_a on end
end
chip vendorcode/amd/opensil/genoa_poc/mpio # G2
chip vendorcode/amd/opensil/chip/mpio # G2
register "type" = "IFTYPE_PCIE"
register "start_lane" = "112"
register "end_lane" = "127"
@@ -72,7 +72,7 @@ chip soc/amd/genoa_poc
register "hotplug" = "ServerExpress"
device ref gpp_bridge_0_0_b on end
end
chip vendorcode/amd/opensil/genoa_poc/mpio
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "128"
register "end_lane" = "131"
@@ -93,7 +93,7 @@ chip soc/amd/genoa_poc
device domain 1 on
device ref iommu_1 on end
device ref rcec_1 on end
chip vendorcode/amd/opensil/genoa_poc/mpio # P3
chip vendorcode/amd/opensil/chip/mpio # P3
register "type" = "IFTYPE_PCIE"
register "start_lane" = "16"
register "end_lane" = "31"
@@ -101,7 +101,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_1_0_a on end
end
chip vendorcode/amd/opensil/genoa_poc/mpio # G3
chip vendorcode/amd/opensil/chip/mpio # G3
register "type" = "IFTYPE_PCIE"
register "start_lane" = "80"
register "end_lane" = "95"
@@ -114,7 +114,7 @@ chip soc/amd/genoa_poc
device domain 2 on
device ref iommu_2 on end
device ref rcec_2 on end
chip vendorcode/amd/opensil/genoa_poc/mpio # P1
chip vendorcode/amd/opensil/chip/mpio # P1
register "type" = "IFTYPE_PCIE"
register "start_lane" = "32"
register "end_lane" = "47"
@@ -123,7 +123,7 @@ chip soc/amd/genoa_poc
register "hotplug" = "ServerExpress"
device ref gpp_bridge_2_0_a on end
end
chip vendorcode/amd/opensil/genoa_poc/mpio # G1
chip vendorcode/amd/opensil/chip/mpio # G1
register "type" = "IFTYPE_PCIE"
register "start_lane" = "64"
register "end_lane" = "79"
@@ -137,7 +137,7 @@ chip soc/amd/genoa_poc
device domain 3 on
device ref iommu_3 on end
device ref rcec_3 on end
chip vendorcode/amd/opensil/genoa_poc/mpio # P0
chip vendorcode/amd/opensil/chip/mpio # P0
register "type" = "IFTYPE_PCIE"
register "start_lane" = "0"
register "end_lane" = "15"
@@ -145,7 +145,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_3_0_a on end
end
chip vendorcode/amd/opensil/genoa_poc/mpio # G0
chip vendorcode/amd/opensil/chip/mpio # G0
register "type" = "IFTYPE_PCIE"
register "start_lane" = "96"
register "end_lane" = "111"
@@ -153,7 +153,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_3_0_b on end
end
chip vendorcode/amd/opensil/genoa_poc/mpio
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "132"
register "end_lane" = "133"
@@ -161,7 +161,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_3_0_c on end # WAFL
end
chip vendorcode/amd/opensil/genoa_poc/mpio
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "134"
register "end_lane" = "134"
@@ -170,7 +170,7 @@ chip soc/amd/genoa_poc
register "bmc" = "1"
device ref gpp_bridge_3_1_c on end # BMC
end
chip vendorcode/amd/opensil/genoa_poc/mpio
chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "135"
register "end_lane" = "135"

View File

@@ -9,3 +9,4 @@ sata_mode=AHCI
usb3_mode=Enable
usb3_drv=Enable
usb3_streams=Enable
audio_panel_type=HDA

View File

@@ -51,6 +51,11 @@ entries
#
424 1 e 1 usb3_streams
# audio_panel_type
# HD Audio or AC'97
#
425 1 e 9 audio_panel_type
# -----------------------------------------------------------------
# Sandy/Ivy Bridge MRC Scrambler Seed values
# note: MUST NOT be covered by checksum!
@@ -128,6 +133,10 @@ enumerations
8 2 Auto
8 3 SmartAuto
# audio_panel_type
9 0 HDA
9 1 AC97
# -----------------------------------------------------------------
# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
# <bit where to start storing checksum[must be 16bits-aligned]>

View File

@@ -1,6 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/azalia_device.h>
#include <stdint.h>
#include <option.h>
const u32 cim_verb_data[] = {
0x10ec0887, /* Codec Vendor / Device ID: Realtek */
@@ -34,3 +37,32 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;
void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
{
unsigned int ac97 = get_uint_option("audio_panel_type", 0) & 0x1;
/*
* The verbs above are for a HD Audio front panel.
* With vendor firmware, if audio front panel type is set as AC97, line out 2
* (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently.
*
* The differences are all in the "Misc" fields of configuration defaults (in byte 2)
* as shown below. ALC887 datasheet did not offer details on what those bits
* (listed as reserved in HDA spec) are, so we'll have to take their word for it.
*
* Pin | 0x19 | 0x1b
* -----+------+-----
* HDA | 1100 | 1100
* AC97 | 1001 | 0001
*/
const u32 verbs[] = {
AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99),
AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41)
};
if ((viddid == 0x10ec0887) && ac97) {
azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs));
}
}

View File

@@ -44,7 +44,7 @@ config BOARD_GOOGLE_BASEBOARD_BROX
select DRIVERS_AUDIO_SOF
select DRIVERS_GFX_GENERIC
select HAVE_SLP_S0_GATE
select MEMORY_SOLDERDOWN
select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_GREENBAYUPOC
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CRASHLOG
select SOC_INTEL_RAPTORLAKE
@@ -70,6 +70,8 @@ config BOARD_GOOGLE_LOTSO
config BOARD_GOOGLE_GREENBAYUPOC
select BOARD_GOOGLE_BASEBOARD_BROX
select CHROMEOS_WIFI_SAR if CHROMEOS
select MEMORY_SODIMM
if BOARD_GOOGLE_BROX_COMMON

View File

@@ -21,6 +21,9 @@ chip soc/intel/alderlake
# seen on J0 and Q0 SKUs
register "disable_package_c_state_demotion" = "1"
# Disable C1 state auto-demotion for all brox baseboards
register "disable_c1_state_auto_demotion" = "1"
# DPTF enable
register "dptf_enable" = "1"

View File

@@ -0,0 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c
ramstage-$(CONFIG_FW_CONFIG) += variant.c
ramstage-y += gpio.c
ramstage-y += ramstage.c

View File

@@ -0,0 +1,139 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* This header block is used to supply information to arbitrage, a
* google-internal tool. Updating it incorrectly will lead to issues,
* so please don't update it unless a change is specifically required.
* BaseID: E3110FFB1FCDA587
* Overrides: None
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */
PAD_NC(GPP_A18, NONE),
/* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */
PAD_NC(GPP_A19, NONE),
/* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */
PAD_NC(GPP_A20, NONE),
/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX
* NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */
PAD_NC(GPP_D9, NONE),
/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX
* NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */
PAD_NC(GPP_D10, NONE),
/* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */
PAD_NC(GPP_E4, NONE),
/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */
PAD_NC(GPP_E10, NONE),
/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */
PAD_NC(GPP_E12, NONE),
/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */
PAD_NC(GPP_E13, NONE),
/* GPP_E15 : SRCCLK_OE8_L ==> NC */
PAD_NC(GPP_E15, NONE),
/* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */
PAD_NC(GPP_H15, NONE),
/* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */
PAD_NC(GPP_H17, NONE),
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
PAD_NC(GPP_S0, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */
PAD_NC(GPP_D11, NONE),
/* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_F9, 0, DEEP),
/* F21 : EXT_PWR_GATE2# ==> NC */
PAD_NC(GPP_F21, NONE),
/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
PAD_NC(GPP_S0, NONE),
/* CPU PCIe VGPIO for PEG60 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
};
static const struct pad_config romstage_gpio_table[] = {
/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */
PAD_NC(GPP_E10, NONE),
/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */
PAD_NC(GPP_E12, NONE),
/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */
PAD_NC(GPP_E13, NONE),
/* GPP_E15 : SRCCLK_OE8_L ==> NC */
PAD_NC(GPP_E15, NONE),
/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
PAD_CFG_GPO(GPP_F7, 1, PLTRST),
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_F9, 1, DEEP),
/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_F17, 0, DEEP),
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
PAD_NC(GPP_S0, NONE),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

View File

@@ -7,13 +7,13 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256
0x10ec12ac, // Subsystem ID
0x10ec0236, // Codec Vendor / Device ID: Realtek ALC236
0x103C8C60, // Subsystem ID
0x00000013, // Number of jacks (NID entries)
AZALIA_RESET(0x1),
/* NID 0x01, HDA Codec Subsystem ID Verb table */
AZALIA_SUBVENDOR(0, 0x10ec12ac),
AZALIA_SUBVENDOR(0, 0x103C8C60),
/* Pin Widget Verb Table */
@@ -30,41 +30,56 @@ const u32 cim_verb_data[] = {
/* Pin widget 0x18 - NPC */
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
/* Pin widget 0x19 - MIC2 (Port-F) */
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
AZALIA_PIN_CFG(0, 0x19, 0x03A11020),
/* Pin widget 0x1A - LINE1 (Port-C) */
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
/* Pin widget 0x1B - NPC */
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
/* Pin widget 0x1D - BEEP-IN */
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
AZALIA_PIN_CFG(0, 0x1d, 0x40600001),
/* Pin widget 0x1E - NPC */
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
/* Pin widget 0x21 - HP1-OUT (Port-I) */
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
AZALIA_PIN_CFG(0, 0x21, 0x03211040),
/*
* ;Pin widget 0x19 - MIC2 (Port-F)
*/
0x01971C20,
0x01971D10,
0x01971EA1,
0x01971F03,
/*
* Pin widget 0x21 - HP1-OUT (Port-I)
*/
0x02171C40,
0x02171D10,
0x02171E21,
0x02171F03,
/*
* Widget node 0x20 - 1
* Codec hidden reset and speaker power 2W/4ohm
*/
0x0205001A,
0x0204C003,
0x02050038,
0x02047901,
/*
* Widget node 0x20 - 2
* Class D power on Reset
*/
0x0205003C,
0x02040354,
0x0205003C,
0x02040314,
/*
* Widget node 0x20 - 2
* Class D power on Reset
*/
0x0205001B,
0x02040A4B,
0x0205000B,
0x02047778,
/*
* Widget node 0x20 - 3
* Disable AGC and set AGC limit to -1.5dB
*/
0x02050016,
0x02040C50,
0x02050012,
0x0204EBC1,
0x02050046,
0x02040004,
0x05750003,
0x057409A3,
/*
* Widget node 0x20 - 4
* Set AGC Post gain +1.5dB then Enable AGC

View File

@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <soc/romstage.h>
static const struct mb_cfg ddr4_mem_config = {
.type = MEM_TYPE_DDR4,
.rcomp = {
.resistor = 100,
.targets = {50, 20, 25, 25, 25},
},
.LpDdrDqDqsReTraining = 1,
.ect = 1,
.UserBd = BOARD_TYPE_MOBILE,
.ddr_config = {
.dq_pins_interleaved = 0,
},
};
const struct mb_cfg *variant_memory_params(void)
{
return &ddr4_mem_config;
}
bool variant_is_half_populated(void)
{
return false;
}
void variant_get_spd_info(struct mem_spd *spd_info)
{
spd_info->topo = MEM_TOPO_DIMM_MODULE;
spd_info->smbus[0].addr_dimm[0] = 0x50;
spd_info->smbus[0].addr_dimm[1] = 0x51;
spd_info->smbus[1].addr_dimm[0] = 0x52;
spd_info->smbus[1].addr_dimm[1] = 0x53;
}

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@@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
DRAM Part Name ID to assign

View File

@@ -1,14 +1,202 @@
fw_config
field STORAGE 0 1
field RETIMER 0 1
option RETIMER_UNKNOWN 0
option RETIMER_BYPASS 1
end
field STORAGE 2 3
option STORAGE_UNKNOWN 0
option STORAGE_UFS 1
option STORAGE_NVME 2
option STORAGE_NVME 1
option STORAGE_UFS 2
end
field WIFI 4
option WIFI_CNVI_WIFI 0
option WIFI_BT_PCIE 1
end
field UFC 5
option UFC_NONE 0
option UFC_USB 1
end
field AUDIO 6 7
option AUDIO_UNKNOWN 0
option AUDIO_REALTEK_ALC3247 1
end
end
chip soc/intel/alderlake
register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI)
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD0""
register "device[0].type" = "panel"
# DDIB for HDMI
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port3 as usb2_port
use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
register "has_power_resource" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (DCI)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (DCI)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port3 on end
end
end
end
end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 3
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 3,
.clk_src = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
probe STORAGE STORAGE_NVME
probe STORAGE STORAGE_UNKNOWN
end
device ref pcie_rp5 on
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_03"
register "add_acpi_dma_property" = "true"
device pci 00.0 on
probe WIFI WIFI_BT_PCIE
end
end
chip soc/intel/common/block/pcie/rtd3
# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "1"
device generic 0 on end
end
probe WIFI WIFI_BT_PCIE
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end
end
probe WIFI WIFI_CNVI_WIFI
end
device ref smbus on end
end
end

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@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <device/pci_ids.h>
const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
/* All values are for performance config as per document #686872 */
{ PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
};
void variant_devtree_update(void)
{
size_t total_entries = ARRAY_SIZE(limits);
variant_update_power_limits(limits, total_entries);
}

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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <baseboard/variants.h>
#include <chip.h>
#include <fw_config.h>
#include <sar.h>
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) {
printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
config->cnvi_bt_core = true;
}
}
const char *get_wifi_sar_cbfs_filename(void)
{
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
}

View File

@@ -67,7 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG
select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
select HAVE_SLP_S0_GATE
select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION
select MEMORY_SODIMM if !(BOARD_GOOGLE_CONSTITUTION || BOARD_GOOGLE_NOVA)
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
@@ -362,6 +362,7 @@ config BOARD_GOOGLE_NOKRIS
config BOARD_GOOGLE_NOVA
select BOARD_GOOGLE_BASEBOARD_BRASK
select SOC_INTEL_RAPTORLAKE
select MEMORY_SOLDERDOWN
config BOARD_GOOGLE_OMNIGUL
select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -370,6 +371,9 @@ config BOARD_GOOGLE_OMNIGUL
select SOC_INTEL_RAPTORLAKE
select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
config BOARD_GOOGLE_ORISA
select BOARD_GOOGLE_BASEBOARD_TRULO
config BOARD_GOOGLE_OSIRIS
select BOARD_GOOGLE_BASEBOARD_BRYA
select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -446,6 +450,7 @@ config BOARD_GOOGLE_REDRIX4ES
config BOARD_GOOGLE_RIVEN
select BOARD_GOOGLE_BASEBOARD_NISSA
select INTEL_GMA_HAVE_VBT
select SOC_INTEL_TWINLAKE
config BOARD_GOOGLE_SKOLAS
@@ -643,6 +648,7 @@ config DRIVER_TPM_I2C_BUS
default 0x0 if BOARD_GOOGLE_NIVVIKS
default 0x1 if BOARD_GOOGLE_NOVA
default 0x1 if BOARD_GOOGLE_OMNIGUL
default 0x0 if BOARD_GOOGLE_ORISA
default 0x1 if BOARD_GOOGLE_OSIRIS
default 0x0 if BOARD_GOOGLE_PIRRHA
default 0x1 if BOARD_GOOGLE_PRIMUS
@@ -732,6 +738,7 @@ config MAINBOARD_PART_NUMBER
default "Nokris" if BOARD_GOOGLE_NOKRIS
default "Nova" if BOARD_GOOGLE_NOVA
default "Omnigul" if BOARD_GOOGLE_OMNIGUL
default "Orisa" if BOARD_GOOGLE_ORISA
default "Osiris" if BOARD_GOOGLE_OSIRIS
default "Pirrha" if BOARD_GOOGLE_PIRRHA
default "Primus" if BOARD_GOOGLE_PRIMUS
@@ -796,6 +803,7 @@ config VARIANT_DIR
default "nokris" if BOARD_GOOGLE_NOKRIS
default "nova" if BOARD_GOOGLE_NOVA
default "omnigul" if BOARD_GOOGLE_OMNIGUL
default "orisa" if BOARD_GOOGLE_ORISA
default "osiris" if BOARD_GOOGLE_OSIRIS
default "pirrha" if BOARD_GOOGLE_PIRRHA
default "primus" if BOARD_GOOGLE_PRIMUS

View File

@@ -184,3 +184,6 @@ config BOARD_GOOGLE_SUNDANCE
config BOARD_GOOGLE_PUJJOGA
bool "-> Pujjoga"
config BOARD_GOOGLE_ORISA
bool "-> Orisa"

View File

@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c

View File

@@ -0,0 +1,149 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* A14 : USB_OC1# ==> NC */
PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG),
/* A15 : USB_OC2# ==> NC */
PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG),
/* A18 : DDSP_HPDB ==> HDMIB_HPD */
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* A19 : DDSP_HPD1 ==> NC */
PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG),
/* A20 : DDSP_HPD2 ==> NC */
PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
/* A21 : DDPC_CTRCLK ==> NC */
PAD_NC(GPP_A21, NONE),
/* A22 : DDPC_CTRLDATA ==> NC */
PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
/* B2 : VRALERT# ==> M2_SSD_PLA_L */
PAD_NC(GPP_B2, NONE),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
/* D0 : ISH_GP0 ==> NC */
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
/* D1 : ISH_GP1 ==> NC */
PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> NC */
PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> NC */
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D8 : SRCCLKREQ3# ==> NC */
PAD_NC(GPP_D8, NONE),
/* D9 : ISH_SPI_CS# ==> NC */
PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
/* D10 : ISH_SPI_CLK ==> GPI */
PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG),
/* D17 : UART1_RXD */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* D18 : UART1_TXD */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* E14 : DDSP_HPDA ==> HDMIA_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* F11 : THC1_SPI2_CLK ==> NC */
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
/* F12 : GSXDOUT ==> NC */
PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
/* F13 : GSXDOUT ==> NC */
PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
/* F15 : GSXSRESET# ==> NC */
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
/* F16 : GSXCLK ==> NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* H12 : I2C7_SDA ==> NC */
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
/* H13 : I2C7_SCL ==> NC */
PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
/* R4 : HDA_RST# ==> NC */
PAD_NC(GPP_R4, NONE),
/* R5 : HDA_SDI1 ==> NC */
PAD_NC(GPP_R5, NONE),
/* R6 : I2S2_TXD ==> NC */
PAD_NC(GPP_R6, NONE),
/* R7 : I2S2_RXD ==> NC */
PAD_NC(GPP_R7, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F14 : GSXDIN ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_F14, 1, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* CPU PCIe VGPIO for PEG60 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
};
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

View File

@@ -1,6 +1,318 @@
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
device domain 0 on
end
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI1 | NC |
#| I2C0 | Audio |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C3 | NC |
#| I2C5 | NC |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
}"
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable Port 6
register "usb3_ports[2]" = "USB3_PORT_EMPTY " # Disable Port 2
# USB3 Port 3 for OPS interface
register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_1] = DDI_ENABLE_HPD,
[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DRAM""
register "options.tsr[1].desc" = ""Charger""
# TODO: below values are initial reference values only
## Active Policy
register "policies.active" = "{
[0] = {
.target = DPTF_CPU,
.thresholds = {
TEMP_PCT(85, 90),
TEMP_PCT(80, 80),
TEMP_PCT(75, 70),
}
}
}"
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
.max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 55000,
.max_power = 55000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 1700 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
[1] = { 80, 5800, 180, 1800, },
[2] = { 70, 5000, 145, 1450, },
[3] = { 60, 4900, 115, 1150, },
[4] = { 50, 3838, 90, 900, },
[5] = { 40, 2904, 55, 550, },
[6] = { 30, 2337, 30, 300, },
[7] = { 20, 1608, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
## Fan options
register "options.fan.fine_grained_control" = "1"
register "options.fan.step_size" = "2"
device generic 0 alias dptf_policy on end
end
end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 0,
.clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end #NVME
device ref tbt_pcie_rp1 off end
device ref tbt_pcie_rp2 off end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 off end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""10EC5650""
register "name" = ""RT58""
register "desc" = ""Realtek RT5650""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
register "property_count" = "1"
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-mode""
register "property_list[0].integer" = "2"
device i2c 1a on end
end
end # I2C0
device ref i2c1 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
device i2c 50 on end
end
end # I2C1
device ref pcie_rp7 on
chip drivers/net
register "wake" = "GPE0_DW0_07"
register "customized_leds" = "0x060f"
register "enable_aspm_l1_2" = "1"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
end # RTL8111 Ethernet NIC
device ref pcie_rp8 off end # disable SD reader
device ref gspi1 off end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A3 (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A2 (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 OPS interface TX25A""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 OPS interface TX25A""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 OPS interface TX25A""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))"
register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 OPS interface TX25A""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port4 on end
end
end
end
end
end
end

View File

@@ -4,4 +4,7 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
ramstage-y += variant.c
ramstage-y += ramstage.c

View File

@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->VccInAuxImonIccImax = 100; // 25 * 4 for ADL-N
printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax);
}

View File

@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += memory.c
romstage-y += gpio.c
ramstage-y += gpio.c

View File

@@ -0,0 +1,105 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP4X,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = {40, 30, 30, 30, 30},
},
/* DQ byte map as per doc #573387 */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 3, 0, 2, 1, 4, 6, 5, 7, },
.dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, },
},
.ddr1 = {
.dq0 = { 13, 14, 11, 12, 10, 8, 15, 9, },
.dq1 = { 5, 2, 4, 3, 1, 6, 0, 7, },
},
.ddr2 = {
.dq0 = { 2, 3, 1, 0, 7, 6, 5, 4, },
.dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, },
},
.ddr3 = {
.dq0 = { 13, 14, 12, 15, 11, 9, 8, 10, },
.dq1 = { 5, 2, 1, 4, 7, 0, 3, 6, },
},
.ddr4 = {
.dq0 = { 11, 10, 8, 9, 14, 15, 13, 12, },
.dq1 = { 3, 0, 2, 1, 5, 4, 6, 7, },
},
.ddr5 = {
.dq0 = { 11, 15, 13, 12, 10, 9, 14, 8, },
.dq1 = { 3, 0, 2, 1, 6, 7, 5, 4, },
},
.ddr6 = {
.dq0 = { 11, 13, 10, 12, 15, 9, 14, 8, },
.dq1 = { 4, 3, 5, 2, 7, 0, 1, 6, },
},
.ddr7 = {
.dq0 = { 12, 13, 15, 14, 11, 9, 10, 8, },
.dq1 = { 4, 5, 1, 2, 6, 3, 0, 7, },
},
},
/* DQS CPU<>DRAM map as per doc #573387 */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
},
.LpDdrDqDqsReTraining = 1,
.ect = 1, /* Enable Early Command Training */
};
const struct mb_cfg *variant_memory_params(void)
{
return &baseboard_memcfg;
}
int variant_memory_sku(void)
{
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_F16
* GPIO_MEM_CONFIG_1 GPP_F12
* GPIO_MEM_CONFIG_2 GPP_F13
* GPIO_MEM_CONFIG_3 GPP_F15
*/
gpio_t spd_gpios[] = {
GPP_F16,
GPP_F12,
GPP_F13,
GPP_F15,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
bool variant_is_half_populated(void)
{
/* GPIO_MEM_CH_SEL GPP_F11 */
return gpio_get(GPP_F11);
}
void variant_get_spd_info(struct mem_spd *spd_info)
{
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
spd_info->cbfs_index = variant_memory_sku();
}

View File

@@ -1,8 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE
SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL
SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE

View File

@@ -1,10 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
DRAM Part Name ID to assign
K4U6E3S4AB-MGCL 0 (0000)
H9HCNNNBKMMLXR-NEE 0 (0000)
MT53E1G32D2NP-046 WT:B 1 (0001)
K4UBE3D4AB-MGCL 1 (0001)

View File

@@ -1,4 +1,2 @@
K4U6E3S4AB-MGCL
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:B
K4UBE3D4AB-MGCL

View File

@@ -178,13 +178,6 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"

View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __VARIANT_EC_H__
#define __VARIANT_EC_H__
#include <baseboard/ec.h>
#endif

View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#endif

View File

@@ -0,0 +1 @@
DRAM Part Name ID to assign

View File

@@ -0,0 +1,6 @@
chip soc/intel/alderlake
device domain 0 on
end
end

View File

@@ -264,6 +264,9 @@ chip soc/intel/alderlake
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "50"
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_delay_ms" = "55"
register "generic.stop_off_delay_ms" = "5"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"

Binary file not shown.

View File

@@ -1,5 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
# Generated by:
# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
SPD_SOURCES = placeholder
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP

View File

@@ -1 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
K3LKLKL0EM-MGCN 2 (0010)
K3LKBKB0BM-MGCP 3 (0011)
H9JCNNNCP3MLYR-N6E 0 (0000)

View File

@@ -9,3 +9,9 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
MT62F1G32D4DR-031 WT:B
MT62F512M32D2DR-031 WT:B
H9JCNNNBK3MLYR-N6E
K3LKLKL0EM-MGCN
K3LKBKB0BM-MGCP
H9JCNNNCP3MLYR-N6E

View File

@@ -150,7 +150,7 @@ chip soc/intel/alderlake
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
register "generic.wake" = "GPE0_DW2_14"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x38 on end
end
end

View File

@@ -133,6 +133,15 @@ chip soc/intel/jasperlake
probe DB_PORTS DB_PORTS_1C_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 2.1 on
probe DB_PORTS DB_PORTS_1C_1A
probe DB_PORTS DB_PORTS_1C_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_A"
@@ -151,6 +160,15 @@ chip soc/intel/jasperlake
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.6 on end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 3.1 on
probe DB_PORTS DB_PORTS_1C_1A
probe DB_PORTS DB_PORTS_1C_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"

View File

@@ -11,7 +11,23 @@ static void ext_vr_update(void)
cfg->disable_external_bypass_vr = 1;
}
static void usb_port_update(void)
{
struct soc_intel_jasperlake_config *cfg = config_of_soc();
if (fw_config_is_provisioned() &&
fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_NONE))) {
/* Disable USB C1 port */
cfg->usb2_ports[1].enable = 0;
cfg->usb3_ports[1].enable = 0;
/* Disable USB A1 port */
cfg->usb2_ports[3].enable = 0;
cfg->usb3_ports[3].enable = 0;
}
}
void variant_devtree_update(void)
{
ext_vr_update();
usb_port_update();
}

View File

@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL
SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267
SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4CBAM-ML-A

View File

@@ -1,10 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
DRAM Part Name ID to assign
H9HCNNNBKMMLXR-NEE 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
K4U6E3S4AB-MGCL 0 (0000)
CXDB4CBAM-ML-A 1 (0001)
MT53E512M32D1NP-046 WT:B 0 (0000)
H54G46CYRBX267 0 (0000)

View File

@@ -2,3 +2,5 @@ H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
K4U6E3S4AB-MGCL
CXDB4CBAM-ML-A
MT53E512M32D1NP-046 WT:B
H54G46CYRBX267

View File

@@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <boardid.h>
#include <device/dram/ddr3.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
#include <fsp/soc_binding.h>
@@ -37,7 +38,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
mem_cfg->MemorySpdDataLen = SPD_LEN;
mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3;
/* Limit K4EBE304EB-EGCF memory to 1600MHz for stability */
if (board_id() < 6 && mainboard_get_spd_index() == 5) {

View File

@@ -2,8 +2,10 @@
#include <cbfs.h>
#include <console/console.h>
#include <device/dram/ddr3.h>
#include <gpio.h>
#include <soc/romstage.h>
#include <spd.h>
#include <string.h>
#include "../gpio.h"
@@ -18,7 +20,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
char spd_name[SPD_PART_LEN+1] = { 0 };
char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
@@ -30,21 +32,21 @@ static void mainboard_print_spd_info(uint8_t spd[])
/* Module type */
printk(BIOS_INFO, "SPD: module type is ");
switch (spd[SPD_DRAM_TYPE]) {
case SPD_DRAM_DDR3:
switch (spd[SPD_MEMORY_TYPE]) {
case SPD_MEMORY_TYPE_SDRAM_DDR3:
printk(BIOS_INFO, "DDR3\n");
break;
case SPD_DRAM_LPDDR3:
case SPD_MEMORY_TYPE_LPDDR3_INTEL:
printk(BIOS_INFO, "LPDDR3\n");
break;
default:
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
break;
}
/* Module Part Number */
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
spd_name[SPD_PART_LEN] = 0;
memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
spd_name[SPD_DDR3_PART_LEN] = 0;
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
printk(BIOS_INFO,
@@ -86,16 +88,16 @@ uintptr_t mainboard_get_spd_data(void)
die("SPD data not found.");
/* make sure we have at least one SPD in the file. */
if (spd_file_len < SPD_LEN)
if (spd_file_len < SPD_SIZE_MAX_DDR3)
die("Missing SPD data.");
/* Make sure we did not overrun the buffer */
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
spd_index = 1;
}
spd_index *= SPD_LEN;
spd_index *= SPD_SIZE_MAX_DDR3;
mainboard_print_spd_info((uint8_t *)(spd_file + spd_index));
return (uintptr_t)(spd_file + spd_index);

View File

@@ -3,18 +3,10 @@
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
#define SPD_MANU_OFF 148
int mainboard_get_spd_index(void);
uintptr_t mainboard_get_spd_data(void);

View File

@@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <baseboard/variant.h>
#include <device/dram/ddr3.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/romstage.h>
@@ -30,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
mem_cfg->MemorySpdDataLen = SPD_LEN;
mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3;
mem_cfg->DqPinsInterleaved = FALSE;
spd_memory_init_params(mupd, spd_idx);

View File

@@ -2,8 +2,10 @@
#include <cbfs.h>
#include <console/console.h>
#include <device/dram/ddr3.h>
#include <gpio.h>
#include <soc/romstage.h>
#include <spd.h>
#include <string.h>
#include <baseboard/variant.h>
@@ -19,7 +21,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
char spd_name[SPD_PART_LEN+1] = { 0 };
char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
@@ -31,21 +33,21 @@ static void mainboard_print_spd_info(uint8_t spd[])
/* Module type */
printk(BIOS_INFO, "SPD: module type is ");
switch (spd[SPD_DRAM_TYPE]) {
case SPD_DRAM_DDR3:
switch (spd[SPD_MEMORY_TYPE]) {
case SPD_MEMORY_TYPE_SDRAM_DDR3:
printk(BIOS_INFO, "DDR3\n");
break;
case SPD_DRAM_LPDDR3:
case SPD_MEMORY_TYPE_LPDDR3_INTEL:
printk(BIOS_INFO, "LPDDR3\n");
break;
default:
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
break;
}
/* Module Part Number */
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
spd_name[SPD_PART_LEN] = 0;
memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
spd_name[SPD_DDR3_PART_LEN] = 0;
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
printk(BIOS_INFO,
@@ -83,16 +85,16 @@ void spd_memory_init_params(FSPM_UPD *mupd, int spd_index)
die("SPD data not found.");
/* make sure we have at least one SPD in the file. */
if (spd_file_len < SPD_LEN)
if (spd_file_len < SPD_SIZE_MAX_DDR3)
die("Missing SPD data.");
/* Make sure we did not overrun the buffer */
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
spd_index = 1;
}
const size_t spd_offset = spd_index * SPD_LEN;
const size_t spd_offset = spd_index * SPD_SIZE_MAX_DDR3;
/* Make sure a valid SPD was found */
if (spd_file[spd_offset] == 0)
die("Invalid SPD data.");

View File

@@ -3,17 +3,9 @@
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#define SPD_LEN 256
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
#define SPD_MANU_OFF 148
#endif

View File

@@ -2,6 +2,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <device/dram/ddr3.h>
#include <soc/gpio.h>
#include <soc/mrc_wrapper.h>
#include <soc/romstage.h>
@@ -38,7 +39,7 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
if (dual_channel_config & (1 << ram_id))
*dual = 1;
return &spd_file_content[SPD_SIZE * ram_id];
return &spd_file_content[SPD_SIZE_MAX_DDR3 * ram_id];
}
void mainboard_fill_mrc_params(struct mrc_params *mp)
@@ -52,7 +53,7 @@ void mainboard_fill_mrc_params(struct mrc_params *mp)
if (!spd_file)
die("SPD data not found.");
spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE_MAX_DDR3,
&dual_channel);
mp->mainboard.dram_type = DRAM_DDR3L;

View File

@@ -18,7 +18,6 @@
static const uint32_t dual_channel_config =
(1 << 1) | (1 << 3) | (1 << 5);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -24,7 +24,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -18,7 +18,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -24,7 +24,6 @@ static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
(1 << 4) | (1 << 6) | (1 << 7);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -18,7 +18,6 @@
static const uint32_t dual_channel_config =
(1 << 6) | (1 << 7);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -17,7 +17,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

View File

@@ -20,7 +20,6 @@
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58

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