Remove ESPI config and enable LPC decodes for EC command and debug

Change-Id: I301829fc67fc1b255cf1a6f468a5433b64e03828

.gitmodules

@@ -1,62 +1,62 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

Documentation/community/index.md

@@ -1,7 +0,0 @@
-# Community
-
-* [Code of Conduct](code_of_conduct.md)
-* [Language style](language_style.md)
-* [Community forums](forums.md)
-* [Project services](services.md)
-* [coreboot at conferences](conferences.md)

Documentation/community/services.md

@@ -1,6 +1,6 @@
 # Accounts on coreboot.org
 
-There are a number of places where you can benefit from creating an account
+There are a number of places where you can benefit from creaating an account
 in our community. Since there is no single sign-on system in place (at this
 time), they come with their own setup routines.
 

Documentation/contributing/gsoc.md

@@ -1,249 +0,0 @@
-# Google Summer of Code
-
-
-## Contacts
-
-If you are interested in participating in GSoC as a contributor or mentor,
-please have a look at our [community forums] and reach out to us. Working closely
-with the community is highly encouraged, as we've seen that our most successful
-contributors are generally very involved.
-
-Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
-2022. Please feel free to reach out to them directly if you have any questions.
-
-
-## Why work on coreboot for GSoC?
-
-  * coreboot offers you the opportunity to work with various architectures
-    right on the iron. coreboot supports both current and older silicon for a
-    wide variety of chips and technologies.
-
-  * coreboot has a worldwide developer and user base.
-
-  * We are a very passionate team, so you will interact directly with the
-    project initiators and project leaders.
-
-  * We have a large, helpful community. coreboot has some extremely talented
-    and helpful experts in firmware involved in the project. They are ready to
-    assist and mentor contributors participating in GSoC.
-
-  * One of the last areas where open source software is not common is firmware.
-    Running proprietary firmware can have severe effects on user's freedom and
-    security. coreboot has a mission to change that by providing a common
-    framework for initial hardware initialization and you can help us succeed.
-
-
-## Contributor requirements & commitments
-
-Google Summer of Code is a significant time commitment for you. Medium-sized
-projects are estimated to take 175 hours, while large-sized projects are
-estimated to take 350 hours. Depending on the project size, this means we
-expect you to work roughly half-time or full-time on your project during the
-three months of coding. We expect to be able to see this level of effort in the
-results.
-
-The standard program duration is 12 weeks and in consultation with the mentor
-it can be extended up to 22 weeks. Please keep in mind that the actual number
-of hours you spend on the project highly depends on your skills and previous
-experience.
-
-Make sure that your schedule (exams, courses, day job) gives you a sufficient
-amount of spare time. If this is not the case, then you should not apply.
-
-
-### Before applying
-
-  * Join the [mailing list] and our other [community forums]. Introduce yourself
-    and mention that you are a prospective GSoC contributor. Ask questions and
-    discuss the project that you are considering. Community involvement is a
-    key component of coreboot development.
-
-  * You accept our [Code of Conduct] and [Language style].
-
-  * Demonstrate that you can work with the coreboot codebase.
-
-    * Look over some of the development processes guidelines: [Getting started],
-      [Tutorial], [Flashing firmware tutorial] and [Coding style].
-
-    * Download, build and boot coreboot in QEMU or on real hardware. Please email
-      your serial output results to the [mailing list].
-
-    * Look through some patches on Gerrit to get an understanding of the review
-      process and common issues.
-
-    * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check Easy projects or ask for simple tasks on the [mailing list] or on our
-      other [community forums] if you need ideas.
-
-
-### During the program
-
-  * To pass and to be paid by Google requires that you meet certain milestones.
-
-    * First, you must be in good standing with the community before the official
-      start of the program. We expect you to post some design emails to the
-      [mailing list], and get feedback on them, both before applying, and during
-      the "community bonding period" between acceptance and official start.
-
-    * You must have made progress and committed significant code before the
-      mid-term point and by the final.
-
-    * We require that accepted contributors to maintain a blog, where you are
-      expected to write about your project *WEEKLY*. This is a way to measure
-      progress and for the community at large to be able to help you. GSoC is
-      *NOT* a private contract between your mentor and you.
-
-  * You must be active in the community on IRC and the [mailing list].
-
-  * You are expected to work on development publicly, and to push commits to the
-    project on a regular basis. Depending on the project and what your mentor
-    agrees to, these can be published directly to the project or to a public
-    repository such as Gitlab or Github. If you are not publishing directly to
-    the project codebase, be aware that we do not want large dumps of code that
-    need to be rushed to meet the mid-term and final goals.
-
-We don't expect our contributors to be experts in our problem domain, but we
-don't want you to fail because some basic misunderstanding was in your way of
-completing the task.
-
-
-## Projects
-
-There are many development tasks available in coreboot. We prepared some ideas
-for Summer of Code projects. These are projects that we think can be managed in
-the timeline of GSoC, and they cover areas where coreboot is trying to reach
-new users and new use cases.
-
-Of course your application does not have to be based on any of the ideas listed.
-It is entirely possible that you have a great idea that we just didn't think of
-yet. Please let us know!
-
-The blog posts related to previous GSoC projects might give some insights to
-what it is like to be a coreboot GSoC contributor.
-
-
-## coreboot Summer of Code Application
-
-coreboot welcomes contributors from all backgrounds and levels of experience.
-
-Your application should include a complete project proposal. You should
-document that you have the knowledge and the ability to complete your proposed
-project. This may require a little research and understanding of coreboot prior
-to sending your application. The community and coreboot project mentors are your
-best resource in fleshing out your project ideas and helping with a project
-timeline. We recommend that you get feedback and recommendations on your
-proposal before the application deadline.
-
-Please complete the standard GSoC application and project proposal. Provide the
-following information as part of your application. Make sure to provide multiple
-ways of communicating in case your equipment (such as a laptop) is lost,
-damaged, or stolen, or in case of a natural disaster that disrupts internet
-service. You risk automatically failing if your mentor cannot contact you and if
-you cannot provide updates according to GSoC deadlines.
-
-**Personal Information**
-
-  * Name
-
-  * Email and contact options (IRC, Matrix, …)
-
-  * Phone number (optional, but recommended)
-
-  * Timezone, Usual working hours (UTC)
-
-  * School / University, Degree Program, expected graduation date
-
-  * Short bio / Overview of your background
-
-  * What are your other time commitments? Do you have a job, classes, vacations?
-    When and how long?
-
-**Software experience**
-
-If applicable, please provide the following information:
-
-  * Portfolio, Website, blog, microblog, Github, Gitlab, ...
-
-  * Links to one or more patches submitted
-
-  * Links to posts on the [mailing list] with the serial output of your build.
-
-  * Please comment on your software and firmware experience.
-
-  * Have you contributed to an open source project? Which one? What was your
-    experience?
-
-  * What was your experience while building and running coreboot? Did you have
-    problems?
-
-**Your project**
-
-  * Provide an overview of your project (in your own words).
-
-  * Provide a breakdown of your project in small specific weekly goals. Think
-    about the potential timeline.
-
-  * How will you accomplish this goal? What is your working style?
-
-  * Explain what risks or potential problems your project might experience.
-
-  * What would you expect as a minimum level of success?
-
-  * Do you have a stretch goal?
-
-**Other**
-
-  * Resume (optional)
-
-
-### Advice on how to apply
-
-  * [GSoC Contributor Guide]
-
-  * The Drupal project has a great page on how to write an GSoC application.
-
-  * Secrets for GSoC success: [2]
-
-
-## Mentors
-
-Each accepted project will have at least one mentor. We will match mentors and
-contributors based on the project and experience level. If possible, we also
-will try to match their time zones.
-
-Mentors are expected to stay in frequent contact with the contributor and
-provide guidance such as code reviews, pointers to useful documentation, etc.
-This should generally be a time commitment of several hours per week.
-
-Some projects might have more than one mentor, who can serve as a backup. They
-are expected to coordinate with each other and a contributor on a regular basis,
-and keep track of the contributor process. They should be able to take over
-mentoring duty if one of the mentors is unavailable (vacations, sickness,
-emergencies).
-
-
-### Volunteering to be a mentor
-
-If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide].
-This will give you a better idea of expectations, and where to go for help.
-After that, contact Org Admins (see coreboot contacts section above).
-
-The following coreboot developers have volunteered to be GSoC 2022 mentors.
-Please stop by in our community forums and say hi to them and ask them
-questions.
-
-  * Tim Wawrzynczak
-  * Raul Rangel
-  * Ron Minnich
-
-
-[community forums]: ../community/forums.md
-[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
-[Getting started]: ../getting_started/index.md
-[Tutorial]: ../tutorial/index.md
-[Flashing firmware tutorial]: ../flash_tutorial/index.md
-[Coding style]: coding_style.md
-[Code of Conduct]: ../community/code_of_conduct.md
-[Language style]: ../community/language_style.md
-[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
-[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor

Documentation/contributing/index.md

@@ -1,6 +0,0 @@
-# Contributing
-
-* [Coding Style](coding_style.md)
-* [Project Ideas](project_ideas.md)
-* [Documentation Ideas](documentation_ideas.md)
-* [Google Summer of Code](gsoc.md)

Documentation/index.md

@@ -168,8 +168,14 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Tutorial](tutorial/index.md)
-* [Contributing](contributing/index.md)
+* [Coding Style](contributing/coding_style.md)
-* [Community](community/index.md)
+* [Project Ideas](contributing/project_ideas.md)
+* [Documentation Ideas](contributing/documentation_ideas.md)
+* [Code of Conduct](community/code_of_conduct.md)
+* [Language style](community/language_style.md)
+* [Community forums](community/forums.md)
+* [Project services](community/services.md)
+* [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
 * [Technotes](technotes/index.md)

Documentation/releases/coreboot-4.16-relnotes.md

@@ -1,340 +1,27 @@
-coreboot 4.16
+Upcoming release - coreboot 4.16
-========================================================================
+================================
 
-The 4.16 release was done on February 25th, 2022.
+The 4.16 release is planned for February, 2022.
 
-Since 4.15 there have been more than 1770 new commits by more than 170
+We are increasing the frequency of releases in order to enable others to release quarterly on
-developers.  Of these, more than 35 contributed to coreboot for the
+a fresher version of coreboot.
-first time.
 
-Welcome to the project!
+Update this document with changes that should be in the release notes.
 
-Thank you to all the developers who continue to make coreboot the
+* Please use Markdown.
-great open source firmware project that it is.
+* See the past few release notes for the general format.
-
+* The chip and board additions and removals will be updated right
-New mainboards:
+  before the release, so those do not need to be added.
----------------
-* Acer Aspire VN7-572G
-* AMD Chausie
-* ASROCK H77 Pro4-M
-* ASUS P8Z77-M
-* Emulation QEMU power9
-* Google Agah
-* Google Anahera4ES
-* Google Banshee
-* Google Beadrix
-* Google Brya4ES
-* Google Crota
-* Google Dojo
-* Google Gimble4ES
-* Google Herobrine_Rev0
-* Google Kingler
-* Google Kinox
-* Google Krabby
-* Google Moli
-* Google Nereid
-* Google Nivviks
-* Google Primus4ES
-* Google Redrix4ES
-* Google Skyrim
-* Google Taeko4ES
-* Google Taniks
-* Google Vell
-* Google Volmar
-* Intel Alderlake-N RVP
-* Prodrive Atlas
-* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
-* System76 gaze16 3050
-* System76 gaze16 3060
-* System76 gaze16 3060-b
-
-Removed mainboards:
--------------------
-* Google ->  Corsola
-* Google ->  Nasher
-* Google ->  Stryke
-
-Added processors:
------------------
-* src/cpu/power9
-* src/soc/amd/sabrina
-
-Submodule Updates
------------------
-* /3rdparty/amd_blobs (6 commits)
-* /3rdparty/arm-trusted-firmware (965 commits)
-* /3rdparty/blobs (30 commits)
-* /3rdparty/chromeec (2212 commits)
-* /3rdparty/intel-microcode (1 commits)
-* /3rdparty/qc_blobs (13 commits)
-* /3rdparty/vboot (44 commits)
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the v4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the v4
-allocator.
-
-Plans for Code Deprecation
---------------------------
-As of release 4.18 (November 2022) we plan to deprecate LEGACY_SMP_INIT.
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-A few things are lacking in PARALLEL_MP init:
-- Support for !CONFIG_SMP on single core systems. It's likely easy to
-  extend PARALLEL_MP or write some code that just does CPU detection on
-  the BSP CPU.
-- Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC
-  showed that it's not that hard to do with PARALLEL_MP
-  https://review.coreboot.org/c/coreboot/+/58700
-
-No platforms in the tree have any hardware limitations that would block
-migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
 
 Significant changes
 -------------------
-This is, of course, not a complete list of all changes in the 4.16
+
-coreboot release, but a sampling of some of the more interesting and
+### Add significant changes here
-significant changes.
 
 ### Option to disable Intel Management Engine
-Disable the Intel (Converged Security) Management Engine ((CS)ME) via
+Disable the Intel (Converged Security) Management Engine ((CS)ME) via HECI based
-HECI based on Intel Core processors from Skylake to Alder Lake. State is
+on Intel Core processors from Skylake to Alder Lake. State is set based on a
-set based on a CMOS value of `me_state`. A value of `0` will result in a
+CMOS value of `me_state`. A value of `0` will result in a (CS)ME state of `0`
-(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
+(working) and value of `1` will result in a (CS)ME state of `3` (disabled). For
-state of `3` (disabled). For an example CMOS layout and more info, see
+an example CMOS layout and more info, see
 [cse.c](../../src/soc/intel/common/block/cse/cse.c).
-
-
-### Add [AMD] apcb_v3_edit tool
-apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
-up to 16 SPDs into an existing APCB. The APCB must have a magic number
-at the top of each SPD slot.
-
-
-### Allow enable/disable ME via CMOS
-Add .enable method that will set the CSME state. The state is based on
-the new CMOS option me_state, with values of 0 and 1. The method is very
-stable when switching between different firmware platforms.
-
-This method should not be used in combination with USE_ME_CLEANER.
-
-State 1 will result in:
-ME: Current Working State   : 4
-ME: Current Operation State : 1
-ME: Current Operation Mode  : 3
-ME: Error Code              : 2
-
-State 0 will result in:
-ME: Current Working State   : 5
-ME: Current Operation State : 1
-ME: Current Operation Mode  : 0
-ME: Error Code              : 0
-
-
-### Move LAPIC configuration to MP init
-Implementation for setup_lapic() did two things -- call enable_lapic()
-and virtual_wire_mode_init().
-
-In PARALLEL_MP case enable_lapic() was redundant as it was already
-executed prior to initialize_cpu() call.  For the !PARALLEL_MP case
-enable_lapic() is added to AP CPUs.
-
-
-### Add ANSI escape sequences for highlighting
-Add ANSI escape sequences to highlight a log line based on its loglevel
-to the output of "interactive" consoles that are meant to be displayed
-on a terminal (e.g. UART). This should help make errors and warnings
-stand out better among the usual spew of debug messages. For users whose
-terminal or use case doesn't support these sequences for some reason (or
-who simply don't like them), they can be disabled with a Kconfig.
-
-While ANSI escape sequences can be used to add color, minicom (the
-presumably most common terminal emulator for UART endpoints?) doesn't
-support color output unless explicitly enabled (via -c command line
-flag), and other terminal emulators may have similar restrictions, so in
-an effort to make this as widely useful by default as possible I have
-chosen not to use color codes and implement this highlighting via
-bolding, underlining and inverting alone (which seem to go through in
-all cases). If desired, support for separate color highlighting could be
-added via Kconfig later.
-
-
-### Add cbmem_dump_console
-This function is similar to cbmem_dump_console_to_uart except it uses
-the normally configured consoles. A console_paused flag was added to
-prevent the cbmem console from writing to itself.
-
-
-### Add coreboot-configurator
-A simple GUI to change CMOS settings in coreboot's CBFS, via the
-nvramtool utility.  Testing on Debian, Ubuntu and Manjaro with coreboot
-4.14+, but should work with any distribution or coreboot release that
-has an option table. For more info, please check the
-[README](https://web.archive.org/web/20220225194308/https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/coreboot-configurator/README.md).
-
-
-### Update live ISO configs to NixOS 21.11
-Update configs so that they work with NixOS 21.11. Drop `iasl` package
-since it was replaced with `acpica-tools`.
-
-
-### Move to U-Boot v2021.10
-Move to building the latest U-Boot.
-
-
-### Support systems with >128 cores
-Each time the spinlock is acquired a byte is decreased and then the
-sign of the byte is checked. If there are more than 128 cores the sign
-check will overflow. An easy fix is to increase the word size of the
-spinlock acquiring and releasing.
-
-
-### Add [samsung] sx9360 [proximity sensor] driver
-Add driver for setting up Semtech sx9360 SAR sensor.
-The driver is based on sx9310.c. The core of the driver is the same, but
-the bindings are slightly different.
-
-Registers are documented [in the kernel tree:](https://web.archive.org/web/20220225182803/https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/)
-Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
-
-
-### Add driver for Genesys Logic [SD Controller] GL9750
-The device is a PCIe Gen1 to SD 3.0 card reader controller to be
-used in the Chromebook. The datasheet name is GL9750S and the revision
-is 01.
-
-The patch disables ASPM L0s.
-
-
-### Add support for Realtek RT8125
-The Realtek RT8168 and RT8125 have a similar programming interface,
-therefore add the PCI device ID for the RT8125 into driver for support.
-
-
-### Add Fibocom 5G WWAN ACPI support
-Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
-PXSX._RST is invoked on driver removal.
-
-build dependency:
-  soc/intel/common/block/pcie/rtd3
-
-This driver will use the rtd3 methods for the same parent in the device
-tree. The rtd3 chip needs to be added on the same root port in the
-devicetree separately.
-
-
-### Fix bug in vr_config
-The `cpu_get_power_max()` function returns the TDP in milliwatts, but
-the vr_config code interprets the value in watts. Divide the value by
-1000 to fix this.
-
-This also fixes an integer overflow when `cpu_get_power_max()` returns
-a value greater than 65535 (UINT16_MAX).
-
-
-### Make mixed topology work
-When using a mixed memory topology with DDR4, it's not possible to boot
-when no DIMMs are installed, even though memory-down is available. This
-happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
-available. Relax the length check when no DIMMs are present to overcome
-this problem.
-
-
-### Add FSP 2.3 support
-FSP 2.3 specification introduces following changes:
-
-1. FSP_INFO_HEADER changes
-   Updated SpecVersion from 0x22 to 0x23
-   Updated HeaderRevision from 5 to 6
-   Added ExtendedImageRevision
-   FSP_INFO_HEADER length changed to 0x50
-
-2. Added FSP_NON_VOLATILE_STORAGE_HOB2
-
-Following changes are implemented in the patch to support FSP 2.3:
-
-- Add Kconfig option
-- Update FSP build binary version info based on ExtendedImageRevision
-  field in header
-- New NV HOB related changes will be pushed as part of another patch
-
-
-### Join hash calculation for verification and measurement
-This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
-is enabled from the lookup step into the code where a file is actually
-loaded or mapped from flash. This has the advantage that CBFS routines
-which just look up a file to inspect its metadata (e.g. cbfs_get_size())
-do not cause the file to be measured twice. It also removes the existing
-inefficiency that files are loaded twice when measurement is enabled
-(once to measure and then again when they are used). When CBFS
-verification is enabled and uses the same hash algorithm as the TPM, we
-are even able to only hash the file a single time and use the result for
-both purposes.
-
-
-### Skip FSP Notify APIs
-Alder Lake SoC deselects Kconfigs as below:
-- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
-- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
-to skip FSP notify APIs (Ready to boot and End of Firmware) and make
-use of native coreboot driver to perform SoC recommended operations
-prior booting to payload/OS.
-
-Additionally, created a helper function `heci_finalize()` to keep HECI
-related operations separated for easy guarding again config.
-
-TODO: coreboot native implementation to skip FSP notify phase API (post
-pci enumeration) is still WIP.
-
-
-### Add support for PCIe Resizable BARs
-Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
-indicates support for "Resizable BARs" via a PCIe extended capability.
-
-When support this capability is indicated by the device, the size of
-each BAR is determined in a different way than the normal "moving
-bits" method. Instead, a pair of capability and control registers is
-allocated in config space for each BAR, which can be used to both
-indicate the different sizes the device is capable of supporting for
-the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
-to also inform the device of the size that the allocator actually
-reserved for the MMIO range.
-
-This patch adds a Kconfig for a mainboard to select if it knows that it
-will have a device that requires this support during PCI enumeration.
-If so, there is a corresponding Kconfig to indicate the maximum number
-of bits of address space to hand out to devices this way (again, limited
-by what devices can support and each individual system may want to
-support, but just like above, this number can range from 20 to 63) If
-the device can support more bits than this Kconfig, the resource request
-is truncated to the number indicated by this Kconfig.

Documentation/releases/index.md

@@ -16,7 +16,6 @@ Release notes for previous releases
 * [4.13 - November 2020](coreboot-4.13-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)
-* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -33,4 +32,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.17 - May 2022](coreboot-4.17-relnotes.md)
+* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -1,7 +1,6 @@
 # vboot-enabled devices
 
 ## AMD
-- Chausie
 - Majolica
 
 ## Clevo
@@ -30,37 +29,9 @@
 - Panther (ASUS Chromebox CN60)
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
-- Agah
-- Anahera
-- Anahera4ES
-- Brask
-- Brya 0
-- Brya4ES
-- Felwinter
-- Gimble
-- Gimble4ES
-- Kano
-- Nivviks
-- Nereid
-- Primus
-- Primus4ES
-- Redrix
-- Redrix4ES
-- Taeko
-- Taeko4ES
-- Taniks
-- Vell
-- Volmar
-- Banshee
-- Crota
-- Moli
-- Kinox
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
-- Dojo
 - Tomato
-- Kingler
-- Krabby
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -99,31 +70,31 @@
 - Nipperkin
 - Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
-- Ambassador
-- Dooly
 - Dratini (HP Pro c640 Chromebook)
 - Duffy Legacy (32MB)
 - Duffy (ASUS Chromebox 4)
 - Faffy (ASUS Fanless Chromebox)
-- Genesis
 - Hatch
-- Helios (ASUS Chromebook Flip C436FA)
-- Helios_Diskswap
 - Jinlon (HP Elite c1030 Chromebook)
 - Kaisa Legacy (32MB)
 - Kaisa (Acer Chromebox CXI4)
-- Kindred (Acer Chromebook 712)
 - Kohaku (Samsung Galaxy Chromebook)
-- Moonbuggy
+- Kindred (Acer Chromebook 712)
+- Helios (ASUS Chromebook Flip C436FA)
 - Mushu
+- Palkia
 - Nightfury (Samsung Galaxy Chromebook 2)
 - Noibat (HP Chromebox G3)
-- Palkia
 - Puff
-- Scout
+- Helios_Diskswap
+- Stryke
 - Wyvern (CTL Chromebox CBx2)
+- Dooly
+- Ambassador
+- Genesis
+- Scout
+- Moonbuggy
 - Herobrine
-- Herobrine_Rev0
 - Senor
 - Piglin
 - Hoglin
@@ -194,6 +165,7 @@
 - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
+- Nasher
 - Coral
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
@@ -243,8 +215,6 @@
 - Alderlake-P RVP with Microchip EC
 - Alderlake-M RVP
 - Alderlake-M RVP with Chrome EC
-- Alderlake-N RVP
-- Alderlake-N RVP with Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11

MAINTAINERS

@@ -141,7 +141,6 @@ AMD family 17h and 19h reference boards
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/mainboard/amd/chausie/
 F:	src/mainboard/amd/majolica/
@@ -614,7 +613,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
@@ -624,7 +622,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/common/
 
@@ -633,7 +630,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
@@ -643,7 +639,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/sabrina/
 F:	src/vendorcode/amd/fsp/sabrina/

payloads/external/Makefile.inc

@@ -136,29 +136,22 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
 
 # Tianocore
 
-$(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
+payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/tianocore all \
 		HOSTCC="$(HOSTCC)" \
 		CC="$(HOSTCC)" \
-		CONFIG_TIANOCORE_REPOSITORY=$(CONFIG_TIANOCORE_REPOSITORY) \
+		CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
-		CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \
+		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
+		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
+		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
-		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
+		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
-		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
-		CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \
 		CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
-		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-		CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
-		CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
+		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
-		CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
-		CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
-		CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
-		CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
 		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
-		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -168,7 +161,6 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 		OBJCOPY_arm=$(OBJCOPY_arm) \
 		OBJCOPY_arm64=$(OBJCOPY_arm64) \
 		MFLAGS= MAKEFLAGS=
-	mv payloads/external/tianocore/output/UEFIPAYLOAD.fd $@
 
 # FILO
 

payloads/external/tianocore/Kconfig

@@ -2,7 +2,7 @@ if PAYLOAD_TIANOCORE
 
 config PAYLOAD_FILE
 	string "Tianocore binary"
-	default "$(obj)/UEFIPAYLOAD.fd"
+	default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd"
 	help
 	  The result of a UefiPayloadPkg build
 
@@ -35,30 +35,13 @@ config TIANOCORE_COREBOOTPAYLOAD
 	  Select this option to build using MrChromebox's older (now deprecated)
 	  CorebootPayloadPkg-based Tianocore branch
 
-config TIANOCORE_CUSTOM
-	bool "Custom"
-	help
-	  Specify your own edk2 repository and branch to use.
-
 endchoice
 
-config TIANOCORE_REPOSITORY
+config TIANOCORE_REVISION_ID
-	string "URL to git repository for edk2"
-	default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM
-	default "https://github.com/mrchromebox/edk2" if TIANOCORE_UEFIPAYLOAD || TIANOCORE_COREBOOTPAYLOAD
-	help
-	  coreboot supports an array of build options which can be found below. These options
-	  will only have an effect if the relevant options exist in the target repository.
-
-config TIANOCORE_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD
-	default "origin/master" if TIANOCORE_UPSTREAM
-	default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD
 	help
-	  The commit's SHA-1 or branch name of the revision to use. This must exist in
+	   The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master"
-	  TIANOCORE_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
+	   for master branch of Tianocore release on github.
-	  "origin/uefipayload_202202"
 
 choice
 	prompt "Tianocore build"
@@ -81,33 +64,32 @@ endchoice
 
 if TIANOCORE_UEFIPAYLOAD
 
-config TIANOCORE_ABOVE_4G_MEMORY
+config TIANOCORE_CBMEM_LOGGING
-	bool "Enable above 4G memory"
+	bool "Enable Tianocore logging to CBMEM"
-	default n
 	help
-	  Select this option to enable Above 4G Decode. This will allow the
+	  Select this option if you want to enable Tianocore logging to CBMEM.
-	  payload to use all of the memory, rather than an maximum of 4G.
+	  You may want to increase the default cbmem buffer size when selecting
+	  this option, especially if using a debug (vs release) build.
+	  Selecting this option will increase the payload size in CBFS by ~220KB.
 
-	  Disabling memory above 4G is useful for bootloaders that are not
+config TIANOCORE_BOOTSPLASH_IMAGE
-	  fully 64-bit aware such as Qubes R4.0.4 bootloader.
+	bool "Use a custom bootsplash image"
-
-
-config TIANOCORE_BOOTSPLASH_FILE
-	string "Tianocore Bootsplash path and filename"
-	default "bootsplash.bmp"
 	help
 	  Select this option if you have a bootsplash image that you would
 	  like to be used. If this option is not selected, the default
 	  coreboot logo (European Brown Hare) will used.
 
+config TIANOCORE_BOOTSPLASH_FILE
+	string "Tianocore Bootsplash path and filename"
+	depends on TIANOCORE_BOOTSPLASH_IMAGE
+	default "bootsplash.bmp"
+	help
 	  The path and filename of the file to use as graphical bootsplash
-	  image. The file must be an uncompressed BMP, in BMP 3 format.
+	  image. The file must be an uncompressed BMP.
-
-	  Linux can create these with the below command:
-	      `convert splosh.bmp BMP3:splash.bmp`
 
 	  This image will also be used as the BGRT boot image, which may
-	  persist through your OS boot process.
+	  persist through your OS boot process, and will be displayed
+	  vertically centered 38.2% from the top of the display.
 
 	  See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and
 	  Microsoft's documentation on BGRT positioning:
@@ -119,61 +101,16 @@ config TIANOCORE_BOOTSPLASH_FILE
 	  If an absolute path is not given, the path will assumed to be
 	  relative to the coreboot root directory.
 
-config TIANOCORE_BOOT_MANAGER_ESCAPE
+config TIANOCORE_ABOVE_4G_MEMORY
-	bool "Use Escape key for Boot Manager"
+	bool "Enable above 4G memory"
 	default n
 	help
-	  Use Escape as the hot-key to access the Boot Manager. This replaces
+	  Select this option to enable Above 4G Decode. This will allow the
-	  the default key of F2.
+	  payload to use all of the memory, rather than an maximum of 4G.
 
-config TIANOCORE_BOOT_TIMEOUT
+	  Disabling this option, which will reserve memory above 4G, is
-	int
+	  useful for bootloaders that are not fully 64-bit aware such as
-	default 2
+	  Qubes R4.0.4 bootloader.
-	help
-	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
-	  For boards with an internal display, the default value of 2s is generally sufficient.
-	  For boards with an external display, a value of 5s is generally sufficient.
-
-config TIANOCORE_CBMEM_LOGGING
-	bool "Enable Tianocore logging to CBMEM"
-	help
-	  Select this option if you want to enable Tianocore logging to CBMEM.
-	  You may want to increase the default cbmem buffer size when selecting
-	  this option, especially if using a debug (vs release) build.
-	  Selecting this option will increase the payload size in CBFS by 0x10000.
-
-config TIANOCORE_FOLLOW_BGRT_SPEC
-	bool "Center logo 38.2% from the top of screen"
-	default n
-	help
-	  Follow the BGRT Specification implemented by Microsoft and
-	  the Boot Logo 38.2% will be vertically centered 38.2% from
-	  the top of the display.
-
-config TIANOCORE_HAVE_EFI_SHELL
-	bool "Include EFI Shell"
-	default y
-	help
-	  Include the EFI shell Binary
-
-config TIANOCORE_PRIORITIZE_INTERNAL
-	bool "Prioritize internal boot devices"
-	default y
-	help
-	  Prioritize internal boot devices over external devices
-
-config TIANOCORE_PS2_SUPPORT
-	bool "Support PS/2 Keyboards"
-	default y
-	help
-	  Include support for PS/2 keyboards
-
-config TIANOCORE_SD_MMC_TIMEOUT
-	int "Timeout in μs for initializing SD Card reader"
-	default 1000
-	help
-	  The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
-	  Most only require 1000μs, but certain readers can take 1000000μs.
 
 endif
 
@@ -186,4 +123,12 @@ config TIANOCORE_USE_8254_TIMER
 
 endif
 
+config TIANOCORE_BOOT_TIMEOUT
+	int
+	default 2
+	help
+	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
+	  For boards with an internal display, the default value of 2s is generally sufficient.
+	  For boards without an internal display, a value of 5s is generally sufficient.
+
 endif

payloads/external/tianocore/Makefile

@@ -3,112 +3,84 @@
 # force the shell to bash - the edksetup.sh script doesn't work with dash
 export SHELL := env bash
 
-project_name = Tianocore
+project_name=Tianocore
-project_dir = $(CURDIR)/$(word 3,$(subst /, ,$(CONFIG_TIANOCORE_REPOSITORY)))
+project_dir=$(CURDIR)/tianocore
+project_git_repo=https://github.com/mrchromebox/edk2
+project_git_branch=uefipayload_202107
+upstream_git_repo=https://github.com/tianocore/edk2
+
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
 
-BUILD_STR = -a IA32 -a X64 -t COREBOOT
 ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
-BUILD_STR += -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+project_git_branch=coreboot_fb
+bootloader=CorebootPayloadPkg
 else
-BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
+bootloader=UefiPayloadPkg
-endif
-BUILD_STR += -D BOOTLOADER=COREBOOT -q
-
-#
-# EDK II has the following build options relevant to coreboot:
-#
-#
-# OPTION			= DEFAULT_VALUE
-#
-# ABOVE_4G_MEMORY		= TRUE
-ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
-BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
-endif
-# BOOTSPLASH_IMAGE		= FALSE
-ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),)
-BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
-endif
-# BOOT_MANAGER_ESCAPE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y)
-BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE
-endif
-# BUILD_TARGETS			= DEBUG
-ifeq ($(CONFIG_TIANOCORE_RELEASE),y)
-BUILD_STR += -b RELEASE
-endif
-# FOLLOW_BGRT_SPEC		= FALSE
-ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
-BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
-endif
-# PRIORITIZE_INTERNAL		= FALSE
-ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
-BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
-endif
-# PS2_KEYBOARD_ENABLE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
-BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
-endif
-# PLATFORM_BOOT_TIMEOUT		= 3
-ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
-BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
-endif
-# SIO_BUS_ENABLE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
-BUILD_STR += -D SIO_BUS_ENABLE=TRUE
-endif
-# SHELL_TYPE			= BUILD_SHELL
-ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y)
-BUILD_STR += -D SHELL_TYPE=NONE
-endif
-# USE_CBMEM_FOR_CONSOLE		= FALSE
-ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
-BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
-endif
-# SD_MMC_TIMEOUT		= 1000000
-ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
-BUILD_STR += -D SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT)
-endif
-#
-# The below are legacy options only available in CorebootPayloadPkg:
-#
-# PCIE_BASE			= 0
-ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),)
-BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
-endif
-# USE_HPET_TIMER		= FALSE
-ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y)
-BUILD_STR += -D USE_HPET_TIMER=TRUE
 endif
 
-bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
+ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y)
+TAG=upstream/master
+else
+TAG=origin/$(project_git_branch)
+endif
+
+ifneq ($(CONFIG_TIANOCORE_REVISION_ID),)
+TAG=$(CONFIG_TIANOCORE_REVISION_ID)
+endif
 
 export EDK_TOOLS_PATH=$(project_dir)/BaseTools
 
+ifeq ($(CONFIG_TIANOCORE_DEBUG),y)
+BUILD_TYPE=DEBUG
+else
+BUILD_TYPE=RELEASE
+endif
+
+ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
+CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE
+endif
+
+ifeq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
+4G=-D ABOVE_4G_MEMORY=TRUE
+else
+4G=-D ABOVE_4G_MEMORY=FALSE
+endif
+
+TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
+
+ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
+TIMER=-DUSE_HPET_TIMER
+endif
+
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE
+else
+BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G)
+endif
+
 all: clean build
 
 $(project_dir):
-	echo "    Cloning $(project_name) from $(CONFIG_TIANOCORE_REPOSITORY)"
+	echo "    Cloning $(project_name) from Git"
-	git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
+	git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \
-		cd $(project_dir);
+		cd $(project_dir); \
+		git remote add upstream $(upstream_git_repo)
 
 update: $(project_dir)
-	if [ ! -d "$(project_dir)" ]; then \
-		git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
-	fi
 	cd  $(project_dir); \
-		echo "    Fetching new commits from $(CONFIG_TIANOCORE_REPOSITORY)"; \
+		echo "    Fetching new commits from the $(project_name) repo"; \
-		git fetch origin 2>/dev/null; \
+		git fetch --multiple origin upstream 2>/dev/null; \
-		if ! git rev-parse --verify -q $(CONFIG_TIANOCORE_TAG_OR_REV) >/dev/null; then \
+		if ! git rev-parse --verify -q $(TAG) >/dev/null; then \
-			echo "    $(CONFIG_TIANOCORE_TAG_OR_REV) is not a valid git reference"; \
+			echo "    $(TAG) is not a valid git reference"; \
 			exit 1; \
 		fi; \
 		if git status --ignore-submodules=dirty | grep -qv clean; then \
-			echo "    Checking out $(project_name) revision $(CONFIG_TIANOCORE_TAG_OR_REV)"; \
+			echo "    Checking out $(project_name) revision $(TAG)"; \
-			git checkout --detach $(CONFIG_TIANOCORE_TAG_OR_REV) -f; \
+			git checkout --detach $(TAG); \
 		else \
 			echo "    Working directory not clean; will not overwrite"; \
 		fi; \
-		git submodule update --init --checkout
+		git submodule update --init
 
 checktools:
 	echo "Checking uuid-dev..."
@@ -122,15 +94,15 @@ checktools:
 		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
 
 build: update checktools
-	unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
+	unset CC; $(MAKE) -C $(project_dir)/BaseTools
-	echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)"
+	echo " build $(project_name) $(TAG)"
 	if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
 		echo "    Copying custom bootsplash image"; \
 		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
-			/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+			/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+				$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
-			*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+			*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+				$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
 		esac \
 	fi; \
 	cd $(project_dir); \
@@ -142,14 +114,13 @@ build: update checktools
 			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
 		fi; \
 		build $(BUILD_STR); \
-		mkdir -p $(project_dir)/../output
+		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
-		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/../output/UEFIPAYLOAD.fd; \
 		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true
 
 clean:
 	test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
 
 distclean:
-	rm -rf */
+	rm -rf $(project_dir)
 
 .PHONY: all update checktools config build clean distclean

payloads/libpayload/arch/x86/Makefile.inc

@@ -42,7 +42,6 @@ libc-$(CONFIG_LP_GPL) += string.c
 libgdb-y += gdb.c
 
 libcbfs-$(CONFIG_LP_CBFS) += rom_media.c
-libcbfs-$(CONFIG_LP_CBFS) += boot_media.c
 
 # Multiboot support is configurable
 libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c

payloads/libpayload/arch/x86/boot_media.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
-#include <arch/virtual.h>
 #include <boot_device.h>
 #include <commonlib/bsd/cb_err.h>
 #include <stddef.h>
@@ -12,7 +11,7 @@ __attribute__((weak)) ssize_t boot_device_read(void *buf, size_t offset, size_t
 	/* Memory-mapping usually only works for the top 16MB. */
 	if (!lib_sysinfo.boot_media_size || lib_sysinfo.boot_media_size - offset > 16 * MiB)
 		return CB_ERR_ARG;
-	const void *const ptr = phys_to_virt(0 - lib_sysinfo.boot_media_size + offset);
+	void *ptr = (void *)(uintptr_t)(0 - lib_sysinfo.boot_media_size + offset);
 	memcpy(buf, ptr, size);
 	return size;
 }

payloads/libpayload/bin/lpgcc

@@ -182,7 +182,7 @@ trygccoption -fno-stack-protector
 _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
 _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
 
-_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections"
+_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static"
 
 if [ $DOLINK -eq 0 ]; then
     if [ $DEBUGME -eq 1 ]; then

payloads/libpayload/libcbfs/cbfs.c

@@ -164,13 +164,13 @@ static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t
 
 	if (buf) {
 		if (!size_inout || *size_inout < out_size) {
-			ERROR("'%s' buffer too small\n", mdata->h.filename);
+			ERROR("'%s' buffer too small", mdata->h.filename);
 			return NULL;
 		}
 	} else {
 		buf = malloc(out_size);
 		if (!buf) {
-			ERROR("'%s' allocation failure\n", mdata->h.filename);
+			ERROR("'%s' allocation failure", mdata->h.filename);
 			return NULL;
 		}
 		malloced = true;

payloads/libpayload/vboot/Kconfig

@@ -2,7 +2,6 @@
 
 config VBOOT_LIB
 	bool "Compile verified boot (vboot) library"
-	default y if CHROMEOS
 	default n
 	help
 	  This option enables compiling and building vboot libraries vboot_fw and tlcl.
@@ -17,7 +16,6 @@ config VBOOT_TPM2_MODE
 
 config VBOOT_X86_SHA_EXT
 	bool "x86 SHA Extension"
-	default y if CHROMEOS
 	default n
 	depends on ARCH_X86
 	help

payloads/libpayload/vboot/Makefile.inc

@@ -7,7 +7,7 @@ TLCL_LIB = $(VBOOT_BUILD_DIR)/tlcl.a
 vboot_fw-objs += $(VBOOT_FW_LIB)
 tlcl-objs += $(TLCL_LIB)
 
-kconfig-to-binary=$(if $(strip $(1)),1,0)
+kconfig-to-binary=$(if $(1),1,0)
 vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\
 		       $(patsubst include/%.h,$(top)/include/%.h,\
 		       $(filter-out -I$(obj),$(1))))
@@ -30,14 +30,14 @@ endif
 
 $(VBOOT_FW_LIB): $(obj)/libpayload-config.h
 	@printf "    MAKE       $(subst $(obj)/,,$(@))\n"
-	+$(Q) FIRMWARE_ARCH="$(VBOOT_FIRMWARE_ARCH-y)" \
+	+$(Q) FIRMWARE_ARCH=$(VBOOT_FIRMWARE_ARCH-y) \
-		CC="$(CC)" \
+		CC=$(CC) \
 		CFLAGS="$(VBOOT_CFLAGS)" \
 		$(MAKE) -C "$(VBOOT_SOURCE)" \
 		TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \
 		X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \
 		UNROLL_LOOPS=1 \
-		BUILD="$(VBOOT_BUILD_DIR)" \
+		BUILD=$(VBOOT_BUILD_DIR) \
 		V=$(V) \
 		$(VBOOT_BUILD_DIR)/vboot_fw.a tlcl
 

spd/lp4x/memory_parts.json

@@ -339,18 +339,6 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 4267
             }
-        },
-	{
-            "name": "MT53E2G32D4NQ-046 WT:C",
-            "attribs": {
-                "densityPerChannelGb": 16,
-                "banks": 8,
-                "channelsPerDie": 2,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 2,
-                "speedMbps": 4267
-            }
         }
     ]
 }

spd/lp4x/set-0/parts_spd_manifest.generated.txt

@@ -29,4 +29,3 @@ H54G46CYRBX267,spd-1.hex
 H54G56CYRBX247,spd-3.hex
 K4U6E3S4AB-MGCL,spd-1.hex
 K4UBE3D4AB-MGCL,spd-3.hex
-MT53E2G32D4NQ-046 WT:C,spd-7.hex

spd/lp4x/set-1/parts_spd_manifest.generated.txt

@@ -29,4 +29,3 @@ H54G46CYRBX267,spd-1.hex
 H54G56CYRBX247,spd-3.hex
 K4U6E3S4AB-MGCL,spd-1.hex
 K4UBE3D4AB-MGCL,spd-3.hex
-MT53E2G32D4NQ-046 WT:C,spd-10.hex

src/Kconfig

@@ -878,7 +878,7 @@ config GDB_STUB
 	depends on DRIVERS_UART
 	help
 	  If enabled, you will be able to set breakpoints for gdb debugging.
-	  See src/arch/x86/c_start.S for details.
+	  See src/arch/x86/lib/c_start.S for details.
 
 config GDB_WAIT
 	bool "Wait for a GDB connection in the ramstage"

src/acpi/acpi.c

@@ -18,8 +18,6 @@
 #include <acpi/acpi.h>
 #include <acpi/acpi_ivrs.h>
 #include <acpi/acpigen.h>
-#include <arch/hpet.h>
-#include <arch/mmio.h>
 #include <device/pci.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>
@@ -849,10 +847,10 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
 	addr->space_id = ACPI_ADDRESS_SPACE_MEMORY;
 	addr->bit_width = 64;
 	addr->bit_offset = 0;
-	addr->addrl = HPET_BASE_ADDRESS & 0xffffffff;
+	addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
-	addr->addrh = ((unsigned long long)HPET_BASE_ADDRESS) >> 32;
+	addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
 
-	hpet->id = read32p(HPET_BASE_ADDRESS);
+	hpet->id = *(unsigned int *)CONFIG_HPET_ADDRESS;
 	hpet->number = 0;
 	hpet->min_tick = CONFIG_HPET_MIN_TICKS;
 
@@ -1509,7 +1507,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = asl_revision;
 
-	fadt->FADT_MinorVersion = get_acpi_fadt_minor_version();
 	fadt->firmware_ctrl = (unsigned long) facs;
 	fadt->x_firmware_ctl_l = (unsigned long)facs;
 	fadt->x_firmware_ctl_h = 0;
@@ -1947,16 +1944,11 @@ __weak int acpi_get_gpe(int gpe)
 	return -1; /* implemented by SOC */
 }
 
-u8 get_acpi_fadt_minor_version(void)
-{
-	return ACPI_FADT_MINOR_VERSION_0;
-}
-
 int get_acpi_table_revision(enum acpi_tables table)
 {
 	switch (table) {
 	case FADT:
-		return ACPI_FADT_REV_ACPI_6;
+		return ACPI_FADT_REV_ACPI_6_0;
 	case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */
 		return 3;
 	case MCFG:

src/acpi/acpigen.c

@@ -406,7 +406,8 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
 	acpigen_emit_byte(pblock_len);
 }
 
-void acpigen_write_processor_package(const char *const name, const unsigned int first_core,
+void acpigen_write_processor_package(const char *const name,
+				     const unsigned int first_core,
 				     const unsigned int core_count)
 {
 	unsigned int i;
@@ -429,7 +430,8 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores)
 	acpigen_write_method("\\_SB.CNOT", 1);
 	for (core_id = 0; core_id < number_of_cores; core_id++) {
 		char buffer[DEVICE_PATH_MAX];
-		snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, core_id);
+		snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING,
+			 core_id);
 		acpigen_emit_byte(NOTIFY_OP);
 		acpigen_emit_namestring(buffer);
 		acpigen_emit_byte(ARG0_OP);
@@ -512,19 +514,22 @@ static void acpigen_write_field_length(uint32_t len)
 		acpigen_emit_byte(emit[j]);
 }
 
-static void acpigen_write_field_offset(uint32_t offset, uint32_t current_bit_pos)
+static void acpigen_write_field_offset(uint32_t offset,
+				       uint32_t current_bit_pos)
 {
 	uint32_t diff_bits;
 
 	if (offset < current_bit_pos) {
-		printk(BIOS_WARNING, "%s: Cannot move offset backward", __func__);
+		printk(BIOS_WARNING, "%s: Cannot move offset backward",
+			__func__);
 		return;
 	}
 
 	diff_bits = offset - current_bit_pos;
 	/* Upper limit */
 	if (diff_bits > 0xFFFFFFF) {
-		printk(BIOS_WARNING, "%s: Offset very large to encode", __func__);
+		printk(BIOS_WARNING, "%s: Offset very large to encode",
+			__func__);
 		return;
 	}
 
@@ -596,7 +601,8 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou
 			current_bit_pos = l[i].bits;
 			break;
 		default:
-			printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", __func__, l[i].type);
+			printk(BIOS_ERR, "%s: Invalid field type 0x%X\n"
+				, __func__, l[i].type);
 			break;
 		}
 	}
@@ -624,8 +630,8 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou
  *		PMCS,   2
  *	}
  */
-void acpigen_write_indexfield(const char *idx, const char *data, struct fieldlist *l,
+void acpigen_write_indexfield(const char *idx, const char *data,
-			      size_t count, uint8_t flags)
+			      struct fieldlist *l, size_t count, uint8_t flags)
 {
 	uint16_t i;
 	uint32_t current_bit_pos = 0;
@@ -652,7 +658,8 @@ void acpigen_write_indexfield(const char *idx, const char *data, struct fieldlis
 			current_bit_pos = l[i].bits;
 			break;
 		default:
-			printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", __func__, l[i].type);
+			printk(BIOS_ERR, "%s: Invalid field type 0x%X\n"
+				, __func__, l[i].type);
 			break;
 		}
 	}
@@ -938,8 +945,8 @@ void acpigen_write_PRW(u32 wake, u32 level)
 	acpigen_pop_len();
 }
 
-void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control,
+void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
-			       u32 status)
+			      u32 busmLat, u32 control, u32 status)
 {
 	acpigen_write_package(6);
 	acpigen_write_dword(coreFreq);
@@ -950,8 +957,8 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLa
 	acpigen_write_dword(status);
 	acpigen_pop_len();
 
-	printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", coreFreq, power,
+	printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n",
-	       control, status);
+	       coreFreq, power, control, status);
 }
 
 void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries)
@@ -1186,12 +1193,14 @@ void acpigen_write_resourcetemplate_footer(void)
 	acpigen_pop_len();
 }
 
-static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, struct resource *res)
+static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev,
+						struct resource *res)
 {
 	acpigen_write_mem32fixed(0, res->base, res->size);
 }
 
-static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, struct resource *res)
+static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev,
+						struct resource *res)
 {
 	resource_t base = res->base;
 	resource_t size = res->size;
@@ -1210,13 +1219,13 @@ void acpigen_write_mainboard_resource_template(void)
 	/* Add reserved memory ranges. */
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_RESERVE,
-		IORESOURCE_MEM | IORESOURCE_RESERVE,
+		 IORESOURCE_MEM | IORESOURCE_RESERVE,
 		acpigen_add_mainboard_rsvd_mem32, 0);
 
 	/* Add reserved io ranges. */
 	search_global_resources(
 		IORESOURCE_IO | IORESOURCE_RESERVE,
-		IORESOURCE_IO | IORESOURCE_RESERVE,
+		 IORESOURCE_IO | IORESOURCE_RESERVE,
 		acpigen_add_mainboard_rsvd_io, 0);
 
 	acpigen_write_resourcetemplate_footer();
@@ -1626,7 +1635,8 @@ void acpigen_write_pld(const struct acpi_pld *pld)
 	acpigen_pop_len();
 }
 
-void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *), size_t count, void *arg)
+void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *),
+		       size_t count, void *arg)
 {
 	struct dsm_uuid id = DSM_UUID(uuid, callbacks, count, arg);
 	acpigen_write_dsm_uuid_arr(&id, 1);
@@ -1773,7 +1783,8 @@ void acpigen_write_CPPC_package(const struct cppc_config *config)
 		max = CPPC_MAX_FIELDS_VER_3;
 		break;
 	default:
-		printk(BIOS_ERR, "CPPC version %u is not implemented\n", config->version);
+		printk(BIOS_ERR, "CPPC version %u is not implemented\n",
+		       config->version);
 		return;
 	}
 	acpigen_write_name(CPPC_PACKAGE_NAME);
@@ -1874,7 +1885,8 @@ void acpigen_write_rom(void *bios, const size_t length)
 	acpigen_write_method_serialized("_ROM", 2);
 
 	/* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */
-	struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY, (uintptr_t)bios, length);
+	struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY,
+			(uintptr_t)bios, length);
 	acpigen_write_opregion(&opreg);
 
 	struct fieldlist l[] = {
@@ -1887,7 +1899,8 @@ void acpigen_write_rom(void *bios, const size_t length)
 	 *  Offset (0),
 	 *  RBF0,   0x80000
 	 * } */
-	acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
+	acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC |
+			    FIELD_NOLOCK | FIELD_PRESERVE);
 
 	/* Store (Arg0, Local0) */
 	acpigen_write_store();
@@ -2045,8 +2058,8 @@ void acpigen_get_tx_gpio(const struct acpi_gpio *gpio)
 }
 
 /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */
-void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min,
+void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran,
-			   u16 range_max, u16 translation, u16 length)
+	u16 range_min, u16 range_max, u16 translation, u16 length)
 {
 	acpigen_emit_byte(0x88);
 	/* Byte 1+2: length (0x000d) */
@@ -2068,8 +2081,8 @@ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran
 }
 
 /* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */
-void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, u32 gran,
+void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags,
-			    u32 range_min, u32 range_max, u32 translation, u32 length)
+	u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length)
 {
 	acpigen_emit_byte(0x87);
 	/* Byte 1+2: length (0023) */
@@ -2097,8 +2110,8 @@ static void acpigen_emit_qword(u64 data)
 }
 
 /* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */
-void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran,
+void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags,
-			    u64 range_min, u64 range_max, u64 translation, u64 length)
+	u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length)
 {
 	acpigen_emit_byte(0x8a);
 	/* Byte 1+2: length (0x002b) */

src/acpi/acpigen_ps2_keybd.c

@@ -55,7 +55,6 @@ static const uint32_t action_keymaps[] = {
 					  KEY_PRIVACY_SCREEN_TOGGLE),
 	[PS2_KEY_MICMUTE] = KEYMAP(0x9b, KEY_MICMUTE),			/* e01b */
 	[PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE),	/* e01e */
-	[PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL),	/* e0d5 */
 };
 
 /* Keymap for numeric keypad keys */

src/arch/x86/Kconfig

@@ -191,8 +191,12 @@ config CMOS_DEFAULT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
 	depends on HAVE_CMOS_DEFAULT
 
-config HPET_MIN_TICKS
+config HPET_ADDRESS_OVERRIDE
+	def_bool n
+
+config HPET_ADDRESS
 	hex
+	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
 
 config C_ENV_BOOTBLOCK_SIZE
 	hex

src/arch/x86/include/arch/hpet.h

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef ARCH_X86_HPET_H
-#define ARCH_X86_HPET_H
-
-#define HPET_BASE_ADDRESS	0xfed00000
-
-#endif /* ARCH_X86_HPET_H */

src/console/printk.c

@@ -67,7 +67,7 @@ union log_state {
 	};
 };
 
-#define LOG_FAST(state) (HAS_ONLY_FAST_CONSOLES || ((state).speed == CONSOLE_LOG_FAST))
+#define LOG_FAST(state) (HAS_ONLY_FAST_CONSOLES || ((state).level == CONSOLE_LOG_FAST))
 
 static void wrap_interactive_printf(const char *fmt, ...)
 {

src/cpu/amd/agesa/family14/fixme.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
@@ -29,7 +28,7 @@ void amd_initcpuio(void)
 	PciData |= 1 << 7;	// set NP (non-posted) bit
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	PciData = (HPET_BASE_ADDRESS >> 8) | 3;	// lowest NP address is HPET at FED00000
+	PciData = (0xFED00000 >> 8) | 3;	// lowest NP address is HPET at FED00000
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */

src/cpu/amd/agesa/family15tn/fixme.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
@@ -29,7 +28,7 @@ void amd_initcpuio(void)
 	PciData |= 1 << 7;    /* set NP (non-posted) bit */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+	PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */

src/cpu/amd/agesa/family16kb/fixme.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
@@ -29,7 +28,7 @@ void amd_initcpuio(void)
 	PciData |= 1 << 7;    /* set NP (non-posted) bit */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-	PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+	PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */

src/cpu/amd/pi/00730F01/fixme.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
@@ -33,7 +32,7 @@ void amd_initcpuio(void)
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
 	/* lowest NP address is HPET at FED00000 */
-	PciData = (HPET_BASE_ADDRESS >> 8) | 3;
+	PciData = (0xFED00000 >> 8) | 3;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */

src/cpu/intel/model_2065x/model_2065x.h

@@ -20,7 +20,6 @@
 
 #define MSR_MISC_PWR_MGMT		0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
-#define MSR_TURBO_POWER_CURRENT_LIMIT	0x1ac
 #define MSR_TURBO_RATIO_LIMIT		0x1ad
 #define MSR_POWER_CTL			0x1fc
 

src/device/Kconfig

@@ -527,6 +527,14 @@ config AZALIA_PLUGIN_SUPPORT
 	bool
 	default n
 
+config AZALIA_MAX_CODECS
+	int
+	depends on AZALIA_PLUGIN_SUPPORT
+	default 3
+	range 1 15
+	help
+	  The maximum number of codecs supported on a single HD Audio controller.
+
 config AZALIA_LOCK_DOWN_R_WO_GCAP
 	def_bool n
 	depends on AZALIA_PLUGIN_SUPPORT

src/device/azalia_device.c

@@ -50,6 +50,7 @@ int azalia_exit_reset(u8 *base)
 static u16 codec_detect(u8 *base)
 {
 	struct stopwatch sw;
+	const u16 codec_mask = (1 << CONFIG_AZALIA_MAX_CODECS) - 1;
 	u16 reg16;
 
 	if (azalia_exit_reset(base) < 0)
@@ -60,9 +61,9 @@ static u16 codec_detect(u8 *base)
 		write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
 	}
 
-	/* clear STATESTS bits (BAR + 0x0e)[14:0] */
+	/* clear STATESTS bits (BAR + 0xe)[2:0] */
 	reg16 = read16(base + HDA_STATESTS_REG);
-	reg16 |= 0x7fff;
+	reg16 |= codec_mask;
 	write16(base + HDA_STATESTS_REG, reg16);
 
 	/* Wait for readback of register to
@@ -85,9 +86,9 @@ static u16 codec_detect(u8 *base)
 	if (azalia_exit_reset(base) < 0)
 		goto no_codec;
 
-	/* Read in Codec location (BAR + 0x0e)[14:0] */
+	/* Read in Codec location (BAR + 0xe)[2..0] */
 	reg16 = read16(base + HDA_STATESTS_REG);
-	reg16 &= 0x7fff;
+	reg16 &= codec_mask;
 	if (!reg16)
 		goto no_codec;
 
@@ -273,7 +274,7 @@ void azalia_codecs_init(u8 *base, u16 codec_mask)
 {
 	int i;
 
-	for (i = 14; i >= 0; i--) {
+	for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
 		if (codec_mask & (1 << i))
 			azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
 	}

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus with GC6 3.0
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!dev->enabled || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus graphics device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}

src/drivers/i2c/tpm/cr50.c

@@ -441,14 +441,13 @@ static int cr50_i2c_probe(struct tpm_chip *chip, uint32_t *did_vid)
 	int retries;
 
 	/*
-	 * 1s should be enough to synchronize with the TPM even under the
+	 * 200 ms should be enough to synchronize with the TPM even under the
 	 * worst nested reset request conditions. In vast majority of cases
-	 * there would be no wait at all. If this probe fails, boot likely
+	 * there would be no wait at all.
-	 * cannot proceed, so an extra long timeout is appropriate.
 	 */
 	printk(BIOS_INFO, "Probing TPM I2C: ");
 
-	for (retries = 100; retries > 0; retries--) {
+	for (retries = 20; retries > 0; retries--) {
 		int rc;
 
 		rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4);

src/drivers/intel/fsp2_0/Kconfig

@@ -310,7 +310,7 @@ config FSPS_USE_MULTI_PHASE_INIT
 	  SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
 	  execute FspMultiPhaseSiInit() API.
 
-config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
 	bool
 	help
 	  The FSP API is used to notify the FSP about different phases in the boot process.
@@ -318,28 +318,12 @@ config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	  - Post PCI enumeration
 	  - Ready to Boot
 	  - End of Firmware
-	  This option allows FSP to execute Notify Phase API (Post PCI enumeration).
+	  Select this on a platform where you want to skip calling FSP Notify
-	  SoC users can override this config to use coreboot native implementations
+	  `Post PCI enumeration` API. Instead use coreboot native implementations
-	  to perform the required lock down and chipset register configuration prior
-	  to executing any 3rd-party code during PCI enumeration (i.e. Option ROM).
-
-	  coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration)
-	  is still WIP.
-
-config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
-	bool
-	help
-	  The FSP API is used to notify the FSP about different phases in the boot process.
-	  The current FSP specification supports three notify phases:
-	  - Post PCI enumeration
-	  - Ready to Boot
-	  - End of Firmware
-	  This option allows FSP to execute Notify Phase API (Ready to Boot).
-	  SoC users can override this config to use coreboot native implementations
 	  to perform the required lock down and chipset register configuration prior
 	  boot to payload.
 
-config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	bool
 	help
 	  The FSP API is used to notify the FSP about different phases in the boot process.
@@ -347,9 +331,20 @@ config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 	  - Post PCI enumeration
 	  - Ready to Boot
 	  - End of Firmware
-	  This option allows FSP to execute Notify Phase API (End of Firmware).
+	  Select this on a platform where you want to skip calling FSP Notify `Ready to Boot`
-	  SoC users can override this config to use coreboot native implementations
+	  API. Instead use coreboot native implementations to perform the required lock down
-	  to perform the required lock down and chipset register configuration prior
+	  and chipset register configuration prior boot to payload.
-	  boot to payload.
+
+config SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	bool
+	help
+	  The FSP API is used to notify the FSP about different phases in the boot process.
+	  The current FSP specification supports three notify phases:
+	  - Post PCI enumeration
+	  - Ready to Boot
+	  - End of Firmware
+	  Select this on a platform where you want to skip calling FSP Notify `End of Firmware`
+	  API. Instead use coreboot native implementations to perform the required lock down
+	  and chipset register configuration prior boot to payload.
 
 endif

src/drivers/intel/fsp2_0/hand_off_block.c

@@ -286,6 +286,7 @@ void fsp_display_fvi_version_hob(void)
 {
 	const uint8_t *hob_uuid;
 	const struct hob_header *hob = fsp_get_hob_list();
+	size_t size;
 
 	if (!hob)
 		return;
@@ -299,6 +300,7 @@ void fsp_display_fvi_version_hob(void)
 		hob_uuid = hob_header_to_struct(hob);
 
 		if (fsp_guid_compare(hob_uuid, uuid_fv_info)) {
+			size = hob->length - (HOB_HEADER_LEN + 16);
 			display_fsp_version_info_hob(hob);
 		}
 	}

src/drivers/intel/fsp2_0/notify.c

@@ -20,7 +20,7 @@ struct fsp_notify_phase_data {
 static const struct fsp_notify_phase_data notify_data[] = {
 	{
 		.notify_phase     = AFTER_PCI_ENUM,
-		.skip             = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
+		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM),
 		.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
 		.post_code_after  = POST_FSP_NOTIFY_AFTER_ENUMERATE,
 		.timestamp_before = TS_FSP_BEFORE_ENUMERATE,
@@ -28,7 +28,7 @@ static const struct fsp_notify_phase_data notify_data[] = {
 	},
 	{
 		.notify_phase     = READY_TO_BOOT,
-		.skip             = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
+		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT),
 		.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
 		.post_code_after  = POST_FSP_NOTIFY_AFTER_FINALIZE,
 		.timestamp_before = TS_FSP_BEFORE_FINALIZE,
@@ -36,7 +36,7 @@ static const struct fsp_notify_phase_data notify_data[] = {
 	},
 	{
 		.notify_phase     = END_OF_FIRMWARE,
-		.skip             = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
+		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
 		.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
 		.post_code_after  = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
 		.timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,

src/drivers/intel/mipi_camera/camera.c

@@ -138,8 +138,7 @@ static void camera_fill_cio2(const struct device *dev)
 		port_name[i] = strdup(name);
 		if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) {
 			u32 cpu_id = cpu_get_cpuid();
-			if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1 ||
+			if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1)
-				cpu_id == CPUID_ALDERLAKE_N_A0)
 				acpi_dp_add_integer(dsd, "is_es", 1);
 			else
 				acpi_dp_add_integer(dsd, "is_es", 0);

src/drivers/intel/pmc_mux/conn/conn.c

@@ -67,7 +67,7 @@ static void conn_write_cbmem_entry(struct device *dev)
 	port_info->sbu_orientation = config->sbu_orientation;
 	port_info->data_orientation = config->hsl_orientation;
 
-	printk(BIOS_INFO, "added type-c port%zu info to cbmem: usb2:%d usb3:%d sbu:%d data:%d\n",
+	printk(BIOS_INFO, "added type-c port%ld info to cbmem: usb2:%d usb3:%d sbu:%d data:%d\n",
 			count, port_info->usb2_port_number, port_info->usb3_port_number,
 			port_info->sbu_orientation, port_info->data_orientation);
 

src/drivers/mrc_cache/mrc_cache.c

@@ -255,7 +255,7 @@ static int mrc_cache_get_latest_slot_info(const char *name,
 
 	/* No data to return. */
 	if (region_file_data(cache_file, rdev) < 0) {
-		printk(BIOS_NOTICE, "MRC: no data in '%s'\n", name);
+		printk(BIOS_ERR, "MRC: no data in '%s'\n", name);
 		return fail_bad_data ? -1 : 0;
 	}
 

src/ec/google/chromeec/ec_acpi.c

@@ -185,10 +185,9 @@ static void fill_ssdt_typec_device(const struct device *dev)
 		get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port);
 
 		struct typec_connector_class_config typec_config = {
-			.power_role = (enum usb_typec_power_role)port_caps.power_role_cap,
+			.power_role = port_caps.power_role_cap,
-			.try_power_role =
+			.try_power_role = port_caps.try_power_role_cap,
-				(enum usb_typec_try_power_role)port_caps.try_power_role_cap,
+			.data_role = port_caps.data_role_cap,
-			.data_role = (enum usb_typec_data_role)port_caps.data_role_cap,
 			.usb2_port = usb2_port,
 			.usb3_port = usb3_port,
 			.usb4_port = usb4_port,
@@ -226,7 +225,6 @@ static const enum ps2_action_key ps2_enum_val[] = {
 	[TK_PREV_TRACK] = PS2_KEY_PREV_TRACK,
 	[TK_KBD_BKLIGHT_TOGGLE] = PS2_KEY_KBD_BKLIGHT_TOGGLE,
 	[TK_MICMUTE] = PS2_KEY_MICMUTE,
-	[TK_MENU] = PS2_KEY_MENU,
 };
 
 static void fill_ssdt_ps2_keyboard(const struct device *dev)

src/ec/google/chromeec/ec_commands.h

@@ -177,7 +177,7 @@ extern "C" {
 #define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT    BIT(7)
 
 /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
-#define EC_TEMP_SENSOR_ENTRIES        16
+#define EC_TEMP_SENSOR_ENTRIES     16
 /*
  * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
  *
@@ -185,10 +185,6 @@ extern "C" {
  */
 #define EC_TEMP_SENSOR_B_ENTRIES      8
 
-/* Max temp sensor entries for host commands */
-#define EC_MAX_TEMP_SENSOR_ENTRIES    (EC_TEMP_SENSOR_ENTRIES + \
-				       EC_TEMP_SENSOR_B_ENTRIES)
-
 /* Special values for mapped temperature sensors */
 #define EC_TEMP_SENSOR_NOT_PRESENT    0xff
 #define EC_TEMP_SENSOR_ERROR          0xfe
@@ -1503,10 +1499,6 @@ enum ec_feature_code {
 	 * mux.
 	 */
 	EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
-	/*
-	 * The EC supports entering and residing in S4.
-	 */
-	EC_FEATURE_S4_RESIDENCY = 44,
 };
 
 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
@@ -1773,8 +1765,6 @@ struct ec_params_flash_erase_v1 {
 #define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT   BIT(9)
 /* Rollback information flash region protected now */
 #define EC_FLASH_PROTECT_ROLLBACK_NOW       BIT(10)
-/* Error - Unknown error */
-#define EC_FLASH_PROTECT_ERROR_UNKNOWN      BIT(11)
 
 
 /**
@@ -2716,8 +2706,6 @@ enum motionsensor_chip {
 	MOTIONSENSE_CHIP_ICM42607 = 26,
 	MOTIONSENSE_CHIP_BMA422 = 27,
 	MOTIONSENSE_CHIP_BMI323 = 28,
-	MOTIONSENSE_CHIP_BMI220 = 29,
-	MOTIONSENSE_CHIP_CM32183 = 30,
 	MOTIONSENSE_CHIP_MAX,
 };
 
@@ -2868,7 +2856,7 @@ struct ec_params_motion_sense {
 		 */
 		struct __ec_todo_unpacked {
 			/* Data to set or EC_MOTION_SENSE_NO_VALUE to read.
-			 * kb_wake_angle: angle to wakup AP.
+			 * kb_wake_angle: angle to wake up AP.
 			 */
 			int16_t data;
 		} kb_wake_angle;
@@ -6063,10 +6051,7 @@ struct ec_params_set_cbi {
  * - The semantic meaning of an entry should not change.
  * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons.
  */
-enum chipset_shutdown_reason {
+enum chipset_reset_reason {
-	/*
-	 * Beginning of reset reasons.
-	 */
 	CHIPSET_RESET_BEGIN = 0,
 	CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN,
 	/* Custom reason defined by a board.c or baseboard.c file */
@@ -6090,11 +6075,13 @@ enum chipset_shutdown_reason {
 	/* EC detected an AP watchdog event. */
 	CHIPSET_RESET_AP_WATCHDOG,
 
-	CHIPSET_RESET_COUNT, /* End of reset reasons. */
+	CHIPSET_RESET_COUNT,
+};
 
-	/*
+/*
-	 * Beginning of shutdown reasons.
+ * AP hard shutdowns are logged on the same path as resets.
-	 */
+ */
+enum chipset_shutdown_reason {
 	CHIPSET_SHUTDOWN_BEGIN = BIT(15),
 	CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN,
 	/* Forcing a shutdown as part of EC initialization */
@@ -6116,7 +6103,7 @@ enum chipset_shutdown_reason {
 	/* Force a chipset shutdown from the power button through EC */
 	CHIPSET_SHUTDOWN_BUTTON,
 
-	CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */
+	CHIPSET_SHUTDOWN_COUNT,
 };
 
 
@@ -6423,7 +6410,6 @@ enum action_key {
 	TK_PREV_TRACK = 17,
 	TK_KBD_BKLIGHT_TOGGLE = 18,
 	TK_MICMUTE = 19,
-	TK_MENU = 20,
 };
 
 /*
@@ -6633,7 +6619,6 @@ enum typec_control_command {
 	TYPEC_CONTROL_COMMAND_EXIT_MODES,
 	TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
 	TYPEC_CONTROL_COMMAND_ENTER_MODE,
-	TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY,
 };
 
 /* Modes (USB or alternate) that a type-C port may enter. */
@@ -6643,12 +6628,6 @@ enum typec_mode {
 	TYPEC_MODE_USB4,
 };
 
-/* Replies the AP may specify to the TBT EnterMode command as a UFP */
-enum typec_tbt_ufp_reply {
-	TYPEC_TBT_UFP_REPLY_NAK,
-	TYPEC_TBT_UFP_REPLY_ACK,
-};
-
 struct ec_params_typec_control {
 	uint8_t port;
 	uint8_t command;	/* enum typec_control_command */
@@ -6660,12 +6639,8 @@ struct ec_params_typec_control {
 	 * the command version when adding new sub-commands.
 	 */
 	union {
-		/* Used for CLEAR_EVENTS */
 		uint32_t clear_events_mask;
-		/* Used for ENTER_MODE - enum typec_mode */
+		uint8_t mode_to_enter;      /* enum typec_mode */
-		uint8_t mode_to_enter;
-		/* Used for TBT_UFP_REPLY - enum typec_tbt_ufp_reply */
-		uint8_t tbt_ufp_reply;
 		uint8_t placeholder[128];
 	};
 } __ec_align1;
@@ -6957,9 +6932,8 @@ enum pchg_state {
 
 /* Port number is encoded in bit[28:31]. */
 #define EC_MKBP_PCHG_PORT_SHIFT		28
-/* Utility macros for converting MKBP event <-> port number. */
+/* Utility macro for converting MKBP event to port number. */
 #define EC_MKBP_PCHG_EVENT_TO_PORT(e)	(((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
-#define EC_MKBP_PCHG_PORT_TO_EVENT(p)	(BIT((p) + EC_MKBP_PCHG_PORT_SHIFT))
 /* Utility macro for extracting event bits. */
 #define EC_MKBP_PCHG_EVENT_MASK(e)	((e) \
 					& GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))
@@ -6968,7 +6942,6 @@ enum pchg_state {
 #define EC_MKBP_PCHG_WRITE_COMPLETE	BIT(1)
 #define EC_MKBP_PCHG_UPDATE_CLOSED	BIT(2)
 #define EC_MKBP_PCHG_UPDATE_ERROR	BIT(3)
-#define EC_MKBP_PCHG_DEVICE_EVENT	BIT(4)
 
 enum ec_pchg_update_cmd {
 	/* Reset chip to normal mode. */
@@ -7033,31 +7006,6 @@ enum ec_set_base_state_cmd {
 	EC_SET_BASE_STATE_RESET,
 };
 
-#define EC_CMD_I2C_CONTROL 0x0139
-
-/* Subcommands for I2C control */
-
-enum ec_i2c_control_command {
-	EC_I2C_CONTROL_GET_SPEED,
-	EC_I2C_CONTROL_SET_SPEED,
-};
-
-#define EC_I2C_CONTROL_SPEED_UNKNOWN 0
-
-struct ec_params_i2c_control {
-	uint8_t port;		/* I2C port number */
-	uint8_t cmd;		/* enum ec_i2c_control_command */
-	union {
-		uint16_t speed_khz;
-	} cmd_params;
-} __ec_align_size1;
-
-struct ec_response_i2c_control {
-	union {
-		uint16_t speed_khz;
-	} cmd_response;
-} __ec_align_size1;
-
 /*****************************************************************************/
 /* The command range 0x200-0x2FF is reserved for Rotor. */
 

src/ec/system76/ec/acpi/s76.asl

@@ -10,6 +10,8 @@
 Device (S76D) {
 	Name (_HID, "17761776")
 	Name (_UID, 0)
+	/* Hide the device so that Windows does not complain on missing driver */
+	Name (_STA, 0xB)
 
 	Method (RSET, 0, Serialized) {
 		Debug = "S76D: RSET"

src/include/acpi/acpi.h

@@ -746,8 +746,8 @@ typedef struct acpi_fadt {
 	u32 flags;
 	acpi_addr_t reset_reg;
 	u8 reset_value;
-	u16 ARM_boot_arch;	/* Must be zero if ACPI Revision <= 5.0 */
+	u16 ARM_boot_arch;	/* Revision 6 only, Revision 5: Must be zero */
-	u8 FADT_MinorVersion;	/* Must be zero if ACPI Revision <= 5.0 */
+	u8 FADT_MinorVersion;	/* Revision 6 only, Revision 5: Must be zero */
 	u32 x_firmware_ctl_l;
 	u32 x_firmware_ctl_h;
 	u32 x_dsdt_l;
@@ -768,21 +768,12 @@ typedef struct acpi_fadt {
 } __packed acpi_fadt_t;
 
 /* FADT TABLE Revision values */
-#define ACPI_FADT_REV_ACPI_1	1
+#define ACPI_FADT_REV_ACPI_1_0		1
-#define ACPI_FADT_REV_ACPI_2	3
+#define ACPI_FADT_REV_ACPI_2_0		3
-#define ACPI_FADT_REV_ACPI_3	4
+#define ACPI_FADT_REV_ACPI_3_0		4
-#define ACPI_FADT_REV_ACPI_4	4
+#define ACPI_FADT_REV_ACPI_4_0		4
-#define ACPI_FADT_REV_ACPI_5	5
+#define ACPI_FADT_REV_ACPI_5_0		5
-#define ACPI_FADT_REV_ACPI_6	6
+#define ACPI_FADT_REV_ACPI_6_0		6
-
-/* FADT Minor Version value:
- *  Bits 0-3: minor version
- *  Bits 4-7: Errata
- *   value of 1 means this is compatible with Errata A,
- *   value of 2 would be compatible with Errata B, and so on
- * Version 6.3 Errata A would be: (1 << 4) | 3
- */
-#define ACPI_FADT_MINOR_VERSION_0	0 /* coreboot currently use this version */
 
 /* Flags for p_lvl2_lat and p_lvl3_lat */
 #define ACPI_FADT_C2_NOT_SUPPORTED	101
@@ -1257,6 +1248,8 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
 			       u16 flags, u8 lint);
 void acpi_create_madt(acpi_madt_t *madt);
 unsigned long acpi_create_madt_lapics(unsigned long current);
+unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
+					  u8 lint);
 int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic);
 int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
 				 u16 flags, u8 lint);
@@ -1441,7 +1434,6 @@ static inline uintptr_t acpi_align_current(uintptr_t current)
  * be made into a weak function if there is ever a need to override the
  * coreboot default ACPI spec version supported. */
 int get_acpi_table_revision(enum acpi_tables table);
-u8 get_acpi_fadt_minor_version(void);
 
 #endif  // !defined(__ASSEMBLER__) && !defined(__ACPI__)
 

src/include/acpi/acpigen_ps2_keybd.h

@@ -26,7 +26,6 @@ enum ps2_action_key {
 	PS2_KEY_PREV_TRACK,
 	PS2_KEY_KBD_BKLIGHT_TOGGLE,
 	PS2_KEY_MICMUTE,
-	PS2_KEY_MENU,
 };
 
 #define PS2_MIN_TOP_ROW_KEYS		10

src/include/cpu/intel/cpu_ids.h

@@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1

src/include/device/dram/ddr3.h

@@ -32,6 +32,21 @@
 #define SPD_DIMM_PART_LEN	18
 /** @} */
 
+/**
+ * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP)
+ *
+ * Use this macro instead of printk(); for verbose RAM initialization messages.
+ * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically
+ * disabled.
+ * @{
+ */
+#if CONFIG(DEBUG_RAM_SETUP)
+#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
+#else
+#define printram(x, ...)
+#endif
+/** @} */
+
 /*
  * Module type (byte 3, bits 3:0) of SPD
  * This definition is specific to DDR3. DDR2 SPDs have a different structure.

src/include/smbios.h

@@ -730,7 +730,13 @@ enum misc_slot_type {
 	SlotTypePciExpressGen4x2 = 0xBA,
 	SlotTypePciExpressGen4x4 = 0xBB,
 	SlotTypePciExpressGen4x8 = 0xBC,
-	SlotTypePciExpressGen4x16 = 0xBD
+	SlotTypePciExpressGen4x16 = 0xBD,
+	SlotTypePciExpressGen5 = 0xBE,
+	SlotTypePciExpressGen5x1 = 0xBF,
+	SlotTypePciExpressGen5x2 = 0xC0,
+	SlotTypePciExpressGen5x4 = 0xC1,
+	SlotTypePciExpressGen5x8 = 0xC2,
+	SlotTypePciExpressGen5x16 = 0xC3,
 };
 
 /* System Slots - Slot Data Bus Width. */

src/mainboard/amd/chausie/Kconfig

@@ -51,7 +51,7 @@ config CHAUSIE_MCHP_FW_FILE
 config CHAUSIE_MCHP_FW_OFFSET
 	hex
 	depends on CHAUSIE_HAVE_MCHP_FW
-	default 0xB80000
+	default 0x400000
 	help
 	  The EC firmware blob defaults to the 4MByte offset of the firmware
 	  image. If this offset needs to change, a new signature block must be

src/mainboard/amd/chausie/board.fmd

@@ -1,7 +1,7 @@
 FLASH@0xFF000000 16M {
 	BIOS {
 		EC 4K
-		RW_MRC_CACHE 96K
+		RW_MRC_CACHE 64K
 		FMAP 4K
 		COREBOOT(CBFS)
 	}

src/mainboard/amd/chausie/chromeos.fmd

@@ -1,7 +1,7 @@
 FLASH@0xFF000000 16M {
 	SI_BIOS {
-		EC 4K
+		EC 128K
-		RW_MRC_CACHE(PRESERVE) 96K
+		RW_MRC_CACHE(PRESERVE) 64K
 		RW_SECTION_A 3M {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)

src/mainboard/amd/chausie/devicetree.cb

@@ -13,9 +13,6 @@ chip soc/amd/sabrina
 		.flash_ch_en = 0,
 	}"
 
-	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
-					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
-
 	# I2C Pad Control RX Select Configuration
 	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
 	register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
@@ -76,10 +73,6 @@ chip soc/amd/sabrina
 		end
 	end
 
-	device ref i2c_0 on end
-	device ref i2c_1 on end
-	device ref i2c_2 on end
-	device ref i2c_3 on end
 	device ref uart_0 on end # UART0
 
 end

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c

@@ -1,6 +1,4 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/hpet.h>
 #include <bootblock_common.h>
 #include <device/pnp_ops.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
@@ -91,7 +89,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
+		.hpet_address = CONFIG_HPET_ADDRESS,
 		.rcba = (uintptr_t)DEFAULT_RCBA,
 		.pmbase = DEFAULT_PMBASE,
 		.gpiobase = DEFAULT_GPIOBASE,

src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
-
 /****************************************************************
  * HPET
  ****************************************************************/
@@ -10,7 +8,7 @@ Scope(\_SB) {
     Device(HPET) {
         Name(_HID, EISAID("PNP0103"))
         Name(_UID, 0)
-        OperationRegion(HPTM, SystemMemory, HPET_BASE_ADDRESS, 0x400)
+        OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400)
         Field(HPTM, DWordAcc, Lock, Preserve) {
             VEND, 32,
             PRD, 32,
@@ -29,7 +27,7 @@ Scope(\_SB) {
         }
         Name(_CRS, ResourceTemplate() {
             Memory32Fixed(ReadOnly,
-                HPET_BASE_ADDRESS,  // Address Base
+                0xFED00000,         // Address Base
                 0x00000400,         // Address Length
                 )
         })

src/mainboard/gizmosphere/gizmo/OptionsIds.h

@@ -32,4 +32,5 @@
 //#define IDSOPT_TRACING_ENABLED TRUE
 #define IDSOPT_ASSERT_ENABLED  TRUE
 
+
 #endif

src/mainboard/gizmosphere/gizmo/acpi/gpe.asl

@@ -30,6 +30,7 @@ Scope(\_GPE) {	/* Start Scope GPE */
 		/* DBGO("\\_GPE\\_L10\n") */
 	}
 
+
 	/*  ExtEvent1 SCI event  */
 	Method(_L11) {
 		/* DBGO("\\_GPE\\_L11\n") */

src/mainboard/gizmosphere/gizmo/devicetree.cb

@@ -3,7 +3,7 @@
 chip northbridge/amd/agesa/family14/root_complex
 	device cpu_cluster 0 on
 			chip cpu/amd/agesa/family14
-				device lapic 0 on end
+			  device lapic 0 on end
 			end
 	end
 	device domain 0 on
@@ -19,7 +19,7 @@ chip northbridge/amd/agesa/family14/root_complex
 				device pci 8.0 off end # NB/SB Link P2P bridge
 			end # agesa northbridge
 
-			chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
+			chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
 				device pci 11.0 on end # SATA
 				device pci 12.0 on end # USB
 				device pci 12.1 on end # USB

src/mainboard/google/brya/Kconfig.name

@@ -138,7 +138,6 @@ config BOARD_GOOGLE_TAEKO
 	bool "->  Taeko"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENERIC_BAYHUB_LV2
-	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_GENESYSLOGIC_GL9763E
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 
@@ -146,7 +145,6 @@ config BOARD_GOOGLE_TAEKO4ES
 	bool "->  Taeko4ES"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENERIC_BAYHUB_LV2
-	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_GENESYSLOGIC_GL9763E
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 

src/mainboard/google/brya/romstage.c

@@ -7,9 +7,8 @@
 #include <soc/romstage.h>
 #include <string.h>
 
-void mainboard_memory_init_params(FSPM_UPD *memupd)
+void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
 {
-	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 	const struct mb_cfg *mem_config = variant_memory_params();
 	bool half_populated = variant_is_half_populated();
 	struct mem_spd spd_info;

src/mainboard/google/brya/variants/anahera/memory/Makefile.inc

@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory/ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A

src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory/ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT53E1G32D2NP-046 WT:A         0 (0000)
@@ -18,4 +18,3 @@ H54G46CYRBX267                 1 (0001)
 K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
-MT53E2G32D4NQ-046 WT:C         4 (0100)

src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt

@@ -12,4 +12,3 @@ H54G46CYRBX267
 K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
-MT53E2G32D4NQ-046 WT:C

src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc

@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory/ src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A

src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory/ src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT53E1G32D2NP-046 WT:A         0 (0000)
@@ -18,4 +18,3 @@ H54G46CYRBX267                 1 (0001)
 K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
-MT53E2G32D4NQ-046 WT:C         4 (0100)

src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt

@@ -12,4 +12,3 @@ H54G46CYRBX267
 K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
-MT53E2G32D4NQ-046 WT:C

src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

@@ -61,12 +61,6 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
-	register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
-	register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
-	register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
-	register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
-	register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
-
 	# HD Audio
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -155,6 +155,7 @@ chip soc/intel/alderlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
 				register "reset_off_delay_ms" = "20"
+				register "reset_delay_ms" = "1000"
 				register "srcclk_pin" = "5"
 				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
 				register "skip_on_off_support" = "true"

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -17,9 +17,6 @@ chip soc/intel/alderlake
 	# Enable CNVi BT
 	register "CnviBtCore" = "true"
 
-	# eMMC HS400
-	register "emmc_enable_hs400_mode" = "1"
-
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB2_A0

src/mainboard/google/brya/variants/crota/memory/Makefile.inc

@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
-# Generated by:
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/crota/memory src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt
 
-SPD_SOURCES =
+SPD_SOURCES = placeholder
-SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 0(0b0000)  Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E
-SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
-SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = K3LKBKB0BM-MGCP

src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt

@@ -1,11 +1 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/crota/memory src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt
-
 DRAM Part Name                 ID to assign
-MT62F1G32D4DR-031 WT:B         0 (0000)
-MT62F512M32D2DR-031 WT:B       1 (0001)
-H9JCNNNBK3MLYR-N6E             1 (0001)
-H9JCNNNCP3MLYR-N6E             0 (0000)
-K3LKBKB0BM-MGCP                2 (0010)

src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt

@@ -9,8 +9,3 @@
 # See util/spd_tools/README.md for more details and instructions.
 
 # Part Name
-MT62F1G32D4DR-031 WT:B
-MT62F512M32D2DR-031 WT:B
-H9JCNNNBK3MLYR-N6E
-H9JCNNNCP3MLYR-N6E
-K3LKBKB0BM-MGCP

src/mainboard/google/brya/variants/felwinter/overridetree.cb

@@ -58,28 +58,16 @@ chip soc/intel/alderlake
 	register "common_soc_config" = "{
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 550,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
 		},
 		.i2c[1] = {
 			.early_init = 1,
 			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 550,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
 		},
 		.i2c[3] = {
 			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 550,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
 		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 550,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
 		},
 	}"
 

src/mainboard/google/brya/variants/redrix/memory/Makefile.inc

@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory/ src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A

src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory/ src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT53E1G32D2NP-046 WT:A         0 (0000)
@@ -18,4 +18,3 @@ H54G46CYRBX267                 1 (0001)
 K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
-MT53E2G32D4NQ-046 WT:C         4 (0100)

src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt

@@ -12,4 +12,3 @@ H54G46CYRBX267
 K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
-MT53E2G32D4NQ-046 WT:C

src/mainboard/google/brya/variants/redrix/overridetree.cb

@@ -41,11 +41,6 @@ chip soc/intel/alderlake
 	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
 	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
 
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
-	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc

@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory/ src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
+SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A

src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory/ src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
+# ./util/spd_tools/lp4x/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 MT53E1G32D2NP-046 WT:A         0 (0000)
@@ -18,4 +18,3 @@ H54G46CYRBX267                 1 (0001)
 K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
-MT53E2G32D4NQ-046 WT:C         4 (0100)

src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt

@@ -12,4 +12,3 @@ H54G46CYRBX267
 K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
-MT53E2G32D4NQ-046 WT:C

src/mainboard/google/brya/variants/redrix4es/overridetree.cb

@@ -41,11 +41,6 @@ chip soc/intel/alderlake
 	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
 	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
 
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
-	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/brya/variants/vell/overridetree.cb

@@ -364,28 +364,28 @@ chip soc/intel/alderlake
 						register "desc" = ""USB3 Type-C Port C0 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
 						device ref tcss_usb3_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C1 (MlB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 						device ref tcss_usb3_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C2 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
 						device ref tcss_usb3_port3 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB3 Type-C Port C3 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))"
 						device ref tcss_usb3_port4 on end
 					end
 				end
@@ -398,21 +398,21 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-C Port C0 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
 						device ref usb2_port1 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C1 (MLB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
 						device ref usb2_port2 on end
 					end
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Type-C Port C2 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
 						device ref usb2_port3 on end
 					end
 					chip drivers/usb/acpi
@@ -424,7 +424,7 @@ chip soc/intel/alderlake
 						register "desc" = ""USB2 Type-C Port C3 (DB)""
 						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 						register "use_custom_pld" = "true"
-						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))"
 						device ref usb2_port5 on end
 					end
 					chip drivers/usb/acpi

src/mainboard/google/butterfly/early_init.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <stdint.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
@@ -83,7 +82,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
+		.hpet_address = CONFIG_HPET_ADDRESS,
 		.rcba = (uintptr_t)DEFAULT_RCBA,
 		.pmbase = DEFAULT_PMBASE,
 		.gpiobase = DEFAULT_GPIOBASE,

src/mainboard/google/guybrush/Kconfig

@@ -48,7 +48,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
 	select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
-	select SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES

src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg

@@ -29,7 +29,7 @@ DMCUINTVECTORSDCN21_FILE	TypeId0x59_DmcuIntvectorsDcn21.sbin
 PSPBTLDR_AB_FILE		TypeId0x73_PspBootLoader_AB_CZN.sbin
 
 # BDT
-PSP_PMUI_FILE_SUB0_INS1		TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin	L2
+PSP_PMUI_FILE1			TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin	L2
-PSP_PMUD_FILE_SUB0_INS1		TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin	L2
+PSP_PMUD_FILE1			TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin	L2
-PSP_PMUI_FILE_SUB0_INS4		TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin	L2
+PSP_PMUI_FILE2			TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin	L2
-PSP_PMUD_FILE_SUB0_INS4		TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin	L2
+PSP_PMUD_FILE2			TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin	L2