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Author SHA1 Message Date
Srinidhi N Kaushik
506ff8fb9e src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files
This change updates Intel Copyright License for all header files
under Sapphirerapids dir

Cherry-picked from commit 7e2106627d.

Original-Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Original-Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75469
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01 13:06:21 +00:00
4269 changed files with 97634 additions and 207975 deletions

View File

@@ -8,6 +8,9 @@
--ignore INITIALISED_STATIC --ignore INITIALISED_STATIC
--ignore LINE_SPACING --ignore LINE_SPACING
--ignore NEW_TYPEDEFS --ignore NEW_TYPEDEFS
--ignore PREFER_ALIGNED
--ignore PREFER_PACKED
--ignore PREFER_PRINTF
--ignore SPLIT_STRING --ignore SPLIT_STRING
--ignore BLOCK_COMMENT_STYLE --ignore BLOCK_COMMENT_STYLE
--ignore AVOID_EXTERNS --ignore AVOID_EXTERNS

View File

@@ -1,228 +1,21 @@
# SPDX-License-Identifier: GPL-2.0 BasedOnStyle: LLVM
# Language: Cpp
# clang-format configuration file. Intended for clang-format >= 16. IndentWidth: 8
# UseTab: Always
# For more information, see: BreakBeforeBraces: Linux
# AllowShortIfStatementsOnASingleLine: false
# https://clang.llvm.org/docs/ClangFormat.html IndentCaseLabels: false
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html SortIncludes: false
# https://clang-format-configurator.site/ ContinuationIndentWidth: 8
# ColumnLimit: 96
AlwaysBreakBeforeMultilineStrings: true
--- AllowShortLoopsOnASingleLine: false
Language: Cpp AllowShortFunctionsOnASingleLine: false
AccessModifierOffset: -4 AlignEscapedNewlinesLeft: false
AlignAfterOpenBracket: Align AlignTrailingComments: true
AlignArrayOfStructures: Left AllowAllParametersOfDeclarationOnNextLine: false
AlignConsecutiveAssignments: AlignAfterOpenBracket: true
Enabled: false SpaceAfterCStyleCast: false
AcrossEmptyLines: false MaxEmptyLinesToKeep: 2
AcrossComments: true BreakBeforeBinaryOperators: NonAssignment
AlignCompound: false BreakStringLiterals: false
PadOperators: true
AlignConsecutiveBitFields:
Enabled: true
AcrossEmptyLines: false
AcrossComments: false
AlignCompound: false
PadOperators: true
AlignConsecutiveDeclarations:
Enabled: false
AcrossEmptyLines: false
AcrossComments: false
AlignCompound: false
PadOperators: true
AlignConsecutiveMacros:
Enabled: true
AcrossEmptyLines: false
AcrossComments: false
AlignCompound: false
PadOperators: true
AlignEscapedNewlines: Left
AlignOperands: Align
AlignTrailingComments:
Kind: Always
OverEmptyLines: 0
AllowAllArgumentsOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: Never
AllowShortCaseLabelsOnASingleLine: false
AllowShortEnumsOnASingleLine: true
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: Never
AllowShortLambdasOnASingleLine: All
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
# git grep '^#define [^[:space:]]*__.*[^[:space:]]*__attribute__' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*__[^([:space:]]*\).*$| - '\1'|" | LC_ALL=C sort -u
AttributeMacros:
- '__aligned'
- '__always_inline'
- '__always_unused'
- '__cpu_driver'
- '__fallthrough'
- '__maybe_unused'
- '__must_check'
- '__noreturn'
- '__packed'
- '__pci_driver'
- '__printf'
- '__weak'
BinPackArguments: true
BinPackParameters: true
BitFieldColonSpacing: Both
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: Never
AfterEnum: false
AfterExternBlock: false
AfterFunction: true
AfterNamespace: true
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
BeforeCatch: false
BeforeElse: false
BeforeLambdaBody: false
BeforeWhile: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakAfterAttributes: Never
BreakAfterJavaFieldAnnotations: false
BreakArrays: false
BreakBeforeBinaryOperators: None
BreakBeforeConceptDeclarations: Always
BreakBeforeBraces: Custom
BreakBeforeInlineASMColon: OnlyMultiline
BreakBeforeTernaryOperators: false
BreakConstructorInitializers: AfterColon
BreakInheritanceList: AfterColon
BreakStringLiterals: false
ColumnLimit: 96
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerIndentWidth: 8
ContinuationIndentWidth: 8
Cpp11BracedListStyle: true
DerivePointerAlignment: false
DisableFormat: false
EmptyLineAfterAccessModifier: Never
EmptyLineBeforeAccessModifier: LogicalBlock
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: false
# git grep '^#define [^[:space:]]*for_each[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$| - '\1'|" | LC_ALL=C sort -u
ForEachMacros:
- 'list_for_each'
# git grep -i '^#define \+if[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*if[^[:space:]]*\)(.*$| - '\1'|I" | grep -v IFIX | LC_ALL=C sort -u
IfMacros:
- 'IF_CHANNEL_POPULATED'
- 'IF_DIMM_POPULATED'
- 'IF_RANK_POPULATED'
- 'IfBit0'
IncludeBlocks: Preserve
IncludeIsMainSourceRegex: ''
IndentAccessModifiers: false
IndentCaseBlocks: false
IndentCaseLabels: false
IndentExternBlock: AfterExternBlock
IndentGotoLabels: false
IndentPPDirectives: None
IndentRequiresClause: true
IndentWidth: 8
IndentWrappedFunctionNames: false
InsertBraces: false
InsertNewlineAtEOF: true
InsertTrailingCommas: None
IntegerLiteralSeparator:
Binary: 0
BinaryMinDigits: 0
Decimal: 0
DecimalMinDigits: 0
Hex: 0
HexMinDigits: 0
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
LambdaBodyIndentation: Signature
LineEnding: LF
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 8
ObjCBreakBeforeNestedBlockParam: true
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
PackConstructorInitializers: BinPack
PenaltyBreakAssignment: 10
PenaltyBreakBeforeFirstCallParameter: 30
PenaltyBreakComment: 10
PenaltyBreakFirstLessLess: 0
PenaltyBreakOpenParenthesis: 0
PenaltyBreakString: 10
PenaltyBreakTemplateDeclaration: 10
PenaltyExcessCharacter: 100
PenaltyIndentedWhitespace: 0
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
PPIndentWidth: -1
QualifierAlignment: Left
ReferenceAlignment: Pointer
ReflowComments: false
RemoveBracesLLVM: false
RemoveSemicolon: false
RequiresClausePosition: OwnLine
RequiresExpressionIndentation: OuterScope
SeparateDefinitionBlocks: Leave
ShortNamespaceLines: 1
SortIncludes: Never
SortJavaStaticImport: Before
SortUsingDeclarations: Never
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: true
SpaceAroundPointerQualifiers: Default
SpaceBeforeAssignmentOperators: true
SpaceBeforeCaseColon: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatementsExceptControlMacros
SpaceBeforeParensOptions:
AfterControlStatements: true
AfterForeachMacros: false
AfterFunctionDefinitionName: false
AfterFunctionDeclarationName: false
AfterIfMacros: false
AfterOverloadedOperator: false
AfterRequiresInClause: false
AfterRequiresInExpression: false
BeforeNonEmptyParentheses: false
SpaceBeforeRangeBasedForLoopColon: true
SpaceBeforeSquareBrackets: false
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: Never
SpacesInConditionalStatement: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInLineCommentPrefix:
Minimum: 1
Maximum: 1
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: c++17
TabWidth: 8
UseTab: ForContinuationAndIndentation
...

View File

@@ -9,7 +9,3 @@ charset = utf-8
insert_final_newline = true insert_final_newline = true
end_of_line = lf end_of_line = lf
trim_trailing_whitespace = true trim_trailing_whitespace = true
[*.sh]
indent_style = space
indent_size = 2

3
.gitmodules vendored
View File

@@ -65,6 +65,3 @@
path = util/goswid path = util/goswid
url = ../goswid url = ../goswid
branch = trunk branch = trunk
[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
path = src/vendorcode/amd/opensil/genoa_poc/opensil
url = ../opensil_genoa_poc.git

2
3rdparty/blobs vendored

2
3rdparty/fsp vendored

2
3rdparty/vboot vendored

552
AUTHORS
View File

@@ -10,212 +10,73 @@
3mdeb Embedded Systems Consulting 3mdeb Embedded Systems Consulting
9elements Agency GmbH 9elements Agency GmbH
Aamir Bohra
Aaron Durbin
Abe Levkoy
Abel Briggs
Abhinav Hardikar Abhinav Hardikar
AdaCore
Adam Liu
Adam Mills
Advanced Computing Lab, LANL Advanced Computing Lab, LANL
Advanced Micro Devices, Inc. Advanced Micro Devices, Inc.
AdaCore
AG Electronics Ltd. AG Electronics Ltd.
Ahamed Husni
Akshu Agrawal
Al Hirani
Alan Huang
AlanKY Lee
Alec Wang
Alex James
Alex Levin
Alex Miao
Alex Thiessen Alex Thiessen
Alex Züpke Alex Züpke
Alex1 Kao
Alexander Couzens Alexander Couzens
Alexander Goncharov
Alexandru Gagniuc Alexandru Gagniuc
Alexey Buyanov
Alexey Vazhnov
Alice Sell
Allen-KH Cheng
Amanda Hwang
American Megatrends International, LLC
Amersel
Amit Caleechurn
Analog Devices Inc. Analog Devices Inc.
Analogix Semiconductor Analogix Semiconductor
Anand Mistry
Anand Vaikar
Andre Heider Andre Heider
Andrew McRae
Andrew SH Cheng
Andrey Pronin
Andriy Gapon Andriy Gapon
Andy Fleming Andy Fleming
Andy Pont
Andy-ld Lu
Angel Pons Angel Pons
Anil Kumar K
Anna Karaś
Annie Chen
Anton Kochkov Anton Kochkov
Ao Zhong
Arashk Mahshidfar
Arec Kao
Ariel Fang
ARM Limited and Contributors ARM Limited and Contributors
Arthur Heymans Arthur Heymans
Asami Doi Asami Doi
Aseda Aboagye
Ashish Kumar Mishra
Ashqti
ASPEED Technology Inc. ASPEED Technology Inc.
Atheros Corporation Atheros Corporation
Atmel Corporation Atmel Corporation
Balaji Manigandan
Balázs Vinarz
BAP - Bruhnspace Advanced Projects BAP - Bruhnspace Advanced Projects
Baruch Siach
Ben Chuang
Ben Kao
Ben McMillen
Ben Zhang
Benjamin Doron
Bernardo Perez Priego
Bhanu Prakash Maiya
Bill Xie Bill Xie
Bin Meng
Bitland Tech Inc. Bitland Tech Inc.
Bob Moragues
Bora Guvendik
Boris Barbulovski Boris Barbulovski
Boris Mittelberg
Brandon Breitenstein
Brian Norris
Bryant Ou
Carl-Daniel Hailfinger Carl-Daniel Hailfinger
Casper Chang
Caveh Jalali
Cavium Inc. Cavium Inc.
Chao Gui
Chen-Tsung Hsieh
Chia-Ling Hou
Chien-Chih Tseng
Chris Wang
Christian Gmeiner
Christian Walter
Christoph Grenz Christoph Grenz
Christopher Meis
Chuangwei Technology Co., Ltd
Chun-Jie Chen
Cirrus Logic, Inc.
CK HU
Clay Daniels
Cliff Huang
Code Aurora Forum Code Aurora Forum
Compal Electronics, Inc.
Cong Yang
CoolStar
coresystems GmbH coresystems GmbH
Corey Osgood Corey Osgood
Curt Brune Curt Brune
Curtis Chen
Custom Ideas Custom Ideas
Cyberus Technology GmbH
Da Lao
Daisuke Nojiri
Damien Zammit Damien Zammit
Dan Callaghan
Daniel Campello
Daniel Gröber
Daniel Kang
Daniel Maslowski
Daniel Peng
Daniel Rosa Franzini
Dave Airlie Dave Airlie
David Brownell David Brownell
David Greenman David Greenman
David Hendricks David Hendricks
David Lin
David Milosevic
David Mosberger-Tang David Mosberger-Tang
David Mueller David Mueller
David S. Peterson David S. Peterson
David Wu
Dawei Chien
Deepika Punyamurtula
Deepti Deshatty
Denis 'GNUtoo' Carikli Denis 'GNUtoo' Carikli
Denis Dowling Denis Dowling
DENX Software Engineering DENX Software Engineering
Deomid 'rojer' Ryabkov
Derek Basehore
Derek Huang
Derek Waldner Derek Waldner
Digital Design Corporation Digital Design Corporation
Dinesh Gehlot
Divya S Sasidharan
Dmitry Ponamorev
Dmitry Torokhov
DMP Electronics Inc. DMP Electronics Inc.
Dominik Behr
Donghwa Lee Donghwa Lee
Drew Eckhardt Drew Eckhardt
Dtrain Hsu
Duan Huayang
Dun Tan
Duncan Laurie
Dynon Avionics Dynon Avionics
Ed Sharma
Eddy Lu
Edward Hill
Edward O'Callaghan Edward O'Callaghan
Edward-JW Yang
Egbert Eich Egbert Eich
Elias Souza
Eloy Degen
ELSOFT AG ELSOFT AG
Eltan B.V Eltan B.V
Eltan B.V.
Elyes Haouas Elyes Haouas
Eran Mitrani
Eric Biederman Eric Biederman
Eric Lai
Eric Peers
EricKY Cheng
EricR Lai
Erik van den Bogaert
Eswar Nallusamy Eswar Nallusamy
Ethan Tsao
Eugene Myers
Evan Green
Evgeny Zinoviev Evgeny Zinoviev
Fabian Groffen
Fabian Kunkel Fabian Kunkel
Fabio Aiuto
Fabrice Bellard Fabrice Bellard
Facebook, Inc. Facebook, Inc.
Felix Friedlander
Felix Held Felix Held
Felix Singer Felix Singer
Fengquan Chen
Flora Fu
Florian Laufenböck
Francois Toguo Fotso
Frank Chu
Frank Wu
Franklin Lin
Frans Hendriks
Fred Reitberger
Frederic Potter Frederic Potter
Free Software Foundation, Inc. Free Software Foundation, Inc.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc.
Furquan Shaikh
Gaggery Tsai
Gang C Chen
Garmin Chang
Gary Jennejohn Gary Jennejohn
George Trudeau George Trudeau
Gerald Van Baren Gerald Van Baren
@@ -223,563 +84,164 @@ Gerd Hoffmann
Gergely Kiss Gergely Kiss
Google LLC Google LLC
Greg Watson Greg Watson
Grzegorz Bernacki
Guennadi Liakhovetski Guennadi Liakhovetski
Guodong Liu
Gwendal Grignou
Hal Martin Hal Martin
Hao Chou
Hao Wang
HardenedLinux HardenedLinux
Harsha B R
Harshit Sharma
Henry C Chen
Hewlett Packard Enterprise Development LP
Hewlett-Packard Development Company, L.P. Hewlett-Packard Development Company, L.P.
Himanshu Sahdev Hewlett Packard Enterprise Development LP
Housong Zhang
Hsiao Chien Sung
Hsin-hsiung wang
Hsin-Te Yuan
Hsuan Ting Chen
Huaqin Technology Co., Ltd
Huaqin Telecom Inc. Huaqin Telecom Inc.
Hui Liu
Huijuan Xie
Hung-Te Lin
Ian Douglas Scott
Ian Feng
IBM Corporation IBM Corporation
Idwer Vollering Idwer Vollering
Igor Bagnucki
Igor Pavlov Igor Pavlov
Ikjoon Jang
Imagination Technologies Imagination Technologies
Infineon Technologies Infineon Technologies
InKi Dae InKi Dae
INSPUR Co., Ltd
Intel Corporation Intel Corporation
Inventec Corp
Iru Cai Iru Cai
Isaac Lee
Isaku Yamahata Isaku Yamahata
Ivan Chen
Ivan Vatlin Ivan Vatlin
Ivy Jian
Jack Rosenthal
Jacob Garber
Jairaj Arava
Jakub Czapiga
James Chao
James Lo
James Ye James Ye
Jamie Chen
Jamie Ryu
Jan Dabros
Jan Samek
Jan Tatje
Jason Glenesk
Jason Nein
Jason V Le
Jason Z Chen
Jason Zhao Jason Zhao
jason-ch chen
Jason-jh Lin
Jay Patel
Jeff Chase
Jeff Daly
Jeff Li
Jérémy Compostella
Jeremy Soller
Jes Klinke
Jesper Lin
Jessy Jiang
Jett Rink
Jg Daolongzhu
Jian Tong
Jianeng Ceng
Jianjun Wang
Jim Lai
Jimmy Su
Jincheng Li
Jingle Hsu
Jitao Shi
Joe Pillow Joe Pillow
Joe Tessler
Joel Kitching
Joey Peng
Johanna Schander Johanna Schander
John Su
John Zhao
Johnny Li
Johnny Lin
johnson wang
Jon Murphy
Jonas 'Sortie' Termansen Jonas 'Sortie' Termansen
Jonas Loeffelholz
Jonathan A. Kollasch Jonathan A. Kollasch
Jonathan Neuschäfer Jonathan Neuschäfer
Jonathan Zhang
Jonathon Hall
Jordan Crouse Jordan Crouse
Jörg Mische Jörg Mische
Joseph Smith Joseph Smith
Josie Nordrum
Julia Tsai
Julian Schroeder
Julian Stecklina
Julien Viard de Galbert
Julius Werner
Kacper Stojek
Kaiyen Chang
Kane Chen
Kangheui Won
Kapil Porwal
Karol Zmyslowski
Karthik Ramasubramanian
Keith Hui Keith Hui
Keith Packard Keith Packard
Kenneth Chan
Kevin Chang
Kevin Cheng
Kevin Chiu
Kevin Chowski
Kevin Cody-Little Kevin Cody-Little
Kevin Keijzer
Kevin O'Connor Kevin O'Connor
Kevin3 Yang
kewei xu
Kilari Raasi
Kirk Wang
Konrad Adamczyk
Kontron Europe GmbH Kontron Europe GmbH
Kornel Dulęba
Krishna P Bhat D
Krystian Hebel
Kshitij Kshitij
Kshitiz Godara
Kulkarni. Srinivas
Kun Liu
Kyle Lin
Kyösti Mälkki Kyösti Mälkki
Lance Zhao
Lawrence Chang
Leah Rowe Leah Rowe
Lean Sheng Tan
Lei Wen Lei Wen
Lenovo Group Ltd
Leo Chou
Li-Ta Lo Li-Ta Lo
Liam Flaherty
Libra Li Libra Li
Libretrend LDA Libretrend LDA
Lijian Zhao
Liju-Clr Chen
Linaro Limited Linaro Limited
linear
Linus Torvalds Linus Torvalds
Linux Networx, Inc. Linux Networx, Inc.
LiPPERT ADLINK Technology GmbH LiPPERT ADLINK Technology GmbH
Liya Li
Lubomir Rintel Lubomir Rintel
Luc Verhaegen Luc Verhaegen
Lucas Chen
Mac Chiang
Maciej Matuszczyk Maciej Matuszczyk
Maciej Pijanowski
Macpaul Lin
Madhusudanarao Amara
Magf
Malik Hsu
Mandy Liu
Manoj Gupta
Marc Bertens Marc Bertens
Marc Jones Marc Jones
Marco Chen
Marek Kasiewicz
Marek Vasut Marek Vasut
Mario Scheithauer
Marius Gröger Marius Gröger
Mariusz Szafranski
Mariusz Szafrański
Mark Hasemeyer
Mark Hsieh
Mars Chen
Marshall Dawson
Martin Mares Martin Mares
Martin Renters Martin Renters
Martin Roth Martin Roth
Marvell International Ltd. Marvell International Ltd.
Marvell Semiconductor Inc. Marvell Semiconductor Inc.
Marx Wang
Masanori Ogino
Máté Kukri
Matei Dibu
Mathew King
Matt Chen
Matt Delco
Matt DeVillier Matt DeVillier
Matt Papageorge
Matthew Blecker
Matthew Ziegelbaum
Mattias Nissler
Maulik V Vaghela
MAULIK V VAGHELA
Maulik Vaghela
Max Fritz
Maxim Polyakov Maxim Polyakov
Maximilian Brune
Mediatek Inc.
MediaTek Inc. MediaTek Inc.
Meera Ravindranath
Meng-Huan Yu
Meta Platforms, Inc
mgabryelski1
Mice Lin
Michael Brunner Michael Brunner
Michael Büchler
Michael Niewöhner
Michael Schroeder Michael Schroeder
Michael Strosche Michael Niewöhner
Michael Walle
Michał Kopeć
Michal Suchanek
Michał Żygowski
Micro-Star INT'L CO., LTD.
Mika Westerberg Mika Westerberg
Mike Banon
Mike Shih
Miriam Polzer
mkurumel
Moises Garcia
Mondrian Nuessle Mondrian Nuessle
Monikaanan
MontaVista Software, Inc. MontaVista Software, Inc.
Morgan Jang
Moritz Fischer
Morris Hsu
mtk15698
mturney mturney
Musse Abdullahi
Myles Watson Myles Watson
Nancy.Lin
Naresh Solanki
Nathan Lu
Neill Corlett
Network Appliance Inc. Network Appliance Inc.
Nicholas Chin
Nicholas Sielicki Nicholas Sielicki
Nick Barker Nick Barker
Nick Chen
Nick Vaccaro
Nico Huber Nico Huber
Nico Rikken Nico Rikken
Nicola Corna Nicola Corna
Nicolas Boichat
Nicole Faerber
Nikolai Vyssotski
Nils Jacobs Nils Jacobs
Nina Wu
Nir Tzachar Nir Tzachar
Nokia Corporation Nokia Corporation
Nuvoton Technology Corporation
NVIDIA Corporation NVIDIA Corporation
Olivier Langlois Olivier Langlois
Ollie Lo Ollie Lo
Omar Pakker Omar Pakker
Online SAS Online SAS
Opal Voravootivat
Orion Technologies, LLC Orion Technologies, LLC
Pablo Ceballos
Pablo Stebler
Pan Gao
Patrick Georgi Patrick Georgi
Patrick Huang
Patrick Rudolph Patrick Rudolph
Patrik Tesarik
Pattrick Hueper Pattrick Hueper
Paul Fagerburg
Paul Menzel
Paul2 Huang
Paulo Alcantara Paulo Alcantara
Pavel Sayekat Pavel Sayekat
Paz Zcharya
PC Engines GmbH PC Engines GmbH
Pegatron Corp
Peichao Li
Per Odlund Per Odlund
Peter Korsgaard Peter Korsgaard
Peter Lemenkov
Peter Marheine
Peter Stuge Peter Stuge
Petr Cvek
Philip Chen
Philipp Bartsch
Philipp Degler Philipp Degler
Philipp Deppenwiese Philipp Deppenwiese
Philipp Hug Philipp Hug
Piotr Kleinschmidt
Po Xu
Prasad Malisetty
Prashant Malani
Pratik Vishwakarma
Pratikkumar Prajapati
Pratikkumar V Prajapati
Protectli Protectli
Purism SPC Purism SPC
Purism, SPC Qualcomm Technologies
Qii Wang
Qualcomm Technologies, Inc.
Quanta Computer INC
Raihow Shi
Rajat Jain
Rajesh Patil
Raptor Engineering, LLC Raptor Engineering, LLC
Rasheed Hsueh
Raul Rangel
Ravi Kumar
Ravi Mistry
Ravindra
Ravishankar Sarawadi
Ray Han Lim Ng
Raymond Chung
Red Hat, Inc Red Hat, Inc
ReddestDream
Rehan Ghori
Reinhard Meyer Reinhard Meyer
Reka Norman
Ren Kuo
Renze Nicolai Renze Nicolai
Reto Buerki
Rex Chou
Rex-BC Chen
Ricardo Quesada
Ricardo Ribalda
Richard Spiegel Richard Spiegel
Richard Woodruff Richard Woodruff
Rick Lee
Ricky Chang
Riku Viitanen
Ritul Guru
Rizwan Qureshi
Rnhmjoj
Rob Barnes
Rob Landley Rob Landley
Robert Chen
Robert Reeves Robert Reeves
Robert Zieba
Robinson P. Tryon Robinson P. Tryon
Rockchip, Inc. Rockchip, Inc.
Rocky Phagura
Roger Lu
Roja Rani Yarubandi
Romain Lievin Romain Lievin
Roman Zippel Roman Zippel
Ron Lee
Ron Minnich
Ronak Kanabar
Ronald G. Minnich Ronald G. Minnich
Rory Liu
Rudolf Marek Rudolf Marek
Rui Zhou
Ruihai Zhou
Runyang Chen
Russell King Russell King
Ruud Schramp Ruud Schramp
Ruwen Liu
Ryan Chuang
Ryan Lin
Sage Electronic Engineering, LLC Sage Electronic Engineering, LLC
Sajida Bhanu
Sam Lewis
Sam McNally
Sam Ravnborg Sam Ravnborg
Samsung Electronics Samsung Electronics
Samuel Holland Samuel Holland
Sandeep Maheswaram
Sathya Prakash M R
Satya Priya Kakitapalli
Saurabh Mishra
SciTech Software, Inc. SciTech Software, Inc.
Scott Chao Sebastian Grzywna
SDC Systems Ltd
Sean Rhodes
Sebastian 'Swift Geek' Grzywna
secunet Security Networks AG secunet Security Networks AG
Selma Bensaid
Semihalf
Sen Chu
Sencore Inc Sencore Inc
Sergej Ivanov Sergej Ivanov
Sergii Dmytruk
Serin Yeh
Seven Lee
SH Kim
Shahina Shaik
Shaocheng Wang
Shaoming Chen
Shaunak Saha
Shelley Chen
Shelly Chang
Sheng-Liang Pan
Shiyu Sun
Shon Wang
Shou-Chieh Hsu
Shreesh Chhabbi
Shuo Liu
Siemens AG Siemens AG
SiFive, Inc SiFive, Inc
Silicom Ltd.
Silicon Integrated System Corporation Silicon Integrated System Corporation
Silverback Ltd. Silverback Ltd.
Simon Glass
Simon Yang
Simon Zhou
Sindhoor Tilak
Solomon Alan-Dei
Song Fan
Sridhar Siricilla
Srinidhi N Kaushik
Srinivasa Rao Mandadapu
ST Microelectronics
Stanley Wu
Star Labs Online Ltd
Stefan Binding
Stefan Ott
Stefan Reinauer Stefan Reinauer
Stefan Tauner Stefan Tauner
Stephen Edworthy
Steve Magnani Steve Magnani
Steve Shenton Steve Shenton
Subrata Banik ST Microelectronics
Sudheer Amrabadi
Sugnan Prabhu S
Sukumar Ghorai
Sumeet R Pawnikar
Sunwei Li
SUSE LINUX AG SUSE LINUX AG
Sven Schnelle Sven Schnelle
Syed Mohammed Khasim Syed Mohammed Khasim
System76, Inc. System76
szarpaj
T Michael Turney
TangYiwei
Taniya Das
Tao Xia
Tarun Tuli
Teddy Shih
Terry Chen
Texas Instruments Texas Instruments
The Android Open Source Project The Android Open Source Project
The ChromiumOS Authors The ChromiumOS Authors
The Linux Foundation The Linux Foundation
The Regents of the University of California The Regents of the University of California
Thejaswani Putta
Thomas Heijligen
Thomas Winischhofer Thomas Winischhofer
Tim Chen
Tim Chu
Tim Crawford
Tim Van Patten
Tim Wawrzynczak
Timofey Komarov
Timothy Pearson Timothy Pearson
tinghan shen
Tobias Diedrich Tobias Diedrich
Tom Hiller
Tommie Lin
Tony Huang
Tracy Wu
Trevor Wu
Tristan Corrick Tristan Corrick
Tungsten Graphics, Inc. Tungsten Graphics, Inc.
Tyan Computer Corp. Tyan Computer Corp.
Tyler Wang
Tzung-Bi Shih
U.S. National Security Agency
ucRobotics Inc. ucRobotics Inc.
Uday Bhat
University of Heidelberg University of Heidelberg
Usha P
Uwe Hermann Uwe Hermann
Uwe Poeche
V Sowmya
Václav Straka
Vadim Bendebury
Van Chen
Varshit B Pandya
Veerabhadrarao Badiganti
Venkat Thogaru
Venkata Krishna Nimmagadda
VIA Technologies, Inc VIA Technologies, Inc
Victor Ding
Vidya Gopalakrishnan
Vikram Narayanan Vikram Narayanan
Vikrant L Jadeja
Vinod Polimera
Vipin Kumar Vipin Kumar
Vitaly Rodionov
Vladimir Serbinenko Vladimir Serbinenko
Vlado Cibic Vlado Cibic
Vsujithk
Wang Qing Pei Wang Qing Pei
Wanghao11
Ward Vandewege Ward Vandewege
Wayne Wang
Weimin Wu
Weiyi Lu
Wenbin Mei
Wentao Qin
Werner Zeh
Wilbert Duijvenvoorde Wilbert Duijvenvoorde
William Wei
Wilson Chou
Wim Vervoorn
Win Enterprises Win Enterprises
Wisley Chen
Wistron Corp
Wiwynn Corp. Wiwynn Corp.
Wiwynn Corporation
Wizard Shen
Wojciech Macek
Wolfgang Denk Wolfgang Denk
Won Chung
Wonkyu Kim
Wuxy
Xin Ji
Xixi Chen
Xuxin Xiong
YADRO YADRO
Yan Liu
Yann Collet Yann Collet
Yaroslav Kurlaev
YH Lin
Yidi Lin
Yilin Yang
Yinghai Lu Yinghai Lu
Yolk Shih
Yong Zhi
Yongkun Yu
Yongqiang Niu
Yu-hsuan Hsu
Yu-Ping Wu
Yuanliding
Yuchen He
Yuchen Huang
Yunlong Jia
Zachary Yedidia Zachary Yedidia
Zanxi Chen
Zhanyong Wang
Zheng Bao
Zhenguo Li
Zhi7 Li
Zhiqiang Ma
Zhixing Ma
Zhiyong Tao
zhongtian wu
Zhuohao Lee
Ziang Wang
Zoey Wu
Zoltan Baldaszti
小田喜陽彦
陳建宏

View File

@@ -4,21 +4,47 @@
# hacked together by Stefan Reinauer <stepan@openbios.org> # hacked together by Stefan Reinauer <stepan@openbios.org>
# #
BUILDDIR ?= _build PDFLATEX=pdflatex -t a4
SPHINXOPTS ?= -j auto
export SPHINXOPTS FIGS=codeflow.pdf hypertransport.pdf
all: sphinx all: corebootPortingGuide.pdf
$(BUILDDIR): SVG2PDF=$(shell command -v svg2pdf)
mkdir -p $(BUILDDIR) INKSCAPE=$(shell command -v inkscape)
CONVERT=$(shell command -v convert)
sphinx: $(BUILDDIR) codeflow.pdf: codeflow.svg
$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)" ifneq ($(strip $(SVG2PDF)),)
svg2pdf $< $@
else ifneq ($(strip $(INKSCAPE)),)
inkscape $< --export-pdf=$@
else ifneq ($(strip $(CONVERT)),)
convert $< $@
endif
hypertransport.pdf: hypertransport.svg
ifneq ($(strip $(SVG2PDF)),)
svg2pdf $< $@
else ifneq ($(strip $(INKSCAPE)),)
inkscape $< --export-pdf=$@
else ifneq ($(strip $(CONVERT)),)
convert $< $@
endif
corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
# 2 times to make sure we have a current toc.
$(PDFLATEX) corebootBuildingGuide.tex
$(PDFLATEX) corebootBuildingGuide.tex
corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
$(PDFLATEX) corebootBuildingGuide.tex
sphinx:
$(MAKE) -f Makefile.sphinx html
clean-sphinx: clean-sphinx:
$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)" $(MAKE) -f Makefile.sphinx clean
clean: clean-sphinx clean: clean-sphinx
rm -f *.aux *.idx *.log *.toc *.out $(FIGS) rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
@@ -26,25 +52,5 @@ clean: clean-sphinx
distclean: clean distclean: clean
rm -f corebootPortingGuide.pdf rm -f corebootPortingGuide.pdf
livesphinx: $(BUILDDIR) livesphinx:
$(MAKE) -f Makefile.sphinx livehtml BUILDDIR="$(BUILDDIR)" $(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)"
test:
@echo "Test for logging purposes - Failing tests will not fail the build"
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
help:
@echo "all - Builds all documentation targets"
@echo "sphinx - Builds html documentation in _build directory"
@echo "clean - Cleans intermediate files"
@echo "clean-sphinx - Removes sphinx output files"
@echo "distclean - Removes PDF files as well"
@echo "test - Runs documentation tests"
@echo
@echo " Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
@echo
@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
.phony: help livesphinx sphinx test
.phony: distclean clean clean-sphinx

View File

@@ -11,9 +11,6 @@ upwards.
- [GPIO toggling in ACPI AML](gpio.md) - [GPIO toggling in ACPI AML](gpio.md)
## Windows-specific ACPI documentation
- [Windows-specific documentation](windows.md)
## ACPI specification - Useful links ## ACPI specification - Useful links

View File

@@ -1,9 +0,0 @@
# Testing ACPI changes under Windows
When testing ACPI changes in coreboot against Windows 8 or newer, beware that
during a normal boot after a clean shutdown, Windows will use the fast startup
mechanism which results in it not evaluating the changed ACPI code but instead
using some cached version which won't include the changes that were supposed to
be tested. In order for Windows to actually use the new ACPI tables, either
disable the fast startup or just tell Windows to do a reboot which will make it
read and use the ACPI tables in memory instead of an outdated cached version.

View File

@@ -1,5 +1,7 @@
# Firmware and Computer Acronyms, Initialisms and Definitions # Firmware and Computer Acronyms, Initialisms and Definitions
** Note that this document even more of a work in progress than most **
** of the coreboot documentation **
## _0-9 ## _0-9
@@ -18,25 +20,24 @@ Spec](https://uefi.org/specifications) for details, or run the tool
initialization that happens from the PSP. Significantly, Memory initialization that happens from the PSP. Significantly, Memory
Initialization. Initialization.
* AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current) * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)
* Ack - Acknowledgment / Acknowledged * Ack - Acknowledgment
* ACM [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html) * ACM [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html)
* ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power) * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power)
* ACPI - The [**Advanced Configuration and Power * ACPI - The [**Advanced Configuration and Power
Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface) Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface)
is an industry standard for letting the OS control power management. is an industry standard for letting the OS control power management.
* [https://uefi.org/specifications](https://uefi.org/specifications) * [http://www.acpi.info/](http://www.acpi.info/)
* [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html) * [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html)
* ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter) * ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter)
* ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake) * ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake)
* AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard) * AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)
* AESKL - Intel: AES Key Locker
* AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_) * AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_)
* AGP - The [**Accelerated Graphics * AGP - The [**Accelerated Graphics
Port**](https://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an Port**](http://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
older (1997-2004) point-to-point bus for video cards to communicate older (1997-2004) point-to-point bus for video cards to communicate
with the processor. with the processor.
* AHCI - The [**Advanced Host Controller * AHCI - The [**Advanced Host Controller
Interface**](https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface) Interface**](http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
is a standard register set for communicating with a SATA controller. is a standard register set for communicating with a SATA controller.
* [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm) * [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm)
* [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf) * [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf)
@@ -50,11 +51,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
An open standard to connect and manage functional blocks in an SoC An open standard to connect and manage functional blocks in an SoC
(System on a Chip) (System on a Chip)
* AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64) * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
* AMD-Vi AMD: The AMD name for their IOMMU implementation
* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
SBI: Sideband Interface SBI: Sideband Interface
* AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology) * AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology)
* ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute) * ANSI - [**American National Standards Institute**](American_National_Standards_Institute)
* AOAC - AMD: Always On, Always Connected * AOAC - AMD: Always On, Always Connected
* AP - Application processor - The main processor on the board (as * AP - Application processor - The main processor on the board (as
opposed to the embedded controller or other processors that may be on opposed to the embedded controller or other processors that may be on
@@ -63,7 +63,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* APCB - AMD: AMD PSP Customization Block * APCB - AMD: AMD PSP Customization Block
* API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API) * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
* APIC - [**Advanced Programmable Interrupt * APIC - [**Advanced Programmable Interrupt
Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller) Controller**](http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
this is an advanced version of a PIC that can handle interrupts from this is an advanced version of a PIC that can handle interrupts from
and for multiple CPUs. Modern systems usually have several APICs: and for multiple CPUs. Modern systems usually have several APICs:
Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound. Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
@@ -98,7 +98,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## B ## B
* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the * BAR - [**Base Address Register**](http://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
base address registers in the PCI config space of a PCI device base address registers in the PCI config space of a PCI device
* Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named * Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named
after Émile Baudot after Émile Baudot
@@ -117,7 +117,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
the entire 4GiB of the 32-bit address space. Also known as flat mode the entire 4GiB of the 32-bit address space. Also known as flat mode
or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode). or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode).
* BIOS - [**Basic Input/Output * BIOS - [**Basic Input/Output
System**](https://en.wikipedia.org/wiki/BIOS) System**](http://en.wikipedia.org/wiki/BIOS)
* BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on * BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on
itself when it is first started. Usually, any nonzero value indicates itself when it is first started. Usually, any nonzero value indicates
that the selftest failed. that the selftest failed.
@@ -183,7 +183,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
generally used to describe a section of NVRAM (Non-volatile RAM), in generally used to describe a section of NVRAM (Non-volatile RAM), in
this case a section battery-backed memory in the RTC (Real Time Clock) this case a section battery-backed memory in the RTC (Real Time Clock)
that is typically used to store BIOS settings. that is typically used to store BIOS settings.
*[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory) *[http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
* CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont) * CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont)
* CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi) * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged. * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
@@ -191,14 +191,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CPPC - AMD: Collaborative Processor Performance Controls * CPPC - AMD: Collaborative Processor Performance Controls
* CPS - Characters Per Second * CPS - Characters Per Second
* CPU - [**Central Processing * CPU - [**Central Processing
Unit**](https://en.wikipedia.org/wiki/Central_processing_unit) Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode * CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
* Cr50 - Google: The first generation Google Security Chip (GSC) used on * Cr50 - Google: The first generation Google Security Chip (GSC) used on
ChromeOS devices. ChromeOS devices.
* CRB - Customer Reference Board * CRB - Customer Reference Board
* CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
(End-of-Line) marker. (End-of-Line) marker.
* crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0) * crt0 - [**C Run Time 0**](http://en.wikipedia.org/wiki/Crt0)
* crt0s - crt0 Source code * crt0s - crt0 Source code
* CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube) * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
* CSE - Intel: Converged Security Engine * CSE - Intel: Converged Security Engine
@@ -207,7 +207,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CSME - Intel: Converged Security and Management Engine * CSME - Intel: Converged Security and Management Engine
* CTLE - Intel: Continuous Time Linear Equalization * CTLE - Intel: Continuous Time Linear Equalization
* CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures) * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
* CXMT - ChangXin Memory Technologies
* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h * CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
@@ -226,9 +225,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
still has power. still has power.
* D3 Cold - ACPI Device power state: Power is completely removed from * D3 Cold - ACPI Device power state: Power is completely removed from
the device. the device.
* DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_for_System_Hardware) * DASH - [**Desktop and mobile Architecture for System Hardware**](Desktop_and_mobile_Architecture_for_System_Hardware)
* DB - DaughterBoard * DB - DaughterBoard
* DbC - USB: Debug Capability on the USB host controller
* DC - Electricity: Direct Current * DC - Electricity: Direct Current
* DCP - Digital Content Protection * DCP - Digital Content Protection
* DCR - **Decode Control Register** This is a way of identifying the * DCR - **Decode Control Register** This is a way of identifying the
@@ -244,7 +242,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM) * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
* DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package) * DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package)
* DMA - [**Direct Memory * DMA - [**Direct Memory
Access**](https://en.wikipedia.org/wiki/Direct_memory_access) Allows Access**](http://en.wikipedia.org/wiki/Direct_memory_access) Allows
certain hardware subsystems within a computer to access system memory certain hardware subsystems within a computer to access system memory
for reading and/or writing independently of the main CPU. Examples of for reading and/or writing independently of the main CPU. Examples of
systems that use DMA: Hard Disk Controller, Disk Drive Controller, systems that use DMA: Hard Disk Controller, Disk Drive Controller,
@@ -252,7 +250,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
computers, as it allows devices of different speeds to communicate computers, as it allows devices of different speeds to communicate
without subjecting the CPU to a massive interrupt load. without subjecting the CPU to a massive interrupt load.
* DMI - Direct Media Interface is a link/bus between CPU and PCH. * DMI - Direct Media Interface is a link/bus between CPU and PCH.
* DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface) * DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
* DMIC - Digital Microphone * DMIC - Digital Microphone
* DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force) * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
* DMZ - Demilitarized Zone * DMZ - Demilitarized Zone
@@ -261,7 +259,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DOS - Disk Operating System * DOS - Disk Operating System
* DP - DisplayPort * DP - DisplayPort
* DPM - Mediatek: DRAM Power Manager * DPM - Mediatek: DRAM Power Manager
* DPTC - AMD: Dynamic Power and Thermal Control
* DPTF - Intel: Dynamic Power and Thermal Framework * DPTF - Intel: Dynamic Power and Thermal Framework
* DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory) * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
* DRTM - Dynamic Root of Trust for Measurement * DRTM - Dynamic Root of Trust for Measurement
@@ -288,7 +285,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
vs Integrated TPMs or fTPMs (Firmware TPMs). vs Integrated TPMs or fTPMs (Firmware TPMs).
* DTS - U-Boot: Device Tree Source * DTS - U-Boot: Device Tree Source
* DUT - Device Under Test * DUT - Device Under Test
* DvC - USB: Debug Capability on the USB Device (Device Capability)
* DVFS - ARM: Dynamic Voltage and Frequency Scaling * DVFS - ARM: Dynamic Voltage and Frequency Scaling
* DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface) * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
* DVT - Production Timeline: Design Validation Test * DVT - Production Timeline: Design Validation Test
@@ -301,13 +297,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## E ## E
* EAPD - Intel: [**External Amplifier Power Down**](https://web.archive.org/web/20210203194800/https://www.eeweb.com/hd-audio-eapd/)
* EBDA - Extended BIOS Data Area * EBDA - Extended BIOS Data Area
* EBG - Intel: Emmitsburg PCH * EBG - Intel: Emmitsburg PCH
* ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
memory that can detect and correct memory errors. memory that can detect and correct memory errors.
* EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data) * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
* EDK2 - EFI Development Kit 2 * edk2 - EFI Development Kit 2
* EDO - Memory: [**Extended Data * EDO - Memory: [**Extended Data
Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM) Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
- A DRAM standard introduced in 1994 that improved upon, but was - A DRAM standard introduced in 1994 that improved upon, but was
@@ -329,7 +324,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* EOL - End of Life * EOL - End of Life
* EPP - Intel: Energy-Performance Preference * EPP - Intel: Energy-Performance Preference
* EPROM - Erasable Programmable Read-Only Memory * EPROM - Erasable Programmable Read-Only Memory
* EROFS - Linux: [**Enhanced Read-Only File System**](https://en.wikipedia.org/wiki/EROFS)
* ESD - Electrostatic discharge * ESD - Electrostatic discharge
* eSPI - Enhanced System Peripheral Interface * eSPI - Enhanced System Peripheral Interface
* EVT - Production Timeline: Engineering Validation Test * EVT - Production Timeline: Engineering Validation Test
@@ -340,7 +334,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FADT - ACPI Table: Fixed ACPI Description Table * FADT - ACPI Table: Fixed ACPI Description Table
* FAE - Field Application Engineer * FAE - Field Application Engineer
* FAT - File Allocation Table * FAT - File Allocation Table
* FBVDDQ - Nvidia Power: Framebuffer Voltage
* FCH - AMD: Firmware Control Hub * FCH - AMD: Firmware Control Hub
* FCS - Production Timeline: First Customer Shipment * FCS - Production Timeline: First Customer Shipment
* FDD - Floppy Disk Drive * FDD - Floppy Disk Drive
@@ -358,7 +351,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FPDT - ACPI: Firmware Performance Data Table * FPDT - ACPI: Firmware Performance Data Table
* FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array) * FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
* Framebuffer - The * Framebuffer - The
[**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part [**framebuffer**](http://en.wikipedia.org/wiki/Framebuffer) is a part
of RAM in a computer which is allocated to hold the graphics of RAM in a computer which is allocated to hold the graphics
information for one frame or picture. This information typically information for one frame or picture. This information typically
consists of color values for every pixel on the screen. A framebuffer consists of color values for every pixel on the screen. A framebuffer
@@ -370,15 +363,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM) - A DRAM standard introduced in 1990. * FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM) - A DRAM standard introduced in 1990.
* FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit) * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
* FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus) * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
* FSM - Finite State Machine
* FSP - Intel: Firmware Support Package * FSP - Intel: Firmware Support Package
* FSR - Intel: Firmware Status Register * FSR - Intel: Firmware Status Register
* FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol) * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is * fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is
based in firmware instead of actual hardware. It typically runs in based in firmware instead of actual hardware. It typically runs in
some sort of TEE (Trusted Execution Environment). some sort of TEE (Trusted Execution Environment).
* FWCM Intel: firmware Connection Manager
* FWID - Firmware Identifier
## G ## G
@@ -399,7 +389,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* GMA - Intel: [**Graphics Media * GMA - Intel: [**Graphics Media
Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA) Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
* GNB - Graphics NorthBridge * GNB - Graphics NorthBridge
* GND - Power: Ground
* GNVS - Global Non-Volatile Storage * GNVS - Global Non-Volatile Storage
* GPD - PCH GPIO in Deep Sleep well (D5 power) * GPD - PCH GPIO in Deep Sleep well (D5 power)
* GPE - ACPI: General Purpose Event * GPE - ACPI: General Purpose Event
@@ -416,28 +405,23 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips * GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
* GSPI - Generic SPI - These are SPI controllers available for general * GSPI - Generic SPI - These are SPI controllers available for general
use, not dedicated to flash, for example. use, not dedicated to flash, for example.
* GTDT - ACPI: Generic Timer Description Table
* GTT - [**Graphics Translation Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
* GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier) * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
## H ## H
* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank area past the end of the scanline
* HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio) * HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio)
* HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection) * HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection)
* HDD - Hard Disk Drive * HDD - Hard Disk Drive
* HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI) * HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI)
* HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range) * HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range)
* HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interface) (Replaced by MEI) * HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interface) (Replaced by MEI)
* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank before the start of the next scanline.
* HID - [**Human Interface * HID - [**Human Interface
Device**](https://en.wikipedia.org/wiki/Human_interface_device) Device**](https://en.wikipedia.org/wiki/Human_interface_device)
* HOB - UEFI: Hand-Off Block * HOB - UEFI: Hand-Off Block
* HPD - Hot-Plug Detect * HPD - Hot-Plug Detect
* HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer) * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
* HSP - AMD: Hardware Security Processor * HSP - AMD: Hardware Security Processor
* HSPHY - USB: USB3 High-Speed PHY
* HSTI - Hardware Security Test Interface * HSTI - Hardware Security Test Interface
* HSW - Intel: Haswell * HSW - Intel: Haswell
* Hybrid S3 - System Power State: This is where the operating system * Hybrid S3 - System Power State: This is where the operating system
@@ -446,7 +430,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
resume quickly from S3 if the system stays powered, and resume from resume quickly from S3 if the system stays powered, and resume from
the disk if power is lost. the disk if power is lost.
* Hypertransport - AMD: The * Hypertransport - AMD: The
[**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus [**Hypertransport**](http://en.wikipedia.org/wiki/Hypertransport) bus
is an older (2001-2017) high-speed electrical interconnection protocol is an older (2001-2017) high-speed electrical interconnection protocol
specification between CPU, Memory, and (occasionally) peripheral specification between CPU, Memory, and (occasionally) peripheral
devices. This was originally called the Lightning Data Transport devices. This was originally called the Lightning Data Transport
@@ -467,7 +451,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
- Also known as SenseWire - Also known as SenseWire
* IA - Intel Architecture * IA - Intel Architecture
* IA-64 - Intel Itanium 64-bit architecture * IA-64 - Intel Itanium 64-bit architecture
* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus atomic instructions, single precision floating point instructions, and compressed instructions
* IBB Initial Boot Block * IBB Initial Boot Block
* IBV - Independent BIOS Vendor * IBV - Independent BIOS Vendor
* IC - Integrated Circuit * IC - Integrated Circuit
@@ -485,7 +468,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric) Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
is a superset of AMD's earlier Hypertransport interconnect. is a superset of AMD's earlier Hypertransport interconnect.
* IFD - Intel: Intel Flash Descriptor * IFD - Intel: Intel Flash Descriptor
* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus integer multiply & divide, atomic instructions, single precision floating point instructions, and compressed instructions
* IMC - AMD: Integrated micro-controller - An 8051 microcontroller built * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips. into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
This never worked well for anything beyond fan control and caused This never worked well for anything beyond fan control and caused
@@ -497,7 +479,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* IoC - Security: Indicator of Compromise * IoC - Security: Indicator of Compromise
* IOC - Intel: I/O Cache * IOC - Intel: I/O Cache
* IOE - Intel: I/O Expander * IOE - Intel: I/O Expander
* IOHC - AMD: I/O Hub Controller
* IOM - Intel: I/O Manager * IOM - Intel: I/O Manager
* IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit) * IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit)
* IOMUX - AMD: The I/O Mux block controls how each GPIO is configured. * IOMUX - AMD: The I/O Mux block controls how each GPIO is configured.
@@ -598,14 +579,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MBR - Master Boot Record * MBR - Master Boot Record
* MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture) * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
* MCR - Machine Check Registers * MCR - Machine Check Registers
* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
* MCU - Memory Control Unit * MCU - Memory Control Unit
* MCU - [**MicroController * MCU - [**MicroController
Unit**](https://en.wikipedia.org/wiki/Microcontroller) Unit**](https://en.wikipedia.org/wiki/Microcontroller)
* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM SRAM at system initialization. * MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
* MDFIO - Intel: Multi-Die Fabric IO * MDFIO - Intel: Multi-Die Fabric IO
* MDN - AMD: Mendocino * MDN - AMD: Mendocino
* mDP - Mini DisplayPort connector
* ME - Intel: Management Engine * ME - Intel: Management Engine
* MEI - Intel: ME Interface (Previously known as HECI) * MEI - Intel: ME Interface (Previously known as HECI)
* Memory training - the process of finding the best speeds, voltages, * Memory training - the process of finding the best speeds, voltages,
@@ -622,7 +601,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MKBP - Matrix Keyboard Protocol * MKBP - Matrix Keyboard Protocol
* MMC - [**MultiMedia * MMC - [**MultiMedia
Card**](https://en.wikipedia.org/wiki/MultiMediaCard) Card**](https://en.wikipedia.org/wiki/MultiMediaCard)
* MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO) * MMIO - [**Memory Mapped I/O**](http://en.wikipedia.org/wiki/MMIO)
allows peripherals' memory or registers to be accessed directly allows peripherals' memory or registers to be accessed directly
through the memory bus. When the memory bus size was very small, this through the memory bus. When the memory bus size was very small, this
was initially done by hiding any memory at that address, effectively was initially done by hiding any memory at that address, effectively
@@ -649,17 +628,16 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MSB - Most Significant Bit * MSB - Most Significant Bit
* MSI - Message Signaled Interrupt * MSI - Message Signaled Interrupt
* MSR - Machine-Specific Register * MSR - Machine-Specific Register
* MTS or MT/s - MegaTransfers per second * MT/s - MegaTransfers per second
* MTL - Intel: Meteor Lake * MTL - Intel: Meteor Lake
* MTL - ARM: MHU Transport Layer * MTL - ARM: MHU Transport Layer
* MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR) * MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
allows to set the cache behaviour on memory access in x86. Basically, allows to set the cache behaviour on memory access in x86. Basically,
it tells the CPU how to cache certain ranges of memory it tells the CPU how to cache certain ranges of memory
(e.g. write-through, write-combining, write-back...). Memory ranges (e.g. write-through, write-combining, write-back...). Memory ranges
are specified over physical address ranges. In Linux, they are visible are specified over physical address ranges. In Linux, they are visible
over `/proc/mtrr` and they can be modified there. For further over `/proc/mtrr` and they can be modified there. For further
information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html). information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
* MXM - PCIe: [**Mobile PCI Express Module**](https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module)
## N ## N
@@ -685,7 +663,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* NVME - Non-Volatile Memory Express - An SSD interface that allows * NVME - Non-Volatile Memory Express - An SSD interface that allows
access to the flash memory through a PCIe bus. access to the flash memory through a PCIe bus.
* NVPCF - Nvidia Platform and Control Framework * NVPCF - Nvidia Platform and Control Framework
* NVVDD - Nvidia Power: Core voltage
* NX - No Execute * NX - No Execute
@@ -731,17 +708,17 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PCD - UEFI: Platform Configuration Database * PCD - UEFI: Platform Configuration Database
* PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub) * PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub)
* PCI - [**Peripheral Control * PCI - [**Peripheral Control
Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect) Interconnect**](http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
- Replaced generally by PCIe (PCI Express) - Replaced generally by PCIe (PCI Express)
* PCI Configuration Space - The [**PCI Config * PCI Configuration Space - The [**PCI Config
space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an space**](http://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
[address space](https://en.wikipedia.org/wiki/Address_space) for all [address space](https://en.wikipedia.org/wiki/Address_space) for all
PCI devices. Originally, this address space was accessed through an PCI devices. Originally, this address space was accessed through an
index/data pair by writing the address that you wanted to read/write index/data pair by writing the address that you wanted to read/write
into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC. into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC.
This has been updated to an MMIO method which increases each PCI This has been updated to an MMIO method which increases each PCI
function's configuration space from 256 bytes to 4K. function's configuration space from 256 bytes to 4K.
* PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express) * PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
* PCMCIA: Personal Computer Memory Card International Association * PCMCIA: Personal Computer Memory Card International Association
* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso) * PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
* PCR: TPM: Platform Configuration Register * PCR: TPM: Platform Configuration Register
@@ -755,9 +732,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PEI - UEFI: Pre-EFI Initialization * PEI - UEFI: Pre-EFI Initialization
* PEIM - UEFI: PEI Module * PEIM - UEFI: PEI Module
* PEP - Intel: Power Engine Plug-in * PEP - Intel: Power Engine Plug-in
* PEXVDD - Nvidia Power: PCIExpress Voltage
* PHX - AMD: Phoenix SoC * PHX - AMD: Phoenix SoC
* PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The * PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
hardware that implements the send/receive functionality of a hardware that implements the send/receive functionality of a
communication protocol. communication protocol.
* PI - Platform Initialization * PI - Platform Initialization
@@ -776,7 +752,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PIT - Generally refers to the 8253/8254 [**Programmable Interval * PIT - Generally refers to the 8253/8254 [**Programmable Interval
Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer). Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer).
* PLCC - [**Plastic leaded chip * PLCC - [**Plastic leaded chip
carrier**](https://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier) carrier**](http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
* PLL - [**Phase-Locked * PLL - [**Phase-Locked
Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop) Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop)
* PM - Platform Management * PM - Platform Management
@@ -807,8 +783,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PSF - Intel: Primary Sideband Fabric * PSF - Intel: Primary Sideband Fabric
* PSP - AMD: Platform Security Processor * PSP - AMD: Platform Security Processor
* PSPP - AMD: PCIE Speed Power Policy * PSPP - AMD: PCIE Speed Power Policy
* PSR - Intel: Platform Service Record
* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature specified in eDP
* PTT - Intel: Platform Trust Technology - Intel's firmware based TPM. * PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
* PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a * PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
resistor. The resistor allows the signal to still be set to ground resistor. The resistor allows the signal to still be set to ground
@@ -835,7 +809,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be
used. used.
* RAPL - Running Average Power Limit * RAPL - Running Average Power Limit
* RCB - PCIe: Read Completion Boundary - Sets the address alignment on which a read request may be serviced with multiple completions
* RCS - [**Revision control * RCS - [**Revision control
system**](https://en.wikipedia.org/wiki/Revision_Control_System) system**](https://en.wikipedia.org/wiki/Revision_Control_System)
* Real mode - The original 20-bit addressing mode of the 8086 & 8088 * Real mode - The original 20-bit addressing mode of the 8086 & 8088
@@ -843,7 +816,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Segment:Offset index pair. In 2022, this is still the mode that Segment:Offset index pair. In 2022, this is still the mode that
x86-64 processors are in at the reset vector! x86-64 processors are in at the reset vector!
* RDMA - [**Remote Direct Memory * RDMA - [**Remote Direct Memory
Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is Access**](http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
a concept whereby two or more computers communicate via DMA directly a concept whereby two or more computers communicate via DMA directly
from main memory of one system to the main memory of another. from main memory of one system to the main memory of another.
* RFC - Request for Comment * RFC - Request for Comment
@@ -856,7 +829,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* ROM - Read Only Memory * ROM - Read Only Memory
* RoT - Root of Trust * RoT - Root of Trust
* RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake) * RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake)
* RPP - Intel: Raptor Point PCH
* RRG - AMD (ATI): Register Reference Guide * RRG - AMD (ATI): Register Reference Guide
* RSDP - Root System Description Pointer * RSDP - Root System Description Pointer
* RTC - Real Time Clock * RTC - Real Time Clock
@@ -948,7 +920,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SMBus - [**System Management * SMBus - [**System Management
Bus**](https://en.wikipedia.org/wiki/System_Management_Bus) Bus**](https://en.wikipedia.org/wiki/System_Management_Bus)
* [http://www.smbus.org/](http://www.smbus.org/) * [http://www.smbus.org/](http://www.smbus.org/)
* SME - AMD: Secure Memory Encryption
* SMI - System management interrupt * SMI - System management interrupt
* SMM - [**System management * SMM - [**System management
mode**](https://en.wikipedia.org/wiki/System_Management_Mode) mode**](https://en.wikipedia.org/wiki/System_Management_Mode)
@@ -962,7 +933,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SO-DIMM: Small Outline Dual In-Line Memory Module * SO-DIMM: Small Outline Dual In-Line Memory Module
* SoC - System on a Chip * SoC - System on a Chip
* SOIC - [**Small-Outline Integrated * SOIC - [**Small-Outline Integrated
Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit) Circuit**](http://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
* SPD - [**Serial Presence * SPD - [**Serial Presence
Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect) Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect)
* SPI - [**Serial Peripheral * SPI - [**Serial Peripheral
@@ -987,7 +958,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SSI-TEB - Physical board format: [**SSI Thin Electronics * SSI-TEB - Physical board format: [**SSI Thin Electronics
Bay**](https://en.wikipedia.org/wiki/SSI_CEB) Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing) * SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
* SSPHY - USB: USB3 Super-Speed PHY
* STAPM - AMD: Skin Temperature Aware Power Management * STAPM - AMD: Skin Temperature Aware Power Management
* STB - AMD: Smart Trace Buffer * STB - AMD: Smart Trace Buffer
* SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O) * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
@@ -995,16 +965,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT
Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any
of a number of various other devices. of a number of various other devices.
* SVC - ARM: Supervisor Call
* SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0 * SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0
* SWCM - Intel: Software Connection Manager
## T ## T
* TBT - Thunderbolt * TBT - Thunderbolt
* TBT - Intel: Turbo Boost Technology * TBT - Intel: Turbo Boost Technology
* tBUF - I2C: The bus free time between a STOP and START condition
* TCC - Intel: Thermal Control Circuit * TCC - Intel: Thermal Control Circuit
* TCP - Transmission Control Protocol * TCP - Transmission Control Protocol
* TCPC - Type C Port Controller * TCPC - Type C Port Controller
@@ -1046,7 +1013,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode) * uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode)
* UDK - UEFI: UEFI Development Kit * UDK - UEFI: UEFI Development Kit
* UDP - User Datagram Protocol * UDP - User Datagram Protocol
* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The fastest transfer mode for ATA Hard Drives
* UEFI - Unified Extensible Firmware Interface * UEFI - Unified Extensible Firmware Interface
* UFC - User Facing Camera * UFC - User Facing Camera
* UFP - USB: Upstream Facing Port * UFP - USB: Upstream Facing Port
@@ -1064,7 +1030,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* UPS - Uninterruptible Power Supply * UPS - Uninterruptible Power Supply
* USART - Universal Synchronous/Asynchronous Receiver/Transmitter * USART - Universal Synchronous/Asynchronous Receiver/Transmitter
* USB - Universal Serial Bus * USB - Universal Serial Bus
* USF - Intel: Universal Scalable Firmware
## V ## V
@@ -1073,7 +1038,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* VBNV - Vboot Non-Volatile storage * VBNV - Vboot Non-Volatile storage
* VBT - [**Video BIOS * VBT - [**Video BIOS
Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt) Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
* VDDQ Memory/Power: The supply voltage to the output buffers of a memory chip.
* VESA - Video Electronics Standards Association * VESA - Video Electronics Standards Association
* VGA: Video Graphics Array * VGA: Video Graphics Array
* VID: Vendor Identifier * VID: Vendor Identifier
@@ -1081,17 +1045,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* VLB - VESA Local Bus * VLB - VESA Local Bus
* VOIP - Voice over IP * VOIP - Voice over IP
* Voodoo mode - a silly name for Big Real mode. * Voodoo mode - a silly name for Big Real mode.
* VMX - Intel: CPU flag for Hardware Virtualization
* VPD - Vital Product Data * VPD - Vital Product Data
* VPN - Virtual Private Network * VPN - Virtual Private Network
* VPU - Intel: Versatile Processor Unit
* VR - Voltage Regulator * VR - Voltage Regulator
* VRAM - Video Random Access Memory * VRAM - Video Random Access Memory
* VREF Memory/Power: Reference voltage for the input lines of a chip that determines the voltage level at which the threshold between a logical 1 and a logical 0 occurs. Usually 1/2 VDDQ.
* VRM - Voltage Regulator Module * VRM - Voltage Regulator Module
* VT-d - Intel: Virtualization Technology for Directed I/O * VT-d - Intel: Virtualization Technology for Directed I/O
* VTT Memory/Power: Tracking Termination Voltage
* vUART - Virtual UART
## W ## W
@@ -1109,7 +1068,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* WLAN - Wireless LAN (Local Area Network) * WLAN - Wireless LAN (Local Area Network)
* WWAN - Telecommunication: Wireless WAN (Wide Area Network) * WWAN - Telecommunication: Wireless WAN (Wide Area Network)
* WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29) * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
* WPT - Intel: Wildcat Point - PCH for Broadwell
* WO - Write-only * WO - Write-only
* WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN) * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)
* WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29) * WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
@@ -1130,9 +1088,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
supporting 1.x, 2.0, and 3.x devices. supporting 1.x, 2.0, and 3.x devices.
## Y
* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - A family of color spaces used in video ## Y
## Z ## Z

View File

@@ -95,17 +95,6 @@ If you feel you have been falsely or unfairly accused of violating this
Code of Conduct, you should notify the arbitration team with a concise Code of Conduct, you should notify the arbitration team with a concise
description of your grievance. description of your grievance.
## Legal action
Threatening or starting legal action against the project, sibling
projects hosted on coreboot.org infrastructure, project or infrastructure
maintainers leads to an immediate ban from coreboot.org and related
systems.
The ban can be reconsidered, but it's the default action because the
people who pour lots of time and money into the projects aren't interested
in seeing their resources used against them.
## Scope ## Scope
We expect all community participants (contributors, paid or otherwise; We expect all community participants (contributors, paid or otherwise;

View File

@@ -14,7 +14,7 @@ read its
## Real time chat ## Real time chat
We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot), We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on [Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
[OSF Slack](https://osfw.slack.com/), which has channels on many open source [OSF Slack](https://osfw.slack.com/), which has channels on many open source
firmware related topics. Slack requires that people come from specific domains firmware related topics. Slack requires that people come from specific domains

View File

@@ -55,7 +55,7 @@ else:
# #
# This is also used if you do content translation via gettext catalogs. # This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases. # Usually you set "language" from the command line for these cases.
language = 'en' language = None
# List of patterns, relative to source directory, that match files and # List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files. # directories to ignore when looking for source files.
@@ -87,13 +87,101 @@ html_theme = 'sphinx_rtd_theme'
# so a file named "default.css" will overwrite the builtin "default.css". # so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static'] html_static_path = ['_static']
html_css_files = [ html_context = {
'theme_overrides.css', # override wide tables in RTD theme 'css_files': [
] '_static/theme_overrides.css', # override wide tables in RTD theme
],
}
# Output file base name for HTML help builder. # Output file base name for HTML help builder.
htmlhelp_basename = 'corebootdoc' htmlhelp_basename = 'corebootdoc'
# -- Options for LaTeX output ---------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'coreboot.tex', u'coreboot Documentation',
u'the coreboot project', 'manual'),
]
# The name of an image file (relative to this directory) to place at the top of
# the title page.
#
# latex_logo = None
# For "manual" documents, if this is true, then toplevel headings are parts,
# not chapters.
#
# latex_use_parts = False
# If true, show page references after internal links.
#
# latex_show_pagerefs = False
# If true, show URL addresses after external links.
#
# latex_show_urls = False
# Documents to append as an appendix to all manuals.
#
# latex_appendices = []
# If false, will not define \strong, \code, itleref, \crossref ... but only
# \sphinxstrong, ..., \sphinxtitleref, ... To help avoid clash with user added
# packages.
#
# latex_keep_old_macro_names = True
# If false, no module index is generated.
#
# latex_domain_indices = True
# -- Options for manual page output ---------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'coreboot', u'coreboot Documentation',
[author], 1)
]
# If true, show URL addresses after external links.
#
# man_show_urls = False
# -- Options for Texinfo output -------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'coreboot', u'coreboot Documentation',
author, 'coreboot', 'One line description of project.',
'Miscellaneous'),
]
enable_auto_toc_tree = True enable_auto_toc_tree = True
class MyCommonMarkParser(CommonMarkParser): class MyCommonMarkParser(CommonMarkParser):
@@ -103,6 +191,23 @@ class MyCommonMarkParser(CommonMarkParser):
n = nodes.literal(mdnode.literal, mdnode.literal) n = nodes.literal(mdnode.literal, mdnode.literal)
self.current_node.append(n) self.current_node.append(n)
# Documents to append as an appendix to all manuals.
#
# texinfo_appendices = []
# If false, no module index is generated.
#
# texinfo_domain_indices = True
# How to display URL addresses: 'footnote', 'no', or 'inline'.
#
# texinfo_show_urls = 'footnote'
# If true, do not generate a @detailmenu in the "Top" node's menu.
#
# texinfo_no_detailmenu = False
def setup(app): def setup(app):
from recommonmark.transform import AutoStructify from recommonmark.transform import AutoStructify
# Load recommonmark on old Sphinx # Load recommonmark on old Sphinx

View File

@@ -6,14 +6,14 @@ kernel coding style. In fact, most of this document has been copied from
the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/plain/Documentation/process/4.Coding.rst) the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/plain/Documentation/process/4.Coding.rst)
The guidelines in this file should be seen as a strong suggestion, and The guidelines in this file should be seen as a strong suggestion, and
should overrule personal preference. They may be ignored in individual should overrule personal preference. But they may be ignored in
instances when there are good practical reasons to do so, and reviewers individual instances when there are good practical reasons to do so, and
are in agreement. reviewers are in agreement.
Any style questions that are not mentioned in here should be decided Any style questions that are not mentioned in here should be decided
between the author and reviewers on a case-by-case basis. When modifying between the author and reviewers on a case-by-case basis. When modifying
existing files, authors should try to match the prevalent style in that existing files, authors should try to match the prevalent style in that
file -- otherwise, they should generally match similar existing files in file -- otherwise, they should try to match similar existing files in
coreboot. coreboot.
Bulk style changes to existing code ("cleanup patches") should avoid Bulk style changes to existing code ("cleanup patches") should avoid
@@ -24,8 +24,7 @@ be honored. (Note that `checkpatch.pl` is not part of this style guide,
and neither is `clang-format`. These tools can be useful to find and neither is `clang-format`. These tools can be useful to find
potential issues or simplify formatting in new submissions, but they potential issues or simplify formatting in new submissions, but they
were not designed to directly match this guide and may have false were not designed to directly match this guide and may have false
positives. They should not be bulk-applied to change existing code positives. They should not be bulk-applied to change existing code.)
except in cases where they directly match the style guide.)
## Indentation ## Indentation
@@ -43,8 +42,7 @@ Now, some people will claim that having 8-character indentations makes
the code move too far to the right, and makes it hard to read on a the code move too far to the right, and makes it hard to read on a
80-character terminal screen. The answer to that is that if you need 80-character terminal screen. The answer to that is that if you need
more than 3 levels of indentation, you're screwed anyway, and should more than 3 levels of indentation, you're screwed anyway, and should
fix your program. Note that coreboot has expanded the 80 character fix your program.
limit to 96 characters to allow for modern wider screens.
In short, 8-char indents make things easier to read, and have the added In short, 8-char indents make things easier to read, and have the added
benefit of warning you when you're nesting your functions too deep. benefit of warning you when you're nesting your functions too deep.
@@ -89,9 +87,7 @@ Outside of comments, documentation and except in Kconfig, spaces are
never used for indentation, and the above example is deliberately never used for indentation, and the above example is deliberately
broken. broken.
Get a decent editor and don't leave whitespace at the end of lines. This Get a decent editor and don't leave whitespace at the end of lines.
will actually keep the patch from being tested in the CI, so patches
with ending whitespace cannot be merged.
## Breaking long lines and strings ## Breaking long lines and strings
@@ -507,14 +503,18 @@ comments to note or warn about something particularly clever (or ugly),
but try to avoid excess. Instead, put the comments at the head of the but try to avoid excess. Instead, put the comments at the head of the
function, telling people what it does, and possibly WHY it does it. function, telling people what it does, and possibly WHY it does it.
coreboot style for comments is the C89 "/* ... */" style. You may also When commenting the kernel API functions, please use the kernel-doc
use C99-style "// ..." comments for single-line comments. format. See the files Documentation/kernel-doc-nano-HOWTO.txt and
scripts/kernel-doc for details.
coreboot style for comments is the C89 "/* ... */" style. You may
use C99-style "// ..." comments.
The preferred style for *short* (multi-line) comments is: The preferred style for *short* (multi-line) comments is:
```c ```c
/* This is the preferred style for short multi-line /* This is the preferred style for short multi-line
   comments in the coreboot source code.    comments in the Linux kernel source code.
   Please use it consistently. */    Please use it consistently. */
``` ```
@@ -523,7 +523,7 @@ The preferred style for *long* (multi-line) comments is:
```c ```c
/* /*
 * This is the preferred style for multi-line  * This is the preferred style for multi-line
 * comments in the coreboot source code.  * comments in the Linux kernel source code.
 * Please use it consistently.  * Please use it consistently.
 *  *
 * Description:  A column of asterisks on the left side,  * Description:  A column of asterisks on the left side,
@@ -578,8 +578,7 @@ To do the latter, you can stick the following in your .emacs file:
``` ```
This will make emacs go better with the kernel coding style for C files This will make emacs go better with the kernel coding style for C files
below ~/src/linux-trees. Obviously, this should be updated to match below ~/src/linux-trees.
your own paths for coreboot.
But even if you fail in getting emacs to do sane formatting, not But even if you fail in getting emacs to do sane formatting, not
everything is lost: use "indent". everything is lost: use "indent".
@@ -627,6 +626,38 @@ config ADFS_FS_RW
For full documentation on the configuration files, see the file For full documentation on the configuration files, see the file
Documentation/kbuild/kconfig-language.txt. Documentation/kbuild/kconfig-language.txt.
Data structures
---------------
Data structures that have visibility outside the single-threaded
environment they are created and destroyed in should always have
reference counts. In the kernel, garbage collection doesn't exist (and
outside the kernel garbage collection is slow and inefficient), which
means that you absolutely _have_ to reference count all your uses.
Reference counting means that you can avoid locking, and allows multiple
users to have access to the data structure in parallel - and not having
to worry about the structure suddenly going away from under them just
because they slept or did something else for a while.
Note that locking is _not_ a replacement for reference counting.
Locking is used to keep data structures coherent, while reference
counting is a memory management technique. Usually both are needed, and
they are not to be confused with each other.
Many data structures can indeed have two levels of reference counting,
when there are users of different "classes". The subclass count counts
the number of subclass users, and decrements the global count just once
when the subclass count goes to zero.
Examples of this kind of "multi-level-reference-counting" can be found
in memory management ("struct mm_struct": mm_users and mm_count),
and in filesystem code ("struct super_block": s_count and
s_active).
Remember: if another thread can find your data structure, and you don't
have a reference count on it, you almost certainly have a bug.
Macros, Enums and RTL Macros, Enums and RTL
--------------------- ---------------------
@@ -696,19 +727,35 @@ The cpp manual deals with macros exhaustively. The gcc internals manual
also covers RTL which is used frequently with assembly language in the also covers RTL which is used frequently with assembly language in the
kernel. kernel.
Printing coreboot messages Printing kernel messages
------------------------ ------------------------
coreboot developers like to be seen as literate. Do mind the spelling of Kernel developers like to be seen as literate. Do mind the spelling of
coreboot messages to make a good impression. Do not use crippled words kernel messages to make a good impression. Do not use crippled words
like "dont"; use "do not" or "don't" instead. Make the messages like "dont"; use "do not" or "don't" instead. Make the messages
concise, clear, and unambiguous. concise, clear, and unambiguous.
coreboot messages do not have to be terminated with a period. Kernel messages do not have to be terminated with a period.
Printing numbers in parentheses (%d) adds no value and should be Printing numbers in parentheses (%d) adds no value and should be
avoided. avoided.
There are a number of driver model diagnostic macros in
<linux/device.h> which you should use to make sure messages are
matched to the right device and driver, and are tagged with the right
level: dev_err(), dev_warn(), dev_info(), and so forth. For messages
that aren't associated with a particular device, <linux/printk.h>
defines pr_debug() and pr_info().
Coming up with good debugging messages can be quite a challenge; and
once you have them, they can be a huge help for remote troubleshooting.
Such messages should be compiled out when the DEBUG symbol is not
defined (that is, by default they are not included). When you use
dev_dbg() or pr_debug(), that's automatic. Many subsystems have
Kconfig options to turn on -DDEBUG. A related convention uses
VERBOSE_DEBUG to add dev_vdbg() messages to the ones already enabled
by DEBUG.
Allocating memory Allocating memory
----------------- -----------------
@@ -745,7 +792,12 @@ The inline disease
There appears to be a common misperception that gcc has a magic "make There appears to be a common misperception that gcc has a magic "make
me faster" speedup option called "inline". While the use of inlines me faster" speedup option called "inline". While the use of inlines
can be appropriate (for example as a means of replacing macros, see can be appropriate (for example as a means of replacing macros, see
Chapter 12), it very often is not. Chapter 12), it very often is not. Abundant use of the inline keyword
leads to a much bigger kernel, which in turn slows the system as a whole
down, due to a bigger icache footprint for the CPU and simply because
there is less memory available for the pagecache. Just think about it; a
pagecache miss causes a disk seek, which easily takes 5 milliseconds.
There are a LOT of cpu cycles that can go into these 5 milliseconds.
A reasonable rule of thumb is to not put inline at functions that have A reasonable rule of thumb is to not put inline at functions that have
more than 3 lines of code in them. An exception to this rule are the more than 3 lines of code in them. An exception to this rule are the
@@ -871,7 +923,7 @@ in the same directory that is not part of a normal include path gets included
.c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks, .c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks,
including includes to other headers that don't follow that provision. Where a including includes to other headers that don't follow that provision. Where a
specific include order is required for technical reasons, it should be clearly specific include order is required for technical reasons, it should be clearly
documented with comments. This should not be the norm. documented with comments.
Files should generally include every header they need a definition from Files should generally include every header they need a definition from
directly (and not include any unnecessary extra headers). Excepted from directly (and not include any unnecessary extra headers). Excepted from
@@ -1006,29 +1058,6 @@ This rule only applies to explicit GCC extensions listed in the
should never rely on incidental GCC translation behavior that is not should never rely on incidental GCC translation behavior that is not
explicitly documented as a feature and could change at any moment. explicitly documented as a feature and could change at any moment.
Refactoring
-----------
Because refactoring existing code can add bugs to tested code, any
refactors should be done only with serious consideration. Refactoring
for style differences should only be done if the existing style
conflicts with a documented coreboot guideline. If you believe that the
style should be modified, the pros and cons can be discussed on the
mailing list and in the coreboot leadership meeting.
Similarly, the original author should be respected. Changing working
code simply because of a stylistic disagreement is *prohibited*. This is
not saying that refactors that are objectively better (simpler, faster,
easier to understand) are not allowed, but there has to be a definite
improvement, not simply stylistic changes.
Basically, when refactoring code, there should be a clear benefit to
the project and codebase. The reviewers and submitters get to make the
call on how to interpret this.
When refactoring, adding unit tests to verify that the post-change
functionality matches or improves upon pre-change functionality is
encouraged.
References References
---------- ----------

View File

@@ -9,7 +9,7 @@ friction in the community.
Note that as with many rules, there are exceptions. Some have been noted Note that as with many rules, there are exceptions. Some have been noted
in the 'More Detail' section. If you feel there is an exception not listed in the 'More Detail' section. If you feel there is an exception not listed
here, please discuss it in the mailing list to get this document updated. here, please discuss it in the mailing list to get this document updated.
Don't just assume that it's okay, even if someone on IRC says it is. Don't just assume that it's okay, even if someone on IRC says it is.
@@ -234,7 +234,7 @@ be set when you push the patches into gerrit. For example, to push a set of
commits with the i915-kernel-x60 set, use the command: commits with the i915-kernel-x60 set, use the command:
```Bash ```Bash
git push origin HEAD:refs/for/main%topic=i915-kernel-x60 git push origin HEAD:refs/for/master%topic=i915-kernel-x60
``` ```
* If one of your patches isn't ready to be merged, make sure it's obvious * If one of your patches isn't ready to be merged, make sure it's obvious
@@ -247,7 +247,7 @@ isn't as obvious as the commit message. These patches can also be pushed with
the wip flag: the wip flag:
```Bash ```Bash
git push origin HEAD:refs/for/main%wip git push origin HEAD:refs/for/master%wip
``` ```
* When pushing patches that are not for submission, these should be marked * When pushing patches that are not for submission, these should be marked
@@ -259,13 +259,13 @@ who knows their commit ID, so don't use this for sensitive changes. To push
a private change, use the command: a private change, use the command:
```Bash ```Bash
git push origin HEAD:refs/for/main%private git push origin HEAD:refs/for/master%private
``` ```
* Multiple push options can be combined: * Multiple push options can be combined:
```Bash ```Bash
git push origin HEAD:refs/for/main%private,wip,topic=experiment git push origin HEAD:refs/for/master%private,wip,topic=experiment
``` ```
* Respond to anyone who has taken the time to review your patches, even if * Respond to anyone who has taken the time to review your patches, even if
@@ -292,7 +292,7 @@ changed.
helps others and shows that these mainboards are currently being helps others and shows that these mainboards are currently being
maintained. At some point, boards that are not up to date in the maintained. At some point, boards that are not up to date in the
board-status repo will probably end up getting removed from the coreboot board-status repo will probably end up getting removed from the coreboot
main branch. master branch.
* Abandon patches that are no longer useful, or that you dont intend to * Abandon patches that are no longer useful, or that you dont intend to
keep working on to get submitted. keep working on to get submitted.

View File

@@ -386,7 +386,7 @@ want to submit all commits in the currently checked-out branch for
review on gerrit: review on gerrit:
{ \small { \small
\begin{verbatim} \begin{verbatim}
$ git config remote.origin.push HEAD:refs/for/main $ git config remote.origin.push HEAD:refs/for/master
\end{verbatim} \end{verbatim}
} }
@@ -399,10 +399,10 @@ $ make gitconfig
\subsection{Work flow} \subsection{Work flow}
It is recommended that you make a new branch when you start to work, not pushing changes to main. It is recommended that you make a new branch when you start to work, not pushing changes to master.
{ \small { \small
\begin{verbatim} \begin{verbatim}
$ git checkout main -b mybranch $ git checkout master -b mybranch
\end{verbatim} \end{verbatim}
} }
After you have done your changes, run: After you have done your changes, run:
@@ -452,7 +452,7 @@ make a new local commit that fixes the issues reported by the
reviewers, then rebase the change by preserving the same Change-ID. We reviewers, then rebase the change by preserving the same Change-ID. We
recommend you to use the git rebase command in interactive mode, recommend you to use the git rebase command in interactive mode,
Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/main. Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/master.
% %
% Working with Gerrit % Working with Gerrit
@@ -474,9 +474,9 @@ click \url{https://review.coreboot.org}
|Search for status:open | |Search for status:open |
+-----------------------------------------------------------+ +-----------------------------------------------------------+
|Subject Status Owner Project Branch Updated CR V | |Subject Status Owner Project Branch Updated CR V |
|cpu: Rename.. Alexandru coreboot main 1:20 PM +1 | |cpu: Rename.. Alexandru coreboot master 1:20 PM +1 |
|cpu: Only a.. Alexandru coreboot main 1:17 PM X | |cpu: Only a.. Alexandru coreboot master 1:17 PM X |
|arch/x86: D.. Alexandru coreboot main 1:09 PM | |arch/x86: D.. Alexandru coreboot master 1:09 PM |
| | | |
| Next -> | | Next -> |
|Press '?' to view keyboard shortcuts | Powered by Gerrit | |Press '?' to view keyboard shortcuts | Powered by Gerrit |
@@ -637,7 +637,7 @@ Gerrit makes reviews easier by showing changes in a side-by-side
display, and allowing inline comments to be added by any reviewer. display, and allowing inline comments to be added by any reviewer.
Gerrit simplifies Git based project maintainership by permitting any Gerrit simplifies Git based project maintainership by permitting any
authorized user to submit changes to the upstream Git repository, rather authorized user to submit changes to the master Git repository, rather
than requiring all approved changes to be merged in by hand by the than requiring all approved changes to be merged in by hand by the
project maintainer. This functionality enables a more centralized project maintainer. This functionality enables a more centralized
usage of Git. usage of Git.

View File

@@ -8,25 +8,6 @@ and those providing after-market firmware to extend the usefulness of devices.
## Hardware shipping with coreboot ## Hardware shipping with coreboot
### ChromeOS Devices
All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
Chromebit, etc) released from 2012 onward use coreboot for their main system
firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
running on the Embedded Controller (EC) a small microcontroller which provides
functions like battery management, keyboard support, and sensor interfacing
is open source as well.
### Nitrokey
[Nitrokey](https://nitrokey.com) is a german IT security hardware vendor which
offers a range of laptops, PCs, HSMs, and networking devices with coreboot and
[Dasharo](https://dasharo.com/). The devices come with neutralized Intel
Management Engine (ME) and with pre-installed [Heads](http://osresearch.net) or
EDK2 payload providing measured boot and verified boot protection. For
additional security the systems can be physically sealed and pictures of those
sealings are sent via encrypted email.
### NovaCustom laptops ### NovaCustom laptops
[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with [NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
@@ -36,6 +17,15 @@ Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
and the firmware is equipped with important security features such as measured and the firmware is equipped with important security features such as measured
boot, verified boot, TPM integration and UEFI Secure Boot. boot, verified boot, TPM integration and UEFI Secure Boot.
### ChromeOS Devices
All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
Chromebit, etc) released from 2012 onward use coreboot for their main system
firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
running on the Embedded Controller (EC) a small microcontroller which provides
functions like battery management, keyboard support, and sensor interfacing
is open source as well.
### PC Engines APUs ### PC Engines APUs
[PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that [PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that
@@ -43,13 +33,6 @@ ships with coreboot and support upstream maintenance for the devices through a
third party, [3mdeb](https://3mdeb.com). They provide current and tested third party, [3mdeb](https://3mdeb.com). They provide current and tested
firmware binaries on [GitHub](https://pcengines.github.io). firmware binaries on [GitHub](https://pcengines.github.io).
### Purism
[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
security; part of that effort is to minimize the amount of proprietary and/or
binary code. Their laptops ship with a blob-free OS and coreboot firmware
with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
### Star Labs ### Star Labs
[Star Labs](https://starlabs.systems/) offers a range of laptops designed and [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
@@ -64,8 +47,23 @@ servers. Some models are sold with [System76 Open
Firmware](https://github.com/system76/firmware-open), an open source Firmware](https://github.com/system76/firmware-open), an open source
distribution of coreboot, edk2, and System76 firmware applications. distribution of coreboot, edk2, and System76 firmware applications.
### Purism
[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
security; part of that effort is to minimize the amount of proprietary and/or
binary code. Their laptops ship with a blob-free OS and coreboot firmware
with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
## After-market firmware ## After-market firmware
### Libreboot
[Libreboot](https://libreboot.org) is a downstream coreboot distribution that
provides ready-made firmware images for supported devices: those which can be
built entirely from source code. Their copy of the coreboot repository is
therefore stripped of all devices that require binary components to boot.
### Dasharo ### Dasharo
[Dasharo](https://dasharo.com/) is an open-source based firmware distribution [Dasharo](https://dasharo.com/) is an open-source based firmware distribution
@@ -76,6 +74,18 @@ trustworthiness for all.
Contributions are welcome, Contributions are welcome,
[this document](https://docs.dasharo.com/ways-you-can-help-us/). [this document](https://docs.dasharo.com/ways-you-can-help-us/).
### MrChromebox
[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
images for the vast majority of x86-based Chromebooks and Chromeboxes, using
edk2 as the payload to provide a modern UEFI bootloader. Why replace
coreboot with coreboot? Mr Chromebox's images are built using upstream
coreboot (vs Google's older, static tree/branch), include many features and
fixes not found in the stock firmware, and offer much broader OS compatibility
(i.e., they run Windows as well as Linux). They also offer updated CPU
microcode, as well as firmware updates for the device's embedded controller
(EC). This firmware "takes the training wheels off" your ChromeOS device :)
### Heads ### Heads
[Heads](http://osresearch.net) is an open source custom firmware and OS [Heads](http://osresearch.net) is an open source custom firmware and OS
@@ -89,25 +99,6 @@ Heads is not just another Linux distribution it combines physical hardening
of specific hardware platforms and flash security features with custom coreboot of specific hardware platforms and flash security features with custom coreboot
firmware and a Linux boot loader in ROM. firmware and a Linux boot loader in ROM.
### Libreboot
[Libreboot](https://libreboot.org) is a downstream coreboot distribution that
provides ready-made firmware images for supported devices: those which can be
built entirely from source code. Their copy of the coreboot repository is
therefore stripped of all devices that require binary components to boot.
### MrChromebox
[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
images for the vast majority of x86-based Chromebooks and Chromeboxes, using
edk2 as the payload to provide a modern UEFI bootloader. Why replace
coreboot with coreboot? Mr Chromebox's images are built using upstream
coreboot (vs Google's older, static tree/branch), include many features and
fixes not found in the stock firmware, and offer much broader OS compatibility
(i.e., they run Windows as well as Linux). They also offer updated CPU
microcode, as well as firmware updates for the device's embedded controller
(EC). This firmware "takes the training wheels off" your ChromeOS device :)
### Skulls ### Skulls
[Skulls](https://github.com/merge/skulls) provides firmware images for [Skulls](https://github.com/merge/skulls) provides firmware images for

View File

@@ -113,7 +113,6 @@ as well (such as
* [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html) * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
* [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html) * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
* [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html) * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
* [coreboot on Eagle Stream](https://www.intel.com/content/www/us/en/content-details/778593/coreboot-practice-on-eagle-stream.html)
* Rockchip * Rockchip
* [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page) * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)

View File

@@ -62,23 +62,6 @@ supported options are:
`position` and `align` are mutually exclusive. `position` and `align` are mutually exclusive.
### Adding Makefile fragments
You can use the `add_intermediate` helper to add new post-processing steps for
the final `coreboot.rom` image. For example you can add new files to CBFS by
adding something like this to `site-local/Makefile.inc`
```
$(call add_intermediate, add_mrc_data)
$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
```
Note that the second line must start with a tab, not spaces.
```eval_rst
See also :doc:`../tutorial/managing_local_additions`.
```
#### FMAP region support #### FMAP region support
With the addition of FMAP flash partitioning support to coreboot, there was a With the addition of FMAP flash partitioning support to coreboot, there was a
need to extend the specification of files to provide more precise control need to extend the specification of files to provide more precise control

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@@ -79,7 +79,7 @@ with no properties as a direct child of the SoC.
## Device drivers ## Device drivers
Platform independent device drivers are hooked up via entries in a devicetree. Platform independent device drivers are hooked up via entries in a devicetree.
See [Driver Devicetree Entries](../drivers/dt_entries.md) for more info. See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
## Notes ## Notes

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@@ -69,6 +69,9 @@ These variables are typically set in the makefiles or on the make command line.
These variables were added to Kconfig specifically for coreboot and are not These variables were added to Kconfig specifically for coreboot and are not
included in the Linux version. included in the Linux version.
- KCONFIG_STRICT=value. Define to enable warnings as errors. This is enabled
in coreboot, and should not be changed.
- KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file - KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file
(build/config.h). This is enabled in coreboot, and should not be changed. (build/config.h). This is enabled in coreboot, and should not be changed.
@@ -99,9 +102,6 @@ included in the Linux version.
- KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”. - KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”.
coreboot sets this to $(obj)/config. coreboot sets this to $(obj)/config.
- KCONFIG_WERROR=value. Define to enable warnings as errors. This is enabled
in coreboot, and should not be changed.
#### Used only for make menuconfig #### Used only for make menuconfig
- MENUCONFIG_MODE=single_menu. Set to "single_menu" to enable. All other - MENUCONFIG_MODE=single_menu. Set to "single_menu" to enable. All other
values disable the option. This makes submenus appear below the menu option values disable the option. This makes submenus appear below the menu option
@@ -1160,6 +1160,10 @@ saved .config file. As always, a 'select' statement overrides any specified
- coreboot has added the glob operator '*' for the 'source' keyword. - coreboot has added the glob operator '*' for the 'source' keyword.
- coreboots Kconfig always defines variables except for strings. In other - coreboots Kconfig always defines variables except for strings. In other
Kconfig implementations, bools set to false/0/no are not defined. Kconfig implementations, bools set to false/0/no are not defined.
- coreboots version of Kconfig adds the KCONFIG_STRICT environment variable to
error out if there are any issues in the Kconfig files. In the Linux kernel,
Kconfig will generate a warning, but will still output an updated .config or
config.h file.
## Kconfig Editor Highlighting ## Kconfig Editor Highlighting

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@@ -146,9 +146,9 @@ coreboot is primarily developed in the
system, using [Gerrit](https://review.coreboot.org) to manage system, using [Gerrit](https://review.coreboot.org) to manage
contributions and code review. contributions and code review.
In general we try to keep the `main` branch in the repository functional In general we try to keep the `master` branch in the repository functional
for all hardware we support. So far, the only guarantee we can make is for all hardware we support. So far, the only guarantee we can make is
that the main branch will (nearly) always build for all boards in a that the master branch will (nearly) always build for all boards in a
standard configuration. standard configuration.
However, we're continually working on improvements to our infrastructure to However, we're continually working on improvements to our infrastructure to
@@ -200,4 +200,4 @@ Contents:
* [External Resources](external_docs.md) * [External Resources](external_docs.md)
* [Documentation License](documentation_license.md) * [Documentation License](documentation_license.md)
[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Documentation/ [Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Documentation/

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@@ -24,7 +24,8 @@ issues.
Currently active Jenkins admins: Currently active Jenkins admins:
* Patrick Georgi: * Patrick Georgi:
* Email: [patrick@coreboot.org](mailto:patrick@coreboot.org) * Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de)
* IRC: pgeorgi
* Martin Roth: * Martin Roth:
* Email: [gaumless@gmail.com](mailto:gaumless@gmail.com) * Email: [gaumless@gmail.com](mailto:gaumless@gmail.com)
* IRC: martinr * IRC: martinr
@@ -73,7 +74,7 @@ These times are taken from the week of Feb 21 - Feb 28, 2022
There are a number of builds handled by the coreboot jenkins builders, There are a number of builds handled by the coreboot jenkins builders,
for a number of different projects - coreboot, flashrom, memtest86+, for a number of different projects - coreboot, flashrom, memtest86+,
em100, etc. Many of these have builders for their current main branch em100, etc. Many of these have builders for their current master branch
as well as Gerrit and [Coverity](coverity.md) builds. as well as Gerrit and [Coverity](coverity.md) builds.
@@ -90,14 +91,14 @@ machines. These tasks run overnight in the US timezones.
You can see all the builds in the main jenkins interface: You can see all the builds in the main jenkins interface:
[https://qa.coreboot.org/](https://qa.coreboot.org/) [https://qa.coreboot.org/](https://qa.coreboot.org/)
Most of the time on the builders is taken up by the coreboot main and Most of the time on the builders is taken up by the coreboot master and
coreboot gerrit builds. coreboot gerrit builds.
* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) * [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
* [coreboot main build](https://qa.coreboot.org/job/coreboot/) * [coreboot master build](https://qa.coreboot.org/job/coreboot/)
([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))

View File

@@ -73,7 +73,7 @@ compiler](https://chromium-review.googlesource.com/#/c/255031) inside coreboot
utility folder that can be used to generate final firmware images (i.e. utility folder that can be used to generate final firmware images (i.e.
`coreboot.rom`) formatted by Flashmap. `coreboot.rom`) formatted by Flashmap.
The FMD implementation is in coreboot `util/cbfstool` folder. Here's an The FMD implementation is in coreboot `utils/cbfstool` folder. Here's an
informal language description: informal language description:
``` ```

View File

@@ -106,8 +106,8 @@ protection)* with the `ectool` command in a ChromeOS environment.
For more information on the firmware configuration field on ChromeOS devices see the Chromium For more information on the firmware configuration field on ChromeOS devices see the Chromium
documentation for [Firmware Config][1] and [Board Info][2]. documentation for [Firmware Config][1] and [Board Info][2].
[1]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/firmware_config.md [1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md
[2]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md [2]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md
## Firmware Configuration Table ## Firmware Configuration Table

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@@ -180,5 +180,5 @@ The generated file includes a compressed initrd **initramfs.cpio.xz**, which
will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**, will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**,
which will be decompressed by the FIT loader and an uncompressed devicetree blob. which will be decompressed by the FIT loader and an uncompressed devicetree blob.
[uImage.FIT]: https://github.com/u-boot/u-boot/blob/master/doc/usage/fit/howto.rst [uImage.FIT]: https://raw.githubusercontent.com/u-boot/u-boot/master/doc/uImage.FIT/howto.txt
[U-Boot]: https://www.denx.de/wiki/U-Boot [U-Boot]: https://www.denx.de/wiki/U-Boot

View File

@@ -92,7 +92,7 @@ for only CPU models that the board will actually be run with.
```eval_rst ```eval_rst
+------------------+--------------------------------------------------+ +------------------+--------------------------------------------------+
| Northbridge | Intel I440BX | | Northbridge | :doc:`../../northbridge/intel/i440bx/index` |
+------------------+--------------------------------------------------+ +------------------+--------------------------------------------------+
| Southbridge | i82371eb | | Southbridge | i82371eb |
+------------------+--------------------------------------------------+ +------------------+--------------------------------------------------+

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@@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
```eval_rst ```eval_rst
+------------------+--------------------------------------------------+ +------------------+--------------------------------------------------+
| Northbridge | Intel I440BX | | Northbridge | :doc:`../../northbridge/intel/i440bx/index` |
+------------------+--------------------------------------------------+ +------------------+--------------------------------------------------+
| Southbridge | i82371eb | | Southbridge | i82371eb |
+------------------+--------------------------------------------------+ +------------------+--------------------------------------------------+

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@@ -1,65 +0,0 @@
# HP Compaq Elite 8300 USDT
This page describes how to run coreboot on the [Compaq Elite 8300 USDT] desktop
from [HP].
## Flashing coreboot
```eval_rst
+---------------------+-------------+
| Type | Value |
+=====================+=============+
| Socketed flash | no |
+---------------------+-------------+
| Model | W25Q128BVFG |
+---------------------+-------------+
| Size | 16 MiB |
+---------------------+-------------+
| In circuit flashing | yes |
+---------------------+-------------+
| Package | SOIC-16 |
+---------------------+-------------+
| Write protection | No |
+---------------------+-------------+
| Dual BIOS feature | No |
+---------------------+-------------+
```
### Internal programming
Internal programming is possible. Shorting the Flash Descriptor Override
(FDO) jumper bypasses all write protections.
### External programming
Remove the lid. The flash chip can be found on the edge opposite to the CPU.
There is a spot for a "ROM RCVRY" header next to the flash chip but it is
unpopulated. If you don't feel like using a clip, you can easily solder
a standard pin header there yourself and use it for programming.
Programming powers some parts of the board. Programming when
Wake on LAN is active works great.
## Technology
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | bd82x6x |
+------------------+--------------------------------------------------+
| CPU | model_206ax |
+------------------+--------------------------------------------------+
| SuperIO | NPCD379HAKFX |
+------------------+--------------------------------------------------+
| Coprocessor | Intel ME |
+------------------+--------------------------------------------------+
```
### SuperIO
This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
[Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
[HP]: https://www.hp.com/

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# HP EliteBook 820 G2
This page is about the notebook [HP EliteBook 820 G2].
## Release status
HP EliteBook 820 G2 was released in 2015 and is now end of life.
It can be bought from a secondhand market like Taobao or eBay.
## Required proprietary blobs
The following blobs are required to operate the hardware:
1. EC firmware
2. Intel ME firmware
3. Broadwell mrc.bin and refcode.elf
HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller.
The EC firmware is stored in the flash chip, but we don't need to touch it
or use it in the coreboot build process.
Intel ME firmware is in the flash chip. It is not needed when building coreboot.
The Broadwell memory reference code binary and reference code blob is needed
when building coreboot. Read the document [Blobs used in Intel Broadwell boards]
on how to get these blobs.
## Programming
Before flashing, remove the battery and the hard drive cover according to the
[Maintenance and Service Guide] of this laptop.
HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB
private flash. To install coreboot, we need to program both flash chips.
Read [HP Sure Start] for detailed information.
![HP EliteBook 820 G2 flash chip](elitebook_820_g2_flash.jpg)
To access the system flash, we need to connect the AC adapter to the machine,
then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
made with an STM32 development board is tested to work.
To access the private flash chip, we can use a ch341a based flash programmer and
flash the chip with the AC adapter disconnected.
To flash coreboot on a board running OME firmware, create a backup for both flash
chips, then do the following:
1. Erase the private flash to disable the IFD protection
2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside
the protected flash region
To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
then run:
flashrom -p <programmer> --erase
To modify the IFD, write the following flash layout to a file:
00000000:00000fff fd
00001000:00002fff gbe
00003000:005fffff me
00600000:00bfffff bios
00eb5000:00ffffff pd
Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
is in ``factory-sys.rom``, run:
ifdtool -n layout.txt factory-sys.rom
Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
Flash the IFD of the system flash:
flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
Then flash the coreboot image:
# first extend the 12M coreboot.rom to 16M
fallocate -l 16M build/coreboot.rom
flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
After coreboot is installed, the coreboot firmware can be updated with internal flashing:
flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
## Debugging
The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
## Test status
### Untested
- NFC module
- Fingerprint reader
- Smart Card reader
### Working
- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory
- SATA and M.2 SATA disk
- PCIe SSD
- Webcam
- Touch screen
- Audio output from speaker and headphone jack
- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards])
- WLAN
- WWAN
- SD card reader
- Internal LCD, DisplayPort and VGA video outputs
- Dock
- USB
- Keyboard and touchpad
- EC ACPI
- S3 resume
- TPM
- Arch Linux with Linux 5.11.16
- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1
- Graphics initialization with libgfxinit
- Payload: SeaBIOS 1.16.2
- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05
- Internal flashing under coreboot
## Technology
```eval_rst
+------------------+-----------------------------+
| SoC | Intel Broadwell |
+------------------+-----------------------------+
| EC | SMSC MEC1324 |
+------------------+-----------------------------+
| Coprocessor | Intel Management Engine |
+------------------+-----------------------------+
```
[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/
[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md
[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf
[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
[HP Sure Start]: hp_sure_start.md

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@@ -75,7 +75,6 @@ The boards in this section are not real mainboards, but emulators.
## HP ## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
- [Z220 Workstation SFF](hp/z220_sff.md) - [Z220 Workstation SFF](hp/z220_sff.md)
### EliteBook series ### EliteBook series
@@ -86,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
- [EliteBook 2560p](hp/2560p.md) - [EliteBook 2560p](hp/2560p.md)
- [EliteBook 8760w](hp/8760w.md) - [EliteBook 8760w](hp/8760w.md)
- [EliteBook Folio 9480m](hp/folio_9480m.md) - [EliteBook Folio 9480m](hp/folio_9480m.md)
- [EliteBook 820 G2](hp/elitebook_820_g2.md)
## Intel ## Intel
@@ -125,7 +123,8 @@ The boards in this section are not real mainboards, but emulators.
### Ivy Bridge series ### Ivy Bridge series
- [T430](lenovo/t430.md) - [T430](lenovo/t430.md)
- [T530 / W530](lenovo/w530.md) - [T530](lenovo/w530.md)
- [W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) - [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
- [T431s](lenovo/t431s.md) - [T431s](lenovo/t431s.md)
- [X230s](lenovo/x230s.md) - [X230s](lenovo/x230s.md)
@@ -206,33 +205,24 @@ The boards in this section are not real mainboards, but emulators.
- [Adder Workstation 1](system76/addw1.md) - [Adder Workstation 1](system76/addw1.md)
- [Adder Workstation 2](system76/addw2.md) - [Adder Workstation 2](system76/addw2.md)
- [Adder Workstation 3](system76/addw3.md)
- [Bonobo Workstation 14](system76/bonw14.md) - [Bonobo Workstation 14](system76/bonw14.md)
- [Bonobo Workstation 15](system76/bonw15.md)
- [Darter Pro 6](system76/darp6.md) - [Darter Pro 6](system76/darp6.md)
- [Darter Pro 7](system76/darp7.md) - [Darter Pro 7](system76/darp7.md)
- [Darter Pro 8](system76/darp8.md) - [Darter Pro 8](system76/darp8.md)
- [Darter Pro 9](system76/darp9.md)
- [Galago Pro 4](system76/galp4.md) - [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md) - [Galago Pro 5](system76/galp5.md)
- [Galago Pro 6](system76/galp6.md) - [Galago Pro 6](system76/galp6.md)
- [Galago Pro 7](system76/galp7.md)
- [Gazelle 15](system76/gaze15.md) - [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md) - [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Gazelle 18](system76/gaze18.md)
- [Lemur Pro 9](system76/lemp9.md) - [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md) - [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md) - [Lemur Pro 11](system76/lemp11.md)
- [Lemur Pro 12](system76/lemp12.md)
- [Oryx Pro 5](system76/oryp5.md) - [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md) - [Oryx Pro 6](system76/oryp6.md)
- [Oryx Pro 7](system76/oryp7.md) - [Oryx Pro 7](system76/oryp7.md)
- [Oryx Pro 8](system76/oryp8.md) - [Oryx Pro 8](system76/oryp8.md)
- [Oryx Pro 9](system76/oryp9.md) - [Oryx Pro 9](system76/oryp9.md)
- [Oryx Pro 10](system76/oryp10.md) - [Oryx Pro 10](system76/oryp10.md)
- [Oryx Pro 11](system76/oryp11.md)
- [Serval Workstation 13](system76/serw13.md)
## Texas Instruments ## Texas Instruments

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@@ -9,7 +9,7 @@ updates using an A/B partitioning scheme once enabled.
## Enabling vboot ## Enabling vboot
You can enable [vboot] in Kconfig's *Security* section. Besides a verified You can enable [vboot] in Kconfig's *Security* section. Besides a verified
boot you can also enable a measured boot by setting boot you can also enable a measured boot by setting
`CONFIG_TPM_MEASURED_BOOT`. Both options need a working TPM, which is `CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
present on all recent Lenovo devices. present on all recent Lenovo devices.
## Updating and recovery ## Updating and recovery

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@@ -41,7 +41,7 @@
## Building coreboot ## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file. Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
## Flashing coreboot ## Flashing coreboot
@@ -63,6 +63,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+ +---------------------+------------+
| External flashing | yes | | External flashing | yes |
+---------------------+------------+ +---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd. Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -38,7 +38,7 @@
## Building coreboot ## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file. Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
## Flashing coreboot ## Flashing coreboot
@@ -60,6 +60,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+ +---------------------+------------+
| External flashing | yes | | External flashing | yes |
+---------------------+------------+ +---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd. Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -37,7 +37,7 @@
## Building coreboot ## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file. Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
## Flashing coreboot ## Flashing coreboot
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+ +---------------------+------------+
| External flashing | yes | | External flashing | yes |
+---------------------+------------+ +---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd. Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -37,7 +37,7 @@
## Building coreboot ## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file. Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
## Flashing coreboot ## Flashing coreboot
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+ +---------------------+------------+
| External flashing | yes | | External flashing | yes |
+---------------------+------------+ +---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd. Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -5,8 +5,6 @@
- CPU (full processor specs available at https://ark.intel.com) - CPU (full processor specs available at https://ark.intel.com)
- Intel i7-1260P (Alder Lake) - Intel i7-1260P (Alder Lake)
- Intel i3-1220P (Alder Lake) - Intel i3-1220P (Alder Lake)
- Intel i3-1315U (Raptor Lake)
- Intel i7-1360P (Raptor Lake)
- EC - EC
- ITE IT5570E - ITE IT5570E
- Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
@@ -35,15 +33,14 @@
- RTS5129 MicroSD card reader - RTS5129 MicroSD card reader
- USB - USB
- 1920x1080 CCD camera - 1920x1080 CCD camera
- USB 3.1 Gen 2 (left) (Alder Lake) - USB 3.1 Gen 2 (left)
- Thunderbolt 4.0 (left) (Raptor Lake)
- USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 2 Type-A (left)
- USB 3.1 Gen 1 Type-A (right) - USB 3.1 Gen 1 Type-A (right)
- USB 2.0 Type-A (right) - USB 2.0 Type-A (right)
## Building coreboot ## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file. Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
### Preliminaries ### Preliminaries
@@ -61,21 +58,12 @@ These files exist in the correct location in the StarLabsLtd/blobs repo on GitHu
The following commands will build a working image: The following commands will build a working image:
Alder Lake:
```bash ```bash
make distclean make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
make make
``` ```
Raptor Lake:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_rpl
make
```
## Flashing coreboot ## Flashing coreboot
```eval_rst ```eval_rst
@@ -96,6 +84,5 @@ make
+---------------------+------------+ +---------------------+------------+
| External flashing | yes | | External flashing | yes |
+---------------------+------------+ +---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd. Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -40,7 +40,7 @@
## Building coreboot ## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file. Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
## Flashing coreboot ## Flashing coreboot
@@ -62,6 +62,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+ +---------------------+------------+
| External flashing | yes | | External flashing | yes |
+---------------------+------------+ +---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd. Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -9,7 +9,6 @@ Controller etc.
- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
- [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md) - [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md)
- [X11SSM-F](x11ssm-f/x11ssm-f.md) - [X11SSM-F](x11ssm-f/x11ssm-f.md)
- [X11SSW-F](x11ssw-f/x11ssw-f.md)
## Required proprietary blobs ## Required proprietary blobs

View File

@@ -1,76 +0,0 @@
# Supermicro X11SSW-F
This section details how to run coreboot on the [Supermicro X11SSW-F].
## Flashing coreboot
Flashing was performed through the BMC web interface, when a valid license was entered.
## Tested and working
- SeaBIOS version 1.16.2 Payload loading Ubuntu 22.04, kernel 5.4.0-162-generic
- ECC ram (Linux' ie31200 driver works)
- USB ports
- Ethernet
- SATA ports
- RS232 external
- Left PCIe slot
- BMC (IPMI)
- VGA on Aspeed
## Untested
- Right PCIe slot
- NVMe
- TPM on TPM expansion header
## Known issues
- See general issue section
- LNXTHERM missing
- S3 resume not working
## Technology
```eval_rst
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+
| PCH | Intel C236 |
+------------------+--------------------------------------------------+
| Coprocessor | Intel SPS (server version of the ME) |
+------------------+--------------------------------------------------+
| Super I/O | ASPEED AST2400 |
+------------------+--------------------------------------------------+
| Ethernet | 2x Intel I210-AT 1 GbE |
| | 1x dedicated BMC |
+------------------+--------------------------------------------------+
| PCIe slots | 1x 3.0 x16 (Left Riser) |
| | 1x 3.0 x4 (Right Riser in x16) |
| | 1x 3.0 x4 (NVMe) |
+------------------+--------------------------------------------------+
| USB slots | 2x USB 2.0 (ext) |
| | 2x USB 3.0 (ext) |
| | 1x USB 3.0 (int) |
| | 1x dual USB 3.0 header |
| | 2x dual USB 2.0 header |
+------------------+--------------------------------------------------+
| SATA slots | 6x S-ATA III |
+------------------+--------------------------------------------------+
| Other slots | 1x RS232 (ext) |
| | 1x RS232 header |
| | 1x TPM header |
| | 1x Power SMB header |
| | 6x PWM Fan connector |
| | 1x Chassis Intrusion Header |
+------------------+--------------------------------------------------+
```
## Extra links
- [Supermicro X11SSW-F]
- [Board manual]
[Supermicro X11SSW-F]: https://www.supermicro.com/en/products/motherboard/x11ssw-f
[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1784.pdf
[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
[IPMI]: ../../../../drivers/ipmi_kcs.md

View File

@@ -1,71 +0,0 @@
# System76 Adder Workstation 3 (addw3)
## Specs
- CPU
- Intel Core i9-13900HX
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 4050
- NVIDIA GeForce RTX 4060
- NVIDIA GeForce RTX 4070
- eDP displays
- 15.6" 1920x1080@144Hz LCD
- 17.3" 1920x1080@144Hz LCD
- External outputs
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
- Networking
- Intel I219-V gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6E AX210/AX211
- Power
- 280W (20V, 14A) DC-in port
- Included: Chicony A18-280P1A
- 73Wh 4-cell Lithium-Ion battery
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 (PCIe NVMe Gen 4) SSDs
- MicroSD card reader
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 1x USB 3.2 Gen 1 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 15": 2.71cm x 35.95cm x 23.8cm, 2.05kg
- 17": 2.82cm x 39.69cm x 26.2cm, 2.85kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U65) is above the battery connector.

View File

@@ -1,65 +0,0 @@
# System76 Bonobo Workstation 15 (bonw15)
## Specs
- CPU
- Intel Core i9-13900HX
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 4080
- NVIDIA GeForce RTX 4090
- eDP 17.3" 3840x2160@144Hz LCD (BOE NE173QUM-NY1)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 2x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
- Networking
- Onboard Intel Killer Ethernet E3100X 2.5 GbE
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 330W (19.5V, 16.42A) AC adapter (Chicony A20-330P1A)
- Rectangular connector; not a barrel connector
- 99Wh 8-cell Lithium-ion battery
- Sound
- Realtek ALC1220 codec
- Realtek ALC1318 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 3x M.2 PCIe NVMe Gen 4 SSDs
- USB
- 2x USB Type-C with Thunderbolt 4
- 2x USB 3.2 Gen 2 Type-A
- Dimensions
- 2.49cm x 39.6cm x 27.8cm, 3.29kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U58) is next to the left M.2 port.

View File

@@ -1,62 +0,0 @@
# Syste76 Darter Pro 9 (darp9)
## Specs
- CPU
- Intel Core i5-1340P
- Intel Core i7-1360P
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 15.6" 1920x1080@60Hz LCD
- 1x HDMI
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
- Networking
- Gigabit Ethernet (Realtek RTL8111H)
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6E AX210/211)
- Power
- 90W (19V, 4.74A) AC barrel adapter
- USB-C charging, compatible with 65W+ chargers
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSDs
- MicroSD card reader (OZ711LV2)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 35.7cm x 22.05cm x 1.99cm, 1.74kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U22) is above the left DIMM slot.

View File

@@ -1,58 +0,0 @@
# System76 Galago Pro 7 (galp7)
## Specs
- CPU
- Intel Core i5-13500H
- Intel Core i7-13700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.1" 1920x1080@144Hz LCD (Sharp LQ140M1JW49)
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
- USB-C charging, compatible with 90W+ chargers
- 53Wh 4-cell Lithium-ion battery
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- USB
- 1x USB-C Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 32.49cm x 22.5cm x 1.82cm, 1.45kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U43) is left of the wireless card.

View File

@@ -1,65 +0,0 @@
# System76 Gazelle 17 (gaze17)
The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
## Specs
- CPU
- Intel Core i5-12500H
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 3050
- NVIDIA GeForce RTX 3050 Ti
- NVIDIA GeForce RTX 3060
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
- Networking
- Gigabit Ethernet
- 3050: Realtek RTL8111H controller
- 3060: Onboard Intel I219-V
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX201
- Power
- 3050: 150W (20V, 7.5A) AC barrel adapter
- 3060: 180W (20V, 9A) AC barrel adapter
- Lite-On PA-1181-76, using a C5 power cord
- 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (Realtek RTS5227S/OZ711LV2)
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The position of the flash chip depends on the variant:
- 3050: U24, below the bottom DIMM slot.
- 3060: U55, left of the PCIe 4.0 M.2 slot.

View File

@@ -1,72 +0,0 @@
# System76 Gazelle 18 (gaze18)
## Specs
- CPU
- Intel i9-13900H
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- NVIDIA GeForce RTX 3050 (70W TDP)
- Intel Irix Xe Graphics
- eDP displays
- 17.3" 1920x1080@144Hz LCD
- 15.6" 1920x1080@144Hz LCD
- External outputs
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Realtek RTL8111H gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6E AX210/AX211
- Power
- 150W AC barrel adapter
- Included: LiteOn PA-1151-76, using a C5 power cord
- 54Wh 4-cell battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- HDMI, mDP audio
- Storage
- 1x M.2 (PCIe NVMe Gen 4)
- 1x M.2 (PCIe NVMe Gen 3)
- MicroSD card reader
- Realtek RTS5227S
- USB
- 2x USB 3.2 Gen 2 Type-C
- Does not support USB-C charging (USB-PD) or Thunderbolt
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 15": 35.95cm x 23.8cm x 2.27cm, 1.99kg
- 17": 39.69cm x 26.2cm x 2.5cm, 2.41kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U24) is right of the M.2 SSD connectors.

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@@ -1,62 +0,0 @@
# System76 Lemur Pro 12 (lemp12)
## Specs
- CPU
- Intel Core i5-1335U
- Intel Core i7-1355U
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.0" 1920x1080@60Hz LCD (Innolux N140HCE-EN2)
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Channel 0: 8-GB onboard DDR5 (Samsung M425R1GB4BB0-CQKOD)
- Channel 1: 8/16/32-GB DDR5 SO-DIMM @ 4800 MHz
- Networking
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 65W (19V, 3.42A) AC adapter (AcBel ADA012)
- USB-C charging, compatible with 65W+ charger
- 73Wh 4-cell Lithium-ion battery
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5 mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thudnerbolt 4
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 3.2 Gen 1 Type-A
- Dimensions
- 1.65cm x 32.2cm x 21.68cm, 1.15kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U41) is left of the DIMM slot.

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@@ -1,66 +0,0 @@
# System76 Oryx Pro 11 (oryp11)
## Specs
- CPU
- Intel Core i9-13900H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 4050
- NVIDIA GeForce RTX 4060
- NVIDIA GeForce RTX 4070
- 16" 1920x1200@165Hz LCD
- External outputs:
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
- Networking
- Realtek RTL8125BG-CG 2.5G Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 180W (20V, 9A) AC barrel adapter (Lite-On PA-1181-86)
- 73Wh 4-cell Lithium-ion battery (NV40BAT-4-73)
- Sound
- Realtek ALC1220 codec
- Realtek ALC1318 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (Realtek RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 2x USB 2.1 Gen 1 Type-A
- Dimensions
- 35.95cm x 27.3cm x 1.99cm, 2.7kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U61) is left of the memory slots.

View File

@@ -1,69 +0,0 @@
# System76 Serval Workstation 13 (serw13)
## Specs
- CPU
- Intel Core i9-13900HX
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 4060
- NVIDIA GeForce RTX 4070
- eDP options:
- 15.6" 1920x1080@165Hz LCD (BOE NV156FHM-NY8)
- 17.6" 3840x2160@144Hz LCD (AUO B173ZAN03.0)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
- Networking
- Realtek RTL8125BG-CG 2.5G Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 280W (20V, 14A) AC adapter (Chicony A18-280P1A)
- 80Wh 6-cell Lithium-ion battery ()
- Sound
- Realtek ALC1220 codec
- Realtek ALC1318 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSDs
- MicroSD card reader (Realtek RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 2x USB 3.2 Gen 1 Type-A
- Dimensions
- 15": 2.49cm x 35.8cm x 24.0cm, 2.4kg
- 17": 2.49cm x 39.6cm x 26.2cm, 2.8kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U46) is left of the memory slots.

View File

@@ -1,99 +0,0 @@
Upcoming release - coreboot 24.02
========================================================================
The 24.02 release is scheduled for Mid February, 2024
Update this document with changes that should be in the release notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
### Release number format update
The previous release was the last to use the incrementing 4.xx release
name scheme. For this and future releases, coreboot has switched to a
Year.Month.Sub-version naming scheme. As such, the next release,
scheduled for May of 2024 will be numbered 24.05, with the sub-version
of 00 implied. If we need to do a fix or incremental release, well
append the values .01, .02 and so on to the initial release value.
Significant or interesting changes
----------------------------------
* Add changes that need a full description here
* This section should have full descriptions and can or should have
a link to the referenced commits.
Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
Changes to external resources
-----------------------------
### Toolchain updates
### Git submodule pointers
### External payloads
Platform Updates
----------------
### Added mainboards:
* To be filled in immediately before the release by the release team
### Removed Mainboards
* To be filled in immediately before the release by the release team
### Updated SoCs
* To be filled in immediately before the release by the release team
Plans to move platform support to a branch
------------------------------------------
* To be filled in immediately before the release by the release team
Statistics from the 4.22 to the 24.02 release
--------------------------------------------
* To be filled in immediately before the release by the release team
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
* To be filled in immediately before the release by the release team
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

View File

@@ -15,10 +15,6 @@ It takes constant effort to just stay afloat, let alone improve the
codebase. Thank you very much to everyone who has contributed, both in codebase. Thank you very much to everyone who has contributed, both in
this release and in previous times. this release and in previous times.
Note that the first set of tarballs posted for the 4.19 release had
bad timestamps. This has been fixed. Hashes for all tarballs are at
the bottom of this document.
The 4.20 release is planned for the 20th of April, 2023. The 4.20 release is planned for the 20th of April, 2023.
@@ -248,20 +244,3 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD | | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
+-----+-----------------------------------------------------------------+ +-----+-----------------------------------------------------------------+
``` ```
Hashes for tarballs & signatures
--------------------------------
Old tarballs:
- a1f9ec1252a3cc19f0b4ba1a2b9d66ea9327499cbeecebd85377db7d5c68555d coreboot-4.19.tar.xz
- 6ceaa39429a2094d75e4c8a94615ae60664ddad7b4115570b65b9bb516cbd96d coreboot-4.19.tar.xz.sig
- 881a3477221d1b77e161759344df14eccda115086af3ef54e66485ae0eb2e5d9 coreboot-blobs-4.19.tar.xz
- 16f4f1f7acc6203ce915ffea64edce8512bd9eb9e94e65db22a0cb5282a6e157 coreboot-blobs-4.19.tar.xz.sig
New tarballs:
- 65ccb2f46535b996e0066a1b76f81c8cf1ff3e27df84b3f97d8ad7b3e7cf0a43 coreboot-4.19.tar.xz
- d3c52a209b8ccb49049960318f04f158dd47db52ebe6019d6a3dffe3196d9cbe coreboot-4.19.tar.xz.sig
- 30214caed07b25f11e47bec022ff6234841376e36689eb674de2330a3e980cbc coreboot-blobs-4.19.tar.xz
- 023d511d074703beab98c237c3e964dc7c598af86d5a0e2091195c68980b6c5d coreboot-blobs-4.19.tar.xz.sig

View File

@@ -1,16 +1,10 @@
coreboot 4.20 release Upcoming release - coreboot 4.20
======================================================================== ========================================================================
The 4.20 release was done on May 15, 2023. Unfortunately, a licensing The 4.20 release is being done on May 15, 2023.
issues was found immediately after the release was completed, and it
was decided to hold the release until that was fixed.
Please do not use the 4.20 tag, and use the 4.20.1 git tag instead. The
4.20_branch will contain all code for 4.20, 4.20.1, and any further
changes required for this release.
The coreboot community has done a tremendous amount of work on the The coreboot community has done a tremendous amount of work on the
codebase over the last three and a half months. We've had over 1600 codebase over the last three and a half month. We've had over 1600
commits in that time period, doing ongoing cleanup and improvement. commits in that time period, doing ongoing cleanup and improvement.
It can be hard to remember at times how much the codebase really has It can be hard to remember at times how much the codebase really has
@@ -25,23 +19,20 @@ or push even a single patch to fix a bug that they've noticed.
Many thanks to everyone involved! Many thanks to everyone involved!
We plan to get the 4.21 release done in mid August, 2023. We plan to get the 4.21 release done in mid August, 2023,
Significant or interesting changes Significant or interesting changes
---------------------------------- ----------------------------------
### cpu/mp_init.c: Only enable CPUs once they execute code ### cpu/mp_init.c: Only enable CPUs once they execute code
On some systems the BSP cannot know how many CPUs are present in the On some systems the BSP cannot know how many CPUs are present in the
system. A typical use case is a multi socket system. Setting the enable system. A typical use case is a multi socket system. Setting the enable
flag only on CPUs that actually exist makes it more flexible. flag only on CPUs that actually exist makes it more flexible.
### cpu/x86/smm: Add PCI resource store functionality ### cpu/x86/smm: Add PCI resource store functionality
In certain cases data within protected memory areas like SMRAM could In certain cases data within protected memmory areas like SMRAM could
be leaked or modified if an attacker remaps PCI BARs to point within be leaked or modified if an attacker remaps PCI BARs to point within
that area. Add support to the existing SMM runtime to allow storing that area. Add support to the existing SMM runtime to allow storing
PCI resources in SMRAM and then later retrieving them. PCI resources in SMRAM and then later retrieving them.
@@ -49,12 +40,10 @@ PCI resources in SMRAM and then later retrieving them.
This helps prevent moving BARs around to get SMM to access memory in This helps prevent moving BARs around to get SMM to access memory in
areas that shouldn't be accessed. areas that shouldn't be accessed.
### acpi: Add SRAT x2APIC table support ### acpi: Add SRAT x2APIC table support
For platforms using X2APIC mode add SRAT x2APIC table For platforms using X2APIC mode add SRAT x2APIC table
generation. This allows the setup of proper SRAT tables. generation. This allows to setup proper SRAT tables.
### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port ### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
@@ -68,11 +57,10 @@ The ACPI and USB driver of linux kernel need corresponding functions
to support this feature. Please see to support this feature. Please see
https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
### drivers/efi: Add EFI variable store option support ### drivers/efi: Add EFI variable store option support
Add a driver to read and write EFI variables stored in a region device. Add a driver to read and write EFI variables stored in a region device.
This is particularly useful for EDK2 as payload and allows it to reuse This is particularly useful for EDK2 as payload and allows to reuse
existing EFI tools to set/get options used by the firmware. existing EFI tools to set/get options used by the firmware.
The write implementation is fault tolerant and doesn't corrupt the The write implementation is fault tolerant and doesn't corrupt the
@@ -101,11 +89,11 @@ variable, first a new is written to the end of the store and then the
previous is marked invalid. This only works on PNOR flash that allow to previous is marked invalid. This only works on PNOR flash that allow to
clear set bits, but keep cleared bits state. clear set bits, but keep cleared bits state.
This mechanisms allows a fault tolerant write, but it also requires to This mechanisms allows a fault tolerant write, but it also requires to
"clean" the variable store from time to time. This cleaning would remove "clean" the variable store for time to time. This cleaning would remove
variables that have been marked "deleted". variables that have been marked "deleted".
Such cleaning mechanism in turn must be fault tolerant and thus must use Such cleaning mechanism in turn must be fault tolerant and thus must use
a second partition in the SPI flash as backup/working region. a second partition in the SPI flash as backup/working region.
For now, cleaning is done in coreboot. For now to cleaning is done in coreboot.
Fault checking: Fault checking:
The driver should check if a previous write was successful and if not The driver should check if a previous write was successful and if not
@@ -117,7 +105,6 @@ mark variables as deleted on the next operation.
Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
and prints EWL type 3 primarily associated with MRC training failures. and prints EWL type 3 primarily associated with MRC training failures.
### Toolchain updates ### Toolchain updates
* Upgrade MPC from version 1.2.1 to 1.3.1 * Upgrade MPC from version 1.2.1 to 1.3.1
@@ -127,7 +114,6 @@ and prints EWL type 3 primarily associated with MRC training failures.
* Upgrade GCC from version 11.2.0 to 11.3.0 * Upgrade GCC from version 11.2.0 to 11.3.0
* Upgrade binutils from version 2.37 to 2.40 * Upgrade binutils from version 2.37 to 2.40
Additional coreboot changes Additional coreboot changes
--------------------------- ---------------------------
@@ -149,10 +135,8 @@ Additional coreboot changes
* Do initial work on Xeon SPR * Do initial work on Xeon SPR
* CMOS defaults greater than 128 bytes long now extend to bank 1. * CMOS defaults greater than 128 bytes long now extend to bank 1.
New Mainboards New Mainboards
-------------- --------------
* Asrock: B75M-ITX * Asrock: B75M-ITX
* Dell: Latitude E6400 * Dell: Latitude E6400
* Google: Aurash * Google: Aurash
@@ -178,21 +162,16 @@ New Mainboards
* System76: oryp10 * System76: oryp10
* System76: oryp9 * System76: oryp9
Removed Mainboards Removed Mainboards
------------------ ------------------
* Intel Icelake U DDR4/LPDDR4 RVP * Intel Icelake U DDR4/LPDDR4 RVP
* Intel Icelake Y LPDDR4 RVP * Intel Icelake Y LPDDR4 RVP
* Scaleway TAGADA * Scaleway TAGADA
Updated SoCs Updated SoCs
------------ ------------
* Removed soc/intel/icelake * Removed soc/intel/icelake
Plans to move platform support to a branch Plans to move platform support to a branch
------------------------------------------ ------------------------------------------
@@ -209,57 +188,39 @@ be maintained on the release 4.20 branch.
* Intel Quark SoC * Intel Quark SoC
* Intel Galileo mainboard * Intel Galileo mainboard
Statistics from the 4.19 to the 4.20 release Statistics from the 4.19 to the 4.20 release
-------------------------------------------- --------------------------------------------
Total Commits: 1630 Total Commits: ~1625
Average Commits per day: 13.72 Average Commits per day: ~13.71
Total lines added: 102592 Total lines added: ~101911
Average lines added per commit: 62.94 Average lines added per commit: ~62.71
Number of patches adding more than 100 lines: 128 Number of patches adding more than 100 lines: ~126
Average lines added per small commit: 37.99 Average lines added per small commit: ~37.98
Total lines removed: 34824 Total lines removed: ~34756
Average lines removed per commit: 21.36 Average lines removed per commit: ~21.39
Total difference between added and removed: 67768 Total difference between added and removed: ~67155
Total authors: ~170 Total authors: ~170
New authors: ~35 New authors: ~35
Significant Known and Open Issues Significant Known and Open Issues
--------------------------------- ---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject | | # | Subject |
+=====+=================================================================+ |-----|-----------------------------------------------------------------|
| 478 | X200 booting Linux takes a long time with TSC | | 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM | | 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | | 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit | | 453 | Intel HDMI / DP Audio device not showing up after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking | | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues | | 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post | | 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) | | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues | | 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT | | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend | | 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend | | 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar | | 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD | | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
+-----+-----------------------------------------------------------------+
```

View File

@@ -1,407 +1,51 @@
Upcoming release - coreboot 4.21 Upcoming release - coreboot 4.21
======================================================================== ========================================================================
The 4.21 release is scheduled for August 21st, 2023 The 4.21 release is planned for mid-August, 2023
In the past quarter year, the coreboot project has gotten over 1200 new Update this document with changes that should be in the release notes.
patches from around 140 authors, 20 of whom contributed for the first
time.
Thank you to all of our donors, the code contributors, the people who * Please use Markdown.
take time to review all of those patches and all of the people who care * See the past few release notes for the general format.
about the coreboot project. There have been a number of new companies * The chip and board additions and removals will be updated right
starting to use coreboot recently, and we appreciate all of the before the release, so those do not need to be added.
contributions and support. * Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
### Upcoming switch from master branch to main branch
Historically, the initial branch that was created in a new git
repository was named master. In line with many other projects,
coreboot has decided to switch away from this name and use the name
main instead. You can read about the initial reasoning on the SFCs
website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
At some point before the 4.22 release, coreboot will be switching from
the master branch to the main branch. This shouldnt be a difficult
change for most people, as everyone will just have to rebase on top of
a different branch name.
Weve already created the main branch, and it is currently synced with
the master branch. Please update any scripts to point to main instead
of master.
At the point of the changeover, we will move all patches in gerrit to
the main branch and disable pushes to the master branch.
After the switch, we will sync the main branch to the master branch for
a while to give people a little more time to update any scripts that
are currently pointed at the master branch. Note that this update will
probably be done just once per day, and the frequency of updates will
be decreased over time. We plan to stop updating the master branch
following the 4.22 release.
Significant or interesting changes Significant or interesting changes
---------------------------------- ----------------------------------
### lib: Support localized text of memory_training_desc in ux_locales.c ### Add changes that need a full description here
Most of the text in coreboot is for logging, and does not use
localization. There are however, some bits of text that can be
presented to the user, and this patch supplies a method to localize
them.
To support the localized text, we need to get the locale id by vboot
APIs and read raw string content file: preram_locales located at either
RO or RW.
The preram_locales file follows the format:
[PRERAM_LOCALES_VERSION_BYTE (\x01)]
[string_name_1] [\x00]
[locale_id_1] [\x00] [localized_string_1] [\x00]
[locale_id_2] [\x00] [localized_string_2] …
[\x01]
[string_name_2] [\x00] ...
This code will search for the correct localized string that its string
name is `memory_training_desc` and its locale ID matches the ID vb2api
returns. If no valid string found, we will try to display in English
(locale ID 0).
### Improved the bootsplash support
The JPEG decoder, that was added many years ago to display a bootsplash
in coreboot, has a few quirks. People used to do some voodoo with GIMP
to convert images to the right format, but we can also achieve the same
with ImageMagick's `convert`. The currently known constraints are:
* The framebuffer's color format is ignored,
* only YCC 4:2:0 color sampling is supported, and
* width and height have to be a multiple of 16 pixels.
Beside that, we can only display the bootsplash if it completely fits
into the framebuffer. As the latter's size is often decided at runtime,
we can't do much more than offering an option to set a specific size.
The build system has been extended so that the necessary adjustments to
the picture can be done by it and several options have been added to
Kconfig.
### libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
This is a complete rewrite of the UHCI root-hub driver, based on the
xHCI one. We are doing things by the book as far as possible. One
special case is uhci_rh_reset_port() which does the reset sequencing
that usually the hardware would do.
This abandons some quirks of the old driver:
* Ports are not disabled/re-enabled for every attachment anymore.
* We solely rely on the Connect Status Change bit to track changes.
* Further status changes are now deferred to the next polling round.
### linux_trampoline: Handle coreboot framebuffer & 64-bit addresses
Translate the coreboot framebuffer info from coreboot tables to the
Linux zero page.
To support full 64-bit addresses, there is a new field `ext_lfb_base`
since Linux 4.1. It is unclear, however, how a loader is supposed to
know if the kernel is compatible with this. Filling these previously
reserved bits doesn't hurt, but an old kernel would probably ignore
them and not know that it's handling a clipped, invalid address. So we
play safe, and only allow 64-bit addresses for kernels after the 2.15
version bump of the boot protocol.
### arch/x86: Don't allow hw floating point operations
Even though coreboot does not allow floating point operations, some
compilers like clang generate code using hw floating point registers,
e.g. SSE %XMMx registers on 64bit code by default. Floating point
operations need to be enabled in hardware for this to work (CR4). Also
in SMM we explicitly need to save and restore floating point registers
for this reason. If we instruct the compiler to not generate code with
FPU ops, this simplifies our code as we can skip that step.
With clang this reduces the binary size a bit. For instance ramstage
for emulation/qemu-q35 drops by 4 kB from from 216600 bytes
decompressed to 212768 bytes.
Since we now explicitly compile both ramstage and smihandler code
without floating point operations and associated registers we don't
need to save/restore floating point registers in SMM.
The EFER MSR is in the SMM save state and RSM properly restores it.
Returning to 32bit mode was only done so that fxsave was done in the
same mode as fxrstor, but this is no longer done.
### Caching of PCIe 5.0 HSPHY firmware in SPI flash
This adds the ability to cache the PCIe 5.0 HSPHY firmware in the SPI
flash. A new flashmap region is created for that purpose. The goal of
caching is to reduce the dependency on the CSME (Converged Security and
Management Engine) and the HECI (Host Embedded Controller Interface) IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP (High Assurance Platform mode). By
caching that firmware, this allows the PCIe 5.0 root ports to keep
functioning even if CSME/HECI is not functional.
### Extracting of TPM logs using cbmem tool
CBMEM can contain logs in different forms (at most one is present):
* coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
LB_TAG_TPM_CB_LOG)
* TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
* TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
The last two follow specifications by Trusted Computing Group, but
until now cbmem couldn't print them.
These changes make the cbmem utility check for existence of TPM1.2/TPM2
logs in CBMEM and add code necessary for parsing and printing of their
entries.
`cbmem -L` for CONFIG_TPM1=y case
```
TCPA log:
Specification: 1.21
Platform class: PC Client
TCPA log entry 1:
PCR: 2
Event type: Action
Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
Event data: FMAP: FMAP
```
`cbmem -L` for CONFIG_TPM2=y case
```
TPM2 log:
Specification: 2.00
Platform class: PC Client
TPM2 log entry 1:
PCR: 2
Event type: Action
Digests:
SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
Event data: FMAP: FMAP
```
### soc/amd: read domain resource window configuration from hardware
Read the MMIO and IO decode windows for the PCI root complex and the
PCI bus number range decoded to the PCI root complex from the data
fabric registers and pass the information to the resource allocator so
it has the correct constraints to do its job. Also generate the
corresponding ACPI resource producers in the SSDT so that the OS knows
about this too. This is required for the upcoming USB 4 support.
* This section should have full descriptions and can or should have
a link to the referenced commits.
Additional coreboot changes Additional coreboot changes
--------------------------- ---------------------------
* Added SPDX headers to more files to help automated license checking. The following are changes across a number of patches, or changes worth
The linter has been enabled to check the Makefiles as well. noting, but not needing a full description.
* Cleaned up Kconfig files and source code.
* Enabled acpigen to generate tables for SPCR (Serial Port Console
Redirection) and GTDT (Generic Timer Description Table).
* The resource allocation above the 4GiB boundary has been improved.
* Most of the code has been adjusted to make use of C99 flexible arrays
instead of one-element or zero-length arrays.
* Additional Dockerfiles based on Arch and Alpine Linux have been added
to build-test with alternate build environments, including musl-libc.
They are very basic at the moment and not equal to the coreboot-sdk.
They will be extended in the future.
* Added support for ITE IT8784E to superiotool.
* Added support for Intel 700 chipset series to inteltool and a build
issue with musllibc has been fixed.
* Added support for Intel 800 chipset series to ifdtool.
* The coreboot-sdk container has been extended so that it allows
extracting the MRC binary from Haswell-based ChromeOS firmware images.
* From now on POST code preprocessor macros should have a POSTCODE
prefix following the name of the POST code.
* The NASM compiler provided by the coreboot toolchain wasnt properly
integrated into xcompile and thus it wasnt used by the build system.
Instead, it was required to install NASM on the host in order to use
it. This has been fixed.
* The time measurement done in abuild got improved and also an issue
has been fixed when the variant name contains hyphens.
* The RISC-V code was enabled to build with Clang.
* Initial work has been done to transform Camelcase options to
Snakecase.
* The buildgcc script is now able to just fetch the tarballs if desired,
which is needed for reproducible build environments for example.
* Changes that only need a line or two of description go here.
Platform Updates
----------------
Changes to external resources * To be filled in immediately before the release by the release team
-----------------------------
### Toolchain Plans to move platform support to a branch
------------------------------------------
* binutils
* Added binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch
* Upgrade IASL from 20221020 to 20230628
* Upgrade LLVM from 15.0.7 to 16.0.6
* Upgrade NASM from 2.15.05 to 2.16.01
* Added nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
* Upgrade CMake from 3.26.3 to 3.26.4
* Upgrade GCC from 11.3.0 to 11.4.0
* Added gcc-11.4.0_rv32iafc.patch
### Git submodule pointers
#### /3rdparty
* amd_blobs: Update from commit id 1cd6ea5cc5 to 6a1e1457af (5 commits)
* arm-trusted-firmware: Update from commit id 4c985e8674 to 37366af8d4
(851 commits)
* blobs: Update from commit id 01ba15667f to a8db7dfe82 (14 commits)
* fsp: Update from commit id 6f2f17f3d3 to 3beceb01f9 (24 commits)
* intel-microcode: Update from commit id 2be47edc99 to 6f36ebde45 (5
commits)
* libgfxinit: Update from commit id 066e52eeaa to a4be8a21b0 (18
commits)
* libhwbase: Update from commit id 8be5a82b85 to 584629b9f4 (2 commits)
* qc_blobs: Update from commit id 33cc4f2fd8 to a252198ec6 (4 commits)
* vboot: Update from commit id 35f50c3154 to 0c11187c75 (83 commits)
#### /util
* goswid: Update from commit id bdd55e4202 to 567a1c99b0 (5 commits)
* nvidia/cbootimage: Update from commit id 65a6d94dd5 to 80c499ebbe (1
commit)
### External payloads
* Update the depthcharge payload from commit ID 902681db13 to c48613a71c
* Upgrade EDK2-MrChromebox from version 202304 to version 202306
* Upgrade SeaBIOS from version 1.16.1 to version 1.16.2
* Update tint from version 0.05 to version 0.07
* Update U-Boot from version 2021.07 to version v2023.07
Added mainboards:
-----------------
* ByteDance ByteDance bd_egs
* Google: Craaskov
* Google: Expresso
* Google: Karis
* Google: Karis4ES
* Google: Pirrha
* Google: Ponyta
* Google: Screebo4ES
* Google: Ovis
* Google: Ovis4ES
* Google: Rex EC ISH
* Google: Rex4ES
* HP Compaq Elite 8300 USDT
* HP EliteBook 820 G2
* IBM SBP1
* Intel Raptorlake silicon with Alderlake-P RVP
* Inventec Transformers
* MSI PRO Z790-P (WIFI)
* MSI PRO Z790-P (WIFI) DDR4
* Star Labs Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
* System76 addw3
* System76 bonw15
* System76 darp9
* System76 galp7
* System76 gaze17 3050
* System76 gaze17 3060-b
* System76 gaze18
* System76 lemp12
* System76 oryp11
* System76 serw13
Removed Mainboards
------------------
* Intel Galileo
Updated SoCs
------------
* Removed src/soc/intel/quark
* Seciton to be filled in or removed after discussion
Statistics from the 4.20 to the 4.21 release Statistics from the 4.20 to the 4.21 release
-------------------------------------------- --------------------------------------------
* Total Commits: 1252 * To be filled in immediately before the release by the release team
* Average Commits per day: 12.59
* Total lines added: 317734
* Average lines added per commit: 253.78
* Number of patches adding more than 100 lines: 86
* Average lines added per small commit: 36.22
* Total lines removed: 261063
* Average lines removed per commit: 208.52
* Total difference between added and removed: 56671
* Total authors: 143
* New authors: 21
Significant Known and Open Issues Significant Known and Open Issues
--------------------------------- ---------------------------------
* To be filled in immediately before the release by the release team
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 495 | Stoney chromebooks not booting PSPSecureOS |
+-----+-----------------------------------------------------------------+
| 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
+-----+-----------------------------------------------------------------+
```
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* IRC: https://web.libera.chat/#coreboot
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

View File

@@ -1,349 +0,0 @@
coreboot 4.22 & 4.22.01 releases
========================================================================
The next release is planned for the 19th of February, 2024
These notes cover the latest updates and improvements to coreboot over
the past three months. A big thank you to the returning contributors as
well as the 14 individuals who committed code for the first time. We
greatly appreciate everyone's dedication and expertise. As with past
releases, this one reflects a commitment to open source innovation,
security enhancements, and expanding hardware support.
### 4.22.01 release
The week between tagging a release and announcing it publicly is used
to test the tagged version and make sure everything is working as we
expect. This is done instead of freezing the tree and doing release
candidates before the release.
For the 4.22 release cycle we found an uninitialized variable error on
the sandybridge/ivybridge platforms and rolled that into the 4.22.01
release package.
### coreboot version naming update
This release is the last release to use the incrementing 4.xx release
name scheme. For future releases, coreboot is switching to a
Year.Month.Sub-version naming scheme. As such, the next release,
scheduled for February of 2024 will be numbered 24.02, with the
sub-version of 00 implied. If we need to do a fix or future release of
the 24.02 release, we'll append the values .01, .02 and so on to the
initial release value.
### coreboot default branch update
Immediately after the 4.21 release, the coreboot project changed the
default git branch from 'master' to 'main'. For the first couple of
months after the change, The master branch was synced with the main
branch several times a day, allowing people time to update any scripts.
As of 2023-11-01, the sync rate has slowed to once a week. This will
continue until the next release, at which time the master branch will
be removed.
Significant or interesting changes
----------------------------------
### x86: support .data section for pre-memory stages
x86 pre-memory stages did not support the `.data` section and as a
result developers were required to include runtime initialization code
instead of relying on C global variable definitions.
Other platforms do not have that limitation. Hence, resolving it helps
to align code and reduce compilation-based restrictions (cf. the use of
`ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot
code).
There were three types of binary to consider:
1. eXecute-In-Place pre-memory stages
2. `bootblock` stage is a bit different as it uses Cache-As-Ram but
the memory mapping and its entry code different
3. pre-memory stages loaded in and executed from Cache-As-RAM
(cf. `CONFIG_NO_XIP_EARLY_STAGES`).
eXecute-In-Place pre-memory stages (#1) rely on a new ELF segment as
the code segment Virtual Memory Address and Load Memory Address are
identical but the data needs to be linked in cache-As-RAM (VMA) to be
stored right after the code (LMA).
`bootblock` (#2) also uses this new segment to store the data right
after the code and it loads it to Cache-As-RAM at runtime. However, the
code involved is different.
Not eXecute-In-Place pre-memory stages (#3) did not need any special
work other than enabling a .data section as the code and data VMA / LMA
translation vector is the same.
Related important commits:
- c9cae530e5 ("cbfstool: Make add-stage support multiple ignore sections")
- 79f2e1fc8b ("cbfstool: Make add-stage support multiple loadable segments")
- b7832de026 ("x86: Add .data section support for pre-memory stages")
### x86: Support CBFS cache for pre-memory stages and ramstage
The CBFS cache scratchpad offers a generic way to decompress CBFS files
through the cbfs_map() function without having to reserve a per-file
specific memory region.
CBFS cache x86 support has been added to pre-memory stages and
ramstage.
1. **pre-memory stages**: The new `PRERAM_CBFS_CACHE_SIZE` Kconfig can
be used to set the pre-memory stages CBFS cache size. A cache size
of zero disables the CBFS cache feature for all pre-memory stages.
The default value is 16 KiB which seems a reasonable minimal value
enough to satisfy basic needs such as the decompression of a small
configuration file. This setting can be adjusted depending on the
platform's needs and capabilities.
Note that we have set this size to zero for all the platforms
without enough space in Cache-As-RAM to accommodate the default
size.
2. **ramstage**: The new `RAMSTAGE_CBFS_CACHE_SIZE` Kconfig can be used
to set the ramstage CBFS cache size. A cache size of zero disables
the CBFS cache feature for ramstage. Similarly to pre-memory stages
support, the default size is 16 KiB.
As we want to support the S3 suspend/resume use case, the CBFS cache
memory cannot be released to the operating system and therefore
cannot be an unreserved memory region. The ramstage CBFS cache
scratchpad is defined as a simple C static buffer as it allows us to
keep the simple and robust design of the static initialization of
the `cbfs_cache` global variable (cf. src/lib/cbfs.c).
However, since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR`
Kconfig) already define a `_cbfs_cache` region we also introduced a
`POSTRAM_CBFS_CACHE_IN_BSS` Kconfig to gate the use of a static
buffer as the CBFS cache scratchpad.
### Allow romstage to be combined into the bootblock
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
This is controlled via a Kconfig option.
### soc/intel/cmn/gfx: Add API to report presence of external display
This implements an API to report the presence of an external display on
Intel silicon. The API uses information from the transcoder and
framebuffer to determine if an external display is connected.
For example, if the transcoder is attached to any DDI ports other than
DDI-A (eDP), and the framebuffer is initialized, then it is likely that
an external display is present.
This information can be used by payloads to determine whether or not to
power on the display, even if eDP is not initialized.
### device/pci_rom: Set VBIOS checksum when filling VFCT table
AMD's Windows display drivers validate the checksum of the VBIOS data
in the VFCT table (which gets modified by the FSP GOP driver), so
ensure it is set correctly after copying the VBIOS into the table if
the FSP GOP driver was run. Without the correct checksum, the Windows
GPU drivers will fail to load with a code 43 error in Device Manager.
Additional coreboot changes
---------------------------
* Move all 'select' statements from Kconfig.name files to Kconfig
* acpigen now generates variable-length PkgLength fields instead of a
fixed 3-byte size to improve compatibility and to bring it in line
with IASL
* Work to allow Windows to run on more Chromebooks
* General cleanup and reformatting
* Add initial AMD openSIL implementation
* Add ACPI table generation for ARM64
* Stop resetting CMOS during s3 resume even if marked as invalid
* Comply with ACPI specification by making _STR Unicode strings
* Fix SMM get_save_state calculation, which was broken when STM was
enabled
* SNB+MRC boards: Migrate MRC settings to devicetree
* Work on chipset devicetrees for all platforms
Changes to external resources
-----------------------------
### Toolchain updates
* Upgrade GMP from 6.2.1 to 6.3.0
* Upgrade binutils from 2.40 to 2.41
* Upgrade MPFR from 4.2.0 to 4.2.1
### Git submodule pointers
* amd_blobs: Update from commit id 6a1e1457af to e4519efca7 (16
commits)
* arm-trusted-firmware: Update from commit id 37366af8d4 to 88b2d81345
(214 commits)
* fsp: Update from commit id 3beceb01f9 to 481ea7cf0b (15 commits)
* intel-microcode: Update from commit id 6f36ebde45 to 6788bb07eb (1
commit)
* vboot: Update from commit id 0c11187c75 to 24cb127a5e (24 commits)
* genoa_poc/opensil: New submodule updated to 0411c75e17 (41 commits)
### External payloads
* U-Boot: Use github mirror and the latest version
* edk2: Update default branch for MrChromebox repo to 2023-09
Platform Updates
----------------
### Added 17 mainboards
* AMD Onyx
* Google: Anraggar
* Google: Brox
* Google: Chinchou
* Google: Ciri
* Google: Deku
* Google: Deku4ES
* Google: Dexi
* Google: Dochi
* Google: Nokris
* Google: Quandiso
* Google: Rex4ES EC ISH
* Intel: Meteorlake-P RVP with Chrome EC for non-Prod Silicon
* Purism Librem 11
* Purism Librem L1UM v2
* Siemens FA EHL
* Supermicro X11SSW-F
### Added 1 SoC
* src/soc/amd/genoa
Statistics from the 4.21 to the 4.22 release
--------------------------------------------
* Total Commits: 977
* Average Commits per day: 10.98
* Total lines added: 62993
* Average lines added per commit: 64.48
* Number of patches adding more than 100 lines: 60
* Average lines added per small commit: 37.55
* Total lines removed: 30042
* Average lines removed per commit: 30.75
* Total difference between added and removed: 32951
* Total authors: 135
* New authors: 14
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
### Payload-specific issues
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 496 | Missing malloc check in libpayload |
+-----+-----------------------------------------------------------------+
| 484 | No USB keyboard support with secondary payloads |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
```
### Platform-specific issues
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 509 | SD Card hotplug not working on Apollo Lake |
+-----+-----------------------------------------------------------------+
| 507 | Windows GPU driver fails on Google guybrush & skyrim boards |
+-----+-----------------------------------------------------------------+
| 506 | APL/GML don't boot OS when CPU microcode included "from tree" |
+-----+-----------------------------------------------------------------+
| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system |
+-----+-----------------------------------------------------------------+
| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 495 | Stoney Chromebooks not booting PSPSecureOS |
+-----+-----------------------------------------------------------------+
| 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
```
Plans for the next release
--------------------------
* Finish adding chipset device trees for all SOCs
* Improve code for options/setup
* Start reformatting C files with clang-format
* Add warning/error step for Makefiles at the end
coreboot Links and Contact Information
--------------------------------------
* Main Website: https://www.coreboot.org
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

View File

@@ -3,7 +3,7 @@
## Upcoming release ## Upcoming release
Please add to the release notes as changes are added: Please add to the release notes as changes are added:
* [24.02 - February 2024](coreboot-24.02-relnotes.md) * [4.21 - August 2023](coreboot-4.21-relnotes.md)
The [checklist] contains instructions to ensure that a release covers all The [checklist] contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch important things and provides a reliable format for tarballs, branch
@@ -15,28 +15,26 @@ important is taken care of.
## Previous releases ## Previous releases
* [4.22 - November 2023](coreboot-4.22-relnotes.md) * [4.20 - May 2023](coreboot-4.20-relnotes.md)
* [4.21 - August 2023](coreboot-4.21-relnotes.md) * [4.19 - January 2023](coreboot-4.19-relnotes.md)
* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md) * [4.18 - October 2022](coreboot-4.18-relnotes.md)
* [4.19 - January 2023](coreboot-4.19-relnotes.md) * [4.17 - May 2022](coreboot-4.17-relnotes.md)
* [4.18 - October 2022](coreboot-4.18-relnotes.md) * [4.16 - February 2022](coreboot-4.16-relnotes.md)
* [4.17 - May 2022](coreboot-4.17-relnotes.md) * [4.15 - November 2021](coreboot-4.15-relnotes.md)
* [4.16 - February 2022](coreboot-4.16-relnotes.md) * [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md) * [4.13 - November 2020](coreboot-4.13-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md) * [4.12 - May 2020](coreboot-4.12-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md) * [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md) * [4.10 - July 2019](coreboot-4.10-relnotes.md)
* [4.11 - November 2019](coreboot-4.11-relnotes.md) * [4.9 - December 2018](coreboot-4.9-relnotes.md)
* [4.10 - July 2019](coreboot-4.10-relnotes.md) * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
* [4.9 - December 2018](coreboot-4.9-relnotes.md) * [4.7 - January 2018](coreboot-4.7-relnotes.md)
* [4.8.1 - May 2018](coreboot-4.8.1-relnotes.md) * [4.6 - April 2017](coreboot-4.6-relnotes.md)
* [4.7 - January 2018](coreboot-4.7-relnotes.md) * [4.5 - October 2016](coreboot-4.5-relnotes.md)
* [4.6 - April 2017](coreboot-4.6-relnotes.md) * [4.4 - May 2016](coreboot-4.4-relnotes.md)
* [4.5 - October 2016](coreboot-4.5-relnotes.md) * [4.3 - January 2016](coreboot-4.3-relnotes.md)
* [4.4 - May 2016](coreboot-4.4-relnotes.md) * [4.2 - October 2015](coreboot-4.2-relnotes.md)
* [4.3 - January 2016](coreboot-4.3-relnotes.md) * [4.1 - July 2015](coreboot-4.1-relnotes.md)
* [4.2 - October 2015](coreboot-4.2-relnotes.md)
* [4.1 - July 2015](coreboot-4.1-relnotes.md)
[checklist]: checklist.md [checklist]: checklist.md

View File

@@ -1,81 +0,0 @@
# Relocatable Modules (rmodules)
Relocatable modules are currently only used on x86. Relocatable
modules are executables. Exectuables which can be executed anywhere in
memory. Anywhere means that the module does not need to be executed
at a defined memory address which is known at build/link time. For
coreboot stages like bootblock and romstage it is known at build
time at which addresses they are executed. For some exectuables it
is however not known at which specific address they are executed in
runtime (for example postcar and ramstage). Relocateable modules
usually allocate the space for the modules just before they are
supposed to be executed. After enough space is allocated, CBMEM will
return the location of the allocated space. Now the relocation can be
done by fixing up all relocation entries in the relocatable module
based on the location of the binary (which was returned by CBMEM
at runtime).
# Implementation Details
## build time
At build time the rmodtool (util/cbfstool/rmodtool.c) is used to
create relocatable modules. The rmodtool basically takes an ELF
file as an input and writes an ELF as output. It basically does
a simple conversion from one ELF file to another slighty changed
ELF file. First the tool makes sure that the ELF file fits a few
requirements. For example there can only be one segment (loadable
program header) in the input ELF file. After that it goes through
the ELF relocation table and takes any entry that applies to the one
segment we want to load at runtime. The rmodtool will then write all
these relocation entires in a new ELF section called ".reloc". After
that the ELF relocation table will be cleared.
One can split the rmodules in two different kinds:
1. coreboot stages (postcar, ramstage)
2. simple binaries (smm, smmstub, sipi\_vector)
They are actually handled the same by the build system and only differ
in the fact, that they are either coreboot stages or they are not.
In the end the ELF files will have three different ELF sections,
which are all created by the rmodtool.
1. relocation header (.header)
2. program (.program)
3. relocation entries (.relocs)
## runtime
Either rmodule\_load (lib/rmodule.c) is used directly or through the
rmodule\_stage\_load (lib/rmodule.c) wrapper. It is used to load the
stages (postcar and ramstage) or small programs like (sipi\_vector,
smm, smmstub) into memory before jumping to them. In the case of a
coreboot stage, CBMEM is used to allocate space for the stage in memory
via the rmodule\_cbfs\_allocater (lib/rmodule.c). At this point the
location of the stage in memory is known and all relocation (address
fixups) need to be done now. This is basically just a simple loop that
goes through each relocation entry. Each relocation entry is just an
address pointing to a location that needs relocation. The relocation
itself is just a simple addition, that adds an offset from where the
image was "supposed" to be at link time, to where it is now relocated.
## module\_parameters
module\_parameters is a section inside the rmodule ELF file. Its
basically a way to pass runtime information to an rmodule
before jumping to it. The caller will use rmodule\_parameters()
(lib/rmodule.c) to get the runtime address of the module\_parameters
and the callee (the rmodule itself) usually appends the section to
specific types via compiler attributes. For example:
```
static const
volatile __attribute((aligned(4), __section__(".module_parameters")))
struct smm_runtime smm_runtime;
```
# x86 why rmodules
//TODO
x86: postcar and ramstage cannot conflict with payload regarding
memory placement. Therefore payload location is usually fixed and
postcar/ramstage can be placed at a location in memory that is
figured out at runtime.

View File

@@ -33,42 +33,19 @@
- Panther (ASUS Chromebox CN60) - Panther (ASUS Chromebox CN60)
- Tricky (Dell Chromebox 3010) - Tricky (Dell Chromebox 3010)
- Zako (HP Chromebox G1) - Zako (HP Chromebox G1)
- Brox
- Agah - Agah
- Anahera - Anahera
- Anahera4ES - Anahera4ES
- Aurash
- Banshee
- Brask - Brask
- Brya 0 - Brya 0
- Craask
- Craaskov
- Constitution
- Crota
- Felwinter - Felwinter
- Gaelin
- Gimble - Gimble
- Gimble4ES - Gimble4ES
- Gladios
- Gothrax
- Hades
- Kano - Kano
- Kinox
- Kuldax
- Joxer
- Lisbon
- Marasov
- Mithrax
- Moli
- Nivviks - Nivviks
- Nereid - Nereid
- Omnigul
- Osiris
- Pirrha
- Primus - Primus
- Primus4ES - Primus4ES
- Pujjo
- Quandiso
- Redrix - Redrix
- Redrix4ES - Redrix4ES
- Skolas - Skolas
@@ -76,16 +53,31 @@
- Taeko - Taeko
- Taeko4ES - Taeko4ES
- Taniks - Taniks
- Uldren
- Vell - Vell
- Volmar - Volmar
- Banshee
- Crota
- Moli
- Kinox
- Craask
- Osiris
- Mithrax
- Kuldax
- Joxer
- Pujjo
- Xivu - Xivu
- Gaelin
- Yaviks - Yaviks
- Yavilla - Lisbon
- Zydron - Zydron
- Nokris - Gladios
- Dochi - Marasov
- Anraggar - Omnigul
- Constitution
- Aurash
- Hades
- Uldren
- Yavilla
- Butterfly (HP Pavilion Chromebook 14) - Butterfly (HP Pavilion Chromebook 14)
- Cherry - Cherry
- Dojo - Dojo
@@ -93,11 +85,9 @@
- Kingler - Kingler
- Steelix - Steelix
- Voltorb - Voltorb
- Ponyta
- Krabby - Krabby
- Tentacruel - Tentacruel
- Magikarp - Magikarp
- Chinchou
- Starmie - Starmie
- Banon (Acer Chromebook 15 (CB3-532)) - Banon (Acer Chromebook 15 (CB3-532))
- Celes (Samsung Chromebook 3) - Celes (Samsung Chromebook 3)
@@ -118,7 +108,6 @@
- Foster - Foster
- Gale (Google WiFi) - Gale (Google WiFi)
- Geralt - Geralt
- Ciri
- Asuka (Dell Chromebook 13 3380) - Asuka (Dell Chromebook 13 3380)
- Caroline (Samsung Chromebook Pro) - Caroline (Samsung Chromebook Pro)
- Cave (Asus Chromebook Flip C302SA) - Cave (Asus Chromebook Flip C302SA)
@@ -132,9 +121,9 @@
- Scarlet - Scarlet
- Nefario - Nefario
- Rainier - Rainier
- Dewatt (Acer Chromebook Spin 514)
- Guybrush - Guybrush
- Nipperkin (HP Elite c645 G2 Chromebook) - Nipperkin
- Dewatt
- Akemi (IdeaPad Flex 5/5i Chromebook) - Akemi (IdeaPad Flex 5/5i Chromebook)
- Dratini (HP Pro c640 Chromebook) - Dratini (HP Pro c640 Chromebook)
- Hatch - Hatch
@@ -222,23 +211,13 @@
- Coral - Coral
- Rex 0 - Rex 0
- Screebo - Screebo
- Screebo4ES
- Karis
- Karis4ES
- Rex EC ISH
- Ovis
- Ovis4ES
- Deku
- Deku4ES
- Rex4ES
- Rex4ES EC ISH
- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise) - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
- Sarien (Dell Latitude 5400 Chromebook Enterprise) - Sarien (Dell Latitude 5400 Chromebook Enterprise)
- Crystaldrift
- Frostflow (ASUS Chromebook CM34 Flip)
- Markarth (Acer Chromebook Plus 514)
- Skyrim - Skyrim
- Winterhold (Dell Latitude 3445 Chromebook) - Winterhold
- Frostflow
- Crystaldrift
- Markarth
- Falco (HP Chromebook 14) - Falco (HP Chromebook 14)
- Leon (Toshiba Chromebook) - Leon (Toshiba Chromebook)
- Peppy (Acer C720/C720P Chromebook) - Peppy (Acer C720/C720P Chromebook)
@@ -266,35 +245,35 @@
- Veyron_Speedy (ASUS C201 Chromebook) - Veyron_Speedy (ASUS C201 Chromebook)
- Veyron_Mickey (Asus Chromebit CS10) - Veyron_Mickey (Asus Chromebit CS10)
- Veyron_Rialto - Veyron_Rialto
- Chronicler (FMV Chromebook 14F) - Chronicler
- Collis (Asus Chromebook Flip CX3) - Collis
- Copano (ASUS Chromebook Flip CX5400) - Copano (ASUS Chromebook Flip CX5400)
- Delbin (ASUS Chromebook Flip CX5) - Delbin (ASUS Chromebook Flip CX5)
- Drobit (ASUS Chromebook CX9400) - Drobit (ASUS Chromebook CX9400)
- Eldrid (HP Chromebook x360 14c) - Eldrid
- Elemi (HP Pro c640 G2 Chromebook) - Elemi (HP Pro c640 G2 Chromebook)
- Halvor - Halvor
- Lindar (Lenovo 5i-14/Slim 5 Chromebook) - Lindar
- Malefor - Malefor
- Terrador - Terrador
- Todor - Todor
- Trondo - Trondo
- Voema (Acer Chromebook Spin 514) - Voema
- Volet (Acer Chromebook 515) - Volet
- Volteer - Volteer
- Volteer2 - Volteer2
- Volteer2_Ti50 - Volteer2_Ti50
- Voxel (Acer Chromebook Spin 713 (CP713-3W)) - Voxel (Acer Chromebook Spin 713 (CP713-3W))
- Berknip (HP Pro c645 Chromebook Enterprise)
- Dalboz - Dalboz
- Dirinboz (HP Chromebook 14a-nd0097nr)
- Ezkinil (Acer Chromebook Spin 514)
- Gumboz (HP Chromebook x360 14a)
- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
- Shuboz
- Trembyle
- Vilboz (Lenovo 100e/300e Gen3 AMD) - Vilboz (Lenovo 100e/300e Gen3 AMD)
- Ezkinil (Acer Chromebook Spin 514)
- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
- Trembyle
- Berknip (HP Pro c645 Chromebook Enterprise)
- Woomax (ASUS Chromebook Flip CM5) - Woomax (ASUS Chromebook Flip CM5)
- Dirinboz (HP Chromebook 14a-nd0097nr)
- Shuboz
- Gumboz (HP Chromebook x360 14a)
## HP ## HP
- Z220 CMT Workstation - Z220 CMT Workstation
@@ -308,7 +287,6 @@
- Alderlake-M RVP with Chrome EC - Alderlake-M RVP with Chrome EC
- Alderlake-N RVP - Alderlake-N RVP
- Alderlake-N RVP with Chrome EC - Alderlake-N RVP with Chrome EC
- Raptorlake silicon with Alderlake-P RVP
- Raptorlake silicon with Alderlake-P RVP and Chrome EC - Raptorlake silicon with Alderlake-P RVP and Chrome EC
- Basking Ridge CRB - Basking Ridge CRB
- Coffeelake U SO-DIMM DDR4 RVP - Coffeelake U SO-DIMM DDR4 RVP
@@ -317,6 +295,7 @@
- Coffeelake S U-DIMM DDR4 RVP8 - Coffeelake S U-DIMM DDR4 RVP8
- Cometlake U DDR4 RVP - Cometlake U DDR4 RVP
- Elkhartlake LPDDR4x CRB - Elkhartlake LPDDR4x CRB
- Galileo
- Glkrvp - Glkrvp
- Jasperlake DDR4/LPDDR4 RVP - Jasperlake DDR4/LPDDR4 RVP
- Jasperlake DDR4/LPDDR4 RVP with Chrome EC - Jasperlake DDR4/LPDDR4 RVP with Chrome EC
@@ -326,8 +305,7 @@
- Kabylake DDR4 RVP11 - Kabylake DDR4 RVP11
- Kunimitsu - Kunimitsu
- Meteorlake-P RVP - Meteorlake-P RVP
- Meteorlake-P RVP with Chrome EC for Prod Silicon - Meteorlake-P RVP with Chrome EC
- Meteorlake-P RVP with Chrome EC for non-Prod Silicon
- Meteorlake-P RVP with Microchip EC - Meteorlake-P RVP with Microchip EC
- shadowmountain - shadowmountain
- Strago - Strago
@@ -369,8 +347,6 @@
## MSI ## MSI
- PRO Z690-A (WIFI) DDR4 - PRO Z690-A (WIFI) DDR4
- PRO Z690-A (WIFI) - PRO Z690-A (WIFI)
- PRO Z790-P (WIFI) DDR4
- PRO Z790-P (WIFI)
## OpenCellular ## OpenCellular
- Elgon (GBCv2) - Elgon (GBCv2)
@@ -396,17 +372,11 @@
## Star Labs ## Star Labs
- Star Labs Lite Mk III (N5000) - Star Labs Lite Mk III (N5000)
- Star Labs Lite Mk IV (N5030) - Star Labs Lite Mk IV (N5030)
- Star Labs LabTop Mk III (i7-8550u)
- Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
- Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
- Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
- Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
## Supermicro ## Supermicro
- X11SSH-TF - X11SSH-TF
- X11SSM-F - X11SSM-F
- X11SSH-F/LN4F - X11SSH-F/LN4F
- X11SSW-F
## UP ## UP
- Squared - Squared

View File

@@ -68,7 +68,7 @@ specific IBB measurements without hard-coding them.
#### Runtime Data #### Runtime Data
* CBFS data which changes by external input dynamically. Never stays the same. * CBFS data which changes by external input dynamically. Never stays the same.
* It is identified by TPM_MEASURED_BOOT_RUNTIME_DATA kconfig option and * It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default) measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
in order to avoid PCR pre-calculation issues. in order to avoid PCR pre-calculation issues.

View File

@@ -127,11 +127,11 @@ implementations currently use combo tables.
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Address Mode | 0x0F[7:6] | 2 | 00: x86 Physical address | | Address Mode | 0x0F[7:6] | 2 | 00: x86 Physical address |
| | | | 01: offset from start of | | | | | 01: offset from start of |
| | | | BIOS (flash offset) | | | | | BIOS (flash offset) |
| | | | 02: offset from start of | | | | | 02: offset from start of |
| | | | directory header | | | | | directory header |
| | | | 03: offset from start of | | | | | 03: offset from start of |
| | | | partition | | | | | partition |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
``` ```

View File

@@ -29,25 +29,6 @@ field. For boards with an Intel GbE device, a modification of `refcode` is neede
otherwise `refcode` will disable the Intel GbE device and the OS cannot find it otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
in the list of PCI devices. in the list of PCI devices.
For the refcode binary extracted from Purism Librem 13 v1 (SHA256:
8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4,
.program section starts at file offset 0x2040), we can see the
following code sequence:
1e06b: c6 43 0c 00 movb $0x0,0xc(%ebx)
1e06f: c6 83 7e 03 00 00 00 movb $0x0,0x37e(%ebx)
1e076: c6 83 70 03 00 00 01 movb $0x1,0x370(%ebx)
1e07d: 66 89 43 0a mov %ax,0xa(%ebx)
1e081: c6 83 da 01 00 00 01 movb $0x1,0x1da(%ebx)
1e088: c6 83 86 03 00 00 01 movb $0x1,0x386(%ebx)
The code at 0x1e06f sets the field that is to enable the GbE to the
hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5)
to 0x01 to make the refcode support Intel GbE:
cp refcode.elf refcode_gbe.elf
printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc
## Use Broadwell SoC code for Haswell ULT boards ## Use Broadwell SoC code for Haswell ULT boards
Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT

View File

@@ -12,4 +12,3 @@ This section contains documentation about coreboot on specific Intel SOCs.
- [Firmware Interface Table](fit.md) - [Firmware Interface Table](fit.md)
- [Apollolake](apollolake/index.md) - [Apollolake](apollolake/index.md)
- [CSE FW Update](cse_fw_update/cse_fw_update.md) - [CSE FW Update](cse_fw_update/cse_fw_update.md)
- [Xeon Scalable processor](xeon_sp/index.md)

View File

@@ -1,120 +0,0 @@
Xeon Scalable processor coreboot Community Preview Guide
================================================
## Background
Sapphire Rapids coreboot was already merged into coreboot mainline.
Granite Rapids coreboot upstreaming is coming.
For Granite Rapids coreboot, we are going to perform a phased
upstreaming strategy according to the maturity of the code. A community
preview branch is opensource at:
https://review.coreboot.org/plugins/gitiles/intel-dev-pub/.
The community preview branch initially contains codes on legacy feature
enabling and matured patch set for platform support. More platform
support code will come with the platform development. The subsequent
upstreaming work will be based on this branch. It provides 2 board
targets,
1. Avenue City CRB (Granite Rapids-AP)
2. Beechnut City CRB (Granite Rapids-SP)
The above targets can pass build with Granite Rapids n-1 FSP headers,
which is a set of stub FSP headers used for compilation sanity check.
## Build steps
### Prepare workspace
```
# Create workspace
mkdir workspace && cd workspace
# Prepare coreboot codebase
git clone https://review.coreboot.org/intel-dev-pub ln -s intel-dev-pub/
coreboot
# Prepare stub binaries and update their path in
# configs/builder/config.intel.crb.avc.n-1
# Granite Rapids coreboot uses FSP 2.4, where FSP-I is newly introduced
# as an optional module to provide FSP based SMM capability. For FSP 2.4
# and FSP-I, please further refer to:
# https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf
CONFIG_IFD_BIN_PATH=<path of intel flash descriptor blob>
CONFIG_CPU_UCODE_BINARIES=<path of ucode>
CONFIG_FSP_T_FILE=<path of FSP-T binary>
CONFIG_FSP_M_FILE=<path of FSP-M binary>
CONFIG_FSP_S_FILE=<path of FSP-S binary>
CONFIG_FSP_I_FILE=<path of FSP-I binary>
CONFIG_PAYLOAD_FILE=<path of payload binary>
```
### Download necessary submodules
```
git submodule update --init --checkout 3rdparty/vboot
```
### Or take below alternative if the network connection is not good
```
git clone https://github.com/coreboot/vboot.git 3rdparty/vboot/
```
### Build toolchain
```
make crossgcc-i386 CPUS=$(nproc)
```
### Build BIOS (Avenue City CRB)
```
make distclean
make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc.n-1
make olddefconfig
make clean
make UPDATED_SUBMODULES=1 -j`nproc`
```
### Build BIOS (Beechnut City CRB)
```
make distclean
make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc.n-1
make olddefconfig
make clean
make UPDATED_SUBMODULES=1 -j`nproc`
```
### Obtain the preview patch list
```
# The tag upstream points to the upstream commit that the preview
# branch is based on.
git format-patch upstream..HEAD
```
## About Granite Rapids n-1 FSP Headers
This is a set of stub FSP headers for Granite Rapids server, which will
be forward compatible with the formal Granite Rapids FSP headers which
will be opensource at a later stage. For the n-1 FSP headers, there are
no corresponding n-1 FSP binaries. To pass build, users need to use stub
binaries which could be generated in arbitrary ways. Granite Rapids n-1
FSP headers are at: `src/vendorcode/intel/fsp/fsp2_0/graniterapids_n-1`.
For the formal Granite Rapids FSP headers and binaries, they will be
published at in
https://github.com/coreboot/coreboot/tree/main/src/vendorcode/intel/fsp/fsp2_0
(headers only) and https://github.com/intel/FSP (headers and binaries)
at a later stage.

View File

@@ -1,8 +0,0 @@
# Xeon Scalable processor documentation
This section contains documentation about coreboot on Xeon Scalable
processors.
## Topics
- [Community preview guide](community_preview_guide.md)

View File

@@ -166,7 +166,7 @@ commit --amend` allows you to take back your commit and amend it.
When you are done with your commit, run `git push` to push your commit When you are done with your commit, run `git push` to push your commit
to coreboot.org. **Note:** To submit as a private patch, use `git push to coreboot.org. **Note:** To submit as a private patch, use `git push
origin HEAD:refs/for/main%private`. Submitting as a private patch origin HEAD:refs/for/master%private`. Submitting as a private patch
means that your commit will be on review.coreboot.org, but is only means that your commit will be on review.coreboot.org, but is only
visible to yourself and those you add as reviewers. This mode isn't visible to yourself and those you add as reviewers. This mode isn't
perfect: Somebody who knows the commit ID can still fetch the change and perfect: Somebody who knows the commit ID can still fetch the change and

View File

@@ -1,20 +1,20 @@
# Writing unit tests for coreboot # Writing unit tests for coreboot
## Introduction ## Introduction
General thoughts about unit testing coreboot can be found in General thoughts about unit testing coreboot can be found in [Unit
[Unit-testing coreboot](../technotes/2020-03-unit-testing-coreboot.md). testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
Additionally, [code coverage](../technotes/2021-05-code-coverage.md) Additionally, [code coverage](../technotes/2021-05-code-coverage.md)
support is available for unit tests. support is available for unit tests.
This document aims to guide developers through the process of adding and This document aims to guide developers through the process of adding and
writing unit tests for coreboot modules. writing unit tests for coreboot modules.
As an example of unit-under-test, `src/device/i2c.c` (referred hereafter As an example of unit under test, `src/device/i2c.c` (referred hereafter
as UUT "Unit Under Test") will be used. This is simple module, thus it as UUT "Unit Under Test") will be used. This is simple module, thus it
should be easy for the reader to focus solely on the testing logic, should be easy for the reader to focus solely on the testing logic,
without the need to spend too much time on digging deeply into the without the need to spend too much time on digging deeply into the
source code details and flow of operations. That being said, a good source code details and flow of operations. That being said, a good
understanding of what the unit-under-test is doing is crucial for understanding of what the unit under test is doing is crucial for
writing unit tests. writing unit tests.
This tutorial should also be helpful for developers who want to follow This tutorial should also be helpful for developers who want to follow
@@ -23,7 +23,7 @@ though TDD has a different work flow of building tests first, followed
by the code that satisfies them, the process of writing tests and adding by the code that satisfies them, the process of writing tests and adding
them to the tree is the same. them to the tree is the same.
## Analysis of unit-under-test ## Analysis of unit under test
First of all, it is necessary to precisely establish what we want to First of all, it is necessary to precisely establish what we want to
test in a particular module. Usually this will be an externally exposed test in a particular module. Usually this will be an externally exposed
API, which can be used by other modules. API, which can be used by other modules.
@@ -69,7 +69,7 @@ UUT and not on the other modules. While some software dependencies may
be hard to be mock (for example due to complicated dependencies) and be hard to be mock (for example due to complicated dependencies) and
thus should be simply linked into the test binaries, all hardware thus should be simply linked into the test binaries, all hardware
dependencies need to be mocked out, since in the user-space host dependencies need to be mocked out, since in the user-space host
environment, target hardware is not available. environment, targets hardware is not available.
```eval_rst ```eval_rst
.. admonition:: i2c-test example .. admonition:: i2c-test example
@@ -142,12 +142,12 @@ for coreboot `make unit-tests`.
make unit-tests make unit-tests
``` ```
When trying to build test binary, one can often see the linker complaining When trying to build test binary, one can often see linker complains
about `undefined reference` for a couple of symbols. This is one of the about `undefined reference` to couple of symbols. This is one of
solutions to determine all external dependencies of UUT - iteratively solutions to determine all external dependencies of UUT - iteratively
build test and resolve errors one by one. At this step, developer should build test and resolve errors one by one. At this step, developer should
decide either it's better to add an extra module to provide necessary decide either it's better to add an extra module to provide necessary
definitions or rather mock such dependency. A quick guide about adding definitions or rather mock such dependency. Quick guide through adding
mocks is provided later in this doc. mocks is provided later in this doc.
## Writing new tests ## Writing new tests
@@ -324,8 +324,8 @@ a described range.
.. admonition:: i2c-test example .. admonition:: i2c-test example
In our example, we may want to check that `platform_i2c_transfer` is In our example, we may want to check that `platform_i2c_transfer` is
fed with a number of segments bigger than 0, each segment has flags fed with number of segments bigger than 0, each segment has flags
which are in the supported range and each segment has a buf which is which are in supported range and each segment has buf which is
non-NULL. We are expecting such values for _every_ call, thus the non-NULL. We are expecting such values for _every_ call, thus the
last parameter in `expect*` macros is -1. last parameter in `expect*` macros is -1.
@@ -375,16 +375,16 @@ API documentation.
### Test runner ### Test runner
Finally, the developer needs to implement the test `main()` function. Finally, the developer needs to implement the test `main()` function.
All tests should be registered there and the cmocka test runner invoked. All tests should be registered there and cmocka test runner invoked. All
All methods for invoking Cmocka test are described methods for invoking Cmocka test are described
[here](https://api.cmocka.org/group__cmocka__exec.html). [here](https://api.cmocka.org/group__cmocka__exec.html).
```eval_rst ```eval_rst
.. admonition:: i2c-test example .. admonition:: i2c-test example
We don't need any extra setup and teardown functions for i2c-test, so We don't need any extra setup and teardown functions for i2c-test, so
let's simply register the test for `i2c_read_field` and return from let's simply register test for `i2c_read_field` and return from main
main the output of Cmocka's runner (it returns number of tests value which is output of Cmocka's runner (it returns number of tests
that failed). that failed).
.. code-block:: c .. code-block:: c

View File

@@ -49,8 +49,8 @@ file `Python`
* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
* __chromeos__ - These scripts can be used to access ChromeOS * __chromeos__ - These scripts can be used to access ChromeOS
resources, for example to extract System Agent reference code and other resources, for example to extract System Agent reference code and other
blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS recovery blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
image. `C` recovery image. `C`
* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
libc support) `Bash` libc support) `Bash`
* __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_, * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
@@ -88,7 +88,7 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
embedded controller and insert them to the firmware image. `C` embedded controller and insert them to the firmware image. `C`
* __kconfig__ - Build system `Make` * __kconfig__ - Build system `Make`
* __lint__ - Source linter and linting rules `Shell` * __lint__ - Source linter and linting rules `Shell`
* __nixos__ - A script and NixOS configuration files to create an ISO * __liveiso__ - A script and NixOS configuration files to create an ISO
image for testing purposes and for working on firmware. `Bash` image for testing purposes and for working on firmware. `Bash`
* __mainboard__ - mainboard specific scripts * __mainboard__ - mainboard specific scripts
* _google_ - Directory for google mainboard specific scripts * _google_ - Directory for google mainboard specific scripts
@@ -138,10 +138,6 @@ for the files modified in a patch or for a file `Perl`
license headers `Shell` license headers `Shell`
* _parse-maintainers.pl_ - Script to alphabetize MAINTAINERS * _parse-maintainers.pl_ - Script to alphabetize MAINTAINERS
file `Perl` file `Perl`
* _rm_unused_code_ - Remove all code not used for a platform
from the local git repository for auditing or release `Bash`
* _show_platforms.sh_ - Makes a list of platforms in the tree.
Does not show variants. `Shell`
* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash` * _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
* _update_submodules_ - Check all submodules for updates `Bash` * _update_submodules_ - Check all submodules for updates `Bash`
* __showdevicetree__ - Compile and dump the device tree `C` * __showdevicetree__ - Compile and dump the device tree `C`
@@ -166,9 +162,9 @@ the documentation `Bash`
* __x86__ - Generates 32-bit PAE page tables based on a CSV input file. * __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
`Go` `Go`
* __xcompile__ - Cross compile setup `Bash` * __xcompile__ - Cross compile setup `Bash`
## In depth documentation ## In depth documentation
* [abuild](util/abuild/index.md)
* [cbfstool](util/cbfstool/index.md) * [cbfstool](util/cbfstool/index.md)
* [ifdtool](util/ifdtool/index.md) * [ifdtool](util/ifdtool/index.md)
* [intelp2m](util/intelp2m/index.md) * [intelp2m](util/intelp2m/index.md)

View File

@@ -1,260 +0,0 @@
abuild
======
This utility is a great tool to check whether your coreboot tree
compiles for one or all targets. It compiles the 'default' build for a
mainboard. This is roughly equivalent to removing the .config file,
running `make menuconfig`, selecting the manufacturer and mainboard,
then saving the config without making any other changes.
It is run on all patches submitted via gerrit as part of the process.
Before submitting a patch, it is a very good idea to run abuild first
to make sure your patch compiles cleanly for all.
Note that abuild is a tool to do a simple build test, and binaries it
produces may well not boot if flashed to a system.
### Basic usage
abuild needs to be run from the coreboot directory. If you cd into the
coreboot/util/abuild directory and try to run it from there, it will
not run correctly.
If you invoke abuild with no parameters, it will build all boards
automatically.
You can also specify a single board to build with the -t option. For
example, to build the Lenovo X230 target, run:
```bash
$ util/abuild/abuild -t lenovo/x230
```
### Where builds and logs are stored
The resulting images and logs are stored in directory coreboot-builds/
under your current directory. This can be overridden with --outdir:
```bash
$ util/abuild/abuild --outdir /mnt/portable/coreboot-builds
```
This is useful if you want to divert the build to an external hard
drive, e.g. to keep the solid-state drive holding the coreboot tree
young.
(We will still refer to this directory as "coreboot-builds" below.)
After running the X230 build above, the build log will be in
coreboot-builds/LENOVO_X230/make.log.
For an overview of what passed and what failed, look at
coreboot-builds/passing_boards and coreboot-builds/failing_boards.
**These logs are overwritten with each abuild run.** Save them elsewhere
if you feel a need to reference the results later.
### Payloads
You can also specify a payload directory with -p:
```bash
mkdir payloads
cp /somewhere/filo.elf payloads
```
Then add a file payloads/payload.sh which prints the name of the
payload to use (and takes the mainboard as a parameter) such as:
```bash
echo "`dirname $0`/build/filo.elf"
```
Then you can build an image with payload by specifying:
```bash
util/abuild/abuild -t lenovo/x230 -p ./payloads
```
You can also tell abuild not to use a payload:
```bash
util/abuild/abuild -t lenovo/x230 -p none
```
### Build non-default configurations
Sometimes you do need to build test a custom, non-default configuration.
This can be accomplished by placing a config file in configs/.
First, clean your slate with `make distclean` or `rm .config`.
Then run `make menuconfig`, select the manufacturer and mainboard, and
configure the options you need to test building for.
Then save a minimal config file omitting options that did not change
from default:
```bash
make savedefconfig
```
This file is saved as `defconfig` and can be edited further.
Now this file can be saved in configs/ which will form the basis of a
custom configuration included in an abuild. However, it needs to be
named in a specific way for abuild to pick it up:
```
config.<board>_<suffix>
```
<board> is effectively the BOARD\_xxx Kconfig option without "BOARD\_".
<suffix> is a free form description of the configuration being built.
For example, a config for ASUS P8Z77-M PRO that tests building with MRC
raminit code (as opposed to the default native raminit) would be named
`config.asus_p8z77_m_pro_mrc_bin` and contains:
```
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_P8Z77_M_PRO=y
# CONFIG_USE_NATIVE_RAMINIT is not set
CONFIG_CPU_MICROCODE_CBFS_NONE=y
# CONFIG_BOOTBLOCK_CONSOLE is not set
# CONFIG_POSTCAR_CONSOLE is not set
```
For what we are trying to do, not setting USE_NATIVE_RAMINIT is the
important part. The other three optional changes are meant to speed
things up. All these options can be selected during `make menuconfig`.
Path to MRC binary blob remains default and thus not included here.
Custom configurations can also be put in a file and applied to an entire
abuild run using -K. Assume for example you are not interested in
the postcar stage at all and just want it to shut up, you can create
a file named `myconfig` with this line:
```
# CONFIG_POSTCAR_CONSOLE is not set
```
and run `abuild -K myconfig` to build everything with a silent postcar
stage.
### Selectively build certain targets only (also config file naming caveats)
The P8Z77-M PRO example above would fail for P8Z77-M, because the
config file name is ambiguous. `abuild` would pick up this config when
building for P8Z77-M, but fails when it sees that this config isn't
meant for P8Z77-M (but for P8Z77-M PRO). To avoid this error, you have
to skip this config using --skip_set:
```bash
util/abuild/abuild --skip_set BOARD_ASUS_P8Z77_M_PRO
```
To complete the test, run abuild again specifically for this board
variant (see next section).
You can skip building other targets based on other Kconfigs. To skip
building targets without a Kconfig set, use --skip_unset:
```bash
util/abuild/abuild --skip_unset USE_NATIVE_RAMINIT
```
This example skips building configs not using (Sandy/Ivy Bridge) native
RAM init.
### Additional Examples
Many boards have multiple variants. You can build for a specific
variant of a board:
```bash
util/abuild/abuild -t asus/p8x7x-series -b p8z77-m_pro -p none
```
Many of the boards need files from the 'blobs' repository, which will
be initialized by the -B option. If the blobs repo has already been
initialized in your local tree, it won't hurt to add the -B.
```bash
util/abuild/abuild -B -t lenovo/x230 -p none
```
Adding ccache to your system and telling abuild to use it with the -y
option will speed things up a bit:
```bash
util/abuild/abuild -B -y -t lenovo/x230 -p none
```
Telling abuild to use multiple cores with the -c option helps speed
things up as well:
```bash
util/abuild/abuild -B -y -c 8 -t lenovo/x230 -p none
```
Of course, the real power of abuild is in testing multiple boards.
```bash
util/abuild/abuild -B -y -c 8 -p none
```
### Full options list
```text
coreboot autobuild v0.11.01 (Feb 3, 2023)
[...]
Usage: util/abuild/abuild [options]
util/abuild/abuild [-V|--version]
util/abuild/abuild [-h|--help]
Options:
[-a|--all] Build previously succeeded ports as well
[-A|--any-toolchain] Use any toolchain
[-b|--board-variant <name>] Build specific board variant under the
given target.
[-B|--blobs] Allow using binary files
[--checksum <path/basefile>] Store checksums at path/basefile
[-c|--cpus <numcpus>] Build on <numcpus> at the same time
[-C|--config] Configure-only mode
[-d|--dir <dir>] Directory containing config files
[-e|--exitcode] Exit with a non-zero errorlevel on failure
[-J|--junit] Write JUnit formatted xml log file
[-K|--kconfig <name>] Prepend file to generated Kconfig
[-l|--loglevel <num>] Set loglevel
[-L|--clang] Use clang on supported arch
[-n|--name] Set build name - also sets xmlfile if not
already set
[-o|--outdir <path>] Store build results in path
(defaults to coreboot-builds)
[-p|--payloads <dir>] Use payloads in <dir> to build images
[-P|--prefix <name>] File name prefix in CBFS
[-q|--quiet] Print fewer messages
[-r|--remove] Remove output dir after build
[-R|--root <path>] Absolute path to coreboot sources
(defaults to /usr/src/coreboot)
[--scan-build] Use clang's static analyzer
[--skip_set <value>] Skip building boards with this Kconfig set
[--skip_unset <value>] Skip building boards with this Kconfig not set
[--timeless] Generate timeless builds
[-t|--target <vendor/board>] Attempt to build target vendor/board only
[-T|--test] Submit image(s) to automated test system
[-u|--update] Update existing image
[-v|--verbose] Print more messages
[-x|--chromeos] Build with CHROMEOS enabled
Skip boards without ChromeOS support
[-X|--xmlfile <name>] Set JUnit XML log file filename
(defaults to /usr/src/coreboot/abuild.xml)
[-y|--ccache] Use ccache
[-z|--clean] Remove build results when finished
[-Z|--clean-somewhat] Remove build but keep coreboot.rom + config
[-V|--version] Print version number and exit
[-h|--help] Print this help and exit
[-s|--silent] obsolete
```

View File

@@ -136,7 +136,7 @@ F: src/mainboard/adlink/
AMD non-server family 17h and 19h reference boards AMD family 17h and 19h reference boards
M: Felix Held <felix-coreboot@felixheld.de> M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com> M: Jason Glenesk <jason.glenesk@gmail.com>
M: Fred Reitberger <reitbergerfred@gmail.com> M: Fred Reitberger <reitbergerfred@gmail.com>
@@ -149,13 +149,6 @@ F: src/mainboard/amd/majolica/
F: src/mainboard/amd/mandolin/ F: src/mainboard/amd/mandolin/
F: src/mainboard/amd/mayan/ F: src/mainboard/amd/mayan/
AMD server family 19h reference boards
M: Felix Held <felix-coreboot@felixheld.de>
M: Martin Roth <gaumless@gmail.com>
M: Varshit Pandya <pandyavarshit@gmail.com>
S: Maintained
F: src/mainboard/amd/onyx/
AMD reference boards outside of family 17h and 19h AMD reference boards outside of family 17h and 19h
S: Odd Fixes S: Odd Fixes
L: amd_coreboot_org_changes@googlegroups.com L: amd_coreboot_org_changes@googlegroups.com
@@ -347,24 +340,18 @@ F: src/mainboard/gizmosphere/
GOOGLE REX MAINBOARDS GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com> M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <tstuli@gmail.com> M: Tarun Tuli <taruntuli@google.com>
M: Kapil Porwal <kapilporwal@google.com> M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <czapiga@google.com>
M: Eran Mitrani <mitrani@google.com>
M: Dinesh Gehlot <digehlot@google.com>
S: Maintained S: Maintained
F: src/mainboard/google/rex/ F: src/mainboard/google/rex/
GOOGLE BRYA MAINBOARDS GOOGLE BRYA MAINBOARDS
M: Subrata Banik <subratabanik@google.com> M: Tarun Tuli <taruntuli@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
M: Eric Lai <ericllai@google.com>
S: Maintained S: Maintained
F: src/mainboard/google/brya/ F: src/mainboard/google/brya/
GOOGLE HATCH MAINBOARDS GOOGLE HATCH MAINBOARDS
M: Subrata Banik <subratabanik@google.com> M: Tarun Tuli <taruntuli@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained S: Maintained
F: src/mainboard/google/hatch/ F: src/mainboard/google/hatch/
@@ -430,10 +417,7 @@ M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
S: Maintained S: Maintained
F: src/mainboard/intel/harcuvar/ F: src/mainboard/intel/harcuvar/
INVENTEC MAINBOARDS
M: Annie Chen <Chen.AnnieET@inventec.com>
S: Maintained
F: src/mainboard/inventec/
JETWAY MAINBOARDS JETWAY MAINBOARDS
S: Orphan S: Orphan
@@ -703,7 +687,6 @@ F: src/mainboard/sifive/
F: util/riscv/ F: util/riscv/
X86 ARCHITECTURE X86 ARCHITECTURE
M: Jérémy Compostella <jeremy.compostella@intel.com>
S: MAINTAINED S: MAINTAINED
F: src/arch/x86/ F: src/arch/x86/
F: src/cpu/x86/ F: src/cpu/x86/
@@ -794,7 +777,6 @@ F: src/southbridge/amd/
F: src/include/cpu/amd/ F: src/include/cpu/amd/
INTEL SUPPORT INTEL SUPPORT
R: Intel_Coreboot_Reviewers <intel_coreboot_reviewers@intel.com>
S: Maintained S: Maintained
F: src/vendorcode/intel/ F: src/vendorcode/intel/
F: src/cpu/intel/ F: src/cpu/intel/
@@ -811,7 +793,6 @@ F: src/drivers/intel/fsp1_1/
INTEL FSP 2.0 INTEL FSP 2.0
M: Andrey Petrov <andrey.petrov@gmail.com> M: Andrey Petrov <andrey.petrov@gmail.com>
M: Ronak Kanabar <ronak.kanabar@intel.com>
S: Maintained S: Maintained
F: src/drivers/intel/fsp2_0/ F: src/drivers/intel/fsp2_0/
@@ -822,6 +803,7 @@ F: src/drivers/intel/fsp2_0/
AMD Cezanne AMD Cezanne
M: Felix Held <felix-coreboot@felixheld.de> M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com> M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com> M: Fred Reitberger <reitbergerfred@gmail.com>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
L: amd_coreboot_org_changes@googlegroups.com L: amd_coreboot_org_changes@googlegroups.com
@@ -832,29 +814,13 @@ F: src/vendorcode/amd/fsp/cezanne/
AMD common SoC code AMD common SoC code
M: Felix Held <felix-coreboot@felixheld.de> M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com> M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com> M: Fred Reitberger <reitbergerfred@gmail.com>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
L: amd_coreboot_org_changes@googlegroups.com L: amd_coreboot_org_changes@googlegroups.com
S: Maintained S: Maintained
F: src/soc/amd/common/ F: src/soc/amd/common/
AMD Genoa
M: Felix Held <felix-coreboot@felixheld.de>
M: Martin Roth <gaumless@gmail.com>
M: Varshit Pandya <pandyavarshit@gmail.com>
S: Maintained
F: src/soc/amd/genoa/
AMD Mendocino
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Fred Reitberger <reitbergerfred@gmail.com>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
L: amd_coreboot_org_changes@googlegroups.com
S: Supported
F: src/soc/amd/mendocino/
F: src/vendorcode/amd/fsp/mendocino/
AMD Picasso AMD Picasso
M: Felix Held <felix-coreboot@felixheld.de> M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com> M: Jason Glenesk <jason.glenesk@gmail.com>
@@ -865,6 +831,17 @@ S: Maintained
F: src/soc/amd/picasso/ F: src/soc/amd/picasso/
F: src/vendorcode/amd/fsp/picasso/ F: src/vendorcode/amd/fsp/picasso/
AMD Mendocino
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
L: amd_coreboot_org_changes@googlegroups.com
S: Supported
F: src/soc/amd/mendocino/
F: src/vendorcode/amd/fsp/mendocino/
AMD Phoenix AMD Phoenix
M: Felix Held <felix-coreboot@felixheld.de> M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com> M: Jason Glenesk <jason.glenesk@gmail.com>
@@ -884,17 +861,14 @@ F: src/soc/amd/stoneyridge/
INTEL METEORLAKE SOC INTEL METEORLAKE SOC
M: Subrata Banik <subratabanik@google.com> M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <tstuli@gmail.com> M: Tarun Tuli <taruntuli@google.com>
M: Kapil Porwal <kapilporwal@google.com> M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <czapiga@google.com>
M: Eran Mitrani <mitrani@google.com>
M: Dinesh Gehlot <digehlot@google.com>
S: Maintained S: Maintained
F: src/soc/intel/meteorlake/ F: src/soc/intel/meteorlake/
INTEL ALDERLAKE SOC INTEL ALDERLAKE SOC
M: Subrata Banik <subratabanik@google.com> M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org> M: Tarun Tuli <taruntuli@google.com>
S: Maintained S: Maintained
F: src/soc/intel/alderlake/ F: src/soc/intel/alderlake/
@@ -911,10 +885,6 @@ S: Maintained
F: /src/soc/intel/braswell/ F: /src/soc/intel/braswell/
F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ F: /src/vendorcode/intel/fsp/fsp1_1/braswell/
INTEL CANNONLAKE SOC
S: Orphan
F: src/soc/intel/cannonlake/
INTEL DENVERTON-NS SOC INTEL DENVERTON-NS SOC
M: Jeff Daly <jeffd@silicom-usa.com> M: Jeff Daly <jeffd@silicom-usa.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com> M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
@@ -929,7 +899,7 @@ F: src/soc/intel/elkhartlake/
INTEL TIGERLAKE SOC INTEL TIGERLAKE SOC
M: Subrata Banik <subratabanik@google.com> M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org> M: Tarun Tuli <taruntuli@google.com>
S: Maintained S: Maintained
F: src/soc/intel/tigerlake/ F: src/soc/intel/tigerlake/
@@ -985,12 +955,6 @@ M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Martin Roth <gaumless@gmail.com> M: Martin Roth <gaumless@gmail.com>
F: payloads/external/ F: payloads/external/
COREDOOM PAYLOAD INTEGRATION
M: Nicholas Chin <nic.c3.14@gmail.com>
W: https://github.com/nic3-14159/coreDOOM
S: Maintained
F: payloads/external/coreDOOM/
LINUXBOOT PAYLOAD INTEGRATION LINUXBOOT PAYLOAD INTEGRATION
M: Christian Walter <christian.walter@9elements.com> M: Christian Walter <christian.walter@9elements.com>
M: Marcello Sylvester Bauer <info@marcellobauer.com> M: Marcello Sylvester Bauer <info@marcellobauer.com>
@@ -1031,6 +995,7 @@ F: util/genbuild_h/
TOOLCHAIN TOOLCHAIN
M: Martin Roth <gaumless@gmail.com> M: Martin Roth <gaumless@gmail.com>
M: Felix Singer <felixsinger@posteo.net> M: Felix Singer <felixsinger@posteo.net>
M: Elyes Haouas <ehaouas@noos.fr>
S: Supported S: Supported
F: util/crossgcc/ F: util/crossgcc/
@@ -1055,7 +1020,6 @@ F: util/ifdtool/
INTELTOOL INTELTOOL
M: Stefan Reinauer <stefan.reinauer@coreboot.org> M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
F: util/inteltool/ F: util/inteltool/
INTELMETOOL INTELMETOOL
@@ -1089,7 +1053,6 @@ F: src/drivers/aspeed/common/
F: src/drivers/aspeed/ast2050/ F: src/drivers/aspeed/ast2050/
ACPI ACPI
R: Cliff Huang <cliff.huang@intel.com>
M: Lance Zhao <lance.zhao@gmail.com> M: Lance Zhao <lance.zhao@gmail.com>
M: Tim Wawrzynczak <inforichland@gmail.com> M: Tim Wawrzynczak <inforichland@gmail.com>
S: Supported S: Supported
@@ -1151,7 +1114,8 @@ F: src/drivers/*/tpm/
F: src/security/tpm/ F: src/security/tpm/
SUPERIOS & SUPERIOTOOL SUPERIOS & SUPERIOTOOL
S: Orphan M: Felix Held <felix-coreboot@felixheld.de>
S: Odd Fixes
F: src/superio/ F: src/superio/
F: util/superiotool/ F: util/superiotool/
@@ -1180,7 +1144,7 @@ S: Maintained
F: src/drivers/i2c/tas5825m/ F: src/drivers/i2c/tas5825m/
TESTS TESTS
M: Jakub Czapiga <czapiga@google.com> M: Jakub Czapiga <jacz@semihalf.com>
S: Maintained S: Maintained
F: tests/ F: tests/
F: payloads/libpayload/tests/ F: payloads/libpayload/tests/

View File

@@ -23,27 +23,20 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
DOTCONFIG ?= $(top)/.config DOTCONFIG ?= $(top)/.config
KCONFIG_CONFIG = $(DOTCONFIG) KCONFIG_CONFIG = $(DOTCONFIG)
KCONFIG_AUTOADS := $(obj)/cb-config.ads KCONFIG_AUTOADS := $(obj)/cb-config.ads
KCONFIG_RUSTCCFG := $(obj)/cb-config.rustcfg
KCONFIG_AUTOHEADER := $(obj)/config.h KCONFIG_AUTOHEADER := $(obj)/config.h
KCONFIG_AUTOCONFIG := $(obj)/auto.conf KCONFIG_AUTOCONFIG := $(obj)/auto.conf
KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
KCONFIG_SPLITCONFIG := $(obj)/config/ KCONFIG_SPLITCONFIG := $(obj)/config/
KCONFIG_TRISTATE := $(obj)/tristate.conf KCONFIG_TRISTATE := $(obj)/tristate.conf
KCONFIG_NEGATIVES := 1 KCONFIG_NEGATIVES := 1
KCONFIG_WERROR := 1 KCONFIG_STRICT := 1
KCONFIG_WARN_UNKNOWN_SYMBOLS := 1
KCONFIG_PACKAGE := CB.Config KCONFIG_PACKAGE := CB.Config
KCONFIG_MAKEFILE_REAL ?= $(objk)/Makefile.real KCONFIG_MAKEFILE_REAL ?= $(objk)/Makefile.real
COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
COREBOOT_EXPORTS += KCONFIG_NEGATIVES COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
ifeq ($(filter %config,$(MAKECMDGOALS)),)
COREBOOT_EXPORTS += KCONFIG_WERROR
endif
COREBOOT_EXPORTS += KCONFIG_WARN_UNKNOWN_SYMBOLS
COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
COREBOOT_EXPORTS += KCONFIG_RUSTCCFG
# Make does not offer a recursive wildcard function, so here's one: # Make does not offer a recursive wildcard function, so here's one:
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2)) rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
@@ -92,7 +85,7 @@ help_coreboot help::
@echo ' clean - Remove coreboot build artifacts' @echo ' clean - Remove coreboot build artifacts'
@echo ' distclean - Remove build artifacts and config files' @echo ' distclean - Remove build artifacts and config files'
@echo ' sphinx - Build sphinx documentation for coreboot' @echo ' sphinx - Build sphinx documentation for coreboot'
@echo ' sphinx-lint - Build sphinx documentation for coreboot with warnings as errors' @echo ' sphinx-lint - Build sphinx documenttion for coreboot with warnings as errors'
@echo ' filelist - Show files used in current build' @echo ' filelist - Show files used in current build'
@echo ' printall - print makefile info for debugging' @echo ' printall - print makefile info for debugging'
@echo ' gitconfig - set up git to submit patches to coreboot' @echo ' gitconfig - set up git to submit patches to coreboot'
@@ -197,6 +190,10 @@ endif
# are reproducible # are reproducible
export LANG LC_ALL TZ SOURCE_DATE_EPOCH export LANG LC_ALL TZ SOURCE_DATE_EPOCH
ifneq ($(CONFIG_MMX),y)
CFLAGS_x86_32 += -mno-mmx
endif
ifneq ($(UNIT_TEST),1) ifneq ($(UNIT_TEST),1)
include toolchain.inc include toolchain.inc
endif endif
@@ -204,10 +201,6 @@ endif
strip_quotes = $(strip $(subst ",,$(subst \",,$(1)))) strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
# fix makefile syntax highlighting after strip macro \" ")) # fix makefile syntax highlighting after strip macro \" "))
ifneq ($(NOCOMPILE),1)
$(shell rm -f $(CCACHE_STATSLOG))
endif
# The primary target needs to be here before we include the # The primary target needs to be here before we include the
# other files # other files
@@ -280,18 +273,17 @@ src-to-ali=\
# Add paths to files in X-y to X-srcs # Add paths to files in X-y to X-srcs
# Add subdirs-y to subdirs # Add subdirs-y to subdirs
includemakefiles= \ includemakefiles= \
$(if $(wildcard $(1)), \ $(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \ $(eval -include $(1)) \
$(eval -include $(1)) \ $(foreach class,$(classes-y), $(call add-class,$(class))) \
$(foreach class,$(classes-y), $(call add-class,$(class))) \ $(foreach special,$(special-classes), \
$(foreach special,$(special-classes), \ $(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \ $(foreach class,$(classes), \
$(foreach class,$(classes), \ $(eval $(class)-srcs+= \
$(eval $(class)-srcs+= \ $$(subst $(absobj)/,$(obj)/, \
$$(subst $(absobj)/,$(obj)/, \ $$(subst $(top)/,, \
$$(subst $(top)/,, \ $$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \ $(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))))
# For each path in $(subdirs) call includemakefiles # For each path in $(subdirs) call includemakefiles
# Repeat until subdirs is empty # Repeat until subdirs is empty
@@ -323,11 +315,6 @@ $(eval $(postinclude-hooks))
# Eliminate duplicate mentions of source files in a class # Eliminate duplicate mentions of source files in a class
$(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
ifeq ($(CONFIG_IWYU),y)
MAKEFLAGS += -k
SAVE_IWYU_OUTPUT := 2>&1 | grep "should\|\#include\|---\|include-list\|^[[:blank:]]\?\'" | tee -a $$(obj)/iwyu.txt
endif
# Build Kconfig .ads if necessary # Build Kconfig .ads if necessary
ifeq ($(CONFIG_ROMSTAGE_ADA),y) ifeq ($(CONFIG_ROMSTAGE_ADA),y)
romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS)) romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
@@ -394,7 +381,7 @@ $$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4)
@printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n"
$(CC_$(1)) \ $(CC_$(1)) \
-MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \ -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \
$(3) -c -o $$$$@ $$$$< $(SAVE_IWYU_OUTPUT) $(3) -c -o $$$$@ $$$$<
end$(EMPTY)if end$(EMPTY)if
en$(EMPTY)def en$(EMPTY)def
end$(EMPTY)if end$(EMPTY)if
@@ -475,10 +462,10 @@ cscope:
cscope -bR cscope -bR
sphinx: sphinx:
$(MAKE) -C Documentation sphinx $(MAKE) -C Documentation -f Makefile.sphinx html
sphinx-lint: sphinx-lint:
$(MAKE) SPHINXOPTS=-W -C Documentation sphinx $(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
symlink: symlink:
@echo "Creating Symbolic Links.."; \ @echo "Creating Symbolic Links.."; \

View File

@@ -23,7 +23,7 @@ ifeq ($(BUILD_TIMELESS),1)
KERNELVERSION := -TIMELESS--LESSTIME- KERNELVERSION := -TIMELESS--LESSTIME-
else else
KERNELVERSION := $(strip $(if $(GIT),\ KERNELVERSION := $(strip $(if $(GIT),\
$(shell git describe --abbrev=12 --dirty --always || git describe),\ $(shell git describe --dirty --always || git describe),\
$(if $(wildcard $(top)/.coreboot-version),\ $(if $(wildcard $(top)/.coreboot-version),\
$(shell cat $(top)/.coreboot-version),\ $(shell cat $(top)/.coreboot-version),\
coreboot-unknown$(KERNELREVISION)))) coreboot-unknown$(KERNELREVISION))))
@@ -59,36 +59,19 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES
####################################################################### #######################################################################
# root rule to resolve if in build mode (ie. configuration exists) # root rule to resolve if in build mode (ie. configuration exists)
real-target: $(obj)/config.h coreboot files_added show_coreboot show_notices real-target: $(obj)/config.h coreboot files_added
coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt $(obj)/cse_serger coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt $(obj)/cse_serger
# This target can be used to run scripts or additional targets # This target can be used in site local to run scripts or additional
# after the build completes by creating a target named 'build_complete::' # targets after the build completes by creating a Makefile.inc in the
.PHONY: build_complete # site-local directory with a target named 'build_complete::'
build_complete:: | coreboot build_complete:: coreboot
printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) \
$(CONFIG_MAINBOARD_PART_NUMBER)
# This target can be used to run rules after all files were added to CBFS, # This target can be used to run rules after all files were added to CBFS,
# for example to process FMAP regions or the entire image. # for example to process FMAP regions or the entire image.
.PHONY: files_added files_added:: build_complete
files_added:: | build_complete
# This target should come just before the show_notices target. If there
# are no notices, the build should finish with the text of what was just
# built.
.PHONY: show_coreboot
show_coreboot: | files_added
$(CBFSTOOL) $(obj)/coreboot.rom print -r $(subst $(spc),$(comma),$(all-regions))
printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
if [ -f "$(CCACHE_STATSLOG)" ]; then \
printf "\nccache statistics\n"; \
$(CCACHE) --show-log-stats -v; \
fi
# This is intended to run at the *very end* of the build to show warnings
# notices and the like. If another target needs to be added, add it
# BEFORE this target.
.PHONY: show_notices
show_notices:: | show_coreboot
####################################################################### #######################################################################
# our phony targets # our phony targets
@@ -160,7 +143,6 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \
# tolower: returns the value in all lowercase # tolower: returns the value in all lowercase
# toupper: returns the value in all uppercase # toupper: returns the value in all uppercase
# ws_to_under: returns the value with any whitespace changed to underscores # ws_to_under: returns the value with any whitespace changed to underscores
# get_fmap_value returns the value of a given FMAP field from fmap_config.h
_toint=$(shell printf "%d" $1) _toint=$(shell printf "%d" $1)
_tohex=$(shell printf 0x"%x" $1) _tohex=$(shell printf 0x"%x" $1)
_int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2)) _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2))
@@ -180,7 +162,6 @@ file-size=$(strip $(shell wc -c "$1" | cut -f 1 -d ' '))
tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
ws_to_under=$(shell echo '$1' | tr ' \t' '_') ws_to_under=$(shell echo '$1' | tr ' \t' '_')
get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h)
####################################################################### #######################################################################
# Helper functions for ramstage postprocess # Helper functions for ramstage postprocess
@@ -345,19 +326,6 @@ define cbfs-files-processor-config
mv -f $(2).tmp $(2)) mv -f $(2).tmp $(2))
endef endef
#######################################################################
# Add a file to CBFS with just type and compression values
# arg1: name in CBFS
# arg2: filename and path
# arg3: type in CBFS
# arg4: compression type
define add-cbfs-file-simple
$(eval cbfs-files-y += $(1))
$(eval $(1)-file := $(2))
$(eval $(1)-type := $(3))
$(eval $(1)-compression := $(4))
endef
####################################################################### #######################################################################
# Compile a C file with a bare struct definition into binary # Compile a C file with a bare struct definition into binary
# arg1: C source file # arg1: C source file
@@ -370,41 +338,6 @@ cbfs-files-processor-struct= \
rm -f $(2).tmp) \ rm -f $(2).tmp) \
$(eval DEPENDENCIES += $(2).d) $(eval DEPENDENCIES += $(2).d)
#######################################################################
# Convert image to YCC 4:2:0 JPEG
#
# In two steps:
# 1. Convert to RGB colors, optionally resize and store as BMP.
# 2. Round final size to multiples of 16, optionally swap colors,
# convert (back) to sRGB and store as JPEG.
# The split is necessary because we don't know the exact, scaled
# size due to aspect-ratio. Note: IM v7 would allow us to do the
# calculations in one command using %[fx:...] syntax.
#
# arg1: image input file
# arg2: output jpg
cbfs-files-processor-jpg420= \
$(eval $(2): $(1) $(KCONFIG_AUTOCONFIG); \
printf " CONVERT $$<\n"; \
res=$(CONFIG_BOOTSPLASH_CONVERT_RESOLUTION); \
res=$$$$(convert $$< \
-colorspace RGB \
$$(BOOTSPLASH_RESIZE-y) \
-format '%wx%h' -write info: \
bmp:$$@); \
convert $$@ \
$$(BOOTSPLASH_ROUND16) \
$$(BOOTSPLASH_COLORSWAP-y) \
-colorspace sRGB \
-quality $$(CONFIG_BOOTSPLASH_CONVERT_QUALITY)% \
-interlace none -colorspace YCC -sampling-factor 4:2:0 \
jpg:$$@)
BOOTSPLASH_FLOOR = $$(($${res%%x*} & ~15))x$$(($${res\#\#*x} & ~15))
BOOTSPLASH_RESIZE-$(CONFIG_BOOTSPLASH_CONVERT_RESIZE) = -resize $(BOOTSPLASH_FLOOR)
BOOTSPLASH_CEIL = $$((($${res%%x*} + 15) & ~15))x$$((($${res\#\#*x} + 15) & ~15))
BOOTSPLASH_ROUND16 = -background black -gravity center -extent $(BOOTSPLASH_CEIL)
BOOTSPLASH_COLORSWAP-$(CONFIG_BOOTSPLASH_CONVERT_COLORSWAP) := -channel-fx 'red<=>blue'
####################################################################### #######################################################################
# Add handler for arbitrary files in CBFS # Add handler for arbitrary files in CBFS
$(call add-special-class,cbfs-files) $(call add-special-class,cbfs-files)
@@ -502,7 +435,7 @@ ifeq ($(CONFIG_COMPILER_GCC),y)
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -Wno-packed-not-aligned
CFLAGS_common += -fconserve-stack CFLAGS_common += -fconserve-stack
CFLAGS_common += -Wnull-dereference CFLAGS_common += -Wnull-dereference -Wreturn-type
CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
endif endif
endif endif
@@ -664,8 +597,6 @@ APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
APCB_V3A_EDIT_TOOL:=$(top)/util/apcb/apcb_v3a_edit.py
CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
FUTILITY?=$(objutil)/futility/futility FUTILITY?=$(objutil)/futility/futility
@@ -880,7 +811,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
# mma, efi, deleted, null # mma, efi, deleted, null
# 4 - Compression type [$(FILENAME)-compression] # 4 - Compression type [$(FILENAME)-compression]
# none, LZMA # none, LZMA
# 5 - Base address [$(FILENAME)-position] # 5 - Base address [$(FILANAME)-position]
# 6 - Alignment [$(FILENAME)-align] # 6 - Alignment [$(FILENAME)-align]
# 7 - cbfstool flags [$(FILENAME)-options] # 7 - cbfstool flags [$(FILENAME)-options]
# #
@@ -1082,15 +1013,6 @@ else
FMAP_VPD_ENTRY := FMAP_VPD_ENTRY :=
endif endif
ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y)
FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000)
FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE)
FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE)
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE))
else
FMAP_HSPHY_FW_ENTRY :=
endif
# #
# X86 FMAP region # X86 FMAP region
# #
@@ -1169,7 +1091,6 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
-e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
-e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
-e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \
-e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \
-e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
-e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
$(DEFAULT_FLASHMAP) > $@.tmp $(DEFAULT_FLASHMAP) > $@.tmp
@@ -1255,6 +1176,7 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ layout $(CBFSTOOL) $@ layout
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions))
ifeq ($(CONFIG_CBFS_VERIFICATION),y) ifeq ($(CONFIG_CBFS_VERIFICATION),y)
line=$$($(CBFSTOOL) $@ print -kv 2>/dev/null | grep -F '[CBFS VERIFICATION (COREBOOT)]') ;\ line=$$($(CBFSTOOL) $@ print -kv 2>/dev/null | grep -F '[CBFS VERIFICATION (COREBOOT)]') ;\
if ! printf "$$line" | grep -q 'fully valid'; then \ if ! printf "$$line" | grep -q 'fully valid'; then \
@@ -1263,7 +1185,6 @@ ifeq ($(CONFIG_CBFS_VERIFICATION),y)
fi fi
endif # CONFIG_CBFS_VERIFICATION endif # CONFIG_CBFS_VERIFICATION
ifeq ($(CONFIG_SEPARATE_ROMSTAGE),y)
cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage
$(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf
$(CONFIG_CBFS_PREFIX)/romstage-type := stage $(CONFIG_CBFS_PREFIX)/romstage-type := stage
@@ -1281,11 +1202,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
# #
# Make sure that segment for .car.data is ignored while adding romstage. # Make sure that segment for .car.data is ignored while adding romstage.
$(CONFIG_CBFS_PREFIX)/romstage-align := 64 $(CONFIG_CBFS_PREFIX)/romstage-align := 64
ifeq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data"
else
$(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data,.data"
endif
# If CAR does not support execution of code, romstage on x86 is expected to be # If CAR does not support execution of code, romstage on x86 is expected to be
# xip. # xip.
@@ -1302,9 +1219,6 @@ endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y)
$(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB) $(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB)
endif endif
else # CONFIG_SEPARATE_ROMSTAGE
postinclude-hooks += $$(eval bootblock-srcs += $$(romstage-srcs))
endif
cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
$(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
@@ -1337,19 +1251,10 @@ cbfs-files-y += build_info
build_info-file := $(obj)/build_info build_info-file := $(obj)/build_info
build_info-type := raw build_info-type := raw
ifeq ($(CONFIG_BOOTSPLASH_CONVERT),y)
ifeq ($(shell command -v convert),)
$(error CONFIG_BOOTSPLASH_CONVERT requires the convert program (part of ImageMagick))
endif
cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash.jpg
bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)):jpg420
bootsplash.jpg-type := bootsplash
else
BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))) BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX) cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash
endif
# Ensure that no payload segment overlaps with memory regions used by ramstage # Ensure that no payload segment overlaps with memory regions used by ramstage
# (not for x86 since it can relocate itself in that case) # (not for x86 since it can relocate itself in that case)

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@@ -140,10 +140,9 @@ These uncopyrightable files include:
These may be required to exist as part of the build process but are These may be required to exist as part of the build process but are
not needed for the particular project. not needed for the particular project.
- Configuration files either in binary or text form. Examples would be - Configuration files either in binary or text form. Examples would be
files such as .vbt files describing graphics configuration, .apcb files such as .vbt files describing graphics configuration, spd files
files containing configuration parameters for AMD firmware binaries, as binary .spd or text \*spd\*.hex representing memory chip
and spd files as binary .spd or text \*spd\*.hex representing memory configuration.
chip configuration.
- Machine-generated files containing version numbers, dates, hash - Machine-generated files containing version numbers, dates, hash
values or other "non-creative" content. values or other "non-creative" content.

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@@ -1,16 +0,0 @@
# Inventec Transformers coreboot is modified from Intel ArcherCity CRB
# Inventec Transformers is a dual socket CRB based on Intel.
# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
#
# Type this in coreboot root directory to get a working .config:
# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
CONFIG_VENDOR_INVENTEC=y
CONFIG_BOARD_INVENTEC_TRANSFORMERS=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
CONFIG_PAYLOAD_LINUX=y
CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage"
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"

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@@ -8,3 +8,4 @@ CONFIG_DEBUG_PIRQ=y
CONFIG_DEBUG_MALLOC=y CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_BOOT_STATE=y
CONFIG_DEBUG_ADA_CODE=y CONFIG_DEBUG_ADA_CODE=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y

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@@ -1,3 +1,5 @@
CONFIG_VENDOR_EMULATION=y CONFIG_VENDOR_EMULATION=y
CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
CONFIG_CPU_QEMU_X86_TSEG_SMM=y CONFIG_CPU_QEMU_X86_TSEG_SMM=y
CONFIG_CPU_QEMU_X86_SMMLOADERV2=y

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@@ -10,6 +10,7 @@ CONFIG_ANY_TOOLCHAIN=y
# ChromeOS # ChromeOS
CONFIG_CHROMEOS=y CONFIG_CHROMEOS=y
CONFIG_HAS_RECOVERY_MRC_CACHE=y CONFIG_HAS_RECOVERY_MRC_CACHE=y
CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
# Event Logging # Event Logging
CONFIG_CMOS_POST=y CONFIG_CMOS_POST=y
@@ -33,5 +34,5 @@ CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_115200=y CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_DRIVERS_UART_8250IO is not set # CONFIG_DRIVERS_UART_8250IO is not set
# GLK specific setting to auto select all the correct settings. # GLK specific setting to auto select all the correct settings.
CONFIG_INTEL_LPSS_UART_FOR_CONSOLE=y CONFIG_UART_DEBUG=y
CONFIG_NO_BOOTBLOCK_CONSOLE=y CONFIG_NO_BOOTBLOCK_CONSOLE=y

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@@ -1,4 +1,4 @@
CONFIG_VENDOR_GOOGLE=y CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_OCTOPUS=y CONFIG_BOARD_GOOGLE_OCTOPUS=y
CONFIG_CONSOLE_SPI_FLASH=y CONFIG_CONSOLE_SPI_FLASH=y
# CONFIG_TPM_MEASURED_BOOT is not set # CONFIG_VBOOT_MEASURED_BOOT is not set

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@@ -1,6 +1,7 @@
CONFIG_USE_AMD_BLOBS=y CONFIG_USE_AMD_BLOBS=y
CONFIG_VENDOR_GOOGLE=y CONFIG_VENDOR_GOOGLE=y
# CONFIG_CONSOLE_SERIAL is not set # CONFIG_CONSOLE_SERIAL is not set
CONFIG_AMD_FWM_POSITION_INDEX=4
CONFIG_VBOOT=y CONFIG_VBOOT=y
CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_VBOOT_SLOTS_RW_A=y
# CONFIG_DRIVERS_INTEL_WIFI is not set # CONFIG_DRIVERS_INTEL_WIFI is not set

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@@ -1,18 +1,31 @@
CONFIG_TIMESTAMPS_ON_CONSOLE=y CONFIG_TIMESTAMPS_ON_CONSOLE=y
CONFIG_USE_AMD_BLOBS=y CONFIG_USE_AMD_BLOBS=y
CONFIG_VENDOR_GOOGLE=y CONFIG_VENDOR_GOOGLE=y
CONFIG_VGA_BIOS_ID="1002,1506"
CONFIG_AMD_FWM_POSITION_INDEX=3
CONFIG_VGA_BIOS=y CONFIG_VGA_BIOS=y
CONFIG_CONSOLE_POST=y CONFIG_CONSOLE_POST=y
CONFIG_BOARD_GOOGLE_SKYRIM=y CONFIG_BOARD_GOOGLE_SKYRIM=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin" CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin"
CONFIG_PSP_SOFTFUSE_BITS="34 28" CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin"
CONFIG_DEBUG_SMI=y CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
CONFIG_ASYNC_FILE_LOADING=y CONFIG_ASYNC_FILE_LOADING=y
CONFIG_PSP_SOFTFUSE_BITS="34 28"
CONFIG_UART_PCI_ADDR=0x0
CONFIG_RUN_FSP_GOP=y CONFIG_RUN_FSP_GOP=y
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_DISPLAY_HOBS=y CONFIG_DISPLAY_HOBS=y
CONFIG_DISPLAY_UPD_DATA=y CONFIG_DISPLAY_UPD_DATA=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_POST_IO_PORT=0x80
CONFIG_PAYLOAD_NONE=y CONFIG_PAYLOAD_NONE=y
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y CONFIG_DISPLAY_FSP_HEADER=y
CONFIG_FATAL_ASSERTS=y CONFIG_FATAL_ASSERTS=y
CONFIG_DEBUG_SMI=y
CONFIG_WRITE_STB_BUFFER_TO_CONSOLE=y
CONFIG_ADD_POSTCODES_TO_STB=y

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@@ -0,0 +1,7 @@
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_INTEL=y
CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
CONFIG_USE_CANNONLAKE_FSP_CAR=y
CONFIG_RUN_FSP_GOP=y
CONFIG_PAYLOAD_NONE=y

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@@ -0,0 +1,10 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_GALILEO_GEN2 is not set
# CONFIG_FSP_DEBUG_ALL is not set
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_460800=y

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@@ -0,0 +1,9 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

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@@ -0,0 +1,13 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
CONFIG_DISPLAY_MTRRS=y
CONFIG_DISPLAY_ESRAM_LAYOUT=y
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
CONFIG_VERIFY_HOBS=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_CONSOLE_SERIAL_921600=y

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@@ -0,0 +1,8 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

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@@ -0,0 +1,18 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_COMMONLIB_STORAGE_MMC=y
CONFIG_STORAGE_ERASE=y
CONFIG_STORAGE_EARLY_ERASE=y
CONFIG_STORAGE_WRITE=y
CONFIG_STORAGE_EARLY_WRITE=y
CONFIG_SD_MMC_DEBUG=y
CONFIG_SD_MMC_TRACE=y
CONFIG_SDHC_TRACE=y
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_CONSOLE_SERIAL_921600=y

View File

@@ -0,0 +1,9 @@
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
CONFIG_VBOOT_WITH_CRYPTO_SHIELD=y
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

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@@ -1,11 +0,0 @@
CONFIG_VENDOR_MSI=y
CONFIG_VBOOT=y
CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_TPM2=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
CONFIG_EDK2_CBMEM_LOGGING=y
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

View File

@@ -1,11 +0,0 @@
CONFIG_VENDOR_MSI=y
CONFIG_VBOOT=y
CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_TPM2=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
CONFIG_EDK2_CBMEM_LOGGING=y
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

View File

@@ -6,5 +6,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y CONFIG_PXE=y
CONFIG_BUILD_IPXE=y CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="10ec,8168" CONFIG_PXE_ROM_ID="10ec,8168"
# CONFIG_IPXE_SERIAL_CONSOLE is not set # CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y CONFIG_PXE=y
CONFIG_BUILD_IPXE=y CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,157b" CONFIG_PXE_ROM_ID="8086,157b"
# CONFIG_IPXE_SERIAL_CONSOLE is not set # CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y CONFIG_PXE=y
CONFIG_BUILD_IPXE=y CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539" CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_IPXE_SERIAL_CONSOLE is not set # CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

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