Update amd_blobs

Change-Id: I90b7fd111ec0c57436085fd3f0c977e3cba8910f

Documentation/mainboard/index.md

@@ -182,15 +182,19 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Adder Workstation 1](system76/addw1.md)
 - [Adder Workstation 2](system76/addw2.md)
+- [Bonobo Workstation 14](system76/bonw14.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Gazelle 15](system76/gaze15.md)
+- [Gazelle 16](system76/gaze16.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
+- [Oryx Pro 7](system76/oryp7.md)
+- [Oryx Pro 8](system76/oryp8.md)
 
 ## Texas Instruments
 

Documentation/mainboard/system76/bonw14.md

@@ -0,0 +1,77 @@
+# System76 Bonobo Workstation 14 (bonw14)
+
+## Specs
+
+- CPU
+  - Intel Core i5-10600K
+  - Intel Core i7-10700K
+  - Intel Core i9-10900K
+- Chipset
+  - Intel Z490
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Grahpics
+  - dGPU options
+    - NVIDIA GeForce RTX 2080 Super
+    - NVIDIA GeForce RTX 2070 Super
+    - NVIDIA GeForce RTX 2060
+  - eDP options
+    - 17.3" 1920x1080x144Hz LCD (LG LP173WFG-SPB1)
+    - 17.3" 3840x2160@60Hz LCD (AUO B173ZAN03.0)
+  - 1x HDMI
+  - 2x Mini DisplayPort 1.4
+  - 2x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 128GB (4x32GB) quad-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX200/AX201
+- Power
+  - 2x 280W (20V 14A) AC barrel adapter
+    - Chicony A18-280P1A, using a C13 power cord
+  - 97Wh 8-cell Lithium-Ion battery
+- Sound
+  - Realtek ALC1220 codec
+  - 2x TI TAS5825MRHBR smart AMPs
+  - Internal speakers (stereo + subwoofer) and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Combined 3.5mm microphone and S/PDIF jack
+  - HDMI, Mini DisplayPort, USB-C DisplayPort audio
+- Storage
+  - 2x M.2 PCIe NVMe or SATA SSD
+  - 1x M.2 PCIe NVMe-only SSD
+  - 1x M.2 SATA-only SSD
+  - SD card reader (RTS5260)
+- USB
+  - 1x USB Type-C with Thunderbolt 3
+  - 1x USB 3.2 Gen 2 Type-C with DisplayPort 1.4
+  - 1x USB 3.2 Gen 2x2 Type-C
+  - 3x USB 3.2 Gen 2 Type-A
+- Dimensions
+  - 4.343cm x 39.903cm x 31.902cm, 3.80kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B127D           |
++---------------------+---------------------+
+| Size                | 16 MiB              |
++---------------------+---------------------+
+| Package             | SOIC-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+External flashing via ISP requires removing the board from the chassis.
+The flash chip (U16) is next to the PCH.

Documentation/mainboard/system76/gaze16.md

@@ -0,0 +1,87 @@
+# System76 Gazelle 16 (gaze16)
+
+## Specs
+
+- CPU
+  - Intel Core i7-11800H
+- Chipset
+  - Intel HM570
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+  - eDP displays
+    - 15.6" 1920x1080@144Hz LCD (AUO B156HAN08.4)
+    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
+  - External outputs
+    - RTX 3050/3050 Ti
+      - 1x HDMI
+      - 1x Mini DisplayPort 1.4
+    - RTX 3060
+      - 1x HDMI
+      - 1x Mini DisplayPort 1.2
+      - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+    - Either onboard Intel I219-V or Realtek RTL8111H controller
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX200/AX201
+- Power
+  - RTX 3050/3050 Ti
+    - 150W AC barrel adapter
+      - Included: Chicony A17-150P2A, using a C5 power cord
+  - RTX 3060
+    - 180W AC barrel adapter
+      - Included: Chicony A17-180P4A, using a C5 power cord
+  - 48.96Wh 4-cell battery
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - SD card reader
+    - Realtek RTS5227S on RTX 3050/3050 Ti models
+    - Realtek OZ711LV2 on RTX 3060 models
+- USB
+  - 1x USB 3.2 Gen 2 Type-C
+    - Supports DisplayPort over USB-C on RTX 3060 models only
+    - Does not support USB-C charging (USB-PD) or Thunderbolt
+  - 1x USB 3.2 Gen 2 Type-A
+  - 1x USB 3.2 Gen 1 Type-A
+  - 1x USB 2.0 Type-A
+- Dimensions
+  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
+  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B127D           |
++---------------------+---------------------+
+| Size                | 16 MiB              |
++---------------------+---------------------+
+| Package             | SOIC-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U51 on 3050 variant, U52 on 3060 variant) is left of the top DIMM slot.

Documentation/mainboard/system76/oryp7.md

@@ -0,0 +1,71 @@
+# System76 Oryx Pro 7 (oryp7)
+
+## Specs
+
+- CPU
+  - Intel Core i7-10870H
+- Chipset
+  - Intel HM470
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3060
+    - NVIDIA GeForce RTX 3070 (Max-Q)
+    - NVIDIA GeForce RTX 3080 (Max-Q)
+  - eDP display options
+    - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
+    - 15.6" 1920x1080@60Hz OLED (Samsung ATNA56WR06)
+    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB1)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 2933 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel WiFi 6 AX200/AX201
+- Power
+  - 180W (19.5V, 9.23A) AC barrel adapter
+    - Chicony A17-180P4A, using a C5 power cord
+  - 73Wh 3-cell battery
+- Sound
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone and microphone jack
+  - Combined 3.5mm microphone and S/PDIF jack
+  - HDMI, Mini DisplayPort, USB-C DisplayPort audio
+- Storage
+  - 1x M.2 PCIe NVMe or SATA SSD
+  - 1x M.2 PCIe NVME SSD
+  - MicroSD card reader
+- USB
+  - 1x USB Type-C with Thunderbolt 3
+  - 3x USB 3.2 Gen 1 Type-A
+- Dimensions
+  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
+  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+-----------------+
+| Type                | Value           |
++=====================+=================+
+| Socketed flash      | no              |
++---------------------+-----------------+
+| Vendor              | Macronix        |
++---------------------+-----------------+
+| Model               | MX25L12873F     |
++---------------------+-----------------+
+| Size                | 16 MiB          |
++---------------------+-----------------+
+| Package             | SOIC-8          |
++---------------------+-----------------+
+| Internal flashing   | yes             |
++---------------------+-----------------+
+| External flashing   | yes             |
++---------------------+-----------------+
+```
+
+The flash chip (U66) is above the M.2 SSD connectors.

Documentation/mainboard/system76/oryp8.md

@@ -0,0 +1,67 @@
+# System76 Oryx Pro 8 (oryp8)
+
+## Specs
+
+- CPU
+  - Intel Core i7-11800H
+- Chipset
+  - Intel HM570
+- EC
+  - ITE IT570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3070
+    - NVIDIA GeForce RTX 3080
+  - eDP options
+    - 15.6" 1920x1080@144Hz LCD
+    - 17.3" 1920x1080@144Hz LCD
+  - 1x HDMI
+  - 1x Mini DisplayPort
+  - 1x DisplayPort over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX200/AX201
+- Power
+  - 180W (19.5V, 9.23A) AC barrel adapter
+    - Lite-On PA-1181-16
+  - 73Wh 3-cell battery
+- Sound
+  - Realtek ALC1220 codec
+  - TI TAS5825M smart amp
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Combined 3.5mm microphone & S/PDIF jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA SSD
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 3x USB 3.0 Type-A
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+-----------------+
+| Type                | Value           |
++=====================+=================+
+| Socketed flash      | no              |
++---------------------+-----------------+
+| Vendor              | GigaDevice      |
++---------------------+-----------------+
+| Model               | GD25B127D       |
++---------------------+-----------------+
+| Size                | 16 MiB          |
++---------------------+-----------------+
+| Package             | SOIC-8          |
++---------------------+-----------------+
+| Internal flashing   | yes             |
++---------------------+-----------------+
+| External flashing   | yes             |
++---------------------+-----------------+
+```
+
+The flash chip (U74) is right of the bottom DIMM slot.

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus with GC6 3.0
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/gpu.asl

@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEGP) {
+	Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
+		}
+
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
+		}
+	}
+
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
+}
+
+Device (\_SB.PCI0.PEGP.DEV0) {
+	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+        // TODO: use GPU config to generate address
+	OperationRegion (RPCX, SystemMemory, CONFIG_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
+
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
+
+				Debug = "    Sleep 16"
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
+	}
+
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
+}

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!dev->enabled || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus graphics device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n",
+		__func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n",
+		__func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}

src/ec/system76/ec/Kconfig

@@ -13,6 +13,11 @@ config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	bool
 	default n
 
+config EC_SYSTEM76_EC_DGPU
+	depends on EC_SYSTEM76_EC
+	bool
+	default n
+
 config EC_SYSTEM76_EC_OLED
 	depends on EC_SYSTEM76_EC
 	bool

src/ec/system76/ec/acpi/s76.asl

@@ -117,6 +117,9 @@ Device (S76D) {
 	Method (NFAN, 0, Serialized) {
 		Return (Package() {
 			"CPU fan",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU fan",
+#endif
 		})
 	}
 
@@ -144,6 +147,9 @@ Device (S76D) {
 	Method (NTMP, 0, Serialized) {
 		Return (Package() {
 			"CPU temp",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU temp",
+#endif
 		})
 	}
 

src/include/cpu/intel/cpu_ids.h

@@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1

src/mainboard/system76/addw1/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select EC_SYSTEM76_EC_OLED
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES

src/mainboard/system76/addw1/Makefile.inc

@@ -1,4 +1,5 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/dgpu.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>

src/mainboard/system76/addw1/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-power_on_after_fail=Enable
+ime_mode=Disable

src/mainboard/system76/addw1/cmos.layout

@@ -11,12 +11,16 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
-409	2	e	7	power_on_after_fail
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 

src/mainboard/system76/addw1/devicetree.cb

@@ -58,6 +58,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device
@@ -98,7 +105,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 off end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/system76/addw1/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/dgpu.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Allow higher memory speeds
 	memupd->FspmConfig.SaOcSupport = 1;
 

src/mainboard/system76/addw1/variants/addw1/include/variant/dgpu.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_DGPU_H
+#define VARIANT_DGPU_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+
+#endif

src/mainboard/system76/addw1/variants/addw2/include/variant/dgpu.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_DGPU_H
+#define VARIANT_DGPU_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+
+#endif

src/mainboard/system76/bonw14/Kconfig

@@ -0,0 +1,58 @@
+if BOARD_SYSTEM76_BONW14
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE_S
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/bonw14"
+
+config MAINBOARD_PART_NUMBER
+	default "bonw14"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Bonobo WS"
+
+config MAINBOARD_VERSION
+	default "bonw14"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config UART_FOR_CONSOLE
+	default 2
+
+config MAX_CPUS
+	default 20
+
+config DIMM_MAX
+	default 4
+
+config POST_DEVICE
+	default n
+
+endif

src/mainboard/system76/bonw14/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_BONW14
+	bool "bonw14"

src/mainboard/system76/bonw14/Makefile.inc

@@ -0,0 +1,10 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
+
+romstage-y += romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c

src/mainboard/system76/bonw14/acpi/dgpu.asl

@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEG0)
+{
+	Name (_ADR, 0x00010000)
+
+	Device (PEGP)
+	{
+		Name (_ADR, 0)
+
+		// Convert a byte to a hex string, trimming extra parts
+		Method (BHEX, 1)
+		{
+			Local0 = ToHexString(Arg0)
+			Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+		}
+
+		// UUID to string
+		Method (IDST, 1)
+		{
+			Local0 = ""
+			Fprintf(
+				Local0,
+				"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+				BHEX(DerefOf(Arg0[3])),
+				BHEX(DerefOf(Arg0[2])),
+				BHEX(DerefOf(Arg0[1])),
+				BHEX(DerefOf(Arg0[0])),
+				BHEX(DerefOf(Arg0[5])),
+				BHEX(DerefOf(Arg0[4])),
+				BHEX(DerefOf(Arg0[7])),
+				BHEX(DerefOf(Arg0[6])),
+				BHEX(DerefOf(Arg0[8])),
+				BHEX(DerefOf(Arg0[9])),
+				BHEX(DerefOf(Arg0[10])),
+				BHEX(DerefOf(Arg0[11])),
+				BHEX(DerefOf(Arg0[12])),
+				BHEX(DerefOf(Arg0[13])),
+				BHEX(DerefOf(Arg0[14])),
+				BHEX(DerefOf(Arg0[15]))
+			)
+			Return (Local0)
+		}
+
+		// Safe hex conversion, checks type first
+		Method (SFST, 1)
+		{
+			Local0 = ObjectType(Arg0)
+			If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+				Return (ToHexString(Arg0))
+			} Else {
+				Return (Concatenate("Type: ", Arg0))
+			}
+		}
+
+		Method (_DSM, 4, Serialized)
+		{
+			Debug = "NVIDIA _DSM"
+			Printf("  Arg0: %o", IDST(Arg0))
+			Printf("  Arg1: %o", SFST(Arg1))
+			Printf("  Arg2: %o", SFST(Arg2))
+			Printf("  Arg3: %o", SFST(Arg3))
+
+			If (Arg0 == ToUUID ("d4a50b75-65c7-46f7-bfb7-41514cea0244")) {
+				If (Arg1 != 0x0102) {
+					Printf("  Invalid Arg1, return 0x80000002")
+					Return (0x80000002)
+				}
+
+				If (Arg2 == 0) {
+					Printf("  Arg2 == 0x00, return supported functions")
+					Return (Buffer (4) { 0x01, 0x00, 0x10, 0x00 })
+				}
+
+				If (Arg2 == 0x14) {
+					Printf("  Arg2 == 0x14, return backlight package")
+					Return (Package (9) {
+						0x8000A450,
+						0x0200,
+						0,
+						0,
+						1,
+						1,
+						200,
+						32,
+						1000
+					})
+				}
+
+				Printf("  Unknown Arg2, return 0x80000002")
+				Return (0x80000002)
+			}
+
+			Printf("  Unknown Arg0, return 0x80000001")
+			Return (0x80000001)
+		}
+
+		// _DOD: Display Output Devices
+		Method (_DOD, 0, NotSerialized)
+		{
+			Return (Package (3) {
+				0x80008320,
+				0x80006330,
+				0x8000A450
+			})
+		}
+
+		Device (HDM0)
+		{
+			Name (_ADR, 0x80008320)
+		}
+
+		Device (DSP0)
+		{
+			Name (_ADR, 0x80006330)
+		}
+
+		Device (DSP1)
+		{
+			Name (_ADR, 0x8000A450)
+		}
+	}
+}

src/mainboard/system76/bonw14/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/bonw14/acpi/mainboard.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}
+
+#include "dgpu.asl"

src/mainboard/system76/bonw14/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/bonw14/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: bonw14
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/bonw14/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}

src/mainboard/system76/bonw14/cmos.default

@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+ime_mode=Disable

src/mainboard/system76/bonw14/cmos.layout

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+#409	2	e	7	power_on_after_fail
+412	4	e	6	debug_level
+416	1	e	2	ime_mode
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+checksums
+
+checksum 408 983 984

src/mainboard/system76/bonw14/devicetree.cb

@@ -0,0 +1,226 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 125,
+		.tdp_pl2_override = 160,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
+	}"
+
+	# Misc
+	register "AcousticNoiseMitigation" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	register "tcc_offset" = "13"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x7714 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on      # GPU Port
+			# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
+			register "PcieClkSrcUsage[7]" = "0x40"
+			register "PcieClkSrcClkReq[7]" = "7"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
+		end
+		# TODO: is this enough to disable iGPU?
+		device pci 02.0 off end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on      # USB xHCI
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
+		end
+		device pci 14.2 on  end # Shared SRAM
+		device pci 14.3 on      # CNVi wifi
+			chip drivers/wifi/generic
+				register "wake" = "PME_B0_EN_BIT"
+				device generic 0 on end
+			end
+		end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on      # I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on      # SATA
+			register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
+			register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
+			register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
+		end
+		device pci 19.2 off end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on      # PCI Express Port 17
+			# PCI Express root port #17 x4, Clock 14 (SSD2)
+			register "PcieRpEnable[16]" = "1"
+			register "PcieRpLtrEnable[16]" = "1"
+			register "PcieClkSrcUsage[14]" = "16"
+			register "PcieClkSrcClkReq[14]" = "14"
+		end
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on      # PCI Express Port 21
+			# PCI Express root port #21 x4, Clock 15 (SSD3)
+			register "PcieRpEnable[20]" = "1"
+			register "PcieRpLtrEnable[20]" = "1"
+			register "PcieClkSrcUsage[15]" = "20"
+			register "PcieClkSrcClkReq[15]" = "15"
+		end
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 on      # PCI Express Port 1
+			# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			register "PcieRpHotPlug[0]" = "1"
+			register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
+			register "PcieClkSrcClkReq[6]" = "6"
+		end
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on      # PCI Express Port 5
+			# PCI Express root port #5 x4, Clock 10 (USB 3.2)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieClkSrcUsage[10]" = "4"
+			register "PcieClkSrcClkReq[10]" = "10"
+		end
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on      # PCI Express Port 9
+			# PCI Express root port #9 x4, Clock 8 (SSD)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[8]" = "8"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on      # PCI Express Port 13
+			# PCI Express root port #13 x1, Clock 0 (WLAN)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[0]" = "12"
+			register "PcieClkSrcClkReq[0]" = "0"
+		end
+		device pci 1d.5 on      # PCI Express Port 14
+			# PCI Express root port #14 x1, Clock 1 (GLAN)
+			register "PcieRpEnable[13]" = "1"
+			register "PcieRpLtrEnable[13]" = "1"
+			register "PcieClkSrcUsage[1]" = "13"
+			register "PcieClkSrcClkReq[1]" = "1"
+		end
+		device pci 1d.6 on      # PCI Express Port 15
+			# PCI Express root port #15 x1, Clock 4 (Card Reader)
+			register "PcieRpEnable[14]" = "1"
+			register "PcieRpLtrEnable[14]" = "1"
+			register "PcieClkSrcUsage[4]" = "14"
+			register "PcieClkSrcClkReq[4]" = "4"
+		end
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on      # LPC Interface
+			register "gen1_dec" = "0x00040069"
+			register "gen2_dec" = "0x00fc0e01"
+			register "gen3_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 hidden end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/bonw14/dsdt.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/bonw14/gpio.c

@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // BATLOW_N
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // PCH_LAN_WAKE#
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, UP_20K),
+	PAD_CFG_GPI(GPD7, UP_20K, PWROK),
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE),
+	PAD_NC(GPD10, NONE),
+	PAD_CFG_GPI(GPD11, UP_20K, PWROK), // LANPHYPC
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // 10k pull up
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, UP_20K),
+	_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
+	PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // 10k pull up
+	PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUS_PWR_ACK
+	PAD_NC(GPP_A14, UP_20K),
+	PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUSACK#
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, UP_20K),
+	PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), // XFI_GAIN
+	PAD_CFG_GPO(GPP_A20, 1, DEEP), // GPP_A20 (MB det)
+	PAD_NC(GPP_A21, UP_20K),
+	PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), // GPP_A22 (MB det)
+	PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPP_A23 (MB det)
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_B1, UP_20K),
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // BT_UART_WAKE_N
+	PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
+	PAD_NC(GPP_B4, UP_20K),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R
+	PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ#
+	PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT#
+	PAD_CFG_GPO(GPP_B11, 1, DEEP), // PCIE_GLAN_RESET
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
+	PAD_NC(GPP_B15, UP_20K),
+	PAD_NC(GPP_B16, UP_20K),
+	PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // LPSS_GSPI0_MISO
+	PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI
+	PAD_NC(GPP_B19, UP_20K),
+	_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI#_3242
+	PAD_NC(GPP_B21, UP_20K),
+	PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI
+	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // EXI BOOT STALL STRAP
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // TLS CONFIDENTIALITY STRAP
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SMLINK0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SMLINK0_DATA
+	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // ESPI/LPC SELECT STRAP
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SMC_CPU_THERM_R
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SMD_CPU_THERM
+	PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET#
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // GSYNC_ID
+	PAD_NC(GPP_C10, DN_20K),
+	PAD_CFG_GPO(GPP_C11, 1, DEEP), // FW_RST#
+	PAD_NC(GPP_C12, UP_20K),
+	PAD_NC(GPP_C13, UP_20K),
+	PAD_NC(GPP_C14, UP_20K),
+	PAD_NC(GPP_C15, UP_20K),
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // T_SDA
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // T_SCL
+	PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411
+	PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411
+	//PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, UP_20K),
+	PAD_NC(GPP_C23, UP_20K),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, UP_20K),
+	PAD_NC(GPP_D1, UP_20K),
+	PAD_NC(GPP_D2, UP_20K),
+	PAD_NC(GPP_D3, UP_20K),
+	PAD_NC(GPP_D4, UP_20K),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUR_CLKREQ0
+	PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), // M.2_BT_PCMIN
+	PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), // M.2_BT_PCMCLK
+	PAD_NC(GPP_D9, UP_20K),
+	PAD_NC(GPP_D10, UP_20K),
+	PAD_NC(GPP_D11, UP_20K),
+	PAD_NC(GPP_D12, UP_20K),
+	PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 5825_I2C_DAT
+	PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 5825_I2C_CLK
+	PAD_NC(GPP_D15, UP_20K),
+	PAD_NC(GPP_D16, UP_20K),
+	PAD_NC(GPP_D17, UP_20K),
+	PAD_NC(GPP_D18, UP_20K),
+	PAD_NC(GPP_D19, UP_20K),
+	PAD_NC(GPP_D20, UP_20K),
+	PAD_NC(GPP_D21, UP_20K),
+	PAD_NC(GPP_D22, UP_20K),
+	PAD_NC(GPP_D23, UP_20K),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL
+	PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI#
+	PAD_NC(GPP_E4, UP_20K),
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SSD1_SATA_DEVSLP
+	PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // SSD3_SATA_DEVSLP
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+	PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // RING OSCILLATOR BYPASS STRAP
+	PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP
+	PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP
+	PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // DFX TEST MODE
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST#
+	PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), // 10k pull up
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD4_SATA_DEVSLP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // SSD2_SATA_DEVSLP
+	PAD_NC(GPP_F7, UP_20K),
+	PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // GPU_PWR_EN#
+	PAD_NC(GPP_F9, UP_20K),
+	PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER
+	PAD_CFG_GPO(GPP_F11, 0, DEEP), // SSD1_PWR_DN#
+	PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, UP_20K),
+	PAD_NC(GPP_F16, UP_20K),
+	PAD_NC(GPP_F17, UP_20K),
+	PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // GPIO_PCIESLOT_RST_R
+	PAD_NC(GPP_F19, UP_20K),
+	PAD_NC(GPP_F20, UP_20K),
+	PAD_NC(GPP_F21, UP_20K),
+	//PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F23, 0, DEEP), // GC_OFF_EN
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, UP_20K),
+	PAD_NC(GPP_G1, UP_20K),
+	PAD_NC(GPP_G2, UP_20K),
+	PAD_NC(GPP_G3, UP_20K),
+	PAD_NC(GPP_G4, UP_20K),
+	PAD_NC(GPP_G5, UP_20K),
+	PAD_NC(GPP_G6, UP_20K),
+	PAD_NC(GPP_G7, UP_20K),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ#
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ#
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ#
+	PAD_NC(GPP_H5, NONE),
+	PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N
+	PAD_CFG_GPO(GPP_H7, 0, DEEP), // PCIE_SSD2_RESET
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ#
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ#
+	PAD_NC(GPP_H10, NONE),
+	PAD_CFG_GPO(GPP_H11, 0, DEEP), // SSD3_PWR_DN#
+	PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12
+	PAD_NC(GPP_H13, UP_20K),
+	PAD_NC(GPP_H14, UP_20K),
+	_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000), // GPP_H15_TBT_WAKE#
+	PAD_NC(GPP_H16, UP_20K),
+	PAD_NC(GPP_H17, UP_20K),
+	PAD_NC(GPP_H18, UP_20K),
+	PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD_AUX
+	PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD
+	PAD_NC(GPP_H21, UP_20K),
+	PAD_NC(GPP_H22, UP_20K),
+	PAD_NC(GPP_H23, UP_20K),
+
+	/* ------- GPIO Group GPP_I ------- */
+	_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // GPPDPA_I0
+	_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // GPPDPB_I1
+	_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // DP_F_HPD
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // 100k pull down
+	PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET
+	PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // MXM_GPIO0
+	PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // 10k pull up
+	PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // GPIO_WIFI_RESET_R
+	PAD_CFG_GPO(GPP_I9, 1, DEEP), // WLAN_EN
+	PAD_CFG_GPO(GPP_I10, 0, DEEP), // SSD2_PWR_DN#
+	PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N
+	PAD_CFG_GPO(GPP_I12, 0, DEEP), // PCIE_SSD3_RESET
+	PAD_CFG_GPO(GPP_I13, 0, DEEP), // PCIE_SSD1_RESET
+	PAD_NC(GPP_I14, UP_20K),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // CPI_C10_GATE_N (VCCIO_3P3_PWRGATE)
+	PAD_NC(GPP_J2, UP_20K),
+	PAD_NC(GPP_J3, UP_20K),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT_R
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT_R
+	PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // EDP_OD_EN
+	PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE
+	PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE
+	PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD
+	_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
+	PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R
+	PAD_CFG_GPO(GPP_K5, 0, DEEP), // DP_MUX_SW
+	_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
+	PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN
+	PAD_CFG_GPO(GPP_K8, 0, DEEP), // SSD4_PWR_DN#
+	PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET
+	PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH
+	PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH
+	_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT#
+	PAD_NC(GPP_K13, UP_20K),
+	PAD_CFG_GPO(GPP_K14, 0, DEEP), // 7411_TEST_R
+	PAD_NC(GPP_K15, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R
+	PAD_NC(GPP_K17, UP_20K),
+	PAD_CFG_GPO(GPP_K18, 1, DEEP), // PCH_MUTE#
+	PAD_NC(GPP_K19, UP_20K),
+	PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // TEST_SETUP_MENU
+	PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN
+	//PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
+	PAD_CFG_GPO(GPP_K23, 1, RSMRST), // TBT_RTD3_PWR_EN_R
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/bonw14/gpio_early.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD
+	PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/bonw14/hda_verb.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15587714, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4094022d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451120),
+};
+
+const u32 pc_beep_verbs[] = {
+	// Enable DMIC microphone on ALC1220
+	0x02050036,
+	0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/bonw14/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <mainboard/gpio.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/bonw14/romstage.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa2},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa6},
+	},
+	.rcomp_resistor = { 121, 75, 100 },
+	.rcomp_targets = { 50, 26, 20, 20, 26 },
+	.dq_pins_interleaved = 1,
+	.vref_ca_config = 2,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+
+	// Set primary display to PCIe graphics
+	memupd->FspmConfig.PrimaryDisplay = 1;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/cml-u/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/cml-u"

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -6,6 +6,9 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/cml-u/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-power_on_after_fail=Enable
+ime_mode=Disable

src/mainboard/system76/cml-u/cmos.layout

@@ -11,12 +11,16 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
-409	2	e	7	power_on_after_fail
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 

src/mainboard/system76/cml-u/devicetree.cb

@@ -98,7 +98,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 off end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/system76/cml-u/dsdt.asl

@@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/darp7/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/darp7/acpi/mainboard.asl

@@ -6,4 +6,7 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/darp7/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-power_on_after_fail=Enable
+ime_mode=Enable

src/mainboard/system76/darp7/cmos.layout

@@ -11,12 +11,16 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
-409	2	e	7	power_on_after_fail
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 

src/mainboard/system76/darp7/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/galp5/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_GALP5
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
@@ -22,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/galp5"
@@ -57,4 +60,7 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	default 0x1c
+
 endif

src/mainboard/system76/galp5/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/galp5/acpi/dgpu.asl

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.RP05)
+{
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve)
+		{
+			Offset (0x40),
+			SSID, 32
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0)
+		{
+			Name (_STA, 1)
+
+			Method (_ON)
+			{
+				^^SSID = 0x40181558
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF)
+			{
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}

src/mainboard/system76/galp5/acpi/mainboard.asl

@@ -1,9 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "dgpu.asl"
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/galp5/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-power_on_after_fail=Enable
+ime_mode=Enable

src/mainboard/system76/galp5/cmos.layout

@@ -11,12 +11,16 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
-409	2	e	7	power_on_after_fail
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 

src/mainboard/system76/galp5/devicetree.cb

@@ -279,6 +279,13 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "2" # PEG_CLKREQ#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x1, Clock 3 (CARD)

src/mainboard/system76/galp5/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/galp5/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_U4
+#define DGPU_PWR_EN	GPP_U5
+#define DGPU_GC6	GPP_D2
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
@@ -222,4 +228,6 @@ static const struct pad_config gpio_table[] = {
 	//PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
 };
 
+#endif /* __ACPI__ */
+
 #endif /* MAINBOARD_GPIO_H */

src/mainboard/system76/galp5/romstage.c

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "gpio.h"
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
@@ -18,5 +20,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	// Allow memory clocks higher than 2933 MHz
+	mupd->FspmConfig.SaOcSupport = 1;
+
 	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/gaze15/Kconfig

@@ -1,12 +1,14 @@
-if BOARD_SYSTEM76_GAZE15
+if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -17,53 +19,56 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_TPM2
 	select NO_UART_ON_SUPERIO
 	select SOC_INTEL_CANNONLAKE_PCH_H
-	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COFFEELAKE if BOARD_SYSTEM76_GAZE14
+	select SOC_INTEL_COMETLAKE_1 if BOARD_SYSTEM76_GAZE15
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/gaze15"
 
+config VARIANT_DIR
+	default "gaze14" if BOARD_SYSTEM76_GAZE14
+	default "gaze15" if BOARD_SYSTEM76_GAZE15
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
 config MAINBOARD_PART_NUMBER
-	default "gaze15"
+	default "gaze14" if BOARD_SYSTEM76_GAZE14
+	default "gaze15" if BOARD_SYSTEM76_GAZE15
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	string
 	default "Gazelle"
 
 config MAINBOARD_VERSION
-	string
-	default "gaze15"
+	default "gaze14" if BOARD_SYSTEM76_GAZE14
+	default "gaze15" if BOARD_SYSTEM76_GAZE15
 
 config CBFS_SIZE
 	default 0xA00000
 
 config CONSOLE_POST
-	bool
 	default y
 
 config ONBOARD_VGA_IS_PRIMARY
-	bool
 	default y
 
 config UART_FOR_CONSOLE
-	int
 	default 2
 
 config MAX_CPUS
-	int
 	default 16
 
 config DIMM_MAX
 	default 2
 
 config VGA_BIOS_ID
-	string
 	default "8086,9bc4"
 
 config POST_DEVICE
-	bool
 	default n
 
 endif

src/mainboard/system76/gaze15/Kconfig.name

@@ -1,2 +1,5 @@
+config BOARD_SYSTEM76_GAZE14
+	bool "gaze14"
+
 config BOARD_SYSTEM76_GAZE15
 	bool "gaze15"

src/mainboard/system76/gaze15/Makefile.inc

@@ -1,8 +1,10 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 bootblock-y += bootblock.c
-bootblock-y += gpio_early.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += romstage.c
 
 ramstage-y += ramstage.c
-ramstage-y += gpio.c
-ramstage-y += hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/gaze15/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,11 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/gaze15/board_info.txt

@@ -1,7 +1,5 @@
 Vendor name: System76
-Board name: gaze15
 Category: laptop
-Release year: 2020
 ROM package: SOIC-8
 ROM protocol: SPI
 ROM socketed: n

src/mainboard/system76/gaze15/bootblock.c

@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
-#include <gpio.h>
-#include <mainboard/gpio.h>
+#include <variant/gpio.h>
 
 void bootblock_mainboard_early_init(void)
 {
-	mainboard_configure_early_gpios();
+	variant_configure_early_gpios();
 }

src/mainboard/system76/gaze15/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-power_on_after_fail=Enable
+ime_mode=Disable

src/mainboard/system76/gaze15/cmos.layout

@@ -11,12 +11,16 @@ entries
 # RTC_CLK_ALTCENTURY
 400	8	r	0	century
 
-409	2	e	7	power_on_after_fail
+#409	2	e	7	power_on_after_fail
 412	4	e	6	debug_level
+416	1	e	2	ime_mode
 984	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 

src/mainboard/system76/gaze15/devicetree.cb

@@ -22,14 +22,6 @@ chip soc/intel/cannonlake
 	register "enable_c6dram" = "1"
 
 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
-	# Serial I/O
-	register "SerialIoDevMode" = "{
-		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
-		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
-		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
-	}"
-
-
 	# Misc
 	register "AcousticNoiseMitigation" = "1"
 
@@ -60,12 +52,18 @@ chip soc/intel/cannonlake
 	end
 
 	device domain 0 on
-		subsystemid 0x1558 0x8520 inherit
 		device pci 00.0 on  end # Host Bridge
 		device pci 01.0 on      # GPU Port
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
@@ -101,28 +99,10 @@ chip soc/intel/cannonlake
 			end
 		end
 		device pci 14.5 off end # SDCard
-		device pci 15.0 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
-				register "generic.desc" = ""Synaptics Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
-			end
-		end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection
@@ -192,7 +172,7 @@ chip soc/intel/cannonlake
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on # LPC Interface
+		device pci 1f.0 on      # LPC Interface
 			register "gen1_dec" = "0x00040069"
 			register "gen2_dec" = "0x00fc0e01"
 			register "gen3_dec" = "0x00fc0f01"

src/mainboard/system76/gaze15/dsdt.asl

@@ -7,7 +7,7 @@ DefinitionBlock(
 	ACPI_DSDT_REV_2,
 	OEM_ID,
 	ACPI_TABLE_CREATOR,
-	0x20110725	/* OEM revision */
+	0x20110725
 )
 {
 	#include <acpi/dsdt_top.asl>
@@ -18,7 +18,6 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze15/include/variant/gpio.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/gaze15/ramstage.c

@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
 #include <device/device.h>
+#include <variant/gpio.h>
 
-static void init_mainboard(void *chip_info)
+static void mainboard_init(void *chip_info)
 {
-	mainboard_configure_gpios();
+	variant_configure_gpios();
 }
 
 struct chip_operations mainboard_ops = {
-	.init = init_mainboard,
+	.init = mainboard_init,
 };

src/mainboard/system76/gaze15/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/gaze15/variants/gaze14/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze14
+Release year: 2019

src/mainboard/system76/gaze15/variants/gaze14/gpio.c

@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_NC(GPD0, NONE), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, NONE), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7 (crystal input)
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE), // PCH_SLP_WLAN#
+	PAD_NC(GPD10, NONE),
+	PAD_NC(GPD11, NONE), // LAN_DISABLE_N
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+	PAD_CFG_GPI_APIC_HIGH(GPP_A7, NONE, PLTRST), // NC on 1650, INTP_OUT on 1660TI
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_GPI(GPP_A11, NONE, DEEP), // LAN_WAKEUP#
+	PAD_NC(GPP_A12, NONE), // ISH_GP_6_R
+	PAD_NC(GPP_A13, NONE), // SUSWARN#
+	PAD_NC(GPP_A14, NONE), // S4_STATE#
+	PAD_NC(GPP_A15, NONE), // SUS_PWR_ACK#
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE), // 3G_CONFIG2
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // SATA_PWR_EN
+	PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT#
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE), // VRALERTB#
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE), // EXTTS_SNI_DRV1
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
+	PAD_NC(GPP_B11, NONE), // TODO: DDR Voltage select on 1650, NC on 1660TI
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // NO REBOOT strap
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPC/SPI BOOT strap
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI BSSB mode strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
+	PAD_NC(GPP_C3, NONE), // SML0_CLK
+	PAD_NC(GPP_C4, NONE), // SML0_DATA
+	PAD_NC(GPP_C5, NONE),
+	PAD_NC(GPP_C6, NONE), // SMC_CPU_THERM
+	PAD_NC(GPP_C7, NONE), // SMD_CPU_THERM
+	PAD_NC(GPP_C8, NONE),
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // CNVI_DET# on 1650, NC on 1660TI
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // NC on 1650, SMD_7411 on 1660TI
+	PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // NC on 1650, SMC_7411 on 1660TI
+	//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE), // SATAGP0
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATAGP1
+	PAD_NC(GPP_E2, NONE), // SATAGP2
+	PAD_NC(GPP_E3, NONE), // EXTTS_SNI_DRV0
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1
+	PAD_NC(GPP_E6, NONE), // PCH_MUTE#
+	PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE), // SATAGP3
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_NC(GPP_F4, NONE),
+	PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
+	PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
+	PAD_NC(GPP_F7, NONE),
+	PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // BIOS_REC - BIOS RECOVERY ENABLE strap
+	PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
+	PAD_NC(GPP_F12, NONE), // MFG_MODE - Manufacturing mode strap
+	PAD_NC(GPP_F13, NONE), // GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+	//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
+	PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_NC(GPP_H1, NONE),
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE strap
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_NC(GPP_H18, NONE),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE), // DGPU_SELECT#
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // NC on 1650, I_MDP_HPD on 1660TI
+	PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
+	PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
+	PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // NC on 1650, I_MDP_CLK on 1660TI
+	PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // NC on 1650, I_MDP_DATA on 1660TI
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK on 1650, NC on 1660TI
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA on 1650, NC on 1660TI
+	PAD_NC(GPP_I9, NONE),
+	PAD_NC(GPP_I10, NONE),
+	PAD_CFG_GPI(GPP_I11, NONE, DEEP), // H_SKTOCC_N
+	PAD_NC(GPP_I12, NONE),
+	PAD_NC(GPP_I13, NONE),
+	PAD_NC(GPP_I14, NONE),
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_J1, NONE),
+	PAD_NC(GPP_J2, NONE),
+	PAD_NC(GPP_J3, NONE),
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_J10, NONE),
+	PAD_NC(GPP_J11, NONE),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_NC(GPP_K0, NONE),
+	PAD_NC(GPP_K1, NONE),
+	PAD_NC(GPP_K2, NONE),
+	PAD_CFG_GPI_SCI_LOW(GPP_K3, NONE, PLTRST, LEVEL), // XXX: SCI#
+	PAD_NC(GPP_K4, NONE),
+	PAD_NC(GPP_K5, NONE),
+	PAD_CFG_GPI_SCI_LOW(GPP_K6, NONE, DEEP, LEVEL), // XXX: SWI#
+	PAD_NC(GPP_K7, NONE),
+	PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN1
+	PAD_CFG_GPO(GPP_K9, 1, DEEP), // SATA_M2_PWR_EN2
+	PAD_NC(GPP_K10, NONE),
+	PAD_NC(GPP_K11, NONE),
+	PAD_NC(GPP_K12, NONE),
+	PAD_NC(GPP_K13, NONE),
+	PAD_NC(GPP_K14, NONE), // GPP_K_14_GSXDIN / GPP_K14_TEST_R
+	PAD_NC(GPP_K15, NONE),
+	PAD_NC(GPP_K16, NONE),
+	PAD_NC(GPP_K17, NONE),
+	PAD_NC(GPP_K18, NONE),
+	PAD_CFG_GPI(GPP_K19, NONE, DEEP), // XXX: SMI#
+	PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT#
+	PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH
+	PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_NC(GPP_K23, NONE), // DGPU_PRSNT#
+};
+
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/gaze15/variants/gaze14/gpio_early.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
 #include <soc/gpio.h>
+#include <variant/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
@@ -11,7 +11,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
 };
 
-void mainboard_configure_early_gpios(void)
+void variant_configure_early_gpios(void)
 {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }

src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC269VC */
+	0x10ec0269, /* Vendor ID */
+	0x15588560, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588560),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a1103f),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40f00001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb

@@ -0,0 +1,23 @@
+chip soc/intel/cannonlake
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x8550 inherit
+
+		device pci 15.0 on      # I2C0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+	end
+end

src/mainboard/system76/gaze15/variants/gaze15/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze15
+Release year: 2020

src/mainboard/system76/gaze15/variants/gaze15/gpio.c

@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
+#include <variant/gpio.h>
 
 static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
@@ -271,7 +271,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT#
 };
 
-void mainboard_configure_gpios(void)
+void variant_configure_gpios(void)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }

src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb

@@ -0,0 +1,31 @@
+chip soc/intel/cannonlake
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
+	}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x8520 inherit
+
+		device pci 15.0 on      # I2C0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+	end
+end

src/mainboard/system76/gaze16/Kconfig

@@ -0,0 +1,74 @@
+if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE16_3060_B
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_TIGERLAKE_PCH_H
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/gaze16"
+
+config MAINBOARD_PART_NUMBER
+	default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
+	default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
+	default "gaze16-3060-b" if BOARD_SYSTEM76_GAZE16_3060_B
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Gazelle"
+
+config MAINBOARD_VERSION
+	default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
+	default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
+	default "gaze16-3060-b" if BOARD_SYSTEM76_GAZE16_3060_B
+
+config VARIANT_DIR
+	default "3050" if BOARD_SYSTEM76_GAZE16_3050
+	default "3060" if BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_SPD_SIZE
+	default 512
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config UART_FOR_CONSOLE
+	default 2
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif

src/mainboard/system76/gaze16/Kconfig.name

@@ -0,0 +1,8 @@
+config BOARD_SYSTEM76_GAZE16_3050
+	bool "gaze16 3050"
+
+config BOARD_SYSTEM76_GAZE16_3060
+	bool "gaze16 3060"
+
+config BOARD_SYSTEM76_GAZE16_3060_B
+	bool "gaze16 3060-b"

src/mainboard/system76/gaze16/Makefile.inc

@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+bootblock-y += bootblock.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/gaze16/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/gaze16/acpi/dgpu.asl

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.PEG1)
+{
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve)
+		{
+			Offset (0x40),
+			SSID, 32
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0)
+		{
+			Name (_STA, 1)
+
+			Method (_ON)
+			{
+				^^SSID = 0x40181558
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF)
+			{
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}

src/mainboard/system76/gaze16/acpi/mainboard.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "dgpu.asl"
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}

src/mainboard/system76/gaze16/acpi/sleep.asl

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}

src/mainboard/system76/gaze16/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: gaze16
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y