Update amd_blobs

Change-Id: I90b7fd111ec0c57436085fd3f0c977e3cba8910f

.gitmodules

@@ -1,62 +1,62 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = https://review.coreboot.org/blobs.git
+	url = ../blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = https://review.coreboot.org/nvidia-cbootimage.git
+	url = ../nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = https://review.coreboot.org/vboot.git
+	url = ../vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = https://review.coreboot.org/arm-trusted-firmware.git
+	url = ../arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = https://review.coreboot.org/chrome-ec.git
+	url = ../chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = https://review.coreboot.org/libhwbase.git
+	url = ../libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = https://review.coreboot.org/libgfxinit.git
+	url = ../libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = https://review.coreboot.org/fsp.git
+	url = ../fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = https://review.coreboot.org/opensbi.git
+	url = ../opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = https://review.coreboot.org/intel-microcode.git
+	url = ../intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = https://review.coreboot.org/ffs.git
+	url = ../ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = https://review.coreboot.org/amd_blobs
+	url = ../amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = https://review.coreboot.org/cmocka.git
+	url = ../cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = https://review.coreboot.org/qc_blobs.git
+	url = ../qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = https://review.coreboot.org/9esec-security-tooling.git
+	url = ../9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = https://review.coreboot.org/STM
+	url = ../STM
 	branch = stmpe

Documentation/acpi/gpio.md

@@ -84,6 +84,15 @@ the raw Rx gpio value.
 
 ## Implementation Details
 
+ACPI library in coreboot will provide weak definitions for all the
+above functions with error messages indicating that these functions
+are being used. This allows drivers to conditionally make use of GPIOs
+based on device-tree entries or any other config option. It is
+recommended that the SoC code in coreboot should provide
+implementations of all the above functions generating ACPI AML code
+irrespective of them being used in any driver. This allows mainboards
+to use any drivers and take advantage of this common infrastructure.
+
 Platforms are restricted to using Local5, Local6 and Local7 variables
 only in implementations of the above functions. Any AML methods called
 by the above functions do not have any such restrictions on use of

Documentation/mainboard/system76/oryp8.md

@@ -10,14 +10,14 @@
   - ITE IT570E running [System76 EC](https://github.com/system76/ec)
 - Graphics
   - dGPU options
-    - NVIDIA GeForce RTX 3070 (Max-Q)
-    - NVIDIA GeForce RTX 3080 (Max-Q)
+    - NVIDIA GeForce RTX 3070
+    - NVIDIA GeForce RTX 3080
   - eDP options
-    - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
-    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
+    - 15.6" 1920x1080@144Hz LCD
+    - 17.3" 1920x1080@144Hz LCD
+  - 1x HDMI
+  - 1x Mini DisplayPort
+  - 1x DisplayPort over USB-C
 - Memory
   - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
 - Networking
@@ -26,13 +26,13 @@
     - Intel Wi-Fi 6 AX200/AX201
 - Power
   - 180W (19.5V, 9.23A) AC barrel adapter
-    - Lite-On PA-1181-16, using a C5 power cord
+    - Lite-On PA-1181-16
   - 73Wh 3-cell battery
 - Sound
   - Realtek ALC1220 codec
   - TI TAS5825M smart amp
   - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm headphone/microphone jack
   - Combined 3.5mm microphone & S/PDIF jack
   - HDMI, mDP, USB-C DP audio
 - Storage
@@ -41,9 +41,6 @@
 - USB
   - 1x USB Type-C with Thunderbolt 4
   - 3x USB 3.0 Type-A
-- Dimensions
-  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
-  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
 
 ## Flashing coreboot
 

Documentation/releases/coreboot-4.14-relnotes.md

@@ -142,7 +142,7 @@ primarily to serve the needs of the server market.
 
 coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
 This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
+generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
 or the latest generation [2] on market.
 
 With this release, the codebase for multiple generations of Xeon-SP

Documentation/releases/coreboot-4.15-relnotes.md

@@ -1,22 +1,18 @@
-coreboot 4.15
+Upcoming release - coreboot 4.15
 ================================
 
-coreboot 4.15 was released on November 5th, 2021.
+The 4.15 release is planned for November 1st, 2021.
 
-Since 4.14 there have been more than 2597 new commits by more than 219 developers.
+Since 4.14 there have been more than 2448 new commits by more than 219 developers.
 Of these, over 73 contributed to coreboot for the first time.
 
 Welcome to the project!
 
+
+
 Thank you to all the developers who continue to make coreboot the
 great open source firmware project that it is.
 
-Important Announcement
-----------------------
-We are going to be changing the cadence from every 6 months, to every 3 months.
-That means the 4.16 release will be coming in February, 2022.
-
-
 New mainboards
 --------------
 * Asus p8h61-m_pro_cm6630
@@ -27,19 +23,11 @@ New mainboards
 * Siemens mc_ehl
 * SuperMicro x9sae
 * System76 addw1
-* System76 addw2
-* System76 bonw14
 * System76 darp6
 * System76 darp7
-* System76 galp2
-* System76 galp3
-* System76 galp3-b
 * System76 galp4
 * System76 galp5
-* System76 gaze14
 * System76 lemp10
-* System76 oryp7
-* System76 oryp8
 
 Removed mainboards
 ------------------

Documentation/releases/coreboot-4.16-relnotes.md

@@ -1,10 +1,7 @@
 Upcoming release - coreboot 4.16
 ================================
 
-The 4.16 release is planned for February, 2022.
-
-We are increasing the frequency of releases in order to enable others to release quarterly on
-a fresher version of coreboot.
+The 4.16 release is planned for May 2022.
 
 Update this document with changes that should be in the release notes.
 

Documentation/releases/index.md

@@ -27,4 +27,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
+* [4.16 - May 2022](coreboot-4.16-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -31,7 +31,6 @@
 - Zako (HP Chromebox G1)
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
-- Tomato
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -67,68 +66,60 @@
 - Nefario
 - Rainier
 - Guybrush
-- Nipperkin
-- Dewatt
-- Akemi (IdeaPad Flex 5/5i Chromebook)
-- Dratini (HP Pro c640 Chromebook)
+- Akemi
+- Dratini
 - Duffy Legacy (32MB)
-- Duffy (ASUS Chromebox 4)
-- Faffy (ASUS Fanless Chromebox)
+- Duffy
+- Faffy
 - Hatch
-- Jinlon (HP Elite c1030 Chromebook)
+- Jinlon
 - Kaisa Legacy (32MB)
-- Kaisa (Acer Chromebox CXI4)
-- Kohaku (Samsung Galaxy Chromebook)
-- Kindred (Acer Chromebook 712)
-- Helios (ASUS Chromebook Flip C436FA)
+- Kaisa
+- Kohaku
+- Kindred
+- Helios
 - Mushu
 - Palkia
-- Nightfury (Samsung Galaxy Chromebook 2)
-- Noibat (HP Chromebox G3)
+- Nightfury
+- Noibat
 - Puff
 - Helios_Diskswap
 - Stryke
-- Wyvern (CTL Chromebox CBx2)
+- Wyvern
 - Dooly
 - Ambassador
 - Genesis
-- Scout
-- Moonbuggy
 - Herobrine
-- Senor
-- Piglin
-- Hoglin
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
 - Tidus (Lenovo ThinkCentre Chromebox)
-- Aleena/Kasumi (Acer Chromebook  315 (CB315-2H), 311 (C721) / Spin 311 (R721T))
-- Barla/Careena (HP Chromebook 11A G6/G8 EE, 14A G5/G6)
+- Aleena
+- Careena
 - Grunt
-- Liara (Lenovo 14e Chromebook, Chromebook S345-14)
+- Liara
 - Nuwani
-- Treeya (Lenovo 100e/300e Gen2 AMD)
+- Treeya
 - Kukui
-- Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook)
-- Kodama (Lenovo 10e Chromebook Tablet)
+- Krane
+- Kodama
 - Kakadu
 - Flapjack
 - Katsu
 - Jacuzzi
-- Juniper (Acer Chromebook Spin 311 (CP311-3H))
+- Juniper
 - Kappa
-- Damu (ASUS Chromebook Flip CM3 (CM3200))
+- Damu
 - Cerise
 - Stern
 - Willow
-- Esche (HP Chromebook 11MK G9 EE)
-- Burnet (HP Chromebook x360 11MK G3 EE)
+- Esche
+- Burnet
 - Fennel
 - Cozmo
 - Makomo
-- Munna
-- Pico
 - Link (Google Chromebook Pixel (2013))
+- Mancomb
 - Mistral
 - Nyan
 - Nyan Big (Acer Chromebook 13 (CB5-311))
@@ -141,7 +132,7 @@
 - Atlas (Google Pixelbook Go)
 - Poppy
 - Nami
-- Nautilus (Samsung Chromebook Plus V2, V2 LTE)
+- Nautilus (Samsung Chromebook Plus (V2 / LTE))
 - Nocturne (Google Pixel Slate)
 - Rammus (Asus Chromebook C425, Flip C433, Flip C434)
 - Soraka (HP Chromebook x2)
@@ -167,8 +158,8 @@
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Nasher
 - Coral
-- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
-- Sarien (Dell Latitude 5400 Chromebook Enterprise)
+- Arcada
+- Sarien
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -186,8 +177,8 @@
 - Pazquel
 - Pompom
 - Quackingstick
-- Wormdingler
 - Trogdor
+- Wormdingler
 - Veyron_Jaq (Haier Chromebook 11)
 - Veyron_Jerry (Hisense Chromebook 11)
 - Veyron_Mighty (Haier Chromebook 11(edu))
@@ -196,15 +187,15 @@
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
 - Dalboz
-- Vilboz (Lenovo 100e/300e Gen3 AMD)
-- Ezkinil (Acer Chromebook Spin 514)
-- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
+- Vilboz
+- Ezkinil
+- Morphius
 - Trembyle
-- Berknip (HP Pro c645 Chromebook Enterprise)
-- Woomax (ASUS Chromebook Flip CM5)
-- Dirinboz (HP Chromebook 14a-nd0097nr)
+- Berknip
+- Woomax
+- Dirinboz
 - Shuboz
-- Gumboz (HP Chromebook x360 14a)
+- Gumboz
 
 ## HP
 - Z220 SFF Workstation
@@ -212,7 +203,6 @@
 ## Intel
 - Alderlake-P RVP
 - Alderlake-P RVP with Chrome EC
-- Alderlake-P RVP with Microchip EC
 - Alderlake-M RVP
 - Alderlake-M RVP with Chrome EC
 - Basking Ridge CRB

payloads/external/Makefile.inc

@@ -146,7 +146,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
-		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
+		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
 		CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \

payloads/external/tianocore/Makefile

@@ -9,7 +9,7 @@ project_git_repo=https://github.com/mrchromebox/edk2
 project_git_branch=uefipayload_202107
 upstream_git_repo=https://github.com/tianocore/edk2
 
-build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
 
 ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
 project_git_branch=coreboot_fb

payloads/libpayload/include/mock/arch/io.h

@@ -26,21 +26,4 @@ void write16(volatile void *addr, uint16_t val);
 void write32(volatile void *addr, uint32_t val);
 void write64(volatile void *addr, uint64_t val);
 
-/* x86 I/O functions */
-unsigned int inl(int port);
-unsigned short inw(int port);
-unsigned char inb(int port);
-
-void outl(unsigned int val, int port);
-void outw(unsigned short val, int port);
-void outb(unsigned char val, int port);
-
-void outsl(int port, const void *addr, unsigned long count);
-void outsw(int port, const void *addr, unsigned long count);
-void outsb(int port, const void *addr, unsigned long count);
-
-void insl(int port, void *addr, unsigned long count);
-void insw(int port, void *addr, unsigned long count);
-void insb(int port, void *addr, unsigned long count);
-
 #endif /* _ARCH_IO_H */

payloads/libpayload/tests/drivers/Makefile.inc

@@ -6,3 +6,4 @@ speaker-test-srcs += tests/drivers/speaker-test.c
 speaker-test-mocks += inb
 speaker-test-mocks += outb
 speaker-test-mocks += arch_ndelay
+speaker-test-cflags += -include $(testsrc)/include/mocks/x86_io.h

payloads/libpayload/tests/drivers/speaker-test.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <libpayload.h>
+#include <mocks/x86_io.h>
 
 /* Include source to gain access to private defines */
 #include "../drivers/speaker.c"

payloads/libpayload/tests/include/mocks/x86_io.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef TESTS_MOCKS_X86_IO_H_
+#define TESTS_MOCKS_X86_IO_H_
+
+unsigned int inl(int port);
+
+unsigned short inw(int port);
+
+unsigned char inb(int port);
+
+void outl(unsigned int val, int port);
+
+void outw(unsigned short val, int port);
+
+void outb(unsigned char val, int port);
+
+void outsl(int port, const void *addr, unsigned long count);
+
+void outsw(int port, const void *addr, unsigned long count);
+
+void outsb(int port, const void *addr, unsigned long count);
+
+void insl(int port, void *addr, unsigned long count);
+
+void insw(int port, void *addr, unsigned long count);
+
+void insb(int port, void *addr, unsigned long count);
+
+#endif

spd/lp5/memory_parts.json

@@ -1,34 +0,0 @@
-{
-    "parts": [
-        {
-            "name": "MT62F512M32D2DR-031 WT:B",
-            "attribs": {
-                "densityPerDieGb": 8,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 6400
-            }
-        },
-        {
-            "name": "MT62F1G32D4DR-031 WT:B",
-            "attribs": {
-                "densityPerDieGb": 8,
-                "diesPerPackage": 4,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 2,
-                "speedMbps": 6400
-            }
-        },
-        {
-            "name": "H9JCNNNCP3MLYR-N6E",
-            "attribs": {
-                "densityPerDieGb": 8,
-                "diesPerPackage": 4,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 2,
-                "speedMbps": 6400
-            }
-        }
-    ]
-}

spd/lp5/platforms_manifest.generated.txt

@@ -1,4 +0,0 @@
-# Generated by:
-# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
-
-ADL,set-0

spd/lp5/set-0/parts_spd_manifest.generated.txt

@@ -1,6 +0,0 @@
-# Generated by:
-# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
-
-MT62F512M32D2DR-031 WT:B,spd-1.hex
-MT62F1G32D4DR-031 WT:B,spd-2.hex
-H9JCNNNCP3MLYR-N6E,spd-2.hex

spd/lp5/set-0/spd-1.hex

@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A 95 08 00 00 00 00 02 01 00 00
-00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-0/spd-2.hex

@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A B5 08 00 00 00 00 0A 01 00 00
-00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-0/spd-empty.hex

@@ -1,32 +0,0 @@
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/Kconfig

@@ -395,6 +395,16 @@ config FW_CONFIG
 	  Enable support for probing devices with fw_config.  This is a simple
 	  bitmask broken into fields and options for probing.
 
+config FW_CONFIG_SOURCE_CBFS
+	bool "Obtain Firmware Configuration value from CBFS"
+	depends on FW_CONFIG
+	default n
+	help
+	  With this option enabled coreboot will look for the 32bit firmware
+	  configuration value in CBFS at the selected prefix with the file name
+	  "fw_config".  This option will override other sources and allow the
+	  local image to preempt the mainboard selected source.
+
 config FW_CONFIG_SOURCE_CHROMEEC_CBI
 	bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
 	depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
@@ -405,27 +415,6 @@ config FW_CONFIG_SOURCE_CHROMEEC_CBI
 	  is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
 	  found in CBFS.
 
-config FW_CONFIG_SOURCE_CBFS
-	bool "Obtain Firmware Configuration value from CBFS"
-	depends on FW_CONFIG
-	default n
-	help
-	  With this option enabled coreboot will look for the 32bit firmware
-	  configuration value in CBFS at the selected prefix with the file name
-	  "fw_config".  This option will override other sources and allow the
-	  local image to preempt the mainboard selected source and can be used as
-	  FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option.
-
-config FW_CONFIG_SOURCE_VPD
-	bool "Obtain Firmware Configuration value from VPD"
-	depends on FW_CONFIG && VPD
-	default n
-	help
-	  With this option enabled coreboot will look for the 32bit firmware
-	  configuration value in VPD key name "fw_config".  This option will
-	  override other sources and allow the local image to preempt the mainboard
-	  selected source and can be used for other FW_CONFIG_SOURCEs fallback option.
-
 config HAVE_RAMPAYLOAD
 	bool
 
@@ -688,12 +677,12 @@ config TIMER_QUEUE
 
 config COOP_MULTITASKING
 	def_bool n
-	select TIMER_QUEUE
-	depends on ARCH_X86 && CPU_INFO_V2
+	depends on TIMER_QUEUE && ARCH_X86 && CPU_INFO_V2
 	help
 	  Cooperative multitasking allows callbacks to be multiplexed on the
-	  main thread. With this enabled it allows for multiple execution paths
-	  to take place when they have udelay() calls within their code.
+	  main thread of ramstage. With this enabled it allows for multiple
+	  execution paths to take place when they have udelay() calls within
+	  their code.
 
 config NUM_THREADS
 	int
@@ -796,21 +785,6 @@ config GENERATE_SMBIOS_TABLES
 
 	  If unsure, say Y.
 
-config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE
-	bool
-	depends on ARCH_X86
-	help
-	  If enabled, only generate SMBIOS Type 41 entries for PCI devices in
-	  the devicetree for which Type 41 information is provided, e.g. with
-	  the `smbios_dev_info` devicetree syntax. This is useful to manually
-	  assign specific instance IDs to onboard devices irrespective of the
-	  device traversal order. It is assumed that instance IDs for devices
-	  of the same class are unique.
-	  When disabled, coreboot autogenerates SMBIOS Type 41 entries for all
-	  appropriate PCI devices in the devicetree. Instance IDs are assigned
-	  successive numbers from a monotonically increasing counter, with one
-	  counter for each device class.
-
 config SMBIOS_PROVIDED_BY_MOBO
 	bool
 	default n
@@ -1179,7 +1153,7 @@ config DEBUG_INTEL_ME
 endif
 
 config DEBUG_FUNC
-	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
+	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
 	default n
 	help
 	  This option enables additional function entry and exit debug messages

src/acpi/acpi.c

@@ -266,8 +266,7 @@ void acpi_create_madt(acpi_madt_t *madt)
 static unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-			CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0,
-			CONFIG_ECAM_MMCONF_BUS_NUMBER - 1);
+			CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
 	return current;
 }
 
@@ -292,7 +291,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
 	header->length = sizeof(acpi_mcfg_t);
 	header->revision = get_acpi_table_revision(MCFG);
 
-	if (CONFIG(ECAM_MMCONF_SUPPORT))
+	if (CONFIG(MMCONF_SUPPORT))
 		current = acpi_fill_mcfg(current);
 
 	/* (Re)calculate length and checksum. */
@@ -1249,7 +1248,7 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
 		printk(BIOS_INFO, "%s: Device not enabled\n", __func__);
 		return current;
 	}
-	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_ERR, "%s: Unable to find resource for %s\n",
 		       __func__, dev_path(dev));

src/acpi/dsdt_top.asl

@@ -31,13 +31,13 @@ Method (_PIC, 1)
 	PICM = Arg0
 }
 
-#if CONFIG(ECAM_MMCONF_SUPPORT)
+#if CONFIG(MMCONF_SUPPORT)
 Scope(\_SB) {
 	/* Base address of PCIe config space */
-	Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
 
 	/* Length of PCIe config space, 1MB each bus */
-	Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
+	Name(PCLN, CONFIG_MMCONF_LENGTH)
 
 	/* PCIe Configuration Space */
 	OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */

src/arch/arm/include/armv4/arch/smp/spinlock.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ARCH_SMP_SPINLOCK_H
+#define _ARCH_SMP_SPINLOCK_H
+
+#define DECLARE_SPIN_LOCK(x)
+#define spin_is_locked(lock)	0
+#define spin_unlock_wait(lock)	do {} while (0)
+#define spin_lock(lock)		do {} while (0)
+#define spin_unlock(lock)	do {} while (0)
+
+#include <smp/node.h>
+#define boot_cpu() 1
+
+#endif

src/arch/x86/Makefile.inc

@@ -43,13 +43,6 @@ cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom
 pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE))
 pci$(stripped_vgabios_dgpu_id).rom-type := optionrom
 
-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-pci$(stripped_vgabios_id).rom-align := 64
-pci$(stripped_second_vbios_id).rom-align := 64
-pci$(stripped_vgabios_dgpu_id).rom-align := 64
-endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
-
 ###############################################################################
 # common support for early assembly includes
 ###############################################################################

src/arch/x86/include/arch/pci_io_cfg.h

@@ -69,7 +69,7 @@ void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
 	outl(value, 0xCFC);
 }
 
-#if !CONFIG(ECAM_MMCONF_SUPPORT)
+#if !CONFIG(MMCONF_SUPPORT)
 
 /* Avoid name collisions as different stages have different signature
  * for these functions. The _s_ stands for simple, fundamental IO or

src/arch/x86/include/arch/pci_ops.h

@@ -4,8 +4,6 @@
 #define ARCH_I386_PCI_OPS_H
 
 #include <arch/pci_io_cfg.h>
-#if CONFIG(ECAM_MMCONF_SUPPORT)
 #include <device/pci_mmio_cfg.h>
-#endif
 
 #endif /* ARCH_I386_PCI_OPS_H */

src/arch/x86/include/arch/smp/spinlock.h

@@ -15,6 +15,10 @@ typedef struct {
 
 #define SPIN_LOCK_UNLOCKED { 1 }
 
+#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE
+
+#if STAGE_HAS_SPINLOCKS
+
 #define DECLARE_SPIN_LOCK(x)	\
 	static spinlock_t x = SPIN_LOCK_UNLOCKED;
 
@@ -67,4 +71,14 @@ static __always_inline void spin_unlock(spinlock_t *lock)
 		: "=m" (lock->lock) : : "memory");
 }
 
+#else
+
+#define DECLARE_SPIN_LOCK(x)
+#define spin_is_locked(lock)	0
+#define spin_unlock_wait(lock)	do {} while (0)
+#define spin_lock(lock)		do {} while (0)
+#define spin_unlock(lock)	do {} while (0)
+
+#endif
+
 #endif /* ARCH_SMP_SPINLOCK_H */

src/arch/x86/smbios.c

@@ -224,9 +224,6 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 					 unsigned long *current, int *handle,
 					 int type16_handle)
 {
-	struct spd_info info;
-	get_spd_info(dimm->ddr_type, dimm->mod_type, &info);
-
 	struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
 						     sizeof(*t), *handle);
 
@@ -247,7 +244,24 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	}
 	t->data_width = 8 * (1 << (dimm->bus_width & 0x7));
 	t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3);
-	t->form_factor = info.form_factor;
+
+	switch (dimm->mod_type) {
+	case SPD_RDIMM:
+	case SPD_MINI_RDIMM:
+		t->form_factor = MEMORY_FORMFACTOR_RIMM;
+		break;
+	case SPD_UDIMM:
+	case SPD_MICRO_DIMM:
+	case SPD_MINI_UDIMM:
+		t->form_factor = MEMORY_FORMFACTOR_DIMM;
+		break;
+	case SPD_SODIMM:
+		t->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		break;
+	default:
+		t->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
+		break;
+	}
 
 	smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t);
 	smbios_fill_dimm_serial_number(dimm, t);
@@ -264,8 +278,19 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	t->maximum_voltage = dimm->vdd_voltage;
 
 	/* Fill in type detail */
-	t->type_detail = info.type_detail;
-
+	switch (dimm->mod_type) {
+	case SPD_RDIMM:
+	case SPD_MINI_RDIMM:
+		t->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case SPD_UDIMM:
+	case SPD_MINI_UDIMM:
+		t->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	default:
+		t->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	}
 	/* Synchronous = 1 */
 	t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
 	/* no handle for error information */
@@ -1152,55 +1177,30 @@ static u8 smbios_get_device_type_from_dev(struct device *dev)
 	}
 }
 
-static bool smbios_get_type41_instance_id(struct device *dev, u8 device_type, u8 *instance_id)
-{
-#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
-	*instance_id = dev->smbios_instance_id;
-	return dev->smbios_instance_id_valid;
-#else
-	static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {};
-
-	if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
-	    device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
-		return false;
-
-	if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
-		return false;
-
-	*instance_id = type41_inst_cnt[device_type]++;
-	return true;
-#endif
-}
-
-static const char *smbios_get_type41_refdes(struct device *dev)
-{
-#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
-	if (dev->smbios_refdes)
-		return dev->smbios_refdes;
-#endif
-	return get_pci_subclass_name(dev);
-}
-
 static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
 					       unsigned long *current)
 {
+	static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {};
+
 	if (dev->path.type != DEVICE_PATH_PCI)
 		return 0;
 	if (!dev->on_mainboard)
 		return 0;
 
-	const u8 device_type = smbios_get_device_type_from_dev(dev);
+	u8 device_type = smbios_get_device_type_from_dev(dev);
 
-	u8 instance_id;
-
-	if (!smbios_get_type41_instance_id(dev, device_type, &instance_id))
+	if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
+	    device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
 		return 0;
 
-	const char *name = smbios_get_type41_refdes(dev);
+	if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
+		return 0;
+
+	const char *name = get_pci_subclass_name(dev);
 
 	return smbios_write_type41(current, handle,
 					name, // name
-					instance_id, // inst
+					type41_inst_cnt[device_type]++, // inst
 					0, // segment
 					dev->bus->secondary, //bus
 					PCI_SLOT(dev->path.pci.devfn), // device

src/commonlib/Makefile.inc

@@ -22,9 +22,6 @@ smm-y += region.c
 postcar-y += region.c
 
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c
-ifeq ($(CONFIG_FSP_M_XIP),)
-romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
-endif
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
 
 bootblock-y += cbfs.c

src/commonlib/include/commonlib/mem_pool.h

@@ -3,7 +3,6 @@
 #ifndef _MEM_POOL_H_
 #define _MEM_POOL_H_
 
-#include <assert.h>
 #include <stddef.h>
 #include <stdint.h>
 
@@ -17,23 +16,23 @@
  * were chosen to optimize for the CBFS cache case which may need two buffers
  * to map a single compressed file, and will free them in reverse order.)
  *
- * You must ensure the backing buffer is 'alignment' aligned.
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
  */
 
 struct mem_pool {
 	uint8_t *buf;
 	size_t size;
-	size_t alignment;
 	uint8_t *last_alloc;
 	uint8_t *second_to_last_alloc;
 	size_t free_offset;
 };
 
-#define MEM_POOL_INIT(buf_, size_, alignment_)	\
+#define MEM_POOL_INIT(buf_, size_)		\
 	{					\
 		.buf = (buf_),			\
 		.size = (size_),		\
-		.alignment = (alignment_),	\
 		.last_alloc = NULL,		\
 		.second_to_last_alloc = NULL,	\
 		.free_offset = 0,		\
@@ -47,15 +46,10 @@ static inline void mem_pool_reset(struct mem_pool *mp)
 }
 
 /* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz,
-					 size_t alignment)
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
 {
-	assert(alignment);
-	assert((uintptr_t)buf % alignment == 0);
-
 	mp->buf = buf;
 	mp->size = sz;
-	mp->alignment = alignment;
 	mem_pool_reset(mp);
 }
 

src/commonlib/include/commonlib/timestamp_serialized.h

@@ -56,8 +56,6 @@ enum timestamp_id {
 	TS_DELAY_END = 111,
 	TS_READ_UCODE_START = 112,
 	TS_READ_UCODE_END = 113,
-	TS_ELOG_INIT_START = 114,
-	TS_ELOG_INIT_END = 115,
 
 	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
 	TS_START_COPYVER = 501,
@@ -202,8 +200,6 @@ static const struct timestamp_id_to_name {
 	{ TS_DELAY_END,		"Forced delay end" },
 	{ TS_READ_UCODE_START,	"started reading uCode" },
 	{ TS_READ_UCODE_END,	"finished reading uCode" },
-	{ TS_ELOG_INIT_START,	"started elog init" },
-	{ TS_ELOG_INIT_END,	"finished elog init" },
 
 	{ TS_START_COPYVER,	"starting to load verstage" },
 	{ TS_END_COPYVER,	"finished loading verstage" },

src/commonlib/mem_pool.c

@@ -7,11 +7,8 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
 {
 	void *p;
 
-	if (mp->alignment == 0)
-		return NULL;
-
-	/* We assume that mp->buf started mp->alignment aligned */
-	sz = ALIGN_UP(sz, mp->alignment);
+	/* Make all allocations be at least 8 byte aligned. */
+	sz = ALIGN_UP(sz, 8);
 
 	/* Determine if any space available. */
 	if ((mp->size - mp->free_offset) < sz)

src/cpu/amd/agesa/family14/Kconfig

@@ -3,3 +3,11 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_AGESA_FAMILY14
+
+config CPU_ADDR_BITS
+	int
+	default 36
+
+endif

src/cpu/amd/agesa/family14/model_14_init.c

@@ -25,7 +25,9 @@ static void model_14_init(struct device *dev)
 	disable_cache();
 	/*
 	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
-	 * by coreboot.
+	 * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.
+	 * TODO:
+	 * amd_setup_mtrrs();
 	 */
 
 	/* Enable access to AMD RdDram and WrDram extension bits */

src/cpu/amd/agesa/family15tn/Kconfig

@@ -4,3 +4,11 @@ config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select IDS_OPTIONS_HOOKED_UP
 	select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_AGESA_FAMILY15_TN
+
+config CPU_ADDR_BITS
+	int
+	default 48
+
+endif

src/cpu/amd/agesa/family15tn/model_15_init.c

@@ -25,10 +25,9 @@ static void model_15_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	/*
-	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
-	 * by coreboot.
-	 */
+	//enable_cache();
+	//amd_setup_mtrrs();
+	//x86_mtrr_check();
 	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);

src/cpu/amd/agesa/family16kb/Kconfig

@@ -6,6 +6,10 @@ config CPU_AMD_AGESA_FAMILY16_KB
 
 if CPU_AMD_AGESA_FAMILY16_KB
 
+config CPU_ADDR_BITS
+	int
+	default 40
+
 config FORCE_AM1_SOCKET_SUPPORT
 	bool
 	default n

src/cpu/amd/agesa/family16kb/model_16_init.c

@@ -23,10 +23,9 @@ static void model_16_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	/*
-	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
-	 * by coreboot.
-	 */
+	//enable_cache();
+	//amd_setup_mtrrs();
+	//x86_mtrr_check();
 	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);

src/cpu/amd/mtrr/amd_mtrr.c

@@ -3,11 +3,72 @@
 #include <amdblocks/biosram.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <arch/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/x86/cache.h>
+
+/* These will likely move to some device node or cbmem. */
+static uint64_t amd_topmem = 0;
+static uint64_t amd_topmem2 = 0;
+
+uint64_t bsp_topmem(void)
+{
+	return amd_topmem;
+}
+
+uint64_t bsp_topmem2(void)
+{
+	return amd_topmem2;
+}
+
+/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers,
+ * so they can be distributed to AP CPUs. Not strictly MTRRs,
+ * but this is not that bad a place to have this code.
+ */
+void setup_bsp_ramtop(void)
+{
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk(BIOS_INFO,
+	    "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk(BIOS_INFO,
+	    "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	amd_topmem = (uint64_t) msr.hi << 32 | msr.lo;
+	amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo;
+}
+
+static void setup_ap_ramtop(void)
+{
+	msr_t msr;
+	uint64_t v;
+
+	v = bsp_topmem();
+	if (!v)
+		return;
+
+	msr.hi = v >> 32;
+	msr.lo = (uint32_t) v;
+	wrmsr(TOP_MEM, msr);
+
+	v = bsp_topmem2();
+	msr.hi = v >> 32;
+	msr.lo = (uint32_t) v;
+	wrmsr(TOP_MEM2, msr);
+}
 
 void add_uma_resource_below_tolm(struct device *nb, int idx)
 {
-	uint32_t topmem = amd_topmem();
+	uint32_t topmem = bsp_topmem();
 	uint32_t top_of_cacheable = restore_top_of_low_cacheable();
 
 	if (top_of_cacheable == topmem)
@@ -21,3 +82,79 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
 
 	uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
 }
+
+void amd_setup_mtrrs(void)
+{
+	unsigned long address_bits;
+	unsigned long i;
+	msr_t msr, sys_cfg;
+	// Test if this CPU is a Fam 0Fh rev. F or later
+	const int cpu_id = cpuid_eax(0x80000001);
+	printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
+	const int has_tom2wb =
+		// ExtendedFamily > 0
+		 (((cpu_id>>20)&0xf) > 0) ||
+		// Family == 0F
+		((((cpu_id>>8)&0xf) == 0xf) &&
+		// Rev>=F deduced from rev tables
+		 (((cpu_id>>16)&0xf) >= 0x4));
+	if (has_tom2wb)
+		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
+
+	/* Enable the access to AMD RdDram and WrDram extension bits */
+	disable_cache();
+	sys_cfg = rdmsr(SYSCFG_MSR);
+	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, sys_cfg);
+	enable_cache();
+
+	/* Setup fixed MTRRs, but do not enable them just yet. */
+	x86_setup_fixed_mtrrs_no_enable();
+
+	disable_cache();
+
+	setup_ap_ramtop();
+
+	/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */
+	sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
+	if (bsp_topmem2() > (uint64_t)1 << 32) {
+		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
+		if (has_tom2wb)
+			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
+	}
+
+	/* zero the IORR's before we enable to prevent
+	 * undefined side effects.
+	 */
+	msr.lo = msr.hi = 0;
+	for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++)
+		wrmsr(i, msr);
+
+	/* Enable Variable Mtrrs
+	 * Enable the RdMem and WrMem bits in the fixed mtrrs.
+	 * Disable access to the RdMem and WrMem in the fixed mtrr.
+	 */
+	sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn;
+	sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, sys_cfg);
+
+	enable_fixed_mtrr();
+
+	enable_cache();
+
+	//K8 could be 40, and GH could be 48
+	address_bits = CONFIG_CPU_ADDR_BITS;
+
+	/* AMD specific cpuid function to query number of address bits */
+	if (cpuid_eax(0x80000000) >= 0x80000008)
+		address_bits = cpuid_eax(0x80000008) & 0xff;
+
+	/* Now that I have mapped what is memory and what is not
+	 * Set up the mtrrs so we can cache the memory.
+	 */
+
+	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need
+	// variable MTRR to span memory above 4GB
+	// Lower revisions K8 need variable MTRR over 4GB
+	x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
+}

src/cpu/amd/pi/00730F01/Kconfig

@@ -5,3 +5,11 @@ config CPU_AMD_PI_00730F01
 	select X86_AMD_FIXED_MTRRS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select MICROCODE_BLOB_UNDISCLOSED
+
+if CPU_AMD_PI_00730F01
+
+config CPU_ADDR_BITS
+	int
+	default 40
+
+endif

src/cpu/intel/haswell/haswell_init.c

@@ -588,8 +588,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	unsigned int num_threads;
-	unsigned int num_cores;
+	int num_threads;
+	int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;

src/cpu/intel/model_1067x/mp_init.c

@@ -23,7 +23,7 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	const struct cpuid_result cpuid1 = cpuid(1);
-	const unsigned int cores = (cpuid1.ebx >> 16) & 0xf;
+	const char cores = (cpuid1.ebx >> 16) & 0xf;
 
 	printk(BIOS_DEBUG, "CPU has %u cores.\n", cores);
 

src/cpu/intel/model_106cx/Kconfig

@@ -11,3 +11,11 @@ config CPU_INTEL_MODEL_106CX
 	select SERIALIZED_SMM_INITIALIZATION
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
+
+if CPU_INTEL_MODEL_106CX
+
+config CPU_ADDR_BITS
+	int
+	default 32
+
+endif

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -124,8 +124,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	unsigned int num_threads;
-	unsigned int num_cores;
+	int num_threads;
+	int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -380,8 +380,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	unsigned int num_threads;
-	unsigned int num_cores;
+	int num_threads;
+	int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;

src/cpu/x86/Kconfig

@@ -90,6 +90,10 @@ config SETUP_XIP_CACHE
 	  non-eviction mode and therefore need to be careful to avoid
 	  eviction.
 
+config CPU_ADDR_BITS
+	int
+	default 36
+
 config LOGICAL_CPUS
 	bool
 	default y

src/device/Kconfig

@@ -499,21 +499,13 @@ config PCI
 
 if PCI
 
-config NO_ECAM_MMCONF_SUPPORT
+config NO_MMCONF_SUPPORT
 	bool
 	default n
-	help
-	  Disable the use of the Enhanced Configuration
-	  Access mechanism (ECAM) method for accessing PCI config
-	  address space.
 
-config ECAM_MMCONF_SUPPORT
+config MMCONF_SUPPORT
 	bool
-	default !NO_ECAM_MMCONF_SUPPORT
-	help
-	  Enable the use of the Enhanced Configuration
-	  Access mechanism (ECAM) method for accessing PCI config
-	  address space.
+	default !NO_MMCONF_SUPPORT
 
 config PCIX_PLUGIN_SUPPORT
 	bool
@@ -548,20 +540,20 @@ config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
 
-config ECAM_MMCONF_BASE_ADDRESS
+config MMCONF_BASE_ADDRESS
 	hex
-	depends on ECAM_MMCONF_SUPPORT
+	depends on MMCONF_SUPPORT
 
-config ECAM_MMCONF_BUS_NUMBER
+config MMCONF_BUS_NUMBER
 	int
-	depends on ECAM_MMCONF_SUPPORT
+	depends on MMCONF_SUPPORT
 
-config ECAM_MMCONF_LENGTH
+config MMCONF_LENGTH
 	hex
-	depends on ECAM_MMCONF_SUPPORT
-	default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
-	default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
-	default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
+	depends on MMCONF_SUPPORT
+	default 0x04000000 if MMCONF_BUS_NUMBER = 64
+	default 0x08000000 if MMCONF_BUS_NUMBER = 128
+	default 0x10000000 if MMCONF_BUS_NUMBER = 256
 	default 0x0
 
 config PCI_ALLOW_BUS_MASTER
@@ -627,7 +619,7 @@ config PCIEXP_CLK_PM
 config PCIEXP_L1_SUB_STATE
 	prompt "Enable PCIe ASPM L1 SubState"
 	bool
-	depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
+	depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT)
 	default n
 	help
 	  Detect and enable ASPM on PCIe links.
@@ -643,8 +635,8 @@ if PCIEXP_HOTPLUG
 
 config PCIEXP_HOTPLUG_BUSES
 	int "PCI Express Hotplug Buses"
-	default  8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <=  64
-	default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
+	default  8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <=  64
+	default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128
 	default 32
 	help
 	  This is the number of buses allocated for hotplug PCI express

src/device/azalia_device.c

@@ -227,7 +227,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 {
 }
 
-void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
+static void codec_init(struct device *dev, u8 *base, int addr)
 {
 	u32 reg32;
 	const u32 *verb;
@@ -252,7 +252,7 @@ void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table
 	/* 2 */
 	reg32 = read32(base + HDA_IR_REG);
 	printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
-	verb_size = azalia_find_verb(verb_table, verb_table_bytes, reg32, &verb);
+	verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
 
 	if (!verb_size) {
 		printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
@@ -261,22 +261,19 @@ void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table
 	printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
 
 	/* 3 */
-	const int rc = azalia_program_verb_table(base, verb, verb_size);
-	if (rc < 0)
-		printk(BIOS_DEBUG, "azalia_audio: verb not loaded.\n");
-	else
-		printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
+	azalia_program_verb_table(base, verb, verb_size);
+	printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
 
 	mainboard_azalia_program_runtime_verbs(base, reg32);
 }
 
-void azalia_codecs_init(u8 *base, u16 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u16 codec_mask)
 {
 	int i;
 
 	for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
 		if (codec_mask & (1 << i))
-			azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
+			codec_init(dev, base, i);
 	}
 
 	azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
@@ -288,7 +285,7 @@ void azalia_audio_init(struct device *dev)
 	struct resource *res;
 	u16 codec_mask;
 
-	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
@@ -300,7 +297,7 @@ void azalia_audio_init(struct device *dev)
 
 	if (codec_mask) {
 		printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
-		azalia_codecs_init(base, codec_mask);
+		codecs_init(dev, base, codec_mask);
 	}
 }
 

src/device/device_util.c

@@ -857,8 +857,8 @@ void fixed_io_resource(struct device *dev, unsigned long index,
 void mmconf_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource = new_resource(dev, index);
-	resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
-	resource->size = CONFIG_ECAM_MMCONF_LENGTH;
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_LENGTH;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 

src/device/dram/ddr3.c

@@ -545,19 +545,19 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 
 		switch (info->dimm_type) {
 		case SPD_DDR3_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = DDR3_SPD_SODIMM;
+			dimm->mod_type = SPD_SODIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
-			dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
+			dimm->mod_type = SPD_72B_SO_CDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
+			dimm->mod_type = SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UDIMM:
-			dimm->mod_type = DDR3_SPD_UDIMM;
+			dimm->mod_type = SPD_UDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_RDIMM:
-			dimm->mod_type = DDR3_SPD_RDIMM;
+			dimm->mod_type = SPD_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UNDEFINED:
 		default:

src/device/dram/ddr4.c

@@ -299,16 +299,16 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel
 
 		switch (info->dimm_type) {
 		case SPD_DDR4_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = DDR4_SPD_SODIMM;
+			dimm->mod_type = SPD_SODIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = DDR4_SPD_72B_SO_RDIMM;
+			dimm->mod_type = SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_UDIMM:
-			dimm->mod_type = DDR4_SPD_UDIMM;
+			dimm->mod_type = SPD_UDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_RDIMM:
-			dimm->mod_type = DDR4_SPD_RDIMM;
+			dimm->mod_type = SPD_RDIMM;
 			break;
 		default:
 			dimm->mod_type = SPD_UNDEFINED;

src/device/dram/spd.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/dram/spd.h>
-#include <spd.h>
 
 const char *spd_manufacturer_name(const uint16_t mod_id)
 {
@@ -39,219 +38,3 @@ const char *spd_manufacturer_name(const uint16_t mod_id)
 		return NULL;
 	}
 }
-
-static void convert_default_module_type_to_spd_info(struct spd_info *info)
-{
-	info->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
-	info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-}
-
-static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type,
-		struct spd_info *info)
-{
-	switch (module_type) {
-	case DDR2_SPD_RDIMM:
-	case DDR2_SPD_MINI_RDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_RIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case DDR2_SPD_UDIMM:
-	case DDR2_SPD_MINI_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_DIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	case DDR2_SPD_MICRO_DIMM:
-		info->form_factor = MEMORY_FORMFACTOR_DIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	case DDR2_SPD_SODIMM:
-		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	default:
-		convert_default_module_type_to_spd_info(info);
-		break;
-	}
-}
-
-static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
-		struct spd_info *info)
-{
-	switch (module_type) {
-	case DDR3_SPD_RDIMM:
-	case DDR3_SPD_MINI_RDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_RIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case DDR3_SPD_UDIMM:
-	case DDR3_SPD_MINI_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_DIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	case DDR3_SPD_MICRO_DIMM:
-		info->form_factor = MEMORY_FORMFACTOR_DIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	case DDR3_SPD_SODIMM:
-	case DDR3_SPD_72B_SO_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	default:
-		convert_default_module_type_to_spd_info(info);
-		break;
-	}
-}
-
-static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type,
-		struct spd_info *info)
-{
-	switch (module_type) {
-	case DDR4_SPD_RDIMM:
-	case DDR4_SPD_MINI_RDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_RIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case DDR4_SPD_UDIMM:
-	case DDR4_SPD_MINI_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_DIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	case DDR4_SPD_SODIMM:
-	case DDR4_SPD_72B_SO_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	default:
-		convert_default_module_type_to_spd_info(info);
-		break;
-	}
-}
-
-static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type,
-		struct spd_info *info)
-{
-	switch (module_type) {
-	case DDR5_SPD_RDIMM:
-	case DDR5_SPD_MINI_RDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_RIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case DDR5_SPD_UDIMM:
-	case DDR5_SPD_MINI_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_DIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	case DDR5_SPD_SODIMM:
-	case DDR5_SPD_72B_SO_UDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	case DDR5_SPD_2DPC:
-		info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	default:
-		convert_default_module_type_to_spd_info(info);
-		break;
-	}
-}
-
-static void convert_lpx_module_type_to_spd_info(enum lpx_module_type module_type,
-		struct spd_info *info)
-{
-	switch (module_type) {
-	case LPX_SPD_NONDIMM:
-		info->form_factor = MEMORY_FORMFACTOR_ROC;
-		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	default:
-		convert_default_module_type_to_spd_info(info);
-		break;
-	}
-}
-
-void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info)
-{
-	switch (memory_type) {
-	case MEMORY_TYPE_DDR2:
-		convert_ddr2_module_type_to_spd_info(module_type, info);
-		break;
-	case MEMORY_TYPE_DDR3:
-		convert_ddr3_module_type_to_spd_info(module_type, info);
-		break;
-	case MEMORY_TYPE_DDR4:
-		convert_ddr4_module_type_to_spd_info(module_type, info);
-		break;
-	case MEMORY_TYPE_DDR5:
-		convert_ddr5_module_type_to_spd_info(module_type, info);
-		break;
-	case MEMORY_TYPE_LPDDR3:
-	case MEMORY_TYPE_LPDDR4:
-	case MEMORY_TYPE_LPDDR5:
-		convert_lpx_module_type_to_spd_info(module_type, info);
-		break;
-	default:
-		convert_default_module_type_to_spd_info(info);
-		break;
-	}
-}
-
-static uint8_t convert_default_form_factor_to_module_type(void)
-{
-	return SPD_UNDEFINED;
-}
-
-static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor)
-{
-	uint8_t module_type;
-
-	switch (form_factor) {
-	case MEMORY_FORMFACTOR_DIMM:
-		return DDR2_SPD_UDIMM;
-	case MEMORY_FORMFACTOR_RIMM:
-		return DDR2_SPD_RDIMM;
-	case MEMORY_FORMFACTOR_SODIMM:
-		module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM
-				: DDR3_SPD_SODIMM;
-		return module_type;
-	default:
-		return convert_default_form_factor_to_module_type();
-	}
-}
-
-static uint8_t convert_lpx_form_factor_to_module_type(smbios_memory_form_factor form_factor)
-{
-	switch (form_factor) {
-	case MEMORY_FORMFACTOR_ROC:
-		return LPX_SPD_NONDIMM;
-	default:
-		return convert_default_form_factor_to_module_type();
-	}
-}
-
-uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor)
-{
-	uint8_t module_type;
-
-	switch (memory_type) {
-	case MEMORY_TYPE_DDR2:
-	case MEMORY_TYPE_DDR3:
-	case MEMORY_TYPE_DDR4:
-	case MEMORY_TYPE_DDR5:
-		module_type = convert_ddrx_form_factor_to_module_type(memory_type, form_factor);
-		break;
-	case MEMORY_TYPE_LPDDR3:
-	case MEMORY_TYPE_LPDDR4:
-	case MEMORY_TYPE_LPDDR5:
-		module_type = convert_lpx_form_factor_to_module_type(form_factor);
-		break;
-	default:
-		module_type = convert_default_form_factor_to_module_type();
-		break;
-	}
-
-	return module_type;
-}

src/device/pci_ops.c

@@ -7,7 +7,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 
-u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS;
 
 /**
  * Given a device, a capability type, and a last position, return the next

src/drivers/amd/agesa/romstage.c

@@ -36,18 +36,22 @@ static void romstage_main(void)
 	struct postcar_frame pcf;
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
+	unsigned int initial_apic_id = initial_lapicid();
 	int cbmem_initted = 0;
 
 	fill_sysinfo(cb);
 
-	timestamp_add_now(TS_START_ROMSTAGE);
+	if (initial_apic_id == 0) {
 
-	board_BeforeAgesa(cb);
+		timestamp_add_now(TS_START_ROMSTAGE);
 
-	console_init();
+		board_BeforeAgesa(cb);
+
+		console_init();
+	}
 
 	printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n",
-	       initial_lapicid(), cpuid_eax(1));
+		initial_apic_id, cpuid_eax(1));
 
 	set_ap_entry_ptr(ap_romstage_main);
 

src/drivers/aspeed/common/ast_mode_corebootfb.c

@@ -22,7 +22,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc)
 	struct drm_framebuffer *fb = crtc->primary->fb;
 
 	/* PCI BAR 0 */
-	struct resource *res = probe_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
+	struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_ERR, "BAR0 resource not found.\n");
 		return -EIO;

src/drivers/elog/elog.c

@@ -16,7 +16,6 @@
 #include <smbios.h>
 #include <stdint.h>
 #include <string.h>
-#include <timestamp.h>
 
 #define ELOG_MIN_AVAILABLE_ENTRIES	2  /* Shrink when this many can't fit */
 #define ELOG_SHRINK_PERCENTAGE		25 /* Percent of total area to remove */
@@ -750,9 +749,6 @@ int elog_init(void)
 	}
 	elog_state.elog_initialized = ELOG_BROKEN;
 
-	if (!ENV_SMM)
-		timestamp_add_now(TS_ELOG_INIT_START);
-
 	elog_debug("%s()\n", __func__);
 
 	/* Set up the backing store */
@@ -785,10 +781,6 @@ int elog_init(void)
 
 	if (ENV_PAYLOAD_LOADER)
 		elog_add_boot_count();
-
-	if (!ENV_SMM)
-		timestamp_add_now(TS_ELOG_INIT_END);
-
 	return 0;
 }
 

src/drivers/gfx/nvidia/acpi/advanced_optimus.asl

@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// NVIDIA Advanced Optimus
-
-#define NVOP_FUNC_SUPPORT		0
-#define NVOP_FUNC_DISPLAYSTATUS		5
-#define NVOP_FUNC_MDTL			6
-#define NVOP_FUNC_GETOBJBYTYPE		16
-#define NVOP_FUNC_GETALLOBJS		17
-#define NVOP_FUNC_OPTIMUSCAPS		26
-#define NVOP_FUNC_OPTIMUSFLAGS		27
-
-Method (NVOP, 2, Serialized)
-{
-	Printf("NVOP {")
-	Local0 = NVIDIA_ERROR_UNSUPPORTED
-
-	Switch (ToInteger(Arg0)) {
-		Case (NVOP_FUNC_SUPPORT) {
-		}
-
-		Case (NVOP_FUNC_OPTIMUSCAPS) {
-			CreateField (Arg1, 0, 1, FLGS)	// Flag updates
-			CreateField (Arg1, 1, 1, PCOT)	// PCIe Configuration Space Owner Target
-			CreateField (Arg1, 2, 1, PCOW)	// PCIe Configuration Space Owner Write
-			CreateField (Arg1, 24, 2, OPCE)	// Optimus Power Control Enable
-		}
-
-		Default {
-			Printf("  Unsupported NVOP_FUNC: %o", ToInteger(Arg0))
-			Local0 = NVIDIA_ERROR_UNSUPPORTED
-		}
-	}
-
-	Printf("} NVOP")
-	Return(Local0)
-}

src/drivers/gfx/nvidia/acpi/boost.asl

@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// NVIDIA GPU Boost for Notebook and All-In-One-Projects
-
-#define GPS_FUNC_SUPPORT		0
-#define GPS_FUNC_GETOBJBYTYPE		16
-#define GPS_FUNC_GETALLOBJS		17
-#define GPS_FUNC_GETCALLBACKS		19
-#define GPS_FUNC_PCONTROL		28
-#define GPS_FUNC_PSHARESTATUS		32
-#define GPS_FUNC_PSHAREPARAMS		42
-
-Method (GPS, 2, Serialized)
-{
-	Printf("GPS {")
-
-	Switch (ToInteger(Arg0)) {
-		// Bit list of supported functions
-		Case (GPS_FUNC_SUPPORT) {
-			Printf("  GPS_FUNC_SUPPORT")
-			// Functions supported: 0, 32, 42
-			Local0 = Buffer () {0x01, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00}
-		}
-
-		// Get current platform status, thermal budget
-		Case (GPS_FUNC_PSHARESTATUS) {
-			Printf("  GPS_FUNC_PSHARESTATUS: %o", ToHexString(Arg1))
-			Local0 = Buffer (4) { 0 }
-		}
-
-		// Get GPU Boost platform parameters
-		Case (GPS_FUNC_PSHAREPARAMS) {
-			Printf("  GPS_FUNC_PSHAREPARAMS: %o", ToHexString(Arg1))
-			CreateField (Arg1, 0, 3, QTYP)		// Query Type
-			CreateField (Arg1, 8, 1, GTMP)		// GPU temperature status
-			CreateField (Arg1, 9, 1, CTMP)		// CPU temperature status
-
-			Local0 = Buffer (36) { 0 }
-			CreateDWordField (Local0, 0, STAT)	// Status
-			CreateDWordField (Local0, 4, VERS)	// Version
-			CreateDWordField (Local0, 8, TGPU)	// GPU temperature (C)
-			CreateDWordField (Local0, 12, PDTS)	// CPU package temperature (C)
-
-			VERS = 0x00010000
-			STAT = QTYP
-
-			Printf("    Query Type = %o", ToInteger(QTYP))
-
-			Switch (ToInteger(QTYP)) {
-				// Get current status
-				Case (0) {
-					// TGPU must be 0.
-				}
-
-				// Get supported fields
-				Case (1) {
-					STAT |= 0x100
-					// TGPU must be 0.
-				}
-
-				// Get current operating limits
-				Case (2) {
-					// GPU temperature status must be 1.
-					STAT |= 0x100
-					// TGPU should be 0. GPU will use its own default.
-				}
-
-				Default {
-					Printf("    Unsupported Query Type: %o", ToInteger(QTYP))
-					Local0 = NVIDIA_ERROR_UNSUPPORTED
-				}
-			}
-		}
-
-		Default {
-			Printf("  Unsupported GPS_FUNC: %o", ToInteger(Arg0))
-			Local0 = NVIDIA_ERROR_UNSUPPORTED
-		}
-	}
-
-	Printf("} GPS")
-	Return(Local0)
-}

src/drivers/gfx/nvidia/acpi/gpu.asl

@@ -1,197 +1,202 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#define NVIDIA_ERROR_UNSPECIFIED	0x80000001
-#define NVIDIA_ERROR_UNSUPPORTED	0x80000002
-
-#define NBCI_DSM_GUID		"D4A50B75-65C7-46F7-BFB7-41514CEA0244"
-#define NBCI_REVISION_ID	0x102
-
-#define GPS_DSM_GUID		"A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
-#define GPS_REVISION_ID		0x200
-
-#define JT_DSM_GUID		"CBECA351-067B-4924-9CBD-B46B00B86F34"
-#define JT_REVISION_ID		0x103
-
-#define NVOP_DSM_GUID		"A486D8F8-0BDA-471B-A72B-6042A6B5BEE0"
-#define NVOP_REVISION_ID	0x100
-
-// 00:01.0
-Device (\_SB.PCI0.PEG0)
-{
+Device (\_SB.PCI0.PEGP) {
 	Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
 
 	PowerResource (PWRR, 0, 0) {
 		Name (_STA, 1)
 
-		Method (_ON)
-		{
-			Printf("PEG0._ON {")
-			// TODO: Check for deferred GCx action
-			\_SB.PCI0.PEG0.DGPU._ON()
-			_STA = 1
-			Printf("} PEG0._ON")
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
 		}
 
-		Method (_OFF)
-		{
-			Printf("PEG0._OFF {")
-			// TODO: Check for deferred GCx action
-			\_SB.PCI0.PEG0.DGPU._OFF()
-			_STA = 0
-			Printf("} PEG0._OFF")
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
 		}
 	}
 
-	Name (_PR0, Package () { PWRR })
-	Name (_PR2, Package () { PWRR })
-	Name (_PR3, Package () { PWRR })
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
 }
 
-// 01:00.0
-Device (\_SB.PCI0.PEG0.DGPU)
-{
+Device (\_SB.PCI0.PEGP.DEV0) {
 	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
 
-	Name (GPWR, 0)		// GPU Power
-	Name (GCST, 6)		// GCx State
-
-	Name (DPC, 0)		// Deferred power control
-	Name (DPCX, 0)		// Deferred power control on exit
-
-
-	Name (NVID, 0x00000000)
-
-	OperationRegion (PCIM, SystemMemory, 0x0E010000, 0xF0)
-	Field (PCIM, AnyAcc, Lock, Preserve)
-	{
-		Offset(0x2c),
-		SSID, 32,
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+        // TODO: use GPU config to generate address
+	OperationRegion (RPCX, SystemMemory, CONFIG_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
 	}
 
-	// For supporting Hybrid Graphics, the package refers to the PCIe controller
-	// itself, which leverages GC6 Control methods under the dGPU namespace.
-	Name (_PR0, Package() { \_SB.PCI0.PEG0 })
-	Name (_PR3, Package() { \_SB.PCI0.PEG0 })
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
 
-	Method (_STA)
-	{
-		Printf("DGPU._STA")
-		/*
-		 * Only return "On" when:
-		 * - GPU power is good
-		 * - GPU has completed return to GC0
-		 *
-		 * In all other cases, return "Off".
-		 */
-		If ((GPWR == 1) && (GCST == 0)) {
-			Return (0xF)
-		} Else {
-			Return (0)
-		}
-	}
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
 
-	Method (_ON)
-	{
-		Printf("DGPU._ON {")
-		Printf("  Enable GPU power")
-		STXS(DGPU_PWR_EN)
-		Sleep(10)
-
-		Printf("  Take GPU out of reset")
-		STXS(DGPU_RST_N)
-		Sleep(10)
-
-		GPWR = 1
-		GCST = 0
-
-		/*
-		// TODO: Actually check link status
-		Printf("Wait for PCIe link")
-		Sleep(100)
-
-		Printf("Restore SSID: %o", NVID)
-		SSID = NVID
-		*/
-
-		Printf("} DGPU._ON")
-	}
-
-	Method (_OFF)
-	{
-		Printf("DGPU._OFF {")
-
-		/*
-		Printf("Save SSID: %o", SSID)
-		NVID = SSID
-
-		// TODO: Actually check link status
-		Printf("Wait for PCIe link")
-		Sleep(100)
-		*/
-
-		Printf("DGPU._OFF {")
-		Printf("  Put GPU in reset")
-		CTXS(DGPU_RST_N)
-		Sleep(10)
-
-		Printf("  Disable GPU power")
-		CTXS(DGPU_PWR_EN)
-
-		GPWR = 0
-		GCST = 6
-		Printf("} DGPU._OFF")
-	}
-
-	Method (_PS0)
-	{
-		// XGXS, XGIS, XCLM
-		Printf("_PS0 {}")
-	}
-
-	Method (_PS3)
-	{
-		// EGNS, EGIS, EGIN
-		Printf("_PS3 {}")
-	}
-
-	Method (_DSM, 4, Serialized)
-	{
-		// Notebook Common Interface
-		If (Arg0 == ToUUID(NBCI_DSM_GUID)) {
-			Printf("NBCI_DSM_GUID")
-			If (Arg1 <= NBCI_REVISION_ID) {
-				Printf("  TODO: Unimplemented!")
+				Debug = "    Sleep 16"
+				Sleep (16)
 			}
-		}
 
-		// NVIDIA GPU Boost
-		If (Arg0 == ToUUID(GPS_DSM_GUID)) {
-			Printf("GPS_DSM_GUID")
-			If (Arg1 <= GPS_REVISION_ID) {
-				Return(GPS(Arg2, Arg3))
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
 			}
-		}
 
-		// NVIDIA Low Power States
-		If (Arg0 == ToUUID(JT_DSM_GUID)) {
-			Printf("JT_DSM_GUID")
-			If (Arg1 <= JT_REVISION_ID) {
-				Return(NVJT(Arg2, Arg3))
-			}
-		}
+			Debug = "  P0RM = 0"
+			P0RM = 0
 
-		// Advanced Optimus
-		If (Arg0 == ToUUID(NVOP_DSM_GUID)) {
-			Printf("NVOP_DSM_GUID")
-			If (Arg1 <= NVOP_REVISION_ID) {
-				Printf("  TODO: Unimplemented!")
-			}
-		}
+			Debug = "  P0AP = 0"
+			P0AP = 0
 
-		Printf("Unsupported GUID: %o", ToHexString(Arg0))
-		Return(NVIDIA_ERROR_UNSUPPORTED)
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
 	}
 
-	#include "boost.asl"
-	#include "low_power_states.asl"
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
 }

src/drivers/gfx/nvidia/acpi/low_power_states.asl

@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// NVIDIA Low Power States
-
-#define JT_FUNC_SUPPORT		0
-#define JT_FUNC_CAPS		1
-#define JT_FUNC_POWERCONTROL	3
-#define JT_FUNC_PLATPOLICY	4
-
-Method (NVJT, 2, Serialized)
-{
-	Printf("NVJT {")
-
-	Switch (ToInteger(Arg0)) {
-		Case (JT_FUNC_SUPPORT) {
-			Printf("  JT_FUNC_SUPPORT");
-			// Functions supported: 0, 1, 3, 4
-			//Local0 = Buffer() { 0x1B, 0, 0, 0 }
-			Local0 = Buffer() { 0x13, 0, 0, 0 }
-		}
-
-		Case (JT_FUNC_CAPS) {
-			Printf("  JT_FUNC_CAPS");
-			Local0 = Buffer(4) { 0 }
-
-			// G-SYNC NVSR Power Features
-			CreateField (Local0, 0, 1, JTEN)
-			JTEN = 0
-
-			// NVSR
-			CreateField (Local0, 1, 2, NVSE)
-			NVSE = 1
-
-			// Panel Power Rail
-			CreateField (Local0, 3, 2, PPR)
-			PPR = 2
-
-			// Self-Refresh Control (SRC) Power Rail
-			CreateField (Local0, 5, 1, SRPR)
-			SRPR = 0
-
-			// FB Power Rail
-			CreateField (Local0, 6, 2, FBPR)
-			FBPR = 0
-
-			// GPU Power Rail
-			CreateField (Local0, 8, 2, GPR)
-			GPR = 0
-
-			// GC6 ROM
-			CreateField (Local0, 10, 1, GCR)
-			GCR = 0
-
-			// Panic Trap Handler
-			CreateField (Local0, 11, 1, PTH)
-			PTH = 1
-
-			// Supports Notify
-			CreateField (Local0, 12, 1, NOTS)
-			NOTS = 0
-
-			// MS Hybrid Support
-			CreateField (Local0, 13, 1, MHYB)
-			MHYB = 1
-
-			// Root Port Control
-			CreateField (Local0, 14, 1, RPC)
-			RPC = 1
-
-			// GC6 Version
-			CreateField (Local0, 15, 2, GC6V)
-			GC6V = 2
-
-			// GC6 Exit ISR Support
-			CreateField (Local0, 17, 1, GEI)
-			GEI = 0
-
-			// GC6 Self Wakeup Support
-			CreateField (Local0, 18, 1, GSW)
-			GSW = 0
-
-			// Maximum Revision Supported
-			CreateField (Local0, 20, 12, MXRV)
-			MXRV = JT_REVISION_ID
-		}
-
-		Case (JT_FUNC_POWERCONTROL) {
-			Printf("  JT_FUNC_POWERCONTROL: %o", ToHexString(Arg1));
-			// TODO
-			Local0 = NVIDIA_ERROR_UNSUPPORTED
-
-			/*
-			CreateField (Arg1, 0, 3, GPC)		// GPU Power Control
-			CreateField (Arg1, 3, 1, GGP)		// Global GPU Power
-			CreateField (Arg1, 4, 1, PPC)		// Panel Power Control
-			CreateField (Arg1, 6, 2, NOC)		// Notify on complete
-			CreateField (Arg1, 8, 2, PRGX)		// PCIe Root Power GC6 Exit Sequence
-			CreateField (Arg1, 10, 2, PRGE)		// PCIe Root Power GC6 Entry Sequence
-			CreateField (Arg1, 12, 1, PRPC)		// Poll for Root Port Completion
-			CreateField (Arg1, 13, 1, PLON)		// PCIe Root Port Control
-			CreateField (Arg1, 14, 2, DFGC)		// Defer GC6 Enter/Exit until D3cold
-			CreateField (Arg1, 16, 3, GPCX)		// Deferred GC6 Exit Control
-			CreateField (Arg1, 19, 1, EGEI)		// Enable GC6 Exit ISR
-			CreateField (Arg1, 20, 2, PLCM)		// PCIe Root Port Control Method for PLON
-
-			Local0 = Buffer(4) {0, 0, 0, 0}
-			CreateField (Local0, 0, 3, GCS)		// GC State
-			CreateField (Local0, 3, 1, GPS)		// GPU Power Status
-			CreateField (Local0, 7, 1, PSS)		// Panel and SRC State
-			*/
-
-			/*
-			 * DFGC
-			 * 0: Perform request immediately
-			 * 1: Defer GPC and GPCX to be processed when setting Device Power State
-			 * 2: Clear any pending deferred requests
-			 */
-			/*
-			If (DFGC == 2) {
-				DPC = 0
-				DPCX = 0
-			}
-			*/
-
-			/*
-			 * GPC
-			 * 0 GSS) Get current GPU GCx Sleep Status
-			 * 1 EGNS: Entery GC6 only. No SMI trap, No Self-Refresh. Panel
-			 *         and GPU will be powred down as normal. FB will remain powered.
-			 * 2 EGIS: Enter GC6, keep Panel in Self-Refresh. Enable SMI trap on
-			 *         VGA I/O regiters. Control of screen is transitioned to the SRC and
-			 *         then the GPU is powered down. Panel and FB remain powered while
-			 *         the GPU is off.
-			 * 3 XGXS: Exit GC6. Exit Panel Self-Refresh (Sparse). GPU is powered on.
-			 *         Disable SMI traps.
-			 * 4 XGIS: Exit GC6 for Self-Refresh Update (Burst). GPU is powered on, but
-			 *         the SRC continues to retain control of screen refresh, while the
-			 *         GPU sends an update to SRC for display. Disable SMI traps.
-			 * 5 EGIN: Enter GC6, keep Pnael in Self-Refresh. No SMI trap on VGA I/O
-			 *         registers. Control of screen is transitioned to SRC and then
-			 *         GPU is powred down. Panel and FB remain powered while the GPU is off.
-			 * 6 XCLM: Trigger GPU_EVENT only. GPU_EVENT would be assered and de-asserted,
-			 *         regardless of GPU power state, without waiting for any GPU-side
-			 *         signaling. No change in GPU power state is made. SMI traps disabled.
-			 */
-		}
-
-		Case (JT_FUNC_PLATPOLICY) {
-			Printf("  JT_FUNC_PLATPOLICY: %o", ToHexString(Arg1));
-			//CreateField (Arg1, 2, 1, AUD)		// Azalia Audio Device
-			//CreateField (Arg1, 3, 1, ADM)		// Audio Disable Mask
-			//CreateField (Arg1, 4, 4, DGS)		// Driver expected State Mask
-
-			// TODO: Save policy settings to NV CMOS?
-
-			Local0 = Buffer(4) { 0, 0, 0, 0 }
-			//CreateField (Local0, 2, 1, AUD)		// Audio Device status
-			//CreateField (Local0, 4, 3, GRE)		// SBIOS requested GPU state
-		}
-
-		Default {
-			Printf("  Unsupported JT_FUNC: %o", ToInteger(Arg0))
-			Local0 = NVIDIA_ERROR_UNSUPPORTED
-		}
-	}
-
-	Printf("} NVJT")
-	Return(Local0)
-}

src/drivers/gfx/nvidia/acpi/nbci.asl

@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Notebook Common Interface
-
-#define NBCI_FUNC_SUPPORT		0
-#define NBCI_FUNC_PLATCAPS		1
-#define NBCI_FUNC_PLATPOLICY		4
-#define NBCI_FUNC_DISPLAYSTATUS		5
-#define NBCI_FUNC_GETOBJBYTYPE		16
-#define NBCI_FUNC_GETALLOBJS		17
-#define NBCI_FUNC_GETEVENTLIST		18
-#define NBCI_FUNC_CALLBACKS		29
-#define NBCI_FUNC_GETBACKLIGHT		20
-#define NBCI_FUNC_GETLICENSE		22
-#define NBCI_FUNC_GETEFITABLE		23
-
-Scope (\_SB.PCI0.PEG0.DGPU)
-{
-	Method (NBCI, 2, NotSerialized)
-	{
-		Printf("NBCI {")
-		Local0 = NVIDIA_ERROR_UNSUPPORTED
-
-		Switch (ToInteger(Arg0)) {
-			// Bit list of supported functions
-			Case (NBCI_FUNC_SUPPORT) {
-				// Supported functions: 0
-				Local0 = Buffer() {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-			}
-
-			// Query Plaform Capabilities
-			Case (NBCI_FUNC_PLATCAPS) {
-				Printf("  NBCI_FUNC_PLATCAPS: Unimplemented!")
-			}
-
-			// Query Platform Policies
-			Case (NBCI_FUNC_PLATPOLICY) {
-				Printf("  NBCI_FUNC_PLATPOLICY: Unimplemented!")
-			}
-
-			// Query Display status
-			Case (NBCI_FUNC_DISPLAYSTATUS) {
-				Printf("  NBCI_FUNC_DISPLAYSTATUS: Unimplemented!")
-			}
-
-			// Fetch and specific Object by Type
-			Case (NBCI_FUNC_GETOBJBYTYPE) {
-				Printf("  NBCI_FUNC_GETOBJBYTYPE: Unimplemented!")
-			}
-
-			// Fetch all Objects
-			Case (NBCI_FUNC_GETALLOBJS) {
-				Printf("  NBCI_FUNC_GETALLOBJS: Unimplemented!")
-			}
-
-			// Get list of Notify events and their meaning
-			Case (NBCI_FUNC_GETEVENTLIST) {
-				Printf("  NBCI_FUNC_GETEVENTLIST: Unimplemented!")
-			}
-
-			// Get list of system-required callbacks
-			Case (NBCI_FUNC_CALLBACKS) {
-				Printf("  NBCI_FUNC_CALLBACKS: Unimplemented!")
-			}
-
-			// Get the Backlight setup settings
-			Case (NBCI_FUNC_GETBACKLIGHT) {
-				Printf("  NBCI_FUNC_GETBACKLIGHT: Unimplemented!")
-			}
-
-			// Get Software License Number
-			Case (NBCI_FUNC_GETLICENSE) {
-				Printf("  NBCI_FUNC_GETLICENSE: Unimplemented!")
-			}
-
-			// Get EFI System Table
-			Case (NBCI_FUNC_GETEFITABLE) {
-				Printf("  NBCI_FUNC_GETEFITABLE: Unimplemented!")
-			}
-
-			Default {
-				Printf("  Unsupported NBCI_FUNC: %o", ToInteger(Arg0))
-				Local0 = NVIDIA_ERROR_UNSUPPORTED
-			}
-		}
-
-		Printf("} NBCI")
-		Return(Local0)
-	}
-}

src/drivers/gfx/nvidia/romstage.c

@@ -15,8 +15,10 @@ void nvidia_set_power(const struct nvidia_gpu_config *config)
 		return;
 	}
 
-	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
-	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n",
+		__func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n",
+		__func__, config->reset_gpio);
 
 	gpio_set(config->reset_gpio, 0);
 	mdelay(4);

src/drivers/intel/fsp1_1/romstage.c

@@ -18,6 +18,7 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 static void raminit_common(struct romstage_params *params)
 {
@@ -103,9 +104,9 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* Display parameters */
-	if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
-		printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n",
-			CONFIG_ECAM_MMCONF_BASE_ADDRESS);
+	if (!CONFIG(NO_MMCONF_SUPPORT))
+		printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
+			CONFIG_MMCONF_BASE_ADDRESS);
 	printk(BIOS_INFO, "Using FSP 1.1\n");
 
 	/* Display FSP banner */

src/drivers/intel/fsp2_0/Kconfig

@@ -218,16 +218,6 @@ config FSP_COMPRESS_FSP_M_LZ4
 	bool
 	depends on !FSP_M_XIP
 
-config FSP_ALIGNMENT_FSP_S
-	int
-	help
-	  Sets the CBFS alignment for FSP-S
-
-config FSP_ALIGNMENT_FSP_M
-	int
-	help
-	  Sets the CBFS alignment for FSP-M
-
 config FSP_M_ADDR
 	hex
 	help

src/drivers/intel/fsp2_0/Makefile.inc

@@ -65,9 +65,6 @@ endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y)
 $(FSP_M_CBFS)-compression := LZ4
 endif
-ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),)
-$(FSP_M_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_M)
-endif
 
 cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS)
 $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
@@ -78,9 +75,6 @@ endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y)
 $(FSP_S_CBFS)-compression := LZ4
 endif
-ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),)
-$(FSP_S_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_S)
-endif
 
 ifeq ($(CONFIG_FSP_FULL_FD),y)
 $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG)

src/drivers/intel/fsp2_0/include/fsp/api.h

@@ -32,9 +32,7 @@ enum fsp_notify_phase {
 };
 
 /* Main FSP stages */
-void preload_fspm(void);
 void fsp_memory_init(bool s3wake);
-void preload_fsps(void);
 void fsp_silicon_init(void);
 
 /*

src/drivers/intel/fsp2_0/memory_init.c

@@ -340,15 +340,6 @@ static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unus
 	return (void *)fspm_begin;
 }
 
-void preload_fspm(void)
-{
-	if (!CONFIG(CBFS_PRELOAD))
-		return;
-
-	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS);
-	cbfs_preload(CONFIG_FSP_M_CBFS);
-}
-
 void fsp_memory_init(bool s3wake)
 {
 	struct range_entry prog_ranges[2];

src/drivers/intel/fsp2_0/silicon_init.c

@@ -230,15 +230,6 @@ void fsps_load(void)
 	load_done = 1;
 }
 
-void preload_fsps(void)
-{
-	if (!CONFIG(CBFS_PRELOAD))
-		return;
-
-	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS);
-	cbfs_preload(CONFIG_FSP_S_CBFS);
-}
-
 void fsp_silicon_init(void)
 {
 	timestamp_add_now(TS_FSP_SILICON_INIT_LOAD);

src/drivers/intel/fsp2_0/util.c

@@ -163,8 +163,8 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea
 	if (!dest)
 		return CB_ERR;
 
-	/* Don't allow FSP-M relocation when XIP. */
-	if (!fspm_xip() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
+	/* Don't allow FSP-M relocation. */
+	if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
 		printk(BIOS_ERR, "Unable to relocate FSP component!\n");
 		return CB_ERR;
 	}

src/drivers/net/atl1e.c

@@ -106,7 +106,7 @@ static int atl1e_eeprom_exist(u32 mem_base)
 static void atl1e_init(struct device *dev)
 {
 	/* Get the resource of the NIC mmio */
-	struct resource *nic_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0);
 
 	if (nic_res == NULL) {
 		printk(BIOS_ERR, "atl1e: resource not found\n");

src/drivers/parade/ps8640/ps8640.c

@@ -5,7 +5,7 @@
 #include <edid.h>
 #include <console/console.h>
 #include <timer.h>
-#include <dp_aux.h>
+
 #include "ps8640.h"
 
 int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out)
@@ -80,101 +80,3 @@ int ps8640_init(uint8_t bus, uint8_t chip)
 
 	return 0;
 }
-
-static cb_err_t ps8640_bridge_aux_request(uint8_t bus,
-					  uint8_t chip,
-					  unsigned int target_reg,
-					  unsigned int total_size,
-					  enum aux_request request,
-					  uint8_t *data)
-{
-	int i;
-	uint32_t length;
-	uint8_t buf;
-	uint8_t reg;
-	int ret;
-
-	if (target_reg & ~SWAUX_ADDR_MASK)
-		return CB_ERR;
-
-	while (total_size) {
-		length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES);
-		total_size -= length;
-
-		ret = i2c_writeb(bus, chip, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
-		if (ret)
-			return CB_ERR;
-
-		enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size);
-		if (i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_23_16,
-			(target_reg >> 16) | (cmd << 4)) ||
-		    i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_15_8, target_reg >> 8) ||
-		    i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_7_0, target_reg)) {
-			return CB_ERR;
-		}
-
-		if (dp_aux_request_is_write(request)) {
-			reg = PAGE0_SWAUX_WDATA;
-			for (i = 0; i < length; i++) {
-				ret = i2c_writeb(bus, chip, reg++, *data++);
-				if (ret)
-					return CB_ERR;
-			}
-		} else {
-			if (length == 0)
-				i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, SWAUX_NO_PAYLOAD);
-			else
-				i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, length - 1);
-		}
-
-		ret = i2c_writeb(bus, chip, PAGE0_SWAUX_CTRL, SWAUX_SEND);
-		if (ret)
-			return CB_ERR;
-
-		if (!wait_ms(100, !i2c_readb(bus, chip, PAGE0_SWAUX_CTRL, &buf) &&
-				  !(buf & SWAUX_SEND)))
-			return CB_ERR;
-
-		if (i2c_readb(bus, chip, PAGE0_SWAUX_STATUS, &buf))
-			return CB_ERR;
-
-		switch (buf & SWAUX_STATUS_MASK) {
-		case SWAUX_STATUS_NACK:
-		case SWAUX_STATUS_I2C_NACK:
-		case SWAUX_STATUS_INVALID:
-		case SWAUX_STATUS_TIMEOUT:
-			return CB_ERR;
-		case SWAUX_STATUS_ACKM:
-			length = buf & SWAUX_M_MASK;
-			break;
-		}
-
-		if (length && !dp_aux_request_is_write(request)) {
-			reg = PAGE0_SWAUX_RDATA;
-			for (i = 0; i < length; i++) {
-				if (i2c_readb(bus, chip, reg++, &buf))
-					return CB_ERR;
-				*data++ = buf;
-			}
-		}
-	}
-
-	return CB_SUCCESS;
-}
-
-void ps8640_backlight_enable(uint8_t bus, uint8_t chip)
-{
-	uint8_t val;
-
-	val = DP_BACKLIGHT_CONTROL_MODE_DPCD;
-	ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1,
-				  DPCD_WRITE, &val);
-
-	val = 0xff;
-	ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1,
-				  DPCD_WRITE, &val);
-
-	val = DP_BACKLIGHT_ENABLE;
-	ps8640_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1,
-				  DPCD_WRITE, &val);
-}

src/drivers/parade/ps8640/ps8640.h

@@ -24,33 +24,11 @@ enum {
 };
 
 enum {
-	PAGE0_AUXCH_CFG3 = 0x76,
-	AUXCH_CFG3_RESET = 0xff,
-	PAGE0_SWAUX_ADDR_7_0 = 0x7d,
-	PAGE0_SWAUX_ADDR_15_8 = 0x7e,
-	PAGE0_SWAUX_ADDR_23_16 = 0x7f,
-	SWAUX_ADDR_MASK = 0xfffff,
-	PAGE0_SWAUX_LENGTH = 0x80,
-	SWAUX_LENGTH_MASK = 0xf,
-	SWAUX_NO_PAYLOAD = BIT(7),
-	PAGE0_SWAUX_WDATA = 0x81,
-	PAGE0_SWAUX_RDATA = 0x82,
-	PAGE0_SWAUX_CTRL = 0x83,
-	SWAUX_SEND = BIT(0),
-	PAGE0_SWAUX_STATUS = 0x84,
-	SWAUX_M_MASK = 0x1f,
-	SWAUX_STATUS_MASK = (0x7 << 5),
-	SWAUX_STATUS_NACK = (0x1 << 5),
-	SWAUX_STATUS_DEFER = (0x2 << 5),
-	SWAUX_STATUS_ACKM = (0x3 << 5),
-	SWAUX_STATUS_INVALID = (0x4 << 5),
-	SWAUX_STATUS_I2C_NACK = (0x5 << 5),
-	SWAUX_STATUS_I2C_DEFER = (0x6 << 5),
-	SWAUX_STATUS_TIMEOUT = (0x7 << 5),
+	EDID_LENGTH         = 128,
+	EDID_I2C_ADDR       = 0x50,
+	EDID_EXTENSION_FLAG = 0x7e,
 };
 
 int ps8640_init(uint8_t bus, uint8_t chip);
 int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out);
-void ps8640_backlight_enable(uint8_t bus, uint8_t chip);
-
 #endif

src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c

@@ -4,7 +4,6 @@
 #include <delay.h>
 #include <endian.h>
 #include <device/i2c_simple.h>
-#include <dp_aux.h>
 #include <edid.h>
 #include <timer.h>
 #include <types.h>
@@ -32,6 +31,14 @@
 #define DP_MAX_SUPPORTED_RATES		8 /* 16-bit little-endian */
 #define DP_LANE_COUNT_MASK		0xf
 
+/* Backlight configuration */
+#define DP_BACKLIGHT_MODE_SET			0x721
+#define DP_BACKLIGHT_CONTROL_MODE_MASK		0x3
+#define DP_BACKLIGHT_CONTROL_MODE_DPCD		0x2
+#define DP_DISPLAY_CONTROL_REGISTER		0x720
+#define DP_BACKLIGHT_ENABLE			0x1
+#define DP_BACKLIGHT_BRIGHTNESS_MSB		0x722
+
 /* link configuration */
 #define DP_LINK_BW_SET		0x100
 #define DP_LINK_BW_1_62		0x06
@@ -125,6 +132,17 @@ enum vstream_config {
 	VSTREAM_ENABLE = 1,
 };
 
+enum i2c_over_aux {
+	I2C_OVER_AUX_WRITE_MOT_0 = 0x0,
+	I2C_OVER_AUX_READ_MOT_0 = 0x1,
+	I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2,
+	I2C_OVER_AUX_WRITE_MOT_1 = 0x4,
+	I2C_OVER_AUX_READ_MOT_1 = 0x5,
+	I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6,
+	NATIVE_AUX_WRITE = 0x8,
+	NATIVE_AUX_READ = 0x9,
+};
+
 enum aux_cmd_status {
 	NAT_I2C_FAIL = 1 << 6,
 	AUX_SHORT = 1 << 5,
@@ -148,6 +166,21 @@ enum ml_tx_mode {
 	REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb,
 };
 
+enum aux_request {
+	DPCD_READ,
+	DPCD_WRITE,
+	I2C_RAW_READ,
+	I2C_RAW_WRITE,
+	I2C_RAW_READ_AND_STOP,
+	I2C_RAW_WRITE_AND_STOP,
+};
+
+enum {
+	EDID_LENGTH = 128,
+	EDID_I2C_ADDR = 0x50,
+	EDID_EXTENSION_FLAG = 0x7e,
+};
+
 /*
  * LUT index corresponds to register value and LUT values corresponds
  * to dp data rate supported by the bridge in Mbps unit.
@@ -156,6 +189,41 @@ static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = {
 	0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 };
 
+static bool request_is_write(enum aux_request request)
+{
+	switch (request) {
+	case I2C_RAW_WRITE_AND_STOP:
+	case I2C_RAW_WRITE:
+	case DPCD_WRITE:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this)
+{
+	switch (request) {
+	case I2C_RAW_WRITE_AND_STOP:
+		if (!remaining_after_this)
+			return I2C_OVER_AUX_WRITE_MOT_0;
+		/* fallthrough */
+	case I2C_RAW_WRITE:
+		return I2C_OVER_AUX_WRITE_MOT_1;
+	case I2C_RAW_READ_AND_STOP:
+		if (!remaining_after_this)
+			return I2C_OVER_AUX_READ_MOT_0;
+		/* fallthrough */
+	case I2C_RAW_READ:
+		return I2C_OVER_AUX_READ_MOT_1;
+	case DPCD_WRITE:
+		return NATIVE_AUX_WRITE;
+	case DPCD_READ:
+	default:
+		return NATIVE_AUX_READ;
+	}
+}
+
 static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 					     uint8_t chip,
 					     unsigned int target_reg,
@@ -173,10 +241,10 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 		   NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT);
 
 	while (total_size) {
-		length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES);
+		length = MIN(total_size, 16);
 		total_size -= length;
 
-		enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size);
+		enum i2c_over_aux cmd = get_aux_cmd(request, total_size);
 		if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) ||
 		    i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) ||
 		    i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) ||
@@ -184,7 +252,7 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 		    i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length))
 			return CB_ERR;
 
-		if (dp_aux_request_is_write(request)) {
+		if (request_is_write(request)) {
 			reg = SN_AUX_WDATA_REG_0;
 			for (i = 0; i < length; i++)
 				if (i2c_writeb(bus, chip, reg++, *data++))
@@ -205,7 +273,7 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 			return CB_ERR;
 		}
 
-		if (!dp_aux_request_is_write(request)) {
+		if (!request_is_write(request)) {
 			reg = SN_AUX_RDATA_REG_0;
 			for (i = 0; i < length; i++) {
 				if (i2c_readb(bus, chip, reg++, &buf))

src/drivers/uart/oxpcie.c

@@ -12,7 +12,7 @@ static void oxford_oxpcie_enable(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
 
-	struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
 		return;

src/drivers/usb/pci_ehci.c

@@ -75,7 +75,7 @@ static void pci_ehci_set_resources(struct device *dev)
 
 	if (ehci_drv_ops->set_resources)
 		ehci_drv_ops->set_resources(dev);
-	res = probe_resource(dev, EHCI_BAR_INDEX);
+	res = find_resource(dev, EHCI_BAR_INDEX);
 	if (!res)
 		return;
 

src/ec/google/chromeec/vboot_storage.c

@@ -3,7 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <security/vboot/vboot_common.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #define VBOOT_HASH_VSLOT 0
 #define VBOOT_HASH_VSLOT_MASK (1 << (VBOOT_HASH_VSLOT))

src/include/cbfs.h

@@ -97,21 +97,6 @@ static inline void *cbfs_type_cbmem_alloc(const char *name, uint32_t cbmem_id, s
 static inline void *cbfs_ro_type_cbmem_alloc(const char *name, uint32_t cbmem_id,
 					     size_t *size_out, enum cbfs_type *type);
 
-/*
- * Starts the processes of preloading a file into RAM.
- *
- * This method depends on COOP_MULTITASKING to parallelize the loading. This method is only
- * effective when the underlying rdev supports DMA operations.
- *
- * When `cbfs_load`, `cbfs_alloc`, or `cbfs_map` are called after a preload has been started,
- * they will wait for the preload to complete (if it hasn't already) and then perform
- * verification and/or decompression.
- *
- * This method does not have a return value because the system should boot regardless if this
- * method succeeds or fails.
- */
-void cbfs_preload(const char *name);
-
 /* Removes a previously allocated CBFS mapping. Should try to unmap mappings in strict LIFO
    order where possible, since mapping backends often don't support more complicated cases. */
 void cbfs_unmap(void *mapping);

src/include/cpu/amd/mtrr.h

@@ -43,6 +43,7 @@
 #include <cpu/x86/msr.h>
 #include <stdint.h>
 
+void amd_setup_mtrrs(void);
 struct device;
 void add_uma_resource_below_tolm(struct device *nb, int idx);
 
@@ -66,16 +67,10 @@ static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
 		);
 }
 
-static inline uint64_t amd_topmem(void)
-{
-	return rdmsr(TOP_MEM).lo;
-}
-
-static inline uint64_t amd_topmem2(void)
-{
-	msr_t msr = rdmsr(TOP_MEM2);
-	return (uint64_t)msr.hi << 32 | msr.lo;
-}
+/* To distribute topmem MSRs to APs. */
+void setup_bsp_ramtop(void);
+uint64_t bsp_topmem(void);
+uint64_t bsp_topmem2(void);
 #endif
 
 #endif /* CPU_AMD_MTRR_H */

src/include/device/azalia_device.h

@@ -23,8 +23,6 @@ int azalia_enter_reset(u8 *base);
 int azalia_exit_reset(u8 *base);
 u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb);
 int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size);
-void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes);
-void azalia_codecs_init(u8 *base, u16 codec_mask);
 void azalia_audio_init(struct device *dev);
 extern struct device_operations default_azalia_audio_ops;
 
@@ -128,27 +126,26 @@ enum azalia_pin_location_2 {
 	ARRAY_SIZE(pc_beep_verbs);				\
 	const u32 cim_verb_data_size = sizeof(cim_verb_data)
 
-#define AZALIA_VERB_12B(codec, pin, verb, val)		\
-	((codec) << 28 | (pin) << 20 | (verb) << 8 | (val))
+#define AZALIA_PIN_CFG(codec, pin, val)			\
+	(((codec) << 28) | ((pin) << 20) | (0x71c << 8)	\
+		| ((val) & 0xff)),			\
+	(((codec) << 28) | ((pin) << 20) | (0x71d << 8)	\
+		| (((val) >> 8) & 0xff)),		\
+	(((codec) << 28) | ((pin) << 20) | (0x71e << 8)	\
+		| (((val) >> 16) & 0xff)),		\
+	(((codec) << 28) | ((pin) << 20) | (0x71f << 8)	\
+		| (((val) >> 24) & 0xff))
 
-#define AZALIA_PIN_CFG(codec, pin, val)					\
-	AZALIA_VERB_12B(codec, pin, 0x71c, ((val) >>  0) & 0xff),	\
-	AZALIA_VERB_12B(codec, pin, 0x71d, ((val) >>  8) & 0xff),	\
-	AZALIA_VERB_12B(codec, pin, 0x71e, ((val) >> 16) & 0xff),	\
-	AZALIA_VERB_12B(codec, pin, 0x71f, ((val) >> 24) & 0xff)
+#define AZALIA_PIN_CFG_NC(n)   (0x411111f0 | (n & 0xf))
 
-#define AZALIA_PIN_CFG_NC(n)   (0x411111f0 | ((n) & 0xf))
+#define AZALIA_RESET(pin)					\
+	(((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00),	\
+	(((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00)
 
-#define AZALIA_RESET(pin)			\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0),	\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0),	\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0),	\
-	AZALIA_VERB_12B(0, pin, 0x7ff, 0)
-
-#define AZALIA_SUBVENDOR(codec, val)				\
-	AZALIA_VERB_12B(codec, 1, 0x720, ((val) >>  0) & 0xff),	\
-	AZALIA_VERB_12B(codec, 1, 0x721, ((val) >>  8) & 0xff),	\
-	AZALIA_VERB_12B(codec, 1, 0x722, ((val) >> 16) & 0xff),	\
-	AZALIA_VERB_12B(codec, 1, 0x723, ((val) >> 24) & 0xff)
+#define AZALIA_SUBVENDOR(codec, val)		    \
+	(((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)),	\
+	(((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
+	(((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
+	(((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))
 
 #endif /* DEVICE_AZALIA_H */

src/include/device/device.h

@@ -148,17 +148,6 @@ struct device {
 	u8 smbios_slot_data_width;
 	u8 smbios_slot_length;
 	const char *smbios_slot_designation;
-
-#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
-	/*
-	 * These fields are intentionally guarded so that attempts to use
-	 * the corresponding devicetree syntax without selecting the Kconfig
-	 * option result in build-time errors. Smaller size is a side effect.
-	 */
-	bool smbios_instance_id_valid;
-	u8 smbios_instance_id;
-	const char *smbios_refdes;
-#endif
 #endif
 #endif
 	DEVTREE_CONST void *chip_info;

src/include/device/dram/spd.h

@@ -3,18 +3,8 @@
 #ifndef DEVICE_DRAM_SPD_H
 #define DEVICE_DRAM_SPD_H
 
-#include <smbios.h>
 #include <types.h>
 
 const char *spd_manufacturer_name(const uint16_t mod_id);
 
-struct spd_info {
-	uint16_t type_detail;
-	uint8_t form_factor;
-};
-
-void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info);
-uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor);
-
 #endif /* DEVICE_DRAM_SPD_H */

src/include/device/pci_ids.h

@@ -620,6 +620,8 @@
 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0		0x7916
 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1		0x7917
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD			0x7906
+#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS				0x790B
+#define PCI_DEVICE_ID_AMD_FAM17H_LPC				0x790E
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE			0x1458
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE			0x1641
 #define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97			0x1644
@@ -3332,10 +3334,6 @@
 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6		0x4b3d
 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7		0x4b3e
 
-#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1		0x464d
-#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2		0x460d
-#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3		0x463d
-
 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1		0x51b8
 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2		0x51b9
 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3		0x51ba

src/include/device/pci_mmio_cfg.h

@@ -7,6 +7,10 @@
 #include <device/mmio.h>
 #include <device/pci_type.h>
 
+/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
+ * prevent some sub-optimal constant folding. */
+extern u8 *const pci_mmconf;
+
 /* Using a unique datatype for MMIO writes makes the pointers to _not_
  * qualify for pointer aliasing with any other objects in memory.
  *
@@ -25,66 +29,44 @@ union pci_bank {
 	uint32_t reg32[4096 / sizeof(uint32_t)];
 };
 
-#if CONFIG(ECAM_MMCONF_SUPPORT)
-
-#if CONFIG_ECAM_MMCONF_BASE_ADDRESS == 0
-#error "CONFIG_ECAM_MMCONF_BASE_ADDRESS undefined!"
-#endif
-
-#if CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB != CONFIG_ECAM_MMCONF_LENGTH
-#error "CONFIG_ECAM_MMCONF_LENGTH does not correspond with CONFIG_ECAM_MMCONF_BUS_NUMBER!"
-#endif
-
-/* By not assigning this to CONFIG_ECAM_MMCONF_BASE_ADDRESS here we
-   prevent some sub-optimal constant folding. */
-extern u8 *const pci_mmconf;
-
 static __always_inline
 volatile union pci_bank *pcicfg(pci_devfn_t dev)
 {
 	return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)];
 }
 
-#endif
-
-/*
- * Avoid name collisions as different stages have different signature
- * for these functions. The _s_ stands for simple, fundamental IO or
- * MMIO variant.
- */
-
 static __always_inline
-uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
+uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
 {
 	return pcicfg(dev)->reg8[reg];
 }
 
 static __always_inline
-uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
+uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
 {
 	return pcicfg(dev)->reg16[reg / sizeof(uint16_t)];
 }
 
 static __always_inline
-uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
+uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
 {
 	return pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
 }
 
 static __always_inline
-void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
+void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
 {
 	pcicfg(dev)->reg8[reg] = value;
 }
 
 static __always_inline
-void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
+void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
 {
 	pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value;
 }
 
 static __always_inline
-void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
+void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
 {
 	pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value;
 }
@@ -113,4 +95,57 @@ uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg)
 	return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
 }
 
+#if CONFIG(MMCONF_SUPPORT)
+
+#if CONFIG_MMCONF_BASE_ADDRESS == 0
+#error "CONFIG_MMCONF_BASE_ADDRESS undefined!"
+#endif
+
+#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH
+#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!"
+#endif
+
+/* Avoid name collisions as different stages have different signature
+ * for these functions. The _s_ stands for simple, fundamental IO or
+ * MMIO variant.
+ */
+
+static __always_inline
+uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
+{
+	return pci_mmio_read_config8(dev, reg);
+}
+
+static __always_inline
+uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
+{
+	return pci_mmio_read_config16(dev, reg);
+}
+
+static __always_inline
+uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
+{
+	return pci_mmio_read_config32(dev, reg);
+}
+
+static __always_inline
+void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
+{
+	pci_mmio_write_config8(dev, reg, value);
+}
+
+static __always_inline
+void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
+{
+	pci_mmio_write_config16(dev, reg, value);
+}
+
+static __always_inline
+void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
+{
+	pci_mmio_write_config32(dev, reg, value);
+}
+
+#endif
+
 #endif /* _PCI_MMIO_CFG_H */

src/include/device/usbc_mux.h

@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __USBC_MUX_H__
-#define __USBC_MUX_H__
-
 /* struct to hold all USB-C mux related variables */
 struct usbc_mux_info {
 	bool dp; /* DP connected */
@@ -70,5 +67,3 @@ struct usbc_ops {
 };
 
 const struct usbc_ops *usbc_get_ops(void);
-
-#endif /* __USBC_MUX_H__ */

src/include/dimm_info_util.h

@@ -12,7 +12,7 @@
  * Use this when setting dimm_info.bus_width if the raw SPD values are not
  * available.
  */
-uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width,
+uint8_t smbios_bus_width_to_spd_width(uint16_t total_width,
 				      uint16_t data_width);
 
 /**
@@ -28,7 +28,7 @@ uint32_t smbios_memory_size_to_mib(uint16_t memory_size,
  *
  * Use this when setting dimm_info.mod_type.
  */
-uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor);
+uint8_t
+smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor);
 
 #endif

src/include/dp_aux.h

@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _DP_AUX_H_
-#define _DP_AUX_H_
-
-#include <types.h>
-
-enum {
-	EDID_LENGTH         = 128,
-	EDID_I2C_ADDR       = 0x50,
-	EDID_EXTENSION_FLAG = 0x7e,
-};
-
-enum i2c_over_aux {
-	I2C_OVER_AUX_WRITE_MOT_0 = 0x0,
-	I2C_OVER_AUX_READ_MOT_0 = 0x1,
-	I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2,
-	I2C_OVER_AUX_WRITE_MOT_1 = 0x4,
-	I2C_OVER_AUX_READ_MOT_1 = 0x5,
-	I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6,
-	NATIVE_AUX_WRITE = 0x8,
-	NATIVE_AUX_READ = 0x9,
-};
-
-enum aux_request {
-	DPCD_READ,
-	DPCD_WRITE,
-	I2C_RAW_READ,
-	I2C_RAW_WRITE,
-	I2C_RAW_READ_AND_STOP,
-	I2C_RAW_WRITE_AND_STOP,
-};
-
-/* Backlight configuration */
-#define DP_BACKLIGHT_MODE_SET			0x721
-#define DP_BACKLIGHT_CONTROL_MODE_MASK		0x3
-#define DP_BACKLIGHT_CONTROL_MODE_DPCD		0x2
-#define DP_DISPLAY_CONTROL_REGISTER		0x720
-#define DP_BACKLIGHT_ENABLE			0x1
-#define DP_BACKLIGHT_BRIGHTNESS_MSB		0x722
-
-#define DP_AUX_MAX_PAYLOAD_BYTES	16
-
-
-bool dp_aux_request_is_write(enum aux_request request);
-enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this);
-
-#endif

src/include/list.h

@@ -15,8 +15,6 @@ void list_remove(struct list_node *node);
 void list_insert_after(struct list_node *node, struct list_node *after);
 // Insert list_node node before list_node before in a doubly linked list.
 void list_insert_before(struct list_node *node, struct list_node *before);
-// Appends the node to the end of the list.
-void list_append(struct list_node *node, struct list_node *head);
 
 #define list_for_each(ptr, head, member)                                      \
 	for ((ptr) = container_of((head).next, typeof(*(ptr)), member);       \

src/include/rules.h

@@ -292,17 +292,6 @@
 #define ENV_INITIAL_STAGE		ENV_BOOTBLOCK
 #endif
 
-#if ENV_X86
-#define STAGE_HAS_SPINLOCKS		!ENV_ROMSTAGE_OR_BEFORE
-#elif ENV_RISCV
-#define STAGE_HAS_SPINLOCKS		1
-#else
-#define STAGE_HAS_SPINLOCKS		0
-#endif
-
-/* When set <arch/smp/spinlock.h> is included for the spinlock implementation. */
-#define ENV_STAGE_SUPPORTS_SMP		(CONFIG(SMP) && STAGE_HAS_SPINLOCKS)
-
 /**
  * For pre-DRAM stages and post-CAR always build with simple device model, ie.
  * PCI, PNP and CPU functions operate without use of devicetree. The reason

src/include/smp/spinlock.h

@@ -1,7 +1,7 @@
 #ifndef SMP_SPINLOCK_H
 #define SMP_SPINLOCK_H
 
-#if ENV_STAGE_SUPPORTS_SMP
+#if CONFIG(SMP)
 #include <arch/smp/spinlock.h>
 #else /* !CONFIG_SMP */
 

src/include/spd.h

@@ -197,70 +197,17 @@ enum spd_memory_type {
 #define MODULE_BUFFERED                  1
 #define MODULE_REGISTERED                2
 
-#define SPD_UNDEFINED 0x00
-#define SPD_ECC_8BIT (1<<3)
-#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
-
 /* Byte 3: Module type information */
-enum ddr2_module_type {
-	DDR2_SPD_RDIMM = 0x01,
-	DDR2_SPD_UDIMM = 0x02,
-	DDR2_SPD_SODIMM = 0x04,
-	DDR2_SPD_72B_SO_CDIMM = 0x06,
-	DDR2_SPD_72B_SO_RDIMM = 0x07,
-	DDR2_SPD_MICRO_DIMM = 0x08,
-	DDR2_SPD_MINI_RDIMM = 0x10,
-	DDR2_SPD_MINI_UDIMM = 0x20,
-};
+#define SPD_UNDEFINED 0x00
+#define SPD_RDIMM 0x01
+#define SPD_UDIMM 0x02
+#define SPD_SODIMM 0x04
+#define SPD_72B_SO_CDIMM 0x06
+#define SPD_72B_SO_RDIMM 0x07
+#define SPD_MICRO_DIMM 0x08
+#define SPD_MINI_RDIMM 0x10
+#define SPD_MINI_UDIMM 0x20
 
-enum ddr3_module_type {
-	DDR3_SPD_RDIMM = 0x01,
-	DDR3_SPD_UDIMM = 0x02,
-	DDR3_SPD_SODIMM = 0x03,
-	DDR3_SPD_MICRO_DIMM = 0x04,
-	DDR3_SPD_MINI_RDIMM = 0x05,
-	DDR3_SPD_MINI_UDIMM = 0x06,
-	DDR3_SPD_MINI_CDIMM = 0x07,
-	DDR3_SPD_72B_SO_UDIMM = 0x08,
-	DDR3_SPD_72B_SO_RDIMM = 0x09,
-	DDR3_SPD_72B_SO_CDIMM = 0x0a,
-	DDR3_SPD_LRDIMM = 0x0b,
-	DDR3_SPD_16B_SO_DIMM = 0x0c,
-	DDR3_SPD_32B_SO_RDIMM = 0x0d,
-};
-
-enum ddr4_module_type {
-	DDR4_SPD_RDIMM = 0x01,
-	DDR4_SPD_UDIMM = 0x02,
-	DDR4_SPD_SODIMM = 0x03,
-	DDR4_SPD_LRDIMM = 0x04,
-	DDR4_SPD_MINI_RDIMM = 0x05,
-	DDR4_SPD_MINI_UDIMM = 0x06,
-	DDR4_SPD_72B_SO_UDIMM = 0x08,
-	DDR4_SPD_72B_SO_RDIMM = 0x09,
-	DDR4_SPD_16B_SO_DIMM = 0x0c,
-	DDR4_SPD_32B_SO_RDIMM = 0x0d,
-};
-
-enum ddr5_module_type {
-	DDR5_SPD_RDIMM = 0x01,
-	DDR5_SPD_UDIMM = 0x02,
-	DDR5_SPD_SODIMM = 0x03,
-	DDR5_SPD_LRDIMM = 0x04,
-	DDR5_SPD_MINI_RDIMM = 0x05,
-	DDR5_SPD_MINI_UDIMM = 0x06,
-	DDR5_SPD_72B_SO_UDIMM = 0x08,
-	DDR5_SPD_72B_SO_RDIMM = 0x09,
-	DDR5_SPD_SOLDERED_DOWN = 0x0b,
-	DDR5_SPD_16B_SO_DIMM = 0x0c,
-	DDR5_SPD_32B_SO_RDIMM = 0x0d,
-	DDR5_SPD_1DPC = 0x0e,
-	DDR5_SPD_2DPC = 0x0f,
-};
-
-enum lpx_module_type {
-	LPX_SPD_LPDIMM = 0x07,
-	LPX_SPD_NONDIMM = 0x0e,
-};
+#define SPD_ECC_8BIT (1<<3)
 
 #endif

src/include/thread.h

@@ -5,7 +5,7 @@
 #include <arch/cpu.h>
 #include <bootstate.h>
 #include <commonlib/bsd/cb_err.h>
-#include <types.h>
+#include <stdint.h>
 
 struct thread_mutex {
 	bool locked;

src/lib/Kconfig

@@ -70,7 +70,7 @@ config HWBASE_DYNAMIC_MMIO
 
 config HWBASE_DEFAULT_MMCONF
 	hex
-	default ECAM_MMCONF_BASE_ADDRESS
+	default MMCONF_BASE_ADDRESS
 
 config HWBASE_DIRECT_PCIDEV
 	def_bool y
@@ -99,22 +99,6 @@ config NO_CBFS_MCACHE
 	  lookup must re-read the same CBFS directory entries from flash to find
 	  the respective file.
 
-config CBFS_CACHE_ALIGN
-	int
-	default 8
-	help
-	  Sets the alignment of the buffers returned by the cbfs_cache.
-
-config CBFS_PRELOAD
-	bool
-	depends on COOP_MULTITASKING
-	help
-	  When enabled it will be possible to preload CBFS files into the
-	  cbfs_cache. This helps reduce boot time by loading the files
-	  in the background before they are actually required. This feature
-	  depends on the read-only boot_device having a DMA controller to
-	  perform the background transfer.
-
 config PAYLOAD_PRELOAD
 	bool
 	depends on COOP_MULTITASKING

src/lib/Makefile.inc

@@ -28,8 +28,6 @@ CFLAGS_ramstage += $(CFLAGS_asan)
 $(obj)/ramstage/lib/asan.o: CFLAGS_asan =
 endif
 
-all-y += list.c
-
 decompressor-y += decompressor.c
 $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4
 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4
@@ -149,7 +147,6 @@ ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 ramstage-$(CONFIG_COVERAGE) += libgcov.c
-ramstage-y += dp_aux.c
 ramstage-y += edid.c
 ramstage-y += edid_fill_fb.c
 ramstage-y += memrange.c
@@ -157,6 +154,7 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 ramstage-y += b64_decode.c
 ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
+ramstage-y += list.c
 ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c

src/lib/cbfs.c

@@ -10,28 +10,25 @@
 #include <console/console.h>
 #include <fmap.h>
 #include <lib.h>
-#include <list.h>
 #include <metadata_hash.h>
 #include <security/tpm/tspi/crtm.h>
 #include <security/vboot/vboot_common.h>
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
-#include <thread.h>
 #include <timestamp.h>
 
 #if ENV_STAGE_HAS_DATA_SECTION
-struct mem_pool cbfs_cache =
-	MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN);
+struct mem_pool cbfs_cache = MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache));
 #else
-struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0);
+struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0);
 #endif
 
 static void switch_to_postram_cache(int unused)
 {
 	if (_preram_cbfs_cache != _postram_cbfs_cache)
-		mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache),
-			      CONFIG_CBFS_CACHE_ALIGN);
+		mem_pool_init(&cbfs_cache, _postram_cbfs_cache,
+			      REGION_SIZE(postram_cbfs_cache));
 }
 ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache);
 
@@ -268,156 +265,12 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b
 	}
 }
 
-struct cbfs_preload_context {
-	struct region_device rdev;
-	struct thread_handle handle;
-	struct list_node list_node;
-	void *buffer;
-	char name[];
-};
-
-static struct list_node cbfs_preload_context_list;
-
-static struct cbfs_preload_context *alloc_cbfs_preload_context(size_t additional)
-{
-	struct cbfs_preload_context *context;
-	size_t size = sizeof(*context) + additional;
-
-	context = mem_pool_alloc(&cbfs_cache, size);
-
-	if (!context)
-		return NULL;
-
-	memset(context, 0, size);
-
-	return context;
-}
-
-static void append_cbfs_preload_context(struct cbfs_preload_context *context)
-{
-	list_append(&context->list_node, &cbfs_preload_context_list);
-}
-
-static void free_cbfs_preload_context(struct cbfs_preload_context *context)
-{
-	list_remove(&context->list_node);
-
-	mem_pool_free(&cbfs_cache, context);
-}
-
-static enum cb_err cbfs_preload_thread_entry(void *arg)
-{
-	struct cbfs_preload_context *context = arg;
-
-	if (rdev_readat_full(&context->rdev, context->buffer) < 0) {
-		ERROR("%s(name='%s') readat failed\n", __func__, context->name);
-		return CB_ERR;
-	}
-
-	return CB_SUCCESS;
-}
-
-void cbfs_preload(const char *name)
-{
-	struct region_device rdev;
-	union cbfs_mdata mdata;
-	struct cbfs_preload_context *context;
-	bool force_ro = false;
-	size_t size;
-
-	if (!CONFIG(CBFS_PRELOAD))
-		dead_code();
-
-	DEBUG("%s(name='%s')\n", __func__, name);
-
-	if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev))
-		return;
-
-	size = region_device_sz(&rdev);
-
-	context = alloc_cbfs_preload_context(strlen(name) + 1);
-	if (!context) {
-		ERROR("%s(name='%s') failed to allocate preload context\n", __func__, name);
-		return;
-	}
-
-	context->buffer = mem_pool_alloc(&cbfs_cache, size);
-	if (context->buffer == NULL) {
-		ERROR("%s(name='%s') failed to allocate %zu bytes for preload buffer\n",
-		      __func__, name, size);
-		goto out;
-	}
-
-	context->rdev = rdev;
-	strcpy(context->name, name);
-
-	append_cbfs_preload_context(context);
-
-	if (thread_run(&context->handle, cbfs_preload_thread_entry, context) == 0)
-		return;
-
-	ERROR("%s(name='%s') failed to start preload thread\n", __func__, name);
-	mem_pool_free(&cbfs_cache, context->buffer);
-
-out:
-	free_cbfs_preload_context(context);
-}
-
-static struct cbfs_preload_context *find_cbfs_preload_context(const char *name)
-{
-	struct cbfs_preload_context *context;
-
-	list_for_each(context, cbfs_preload_context_list, list_node) {
-		if (strcmp(context->name, name) == 0)
-			return context;
-	}
-
-	return NULL;
-}
-
-static enum cb_err get_preload_rdev(struct region_device *rdev, const char *name)
-{
-	enum cb_err err;
-	struct cbfs_preload_context *context;
-
-	if (!CONFIG(CBFS_PRELOAD) || (!ENV_RAMSTAGE && !ENV_ROMSTAGE))
-		return CB_ERR_ARG;
-
-	context = find_cbfs_preload_context(name);
-	if (!context)
-		return CB_ERR_ARG;
-
-	err = thread_join(&context->handle);
-	if (err != CB_SUCCESS) {
-		ERROR("%s(name='%s') Preload thread failed: %u\n", __func__, name, err);
-
-		goto out;
-	}
-
-	if (rdev_chain_mem(rdev, context->buffer, region_device_sz(&context->rdev)) != 0) {
-		ERROR("%s(name='%s') chaining failed\n", __func__, name);
-
-		err = CB_ERR;
-		goto out;
-	}
-
-	err = CB_SUCCESS;
-
-	DEBUG("%s(name='%s') preload successful\n", __func__, name);
-
-out:
-	free_cbfs_preload_context(context);
-
-	return err;
-}
-
 void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 		  size_t *size_out, bool force_ro, enum cbfs_type *type)
 {
 	struct region_device rdev;
-	bool preload_successful = false;
 	union cbfs_mdata mdata;
-	void *loc = NULL;
+	void *loc;
 
 	DEBUG("%s(name='%s', alloc=%p(%p), force_ro=%s, type=%d)\n", __func__, name, allocator,
 	      arg, force_ro ? "true" : "false", type ? *type : -1);
@@ -452,10 +305,6 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 	if (CONFIG(CBFS_VERIFICATION))
 		file_hash = cbfs_file_hash(&mdata);
 
-	/* Update the rdev with the preload content */
-	if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS)
-		preload_successful = true;
-
 	/* allocator == NULL means do a cbfs_map() */
 	if (allocator) {
 		loc = allocator(arg, size, &mdata);
@@ -463,11 +312,11 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 		void *mapping = rdev_mmap_full(&rdev);
 
 		if (!mapping)
-			goto out;
+			return NULL;
 
 		if (cbfs_file_hash_mismatch(mapping, size, file_hash)) {
 			rdev_munmap(&rdev, mapping);
-			goto out;
+			return NULL;
 		}
 
 		return mapping;
@@ -478,28 +327,19 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 		 * it is not possible to add a CBFS_CACHE.
 		 */
 		ERROR("Cannot map compressed file %s without cbfs_cache\n", mdata.h.filename);
-		goto out;
+		return NULL;
 	} else {
 		loc = mem_pool_alloc(&cbfs_cache, size);
 	}
 
 	if (!loc) {
 		ERROR("'%s' allocation failure\n", mdata.h.filename);
-		goto out;
+		return NULL;
 	}
 
 	size = cbfs_load_and_decompress(&rdev, loc, size, compression, file_hash);
-
 	if (!size)
-		loc = NULL;
-
-out:
-	/*
-	 * When using cbfs_preload we need to free the preload buffer after populating the
-	 * destination buffer.
-	 */
-	if (preload_successful)
-		cbfs_unmap(rdev_mmap_full(&rdev));
+		return NULL;
 
 	return loc;
 }

src/lib/dimm_info_util.c

@@ -1,13 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/dram/spd.h>
 #include <dimm_info_util.h>
 #include <smbios.h>
 #include <spd.h>
 #include <console/console.h>
 
-uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width,
-				      uint16_t data_width)
+uint8_t smbios_bus_width_to_spd_width(uint16_t total_width, uint16_t data_width)
 {
 	uint8_t out;
 
@@ -40,10 +38,7 @@ uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width,
 
 	switch (extension_bits) {
 	case 8:
-		if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5)
-			out |= SPD_ECC_8BIT_LP5_DDR5;
-		else
-			out |= SPD_ECC_8BIT;
+		out |= SPD_ECC_8BIT;
 		break;
 	case 0:
 		/* No extension bits */
@@ -73,8 +68,18 @@ uint32_t smbios_memory_size_to_mib(uint16_t memory_size, uint32_t extended_size)
 		return memory_size;
 }
 
-uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor)
+uint8_t
+smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor)
 {
-	return convert_form_factor_to_module_type(memory_type, form_factor);
+	/* This switch reverses the switch in smbios.c */
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_DIMM:
+		return SPD_UDIMM;
+	case MEMORY_FORMFACTOR_RIMM:
+		return SPD_RDIMM;
+	case MEMORY_FORMFACTOR_SODIMM:
+		return SPD_SODIMM;
+	default:
+		return SPD_UNDEFINED;
+	}
 }

src/lib/dp_aux.c

@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <delay.h>
-#include <dp_aux.h>
-#include <console/console.h>
-#include <timer.h>
-
-bool dp_aux_request_is_write(enum aux_request request)
-{
-	switch (request) {
-	case I2C_RAW_WRITE_AND_STOP:
-	case I2C_RAW_WRITE:
-	case DPCD_WRITE:
-		return true;
-	default:
-		return false;
-	}
-}
-
-enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this)
-{
-	switch (request) {
-	case I2C_RAW_WRITE_AND_STOP:
-		if (!remaining_after_this)
-			return I2C_OVER_AUX_WRITE_MOT_0;
-		/* fallthrough */
-	case I2C_RAW_WRITE:
-		return I2C_OVER_AUX_WRITE_MOT_1;
-	case I2C_RAW_READ_AND_STOP:
-		if (!remaining_after_this)
-			return I2C_OVER_AUX_READ_MOT_0;
-		/* fallthrough */
-	case I2C_RAW_READ:
-		return I2C_OVER_AUX_READ_MOT_1;
-	case DPCD_WRITE:
-		return NATIVE_AUX_WRITE;
-	case DPCD_READ:
-	default:
-		return NATIVE_AUX_READ;
-	}
-}

src/lib/fw_config.c

@@ -11,7 +11,6 @@
 #include <lib.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include <drivers/vpd/vpd.h>
 
 uint64_t fw_config_get(void)
 {
@@ -22,40 +21,30 @@ uint64_t fw_config_get(void)
 	if (fw_config_value_initialized)
 		return fw_config_value;
 	fw_config_value_initialized = true;
-	fw_config_value = UNDEFINED_FW_CONFIG;
+
+	/* Look in CBFS to allow override of value. */
+	if (CONFIG(FW_CONFIG_SOURCE_CBFS)) {
+		if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value,
+			      sizeof(fw_config_value)) != sizeof(fw_config_value)) {
+			printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n",
+			       __func__);
+			fw_config_value = UNDEFINED_FW_CONFIG;
+		} else {
+			printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n",
+			       fw_config_value);
+			return fw_config_value;
+		}
+	}
 
 	/* Read the value from EC CBI. */
 	if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) {
-		if (google_chromeec_cbi_get_fw_config(&fw_config_value))
-			printk(BIOS_WARNING, "%s: Could not get fw_config from CBI\n",
-				__func__);
-		else
-			printk(BIOS_INFO, "FW_CONFIG value from CBI is 0x%" PRIx64 "\n",
-				fw_config_value);
-	}
-
-	/* Look in CBFS to allow override of value. */
-	if (CONFIG(FW_CONFIG_SOURCE_CBFS) && fw_config_value == UNDEFINED_FW_CONFIG) {
-		if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value,
-			      sizeof(fw_config_value)) != sizeof(fw_config_value))
-			printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n",
-				__func__);
-		else
-			printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n",
-				fw_config_value);
-	}
-
-	if (CONFIG(FW_CONFIG_SOURCE_VPD) && fw_config_value == UNDEFINED_FW_CONFIG) {
-		int vpd_value;
-		if (vpd_get_int("fw_config", VPD_RW_THEN_RO, &vpd_value)) {
-			fw_config_value = vpd_value;
-			printk(BIOS_INFO, "FW_CONFIG value from VPD is 0x%" PRIx64 "\n",
-				fw_config_value);
-		} else
-			printk(BIOS_WARNING, "%s: Could not get fw_config from vpd\n",
-				__func__);
+		if (google_chromeec_cbi_get_fw_config(&fw_config_value)) {
+			printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__);
+			fw_config_value = UNDEFINED_FW_CONFIG;
+		}
 	}
 
+	printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value);
 	return fw_config_value;
 }
 

src/lib/list.c

@@ -28,11 +28,3 @@ void list_insert_before(struct list_node *node, struct list_node *before)
 	if (node->prev)
 		node->prev->next = node;
 }
-
-void list_append(struct list_node *node, struct list_node *head)
-{
-	while (head->next)
-		head = head->next;
-
-	list_insert_after(node, head);
-}