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ArmPlatformPkg: Remove PcdStandalone from Sec module and Introduce ArmPlatformSecExtraAction()

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The PcdStandalone is a PCD ARM Ltd uses to make the difference between a standalone UEFI (boot
from cold boot to Boot Manager without user intervention) and a Debug UEFI firmware (the firmware
engineer has to copy the Normale World image into the DRAM to enable his/her firmware).

By coping the firmware into DRAM in the non standalone version it is much faster than reflashing
the NOR Flash after each build.

ArmPlatformSecExtraAction() function is called just before the Sec module jump to normal world.
The platform firmware can run extra actions at this stage.
The 'ARM Standalone' concept has moved to the implementation of ArmPlatformSecExtraAction() for
the ARM development boards (in ArmPlatformPkg/Library/DebugSecExtraActionLib).


ArmPlatformPkg: Enable DebugAgentLib in Sec and PrePeiCore


ArmPlatformPkg: Fix line endings in some source files

Use CR+LF line endings as defined by the EDK2 coding convention




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11991 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-07-06 16:07:54 +00:00
parent 70aa21d5d6
commit a6caee65ac
29 changed files with 1161 additions and 1036 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
ArmPkg/ArmPkg.dec
View File

@ -57,7 +57,6 @@
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025 gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025
gArmTokenSpaceGuid.PcdSkipPeiCore|FALSE|BOOLEAN|0x00000026
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file. # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.

590
ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm
View File

@ -1,297 +1,297 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// //
// Use ARMv6 instruction to operate on a single stack // Use ARMv6 instruction to operate on a single stack
// //
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
// //
// This program and the accompanying materials // This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License // are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at // which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php // http://opensource.org/licenses/bsd-license.php
// //
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
// //
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
#include <Library/PcdLib.h>
/*
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
R3 0x0c
R4 0x10
R5 0x14
R6 0x18
R7 0x1c
R8 0x20
R9 0x24
R10 0x28
R11 0x2c
R12 0x30
SP 0x34 # reserved via adding 0x20 (32) to the SP
LR 0x38
PC 0x3c
CPSR 0x40
DFSR 0x44
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
EXPORT ExceptionHandlersStart
EXPORT ExceptionHandlersEnd
EXPORT CommonExceptionEntry
EXPORT AsmCommonExceptionEntry
IMPORT CommonCExceptionHandler
PRESERVE8
AREA DxeExceptionHandlers, CODE, READONLY
ALIGN 32
//
// This code gets copied to the ARM vector table
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
//
ExceptionHandlersStart
Reset
b ResetEntry
UndefinedInstruction
b UndefinedInstructionEntry
SoftwareInterrupt
b SoftwareInterruptEntry
PrefetchAbort
b PrefetchAbortEntry
DataAbort
b DataAbortEntry
ReservedException
b ReservedExceptionEntry
Irq
b IrqEntry
Fiq
b FiqEntry
ResetEntry
srsfd #0x13! ; Store return state on SVC stack
; We are already in SVC mode
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#0 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
UndefinedInstructionEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#1 ; ExceptionType
ldr R1,CommonExceptionEntry;
bx R1
SoftwareInterruptEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
; We are already in SVC mode
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#2 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
PrefetchAbortEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#3 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
DataAbortEntry
sub LR,LR,#8
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#4 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
ReservedExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#5 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
IrqEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#6 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
FiqEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
; Since we have already switch to SVC R8_fiq - R12_fiq
; never get used or saved
mov R0,#7 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
//
// This gets patched by the C code that patches in the vector table
//
CommonExceptionEntry
dcd AsmCommonExceptionEntry
ExceptionHandlersEnd
//
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
AsmCommonExceptionEntry
mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1df))
cmpne R3, #0x10 ;
stmeqed R2, {lr}^ ; save unbanked lr
; else
stmneed R2, {lr} ; save SVC lr
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
; Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType ==2)) {
cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 ; PC += 2;
str R5,[SP,#0x58] ; Update LR value pused by srsfd
NoAdjustNeeded
str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
sub R1, SP, #0x60 ; We pused 0x60 bytes on the stack
str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
; R0 is ExceptionType
mov R1,SP ; R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} ; save vstm registers in case they are used in optimizations
#endif
/*
VOID
EFIAPI
CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, R0
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
)
*/
blx CommonCExceptionHandler ; Call exception handler
#if (FixedPcdGet32(PcdVFPEnabled)) #include <Library/PcdLib.h>
/*
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
R3 0x0c
R4 0x10
R5 0x14
R6 0x18
R7 0x1c
R8 0x20
R9 0x24
R10 0x28
R11 0x2c
R12 0x30
SP 0x34 # reserved via adding 0x20 (32) to the SP
LR 0x38
PC 0x3c
CPSR 0x40
DFSR 0x44
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
EXPORT ExceptionHandlersStart
EXPORT ExceptionHandlersEnd
EXPORT CommonExceptionEntry
EXPORT AsmCommonExceptionEntry
IMPORT CommonCExceptionHandler
PRESERVE8
AREA DxeExceptionHandlers, CODE, READONLY
ALIGN 32
//
// This code gets copied to the ARM vector table
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
//
ExceptionHandlersStart
Reset
b ResetEntry
UndefinedInstruction
b UndefinedInstructionEntry
SoftwareInterrupt
b SoftwareInterruptEntry
PrefetchAbort
b PrefetchAbortEntry
DataAbort
b DataAbortEntry
ReservedException
b ReservedExceptionEntry
Irq
b IrqEntry
Fiq
b FiqEntry
ResetEntry
srsfd #0x13! ; Store return state on SVC stack
; We are already in SVC mode
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#0 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
UndefinedInstructionEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#1 ; ExceptionType
ldr R1,CommonExceptionEntry;
bx R1
SoftwareInterruptEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
; We are already in SVC mode
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#2 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
PrefetchAbortEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#3 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
DataAbortEntry
sub LR,LR,#8
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#4 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
ReservedExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#5 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
IrqEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#6 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
FiqEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
; Since we have already switch to SVC R8_fiq - R12_fiq
; never get used or saved
mov R0,#7 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
//
// This gets patched by the C code that patches in the vector table
//
CommonExceptionEntry
dcd AsmCommonExceptionEntry
ExceptionHandlersEnd
//
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
AsmCommonExceptionEntry
mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1df))
cmpne R3, #0x10 ;
stmeqed R2, {lr}^ ; save unbanked lr
; else
stmneed R2, {lr} ; save SVC lr
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
; Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType ==2)) {
cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 ; PC += 2;
str R5,[SP,#0x58] ; Update LR value pused by srsfd
NoAdjustNeeded
str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
sub R1, SP, #0x60 ; We pused 0x60 bytes on the stack
str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
; R0 is ExceptionType
mov R1,SP ; R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} ; save vstm registers in case they are used in optimizations
#endif
/*
VOID
EFIAPI
CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, R0
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
)
*/
blx CommonCExceptionHandler ; Call exception handler
#if (FixedPcdGet32(PcdVFPEnabled))
vpop {d0-d15} vpop {d0-d15}
#endif #endif
ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 ; Write IFSR mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 ; Write DFSR mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR
str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R1, R1, #0x1f ; Check to see if User or System Mode and R1, R1, #0x1f ; Check to see if User or System Mode
cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f)) cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R1, #0x10 ; cmpne R1, #0x10 ;
ldmeqed R2, {lr}^ ; restore unbanked lr ldmeqed R2, {lr}^ ; restore unbanked lr
; else ; else
ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR} ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}
ldmfd SP!,{R0-R12} ; Restore general purpose registers ldmfd SP!,{R0-R12} ; Restore general purpose registers
; Exception handler can not change SP ; Exception handler can not change SP
add SP,SP,#0x20 ; Clear out the remaining stack space add SP,SP,#0x20 ; Clear out the remaining stack space
ldmfd SP!,{LR} ; restore the link register for this context ldmfd SP!,{LR} ; restore the link register for this context
rfefd SP! ; return from exception via srsfd stack slot rfefd SP! ; return from exception via srsfd stack slot
END END

30
ArmPkg/Library/CompilerIntrinsicsLib/Arm/sourcery.S
View File

@ -1,18 +1,18 @@
#------s------------------------------------------------------------------------ #------s------------------------------------------------------------------------
# #
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at # which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php # http://opensource.org/licenses/bsd-license.php
# #
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
.text .text
.align 2 .align 2
GCC_ASM_EXPORT(__aeabi_ulcmp) GCC_ASM_EXPORT(__aeabi_ulcmp)

6
ArmPlatformPkg/ArmPlatformPkg.dec
View File

@ -41,11 +41,15 @@
[PcdsFeatureFlag.common] [PcdsFeatureFlag.common]
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file. # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmPlatformTokenSpaceGuid.PcdStandalone|0|UINT32|0x00000001
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003 gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
# Stack for CPU Cores in Secure Mode # Stack for CPU Cores in Secure Mode

12
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
View File

@ -123,6 +123,8 @@
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
# 1/123 faster than Stm or Vstm version # 1/123 faster than Stm or Vstm version
@ -261,7 +263,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
!endif !endif
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
@ -341,8 +344,6 @@
# #
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
gArmPlatformTokenSpaceGuid.PcdStandalone|1
# Stack for CPU Cores in Secure Mode # Stack for CPU Cores in Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Size of SEC Stack for Secure World gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Size of SEC Stack for Secure World
@ -445,7 +446,10 @@
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
} }
!else !else
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {
<LibraryClasses>
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf { MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses> <LibraryClasses>

18
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
View File

@ -114,6 +114,8 @@
# ARM PL011 UART Driver # ARM PL011 UART Driver
PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
@ -124,6 +126,8 @@
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
# 1/123 faster than Stm or Vstm version # 1/123 faster than Stm or Vstm version
@ -134,9 +138,8 @@
# L2 Cache Driver # L2 Cache Driver
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure # ARM PL390 General Interrupt Driver in Secure
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@ -263,7 +266,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
!endif !endif
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
@ -343,7 +347,6 @@
# #
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000
gArmPlatformTokenSpaceGuid.PcdStandalone|1
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1 gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
# Stacks for MPCores in Secure World # Stacks for MPCores in Secure World
@ -446,13 +449,16 @@
# PEI Phase modules # PEI Phase modules
# #
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiMPCore.inf{ ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses> <LibraryClasses>
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
} }
!else !else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses>
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf { MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses> <LibraryClasses>

5
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
View File

@ -37,10 +37,5 @@
ArmRealViewEbHelper.asm | RVCT ArmRealViewEbHelper.asm | RVCT
ArmRealViewEbHelper.S | GCC ArmRealViewEbHelper.S | GCC
[Protocols]
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone

7
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
View File

@ -13,7 +13,7 @@
[Defines] [Defines]
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005
BASE_NAME = ArmRealViewEbLib BASE_NAME = ArmRealViewEbSecLib
FILE_GUID = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b FILE_GUID = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b
MODULE_TYPE = BASE MODULE_TYPE = BASE
VERSION_STRING = 1.0 VERSION_STRING = 1.0
@ -37,10 +37,5 @@
ArmRealViewEbBoot.asm | RVCT ArmRealViewEbBoot.asm | RVCT
ArmRealViewEbBoot.S | GCC ArmRealViewEbBoot.S | GCC
[Protocols]
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone

170
ArmPlatformPkg/ArmRealViewEbPkg/Library/GdbSerialLib/GdbSerialLib.c
View File

@ -1,51 +1,51 @@
/** @file /** @file
Basic serial IO abstaction for GDB Basic serial IO abstaction for GDB
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/ **/
#include <Uefi.h> #include <Uefi.h>
#include <Library/GdbSerialLib.h> #include <Library/GdbSerialLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Drivers/PL011Uart.h> #include <Drivers/PL011Uart.h>
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
GdbSerialLibConstructor ( GdbSerialLibConstructor (
VOID VOID
) )
{ {
return GdbSerialInit (115200, 0, 8, 1); return GdbSerialInit (115200, 0, 8, 1);
} }
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
GdbSerialInit ( GdbSerialInit (
IN UINT64 BaudRate, IN UINT64 BaudRate,
IN UINT8 Parity, IN UINT8 Parity,
IN UINT8 DataBits, IN UINT8 DataBits,
IN UINT8 StopBits IN UINT8 StopBits
) )
{ {
if ((Parity != 0) || (DataBits != 8) || (StopBits != 1)) { if ((Parity != 0) || (DataBits != 8) || (StopBits != 1)) {
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
if (BaudRate != 115200) { if (BaudRate != 115200) {
// Could add support for different Baud rates.... // Could add support for different Baud rates....
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
UINT32 Base = PcdGet32 (PcdGdbUartBase); UINT32 Base = PcdGet32 (PcdGdbUartBase);
// initialize baud rate generator to 115200 based on EB clock REFCLK24MHZ // initialize baud rate generator to 115200 based on EB clock REFCLK24MHZ
@ -62,14 +62,14 @@ GdbSerialInit (
MmioWrite32 (Base + UARTCR, 0x301); MmioWrite32 (Base + UARTCR, 0x301);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
BOOLEAN BOOLEAN
EFIAPI EFIAPI
GdbIsCharAvailable ( GdbIsCharAvailable (
VOID VOID
) )
{ {
UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR; UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;
if ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0) { if ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0) {
@ -77,42 +77,42 @@ GdbIsCharAvailable (
} else { } else {
return FALSE; return FALSE;
} }
} }
CHAR8 CHAR8
EFIAPI EFIAPI
GdbGetChar ( GdbGetChar (
VOID VOID
) )
{ {
UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR; UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;
UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR; UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;
while ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0); while ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0);
return MmioRead8 (DR); return MmioRead8 (DR);
} }
VOID VOID
EFIAPI EFIAPI
GdbPutChar ( GdbPutChar (
IN CHAR8 Char IN CHAR8 Char
) )
{ {
UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR; UINT32 FR = PcdGet32 (PcdGdbUartBase) + UARTFR;
UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR; UINT32 DR = PcdGet32 (PcdGdbUartBase) + UARTDR;
while ((MmioRead32 (FR) & UART_TX_EMPTY_FLAG_MASK) != 0); while ((MmioRead32 (FR) & UART_TX_EMPTY_FLAG_MASK) != 0);
MmioWrite8 (DR, Char); MmioWrite8 (DR, Char);
return; return;
} }
VOID VOID
GdbPutString ( GdbPutString (
IN CHAR8 *String IN CHAR8 *String
) )
{ {
while (*String != '\0') { while (*String != '\0') {
GdbPutChar (*String); GdbPutChar (*String);
String++; String++;
} }
} }

22
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
View File

@ -136,6 +136,7 @@
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@ -284,10 +285,18 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_ARMVE_STANDALONE) == 1
gArmTokenSpaceGuid.PcdSkipPeiCore|TRUE gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
!else
gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
!endif !endif
!if $(EDK2_SKIP_PEICORE) == 1
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
!endif
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
# It could be set FALSE to save size. # It could be set FALSE to save size.
@ -377,10 +386,6 @@
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1 gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
gArmTokenSpaceGuid.PcdVFPEnabled|1 gArmTokenSpaceGuid.PcdVFPEnabled|1
!if $(EDK2_ARMVE_STANDALONE) == 1
gArmPlatformTokenSpaceGuid.PcdStandalone|1
!endif
# Stacks for MPCores in Secure World # Stacks for MPCores in Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000 # Top of SEC Stack for Secure World gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x49E00000 # Top of SEC Stack for Secure World
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0x2000 # Stack for each of the 4 CPU cores
@ -493,7 +498,10 @@
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
} }
!else !else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses>
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf { MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses> <LibraryClasses>

4
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
View File

@ -42,15 +42,11 @@
CTA9x4Helper.asm | RVCT CTA9x4Helper.asm | RVCT
CTA9x4Helper.S | GCC CTA9x4Helper.S | GCC
[Protocols]
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd] [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdSystemMemorySize

5
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
View File

@ -30,6 +30,7 @@
ArmLib ArmLib
ArmTrustZoneLib ArmTrustZoneLib
ArmPlatformSysConfigLib ArmPlatformSysConfigLib
DebugSecExtraActionLib
IoLib IoLib
L2X0CacheLib L2X0CacheLib
PL301AxiLib PL301AxiLib
@ -45,13 +46,9 @@
CTA9x4Boot.asm | RVCT CTA9x4Boot.asm | RVCT
CTA9x4Boot.S | GCC CTA9x4Boot.S | GCC
[Protocols]
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd] [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdL2x0ControllerBase gArmTokenSpaceGuid.PcdL2x0ControllerBase

2
ArmPlatformPkg/Bds/BootMenu.c
View File

@ -405,7 +405,7 @@ BootMenuMain (
BootOption = NULL; BootOption = NULL;
BootMainEntryCount = sizeof(BootMainEntries) / sizeof(struct BOOT_MAIN_ENTRY); BootMainEntryCount = sizeof(BootMainEntries) / sizeof(struct BOOT_MAIN_ENTRY);
// Get Boot#### list // Get Boot#### list
BootOptionList (&BootOptionsList); BootOptionList (&BootOptionsList);

13
ArmPlatformPkg/Include/Library/ArmPlatformLib.h
View File

@ -94,6 +94,19 @@ ArmPlatformSecInitialize (
VOID VOID
); );
/**
Call before jumping to Normal World
This function allows the firmware platform to do extra actions before
jumping to the Normal World
**/
VOID
ArmPlatformSecExtraAction (
IN UINTN CoreId,
OUT UINTN* JumpAddress
);
/** /**
Initialize controllers that must setup in the normal world Initialize controllers that must setup in the normal world

103
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c Executable file
View File

@ -0,0 +1,103 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include <Drivers/PL390Gic.h>
#define ARM_PRIMARY_CORE 0
// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
VOID
NonSecureWaitForFirmware (
VOID
)
{
VOID (*secondary_start)(VOID);
// The secondary cores will execute the firmware once wake from WFI.
secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
// Jump to secondary core entry point.
secondary_start ();
// PEI Core should always load and never return
ASSERT (FALSE);
}
/**
Call before jumping to Normal World
This function allows the firmware platform to do extra actions before
jumping to the Normal World
**/
VOID
ArmPlatformSecExtraAction (
IN UINTN CoreId,
OUT UINTN* JumpAddress
)
{
CHAR8 Buffer[100];
UINTN CharCount;
if (FeaturePcdGet (PcdStandalone) == FALSE) {
if (CoreId == ARM_PRIMARY_CORE) {
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
// Patch the DRAM to make an infinite loop at the start address
*StartAddress = 0xEAFFFFFE; // opcode for while(1)
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
} else {
// When the primary core is stopped by the hardware debugger to copy the firmware
// into DRAM. The secondary cores are still running. As soon as the first bytes of
// the firmware are written into DRAM, the secondary cores will start to execute the
// code even if the firmware is not entirely written into the memory.
// That's why the secondary cores need to be parked in WFI and wake up once the
// firmware is ready.
*JumpAddress = (UINTN)NonSecureWaitForFirmware;
}
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
if (CoreId == ARM_PRIMARY_CORE) {
// Signal the secondary cores they can jump to PEI phase
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
// To enter into Non Secure state, we need to make a return from exception
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
} else {
// We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
// cores would make crash the system by setting their stacks in DRAM before the primary core has not
// finished to initialize the system memory.
*JumpAddress = (UINTN)NonSecureWaitForFirmware;
}
} else {
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
}
}

51
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf Executable file
View File

@ -0,0 +1,51 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DebugSecExtraActionLib
FILE_GUID = 8fff7a60-a6f8-11e0-990a-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugSecExtraActionLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = ARM
#
[Sources.common]
DebugSecExtraActionLib.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
DebugLib
PcdLib
PL390GicSecLib
PrintLib
SerialPortLib
[FeaturePcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

196
ArmPlatformPkg/PrePeiCore/Exception.S
View File

@ -1,102 +1,102 @@
// //
// Copyright (c) 2011, ARM Limited. All rights reserved. // Copyright (c) 2011, ARM Limited. All rights reserved.
// //
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at # which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php # http://opensource.org/licenses/bsd-license.php
# #
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
# #
# #
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Base.h> #include <Base.h>
#include <AutoGen.h> #include <AutoGen.h>
#start of the code section #start of the code section
.text .text
.align 5 .align 5
# IMPORT # IMPORT
GCC_ASM_IMPORT(PeiCommonExceptionEntry) GCC_ASM_IMPORT(PeiCommonExceptionEntry)
# EXPORT
GCC_ASM_EXPORT(PeiVectorTable)
//============================================================ # EXPORT
//Default Exception Handlers GCC_ASM_EXPORT(PeiVectorTable)
//============================================================
//============================================================
//Default Exception Handlers
ASM_PFX(PeiVectorTable): //============================================================
b _DefaultResetHandler
b _DefaultUndefined
b _DefaultSWI ASM_PFX(PeiVectorTable):
b _DefaultPrefetchAbort b _DefaultResetHandler
b _DefaultDataAbort b _DefaultUndefined
b _DefaultReserved b _DefaultSWI
b _DefaultIrq b _DefaultPrefetchAbort
b _DefaultFiq b _DefaultDataAbort
b _DefaultReserved
// b _DefaultIrq
// Default Exception handlers: There is no plan to return from any of these exceptions. b _DefaultFiq
// No context saving at all.
// //
_DefaultResetHandler: // Default Exception handlers: There is no plan to return from any of these exceptions.
mov r1, lr // No context saving at all.
# Switch to SVC for common stack //
cps #0x13 _DefaultResetHandler:
mov r0, #0 mov r1, lr
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultUndefined: mov r0, #0
sub r1, LR, #4 blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultUndefined:
mov r0, #1 sub r1, LR, #4
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultSWI: mov r0, #1
sub r1, LR, #4 blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultSWI:
mov r0, #2 sub r1, LR, #4
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultPrefetchAbort: mov r0, #2
sub r1, LR, #4 blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultPrefetchAbort:
mov r0, #3 sub r1, LR, #4
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultDataAbort: mov r0, #3
sub r1, LR, #8 blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultDataAbort:
mov r0, #4 sub r1, LR, #8
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultReserved: mov r0, #4
mov r1, lr blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultReserved:
mov r0, #5 mov r1, lr
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultIrq: mov r0, #5
sub r1, LR, #4 blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultIrq:
mov r0, #6 sub r1, LR, #4
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
_DefaultFiq: mov r0, #6
sub r1, LR, #4 blx ASM_PFX(PeiCommonExceptionEntry)
# Switch to SVC for common stack
cps #0x13 _DefaultFiq:
mov r0, #7 sub r1, LR, #4
blx ASM_PFX(PeiCommonExceptionEntry) # Switch to SVC for common stack
cps #0x13
mov r0, #7
blx ASM_PFX(PeiCommonExceptionEntry)

110
ArmPlatformPkg/PrePeiCore/Exception.asm
View File

@ -21,71 +21,71 @@
PRESERVE8 PRESERVE8
AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5 AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5
//============================================================ //============================================================
//Default Exception Handlers //Default Exception Handlers
//============================================================ //============================================================
PeiVectorTable PeiVectorTable
b _DefaultResetHandler b _DefaultResetHandler
b _DefaultUndefined b _DefaultUndefined
b _DefaultSWI b _DefaultSWI
b _DefaultPrefetchAbort b _DefaultPrefetchAbort
b _DefaultDataAbort b _DefaultDataAbort
b _DefaultReserved b _DefaultReserved
b _DefaultIrq b _DefaultIrq
b _DefaultFiq b _DefaultFiq
// //
// Default Exception handlers: There is no plan to return from any of these exceptions. // Default Exception handlers: There is no plan to return from any of these exceptions.
// No context saving at all. // No context saving at all.
// //
_DefaultResetHandler _DefaultResetHandler
mov r1, lr mov r1, lr
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #0 mov r0, #0
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultUndefined _DefaultUndefined
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #1 mov r0, #1
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultSWI _DefaultSWI
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #2 mov r0, #2
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultPrefetchAbort _DefaultPrefetchAbort
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #3 mov r0, #3
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultDataAbort _DefaultDataAbort
sub r1, LR, #8 sub r1, LR, #8
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #4 mov r0, #4
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultReserved _DefaultReserved
mov r1, lr mov r1, lr
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #5 mov r0, #5
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultIrq _DefaultIrq
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #6 mov r0, #6
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
_DefaultFiq _DefaultFiq
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #7 mov r0, #7
blx PeiCommonExceptionEntry blx PeiCommonExceptionEntry
END END

2
ArmPlatformPkg/PrePeiCore/MainMPCore.c
View File

@ -69,7 +69,7 @@ PrimaryMain (
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
if (!PcdGet32(PcdStandalone)) { if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces // Sending SGI to all the Secondary CPU interfaces
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} }

7
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
View File

@ -16,6 +16,7 @@
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/PrintLib.h> #include <Library/PrintLib.h>
#include <Library/ArmLib.h> #include <Library/ArmLib.h>
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
@ -62,7 +63,11 @@ CEntryPoint (
//If not primary Jump to Secondary Main //If not primary Jump to Secondary Main
if(0 == CoreId) { if(0 == CoreId) {
//Goto primary Main. // Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
// Goto primary Main.
PrimaryMain (PeiCoreEntryPoint); PrimaryMain (PeiCoreEntryPoint);
} else { } else {
SecondaryMain (CoreId); SecondaryMain (CoreId);

6
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
View File

@ -42,6 +42,7 @@
ArmMPCoreMailBoxLib ArmMPCoreMailBoxLib
BaseLib BaseLib
DebugLib DebugLib
DebugAgentLib
IoLib IoLib
PL390GicNonSecLib PL390GicNonSecLib
PrintLib PrintLib
@ -50,9 +51,10 @@
[Ppis] [Ppis]
gEfiTemporaryRamSupportPpiGuid gEfiTemporaryRamSupportPpiGuid
[FixedPcd] [FeaturePcd]
gArmPlatformTokenSpaceGuid.PcdStandalone gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize gArmTokenSpaceGuid.PcdNormalFvSize

7
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
View File

@ -41,16 +41,17 @@
ArmPlatformLib ArmPlatformLib
BaseLib BaseLib
DebugLib DebugLib
DebugAgentLib
IoLib IoLib
PrintLib PrintLib
SerialPortLib
[Ppis] [Ppis]
gEfiTemporaryRamSupportPpiGuid gEfiTemporaryRamSupportPpiGuid
[FixedPcd] [FeaturePcd]
gArmPlatformTokenSpaceGuid.PcdStandalone gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize gArmTokenSpaceGuid.PcdNormalFvSize

2
ArmPlatformPkg/PrePi/PeiMPCore.inf
View File

@ -59,9 +59,9 @@
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[FixedPcd] [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdVFPEnabled gArmTokenSpaceGuid.PcdVFPEnabled
gArmTokenSpaceGuid.PcdNormalFdBaseAddress gArmTokenSpaceGuid.PcdNormalFdBaseAddress

2
ArmPlatformPkg/PrePi/PeiUniCore.inf
View File

@ -57,9 +57,9 @@
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[FixedPcd] [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdVFPEnabled gArmTokenSpaceGuid.PcdVFPEnabled
gArmTokenSpaceGuid.PcdNormalFdBaseAddress gArmTokenSpaceGuid.PcdNormalFdBaseAddress

110
ArmPlatformPkg/Sec/Exception.asm
View File

@ -21,71 +21,71 @@
PRESERVE8 PRESERVE8
AREA SecException, CODE, READONLY, CODEALIGN, ALIGN=5 AREA SecException, CODE, READONLY, CODEALIGN, ALIGN=5
//============================================================ //============================================================
//Default Exception Handlers //Default Exception Handlers
//============================================================ //============================================================
SecVectorTable SecVectorTable
b _DefaultResetHandler b _DefaultResetHandler
b _DefaultUndefined b _DefaultUndefined
b _DefaultSWI b _DefaultSWI
b _DefaultPrefetchAbort b _DefaultPrefetchAbort
b _DefaultDataAbort b _DefaultDataAbort
b _DefaultReserved b _DefaultReserved
b _DefaultIrq b _DefaultIrq
b _DefaultFiq b _DefaultFiq
// //
// Default Exception handlers: There is no plan to return from any of these exceptions. // Default Exception handlers: There is no plan to return from any of these exceptions.
// No context saving at all. // No context saving at all.
// //
_DefaultResetHandler _DefaultResetHandler
mov r1, lr mov r1, lr
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #0 mov r0, #0
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultUndefined _DefaultUndefined
sub r1, LR sub r1, LR
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #1 mov r0, #1
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultSWI _DefaultSWI
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #2 mov r0, #2
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultPrefetchAbort _DefaultPrefetchAbort
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #3 mov r0, #3
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultDataAbort _DefaultDataAbort
sub r1, LR, #8 sub r1, LR, #8
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #4 mov r0, #4
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultReserved _DefaultReserved
mov r1, lr mov r1, lr
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #5 mov r0, #5
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultIrq _DefaultIrq
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #6 mov r0, #6
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
_DefaultFiq _DefaultFiq
sub r1, LR, #4 sub r1, LR, #4
cps #0x13 ; Switch to SVC for common stack cps #0x13 ; Switch to SVC for common stack
mov r0, #7 mov r0, #7
blx SecCommonExceptionEntry blx SecCommonExceptionEntry
END END

84
ArmPlatformPkg/Sec/Sec.c
View File

@ -14,6 +14,7 @@
**/ **/
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/PrintLib.h> #include <Library/PrintLib.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
@ -70,6 +71,7 @@ CEntryPoint (
{ {
CHAR8 Buffer[100]; CHAR8 Buffer[100];
UINTN CharCount; UINTN CharCount;
UINTN JumpAddress;
// Primary CPU clears out the SCU tag RAMs, secondaries wait // Primary CPU clears out the SCU tag RAMs, secondaries wait
if (CoreId == ARM_PRIMARY_CORE) { if (CoreId == ARM_PRIMARY_CORE) {
@ -85,6 +87,10 @@ CEntryPoint (
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__);
SerialPortWrite ((UINT8 *) Buffer, CharCount); SerialPortWrite ((UINT8 *) Buffer, CharCount);
// Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
// Now we've got UART, make the check: // Now we've got UART, make the check:
// - The Vector table must be 32-byte aligned // - The Vector table must be 32-byte aligned
ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
@ -119,7 +125,7 @@ CEntryPoint (
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
if (FeaturePcdGet(PcdSkipPeiCore) || !PcdGet32(PcdStandalone)) { if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
// Initialize system memory (DRAM) // Initialize system memory (DRAM)
ArmPlatformInitializeSystemMemory (); ArmPlatformInitializeSystemMemory ();
} }
@ -155,7 +161,7 @@ CEntryPoint (
// //
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase)); PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase)); PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state. // Send SGI to all Secondary core to wake them up from WFI state.
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
@ -170,11 +176,11 @@ CEntryPoint (
ArmCallWFI(); ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE); PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
} }
// Transfer the interrupt to Non-secure World // Transfer the interrupt to Non-secure World
PL390GicSetupNonSecure(PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase)); PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register : // Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World // - Enable CP10 and CP11 accesses in NS World
@ -195,84 +201,24 @@ CEntryPoint (
if (CoreId == ARM_PRIMARY_CORE) { if (CoreId == ARM_PRIMARY_CORE) {
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase)); PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
} }
PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase)); PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
// Status Register as the the current one (CPSR). // Status Register as the the current one (CPSR).
copy_cpsr_into_spsr(); copy_cpsr_into_spsr ();
} }
// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
if (!PcdGet32(PcdStandalone)) { ArmPlatformSecExtraAction (CoreId, &JumpAddress);
if (CoreId == ARM_PRIMARY_CORE) {
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
// Patch the DRAM to make an infinite loop at the start address return_from_exception (JumpAddress);
*StartAddress = 0xEAFFFFFE; // opcode for while(1)
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
// To enter into Non Secure state, we need to make a return from exception
return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
} else {
// When the primary core is stopped by the hardware debugger to copy the firmware
// into DRAM. The secondary cores are still running. As soon as the first bytes of
// the firmware are written into DRAM, the secondary cores will start to execute the
// code even if the firmware is not entirely written into the memory.
// That's why the secondary cores need to be parked in WFI and wake up once the
// firmware is ready.
// Enter Secondary Cores into non Secure State. To enter into Non Secure state, we need to make a return from exception
return_from_exception((UINTN)NonSecureWaitForFirmware);
}
} else if (FeaturePcdGet(PcdSkipPeiCore)) {
if (CoreId == ARM_PRIMARY_CORE) {
// Signal the secondary cores they can jump to PEI phase
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
// To enter into Non Secure state, we need to make a return from exception
return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
} else {
// We wait for the primary core to finish to initialize the System Memory. When we skip PEI Core, we could set the stack in DRAM
// Without this synchronization the secondary cores will complete the SEC before the primary core has finished to intitialize the DRAM.
return_from_exception((UINTN)NonSecureWaitForFirmware);
}
} else {
// To enter into Non Secure state, we need to make a return from exception
return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
}
//-------------------- Non Secure Mode --------------------- //-------------------- Non Secure Mode ---------------------
// PEI Core should always load and never return // PEI Core should always load and never return
ASSERT (FALSE); ASSERT (FALSE);
} }
// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
VOID
NonSecureWaitForFirmware (
VOID
)
{
VOID (*secondary_start)(VOID);
// The secondary cores will execute the firmware once wake from WFI.
secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),ARM_PRIMARY_CORE);
// Jump to secondary core entry point.
secondary_start();
// PEI Core should always load and never return
ASSERT (FALSE);
}
VOID VOID
SecCommonExceptionEntry ( SecCommonExceptionEntry (
IN UINT32 Entry, IN UINT32 Entry,

4
ArmPlatformPkg/Sec/Sec.inf
View File

@ -40,16 +40,16 @@
ArmPlatformLib ArmPlatformLib
BaseLib BaseLib
DebugLib DebugLib
DebugAgentLib
IoLib IoLib
PL390GicSecLib PL390GicSecLib
PrintLib PrintLib
SerialPortLib SerialPortLib
[FeaturePcd] [FeaturePcd]
gArmTokenSpaceGuid.PcdSkipPeiCore gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
[FixedPcd] [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmTokenSpaceGuid.PcdVFPEnabled gArmTokenSpaceGuid.PcdVFPEnabled
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport gArmPlatformTokenSpaceGuid.PcdMPCoreSupport

244
EmbeddedPkg/Ebl/Variable.c
View File

@ -1,20 +1,20 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at * which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php * http://opensource.org/licenses/bsd-license.php
* *
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
* *
**/ **/
#include "Ebl.h" #include "Ebl.h"
#include <Guid/GlobalVariable.h> #include <Guid/GlobalVariable.h>
EFI_STATUS EFI_STATUS
EblGetCmd ( EblGetCmd (
@ -23,55 +23,55 @@ EblGetCmd (
) )
{ {
EFI_STATUS Status = EFI_INVALID_PARAMETER; EFI_STATUS Status = EFI_INVALID_PARAMETER;
UINTN Size; UINTN Size;
VOID* Value; VOID* Value;
CHAR8* AsciiVariableName = NULL; CHAR8* AsciiVariableName = NULL;
CHAR16* VariableName; CHAR16* VariableName;
UINT32 Index; UINT32 Index;
if (Argc == 1) { if (Argc == 1) {
AsciiPrint("Variable name is missing.\n"); AsciiPrint("Variable name is missing.\n");
return Status; return Status;
} }
for (Index = 1; Index < Argc; Index++) { for (Index = 1; Index < Argc; Index++) {
if (Argv[Index][0] == '-') { if (Argv[Index][0] == '-') {
AsciiPrint("Warning: '%a' not recognized.\n",Argv[Index]); AsciiPrint("Warning: '%a' not recognized.\n",Argv[Index]);
} else { } else {
AsciiVariableName = Argv[Index]; AsciiVariableName = Argv[Index];
} }
} }
if (AsciiVariableName == NULL) { if (AsciiVariableName == NULL) {
AsciiPrint("Variable name is missing.\n"); AsciiPrint("Variable name is missing.\n");
return Status; return Status;
} else { } else {
VariableName = AllocatePool((AsciiStrLen (AsciiVariableName) + 1) * sizeof (CHAR16)); VariableName = AllocatePool((AsciiStrLen (AsciiVariableName) + 1) * sizeof (CHAR16));
AsciiStrToUnicodeStr (AsciiVariableName,VariableName); AsciiStrToUnicodeStr (AsciiVariableName,VariableName);
} }
// Try to get the variable size. // Try to get the variable size.
Value = NULL; Value = NULL;
Size = 0; Size = 0;
Status = gRT->GetVariable (VariableName, &gEfiGlobalVariableGuid, NULL, &Size, Value); Status = gRT->GetVariable (VariableName, &gEfiGlobalVariableGuid, NULL, &Size, Value);
if (Status == EFI_NOT_FOUND) { if (Status == EFI_NOT_FOUND) {
AsciiPrint("Variable name '%s' not found.\n",VariableName); AsciiPrint("Variable name '%s' not found.\n",VariableName);
} else if (Status == EFI_BUFFER_TOO_SMALL) { } else if (Status == EFI_BUFFER_TOO_SMALL) {
// Get the environment variable value // Get the environment variable value
Value = AllocatePool (Size); Value = AllocatePool (Size);
if (Value == NULL) { if (Value == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
Status = gRT->GetVariable ((CHAR16 *)VariableName, &gEfiGlobalVariableGuid, NULL, &Size, Value); Status = gRT->GetVariable ((CHAR16 *)VariableName, &gEfiGlobalVariableGuid, NULL, &Size, Value);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
AsciiPrint("Error: '%r'\n",Status); AsciiPrint("Error: '%r'\n",Status);
} else { } else {
AsciiPrint("%a=%a\n",AsciiVariableName,Value); AsciiPrint("%a=%a\n",AsciiVariableName,Value);
} }
FreePool(Value); FreePool(Value);
} else { } else {
AsciiPrint("Error: '%r'\n",Status); AsciiPrint("Error: '%r'\n",Status);
} }
FreePool(VariableName); FreePool(VariableName);
@ -85,60 +85,60 @@ EblSetCmd (
) )
{ {
EFI_STATUS Status = EFI_INVALID_PARAMETER; EFI_STATUS Status = EFI_INVALID_PARAMETER;
CHAR8* AsciiVariableSetting = NULL; CHAR8* AsciiVariableSetting = NULL;
CHAR8* AsciiVariableName; CHAR8* AsciiVariableName;
CHAR8* AsciiValue; CHAR8* AsciiValue;
UINT32 AsciiValueLength; UINT32 AsciiValueLength;
CHAR16* VariableName; CHAR16* VariableName;
UINT32 Index; UINT32 Index;
UINT32 EscapedQuotes = 0; UINT32 EscapedQuotes = 0;
BOOLEAN Volatile = FALSE; BOOLEAN Volatile = FALSE;
if (Argc == 1) { if (Argc == 1) {
AsciiPrint("Variable name is missing.\n"); AsciiPrint("Variable name is missing.\n");
return Status; return Status;
} }
for (Index = 1; Index < Argc; Index++) { for (Index = 1; Index < Argc; Index++) {
if (AsciiStrCmp(Argv[Index],"-v") == 0) { if (AsciiStrCmp(Argv[Index],"-v") == 0) {
Volatile = 0; Volatile = 0;
} else if (Argv[Index][0] == '-') { } else if (Argv[Index][0] == '-') {
AsciiPrint("Warning: '%a' not recognized.\n",Argv[Index]); AsciiPrint("Warning: '%a' not recognized.\n",Argv[Index]);
} else { } else {
AsciiVariableSetting = Argv[Index]; AsciiVariableSetting = Argv[Index];
} }
} }
if (AsciiVariableSetting == NULL) { if (AsciiVariableSetting == NULL) {
AsciiPrint("Variable name is missing.\n"); AsciiPrint("Variable name is missing.\n");
return Status; return Status;
} }
// Check if it is a valid variable setting // Check if it is a valid variable setting
AsciiValue = AsciiStrStr (AsciiVariableSetting,"="); AsciiValue = AsciiStrStr (AsciiVariableSetting,"=");
if (AsciiValue == NULL) { if (AsciiValue == NULL) {
// //
// There is no value. It means this variable will be deleted // There is no value. It means this variable will be deleted
// //
// Convert VariableName into Unicode // Convert VariableName into Unicode
VariableName = AllocatePool((AsciiStrLen (AsciiVariableSetting) + 1) * sizeof (CHAR16)); VariableName = AllocatePool((AsciiStrLen (AsciiVariableSetting) + 1) * sizeof (CHAR16));
AsciiStrToUnicodeStr (AsciiVariableSetting,VariableName); AsciiStrToUnicodeStr (AsciiVariableSetting,VariableName);
Status = gRT->SetVariable ( Status = gRT->SetVariable (
VariableName, VariableName,
&gEfiGlobalVariableGuid, &gEfiGlobalVariableGuid,
( !Volatile ? EFI_VARIABLE_NON_VOLATILE : 0) | ( !Volatile ? EFI_VARIABLE_NON_VOLATILE : 0) |
EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
0, 0,
NULL NULL
); );
if (!EFI_ERROR(Status)) { if (!EFI_ERROR(Status)) {
AsciiPrint("Variable '%s' deleted\n",VariableName); AsciiPrint("Variable '%s' deleted\n",VariableName);
} else { } else {
AsciiPrint("Variable setting is incorrect. It should be VariableName=Value\n"); AsciiPrint("Variable setting is incorrect. It should be VariableName=Value\n");
} }
return Status; return Status;
} }
AsciiValue[0] = '\0'; AsciiValue[0] = '\0';
@ -167,20 +167,20 @@ EblSetCmd (
} }
// Convert VariableName into Unicode // Convert VariableName into Unicode
VariableName = AllocatePool((AsciiStrLen (AsciiVariableName) + 1) * sizeof (CHAR16)); VariableName = AllocatePool((AsciiStrLen (AsciiVariableName) + 1) * sizeof (CHAR16));
AsciiStrToUnicodeStr (AsciiVariableName,VariableName); AsciiStrToUnicodeStr (AsciiVariableName,VariableName);
Status = gRT->SetVariable ( Status = gRT->SetVariable (
VariableName, VariableName,
&gEfiGlobalVariableGuid, &gEfiGlobalVariableGuid,
( !Volatile ? EFI_VARIABLE_NON_VOLATILE : 0) | ( !Volatile ? EFI_VARIABLE_NON_VOLATILE : 0) |
EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
AsciiStrLen (AsciiValue)+1, AsciiStrLen (AsciiValue)+1,
AsciiValue AsciiValue
); );
if (!EFI_ERROR(Status)) { if (!EFI_ERROR(Status)) {
AsciiPrint("'%a'='%a'\n",AsciiVariableName,AsciiValue); AsciiPrint("'%a'='%a'\n",AsciiVariableName,AsciiValue);
} }
return Status; return Status;
} }

384
EmbeddedPkg/Library/PrePiMemoryAllocationLib/MemoryAllocationLib.c
View File

@ -1,192 +1,192 @@
/** @file /** @file
Implementation of the 6 PEI Ffs (FV) APIs in library form. Implementation of the 6 PEI Ffs (FV) APIs in library form.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/ **/
#include <PiPei.h> #include <PiPei.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
#include <Library/PrePiLib.h> #include <Library/PrePiLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
/** /**
Allocates one or more 4KB pages of type EfiBootServicesData. Allocates one or more 4KB pages of type EfiBootServicesData.
Allocates the number of 4KB pages of MemoryType and returns a pointer to the Allocates the number of 4KB pages of MemoryType and returns a pointer to the
allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
is returned. If there is not enough memory remaining to satisfy the request, then NULL is is returned. If there is not enough memory remaining to satisfy the request, then NULL is
returned. returned.
@param Pages The number of 4 KB pages to allocate. @param Pages The number of 4 KB pages to allocate.
@return A pointer to the allocated buffer or NULL if allocation fails. @return A pointer to the allocated buffer or NULL if allocation fails.
**/ **/
VOID * VOID *
EFIAPI EFIAPI
AllocatePages ( AllocatePages (
IN UINTN Pages IN UINTN Pages
) )
{ {
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
EFI_PHYSICAL_ADDRESS Offset; EFI_PHYSICAL_ADDRESS Offset;
Hob.Raw = GetHobList (); Hob.Raw = GetHobList ();
// Check to see if on 4k boundary // Check to see if on 4k boundary
Offset = Hob.HandoffInformationTable->EfiFreeMemoryTop & 0xFFF; Offset = Hob.HandoffInformationTable->EfiFreeMemoryTop & 0xFFF;
if (Offset != 0) { if (Offset != 0) {
// If not aligned, make the allocation aligned. // If not aligned, make the allocation aligned.
Hob.HandoffInformationTable->EfiFreeMemoryTop -= Offset; Hob.HandoffInformationTable->EfiFreeMemoryTop -= Offset;
} }
// //
// Verify that there is sufficient memory to satisfy the allocation // Verify that there is sufficient memory to satisfy the allocation
// //
if (Hob.HandoffInformationTable->EfiFreeMemoryTop - ((Pages * EFI_PAGE_SIZE) + sizeof (EFI_HOB_MEMORY_ALLOCATION)) < Hob.HandoffInformationTable->EfiFreeMemoryBottom) { if (Hob.HandoffInformationTable->EfiFreeMemoryTop - ((Pages * EFI_PAGE_SIZE) + sizeof (EFI_HOB_MEMORY_ALLOCATION)) < Hob.HandoffInformationTable->EfiFreeMemoryBottom) {
return 0; return 0;
} else { } else {
// //
// Update the PHIT to reflect the memory usage // Update the PHIT to reflect the memory usage
// //
Hob.HandoffInformationTable->EfiFreeMemoryTop -= Pages * EFI_PAGE_SIZE; Hob.HandoffInformationTable->EfiFreeMemoryTop -= Pages * EFI_PAGE_SIZE;
// This routine used to create a memory allocation HOB a la PEI, but that's not // This routine used to create a memory allocation HOB a la PEI, but that's not
// necessary for us. // necessary for us.
// //
// Create a memory allocation HOB. // Create a memory allocation HOB.
// //
BuildMemoryAllocationHob ( BuildMemoryAllocationHob (
Hob.HandoffInformationTable->EfiFreeMemoryTop, Hob.HandoffInformationTable->EfiFreeMemoryTop,
Pages * EFI_PAGE_SIZE, Pages * EFI_PAGE_SIZE,
EfiBootServicesData EfiBootServicesData
); );
return (VOID *)(UINTN)Hob.HandoffInformationTable->EfiFreeMemoryTop; return (VOID *)(UINTN)Hob.HandoffInformationTable->EfiFreeMemoryTop;
} }
} }
/** /**
Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment. Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment.
Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an
alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
returned. If there is not enough memory at the specified alignment remaining to satisfy the returned. If there is not enough memory at the specified alignment remaining to satisfy the
request, then NULL is returned. request, then NULL is returned.
If Alignment is not a power of two and Alignment is not zero, then ASSERT(). If Alignment is not a power of two and Alignment is not zero, then ASSERT().
@param Pages The number of 4 KB pages to allocate. @param Pages The number of 4 KB pages to allocate.
@param Alignment The requested alignment of the allocation. Must be a power of two. @param Alignment The requested alignment of the allocation. Must be a power of two.
If Alignment is zero, then byte alignment is used. If Alignment is zero, then byte alignment is used.
@return A pointer to the allocated buffer or NULL if allocation fails. @return A pointer to the allocated buffer or NULL if allocation fails.
**/ **/
VOID * VOID *
EFIAPI EFIAPI
AllocateAlignedPages ( AllocateAlignedPages (
IN UINTN Pages, IN UINTN Pages,
IN UINTN Alignment IN UINTN Alignment
) )
{ {
VOID *Memory; VOID *Memory;
UINTN AlignmentMask; UINTN AlignmentMask;
// //
// Alignment must be a power of two or zero. // Alignment must be a power of two or zero.
// //
ASSERT ((Alignment & (Alignment - 1)) == 0); ASSERT ((Alignment & (Alignment - 1)) == 0);
if (Pages == 0) { if (Pages == 0) {
return NULL; return NULL;
} }
// //
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow. // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
// //
ASSERT (Pages <= (MAX_ADDRESS - EFI_SIZE_TO_PAGES (Alignment))); ASSERT (Pages <= (MAX_ADDRESS - EFI_SIZE_TO_PAGES (Alignment)));
// //
// We would rather waste some memory to save PEI code size. // We would rather waste some memory to save PEI code size.
// //
Memory = (VOID *)(UINTN)AllocatePages (Pages + EFI_SIZE_TO_PAGES (Alignment)); Memory = (VOID *)(UINTN)AllocatePages (Pages + EFI_SIZE_TO_PAGES (Alignment));
if (Alignment == 0) { if (Alignment == 0) {
AlignmentMask = Alignment; AlignmentMask = Alignment;
} else { } else {
AlignmentMask = Alignment - 1; AlignmentMask = Alignment - 1;
} }
return (VOID *) (UINTN) (((UINTN) Memory + AlignmentMask) & ~AlignmentMask); return (VOID *) (UINTN) (((UINTN) Memory + AlignmentMask) & ~AlignmentMask);
} }
/** /**
Allocates a buffer of type EfiBootServicesData. Allocates a buffer of type EfiBootServicesData.
Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a
pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
@param AllocationSize The number of bytes to allocate. @param AllocationSize The number of bytes to allocate.
@return A pointer to the allocated buffer or NULL if allocation fails. @return A pointer to the allocated buffer or NULL if allocation fails.
**/ **/
VOID * VOID *
EFIAPI EFIAPI
AllocatePool ( AllocatePool (
IN UINTN AllocationSize IN UINTN AllocationSize
) )
{ {
EFI_HOB_MEMORY_POOL *Hob; EFI_HOB_MEMORY_POOL *Hob;
Hob = GetHobList (); Hob = GetHobList ();
// //
// Verify that there is sufficient memory to satisfy the allocation // Verify that there is sufficient memory to satisfy the allocation
// //
if (AllocationSize > 0x10000) { if (AllocationSize > 0x10000) {
// Please call AllcoatePages for big allocations // Please call AllcoatePages for big allocations
return 0; return 0;
} else { } else {
Hob = (EFI_HOB_MEMORY_POOL *)CreateHob (EFI_HOB_TYPE_MEMORY_POOL, (UINT16)(sizeof (EFI_HOB_TYPE_MEMORY_POOL) + AllocationSize)); Hob = (EFI_HOB_MEMORY_POOL *)CreateHob (EFI_HOB_TYPE_MEMORY_POOL, (UINT16)(sizeof (EFI_HOB_TYPE_MEMORY_POOL) + AllocationSize));
return (VOID *)(Hob + 1); return (VOID *)(Hob + 1);
} }
} }
/** /**
Frees a buffer that was previously allocated with one of the pool allocation functions in the Frees a buffer that was previously allocated with one of the pool allocation functions in the
Memory Allocation Library. Memory Allocation Library.
Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the
pool allocation services of the Memory Allocation Library. If it is not possible to free pool pool allocation services of the Memory Allocation Library. If it is not possible to free pool
resources, then this function will perform no actions. resources, then this function will perform no actions.
If Buffer was not allocated with a pool allocation function in the Memory Allocation Library, If Buffer was not allocated with a pool allocation function in the Memory Allocation Library,
then ASSERT(). then ASSERT().
@param Buffer Pointer to the buffer to free. @param Buffer Pointer to the buffer to free.
**/ **/
VOID VOID
EFIAPI EFIAPI
FreePool ( FreePool (
IN VOID *Buffer IN VOID *Buffer
) )
{ {
// Not implemented yet // Not implemented yet
} }