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Docs: Replace Recommonmark with MyST Parser

Browse Source 
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.

For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:

* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)

MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:

```{toctree}
:maxdepth: 1

Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```

Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.

The toctrees were converted to the MyST syntax using the following
command and Python script:

`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`

```
import re
import sys

in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()

with open(sys.argv[1], "w") as f:
    for line in lines:
        match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
        if match is not None:
            if not in_list:
                in_list = True
                f.write("```{toctree}\n")
                f.write(":maxdepth: 1\n\n")
            f.write(match.group(1) + " <" + match.group(2) + ">\n")
        else:
            if in_list:
                f.write("```\n")
            f.write(line)
            in_list = False

    if in_list:
        f.write("```\n")
```

While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.

This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.

Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.

These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`

Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.

From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.

TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.

[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html

Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nicholas Chin 2023-02-21 19:41:06 -07:00 committed by Martin L Roth
parent 9203e25a35
commit 35599f9a66
178 changed files with 1261 additions and 1021 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

229
Documentation/Makefile.sphinx
View File

@ -1,60 +1,20 @@
## SPDX-License-Identifier: GPL-2.0-only
# Makefile for Sphinx documentation
# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
# You can set these variables from the command line, and also
# from the environment for the first two.
SPHINXOPTS ?=
SPHINXBUILD = sphinx-build
SPHINXBUILD ?= sphinx-build
SPHINXAUTOBUILD = sphinx-autobuild
PAPER =
SOURCEDIR = .
BUILDDIR = _build
# Internal variables.
PAPEROPT_a4 = -D latex_paper_size=a4
PAPEROPT_letter = -D latex_paper_size=letter
ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
# the i18n builder cannot share the environment and doctrees with the others
I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
.PHONY: help
# Put it first so that "make" without argument is like "make help".
help:
@echo "Please use \`make <target>' where <target> is one of"
@echo " html to make standalone HTML files"
@echo " dirhtml to make HTML files named index.html in directories"
@echo " singlehtml to make a single large HTML file"
@echo " pickle to make pickle files"
@echo " json to make JSON files"
@echo " htmlhelp to make HTML files and a HTML help project"
@echo " qthelp to make HTML files and a qthelp project"
@echo " applehelp to make an Apple Help Book"
@echo " devhelp to make HTML files and a Devhelp project"
@echo " epub to make an epub"
@echo " epub3 to make an epub3"
@echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
@echo " latexpdf to make LaTeX files and run them through pdflatex"
@echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
@echo " text to make text files"
@echo " man to make manual pages"
@echo " texinfo to make Texinfo files"
@echo " info to make Texinfo files and run them through makeinfo"
@echo " gettext to make PO message catalogs"
@echo " changes to make an overview of all changed/added/deprecated items"
@echo " xml to make Docutils-native XML files"
@echo " pseudoxml to make pseudoxml-XML files for display purposes"
@echo " linkcheck to check all external links for integrity"
@echo " doctest to run all doctests embedded in the documentation (if enabled)"
@echo " coverage to run coverage check of the documentation (if enabled)"
@echo " dummy to check syntax errors of document sources"
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: clean
clean:
rm -rf $(BUILDDIR)
.PHONY: html
html:
$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
.PHONY: help Makefile.sphinx
.PHONY: livehtml
livehtml:
@ -63,172 +23,7 @@ livehtml:
@echo
$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
.PHONY: dirhtml
dirhtml:
$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
.PHONY: singlehtml
singlehtml:
$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
@echo
@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
.PHONY: pickle
pickle:
$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
@echo
@echo "Build finished; now you can process the pickle files."
.PHONY: json
json:
$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
@echo
@echo "Build finished; now you can process the JSON files."
.PHONY: htmlhelp
htmlhelp:
$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
@echo
@echo "Build finished; now you can run HTML Help Workshop with the" \
".hhp project file in $(BUILDDIR)/htmlhelp."
.PHONY: qthelp
qthelp:
$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp
@echo
@echo "Build finished; now you can run "qcollectiongenerator" with the" \
".qhcp project file in $(BUILDDIR)/qthelp, like this:"
@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/coreboot.qhcp"
@echo "To view the help file:"
@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/coreboot.qhc"
.PHONY: applehelp
applehelp:
$(SPHINXBUILD) -b applehelp $(ALLSPHINXOPTS) $(BUILDDIR)/applehelp
@echo
@echo "Build finished. The help book is in $(BUILDDIR)/applehelp."
@echo "N.B. You won't be able to view it unless you put it in" \
"~/Library/Documentation/Help or install it in your application" \
"bundle."
.PHONY: devhelp
devhelp:
$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp
@echo
@echo "Build finished."
@echo "To view the help file:"
@echo "# mkdir -p $$HOME/.local/share/devhelp/coreboot"
@echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/coreboot"
@echo "# devhelp"
.PHONY: epub
epub:
$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
@echo
@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
.PHONY: epub3
epub3:
$(SPHINXBUILD) -b epub3 $(ALLSPHINXOPTS) $(BUILDDIR)/epub3
@echo
@echo "Build finished. The epub3 file is in $(BUILDDIR)/epub3."
.PHONY: latex
latex:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo
@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
@echo "Run \`make' in that directory to run these through (pdf)latex" \
"(use \`make latexpdf' here to do that automatically)."
.PHONY: latexpdf
latexpdf:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo "Running LaTeX files through pdflatex..."
$(MAKE) -C $(BUILDDIR)/latex all-pdf
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
.PHONY: latexpdfja
latexpdfja:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo "Running LaTeX files through platex and dvipdfmx..."
$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
.PHONY: text
text:
$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
@echo
@echo "Build finished. The text files are in $(BUILDDIR)/text."
.PHONY: man
man:
$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
@echo
@echo "Build finished. The manual pages are in $(BUILDDIR)/man."
.PHONY: texinfo
texinfo:
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
@echo
@echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
@echo "Run \`make' in that directory to run these through makeinfo" \
"(use \`make info' here to do that automatically)."
.PHONY: info
info:
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
@echo "Running Texinfo files through makeinfo..."
make -C $(BUILDDIR)/texinfo info
@echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
.PHONY: gettext
gettext:
$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
@echo
@echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
.PHONY: changes
changes:
$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
@echo
@echo "The overview file is in $(BUILDDIR)/changes."
.PHONY: linkcheck
linkcheck:
$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
@echo
@echo "Link check complete; look for any errors in the above output " \
"or in $(BUILDDIR)/linkcheck/output.txt."
.PHONY: doctest
doctest:
$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
@echo "Testing of doctests in the sources finished, look at the " \
"results in $(BUILDDIR)/doctest/output.txt."
.PHONY: coverage
coverage:
$(SPHINXBUILD) -b coverage $(ALLSPHINXOPTS) $(BUILDDIR)/coverage
@echo "Testing of coverage in the sources finished, look at the " \
"results in $(BUILDDIR)/coverage/python.txt."
.PHONY: xml
xml:
$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
@echo
@echo "Build finished. The XML files are in $(BUILDDIR)/xml."
.PHONY: pseudoxml
pseudoxml:
$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
@echo
@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
.PHONY: dummy
dummy:
$(SPHINXBUILD) -b dummy $(ALLSPHINXOPTS) $(BUILDDIR)/dummy
@echo
@echo "Build finished. Dummy builder generates no files."
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile.sphinx
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

28
Documentation/acpi/index.md
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@ -5,18 +5,34 @@ backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and
upwards.
- [SSDT UID generation](uid.md)
```{toctree}
:maxdepth: 1
SSDT UID generation <uid.md>
```
## GPIO
- [GPIO toggling in ACPI AML](gpio.md)
```{toctree}
:maxdepth: 1
GPIO toggling in ACPI AML <gpio.md>
```
## Windows-specific ACPI documentation
- [Windows-specific documentation](windows.md)
```{toctree}
:maxdepth: 1
Windows-specific documentation <windows.md>
```
## ACPI specification - Useful links
- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
```{toctree}
:maxdepth: 1
ACPI Specification 6.5 <https://uefi.org/specs/ACPI/6.5/index.html>
ASL 2.0 Syntax <https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions>
Predefined ACPI Names <https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names>
```

6
Documentation/acronyms.md
View File

@ -1141,4 +1141,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## References:
* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf)
```{toctree}
:maxdepth: 1
AMD Glossary of terms <https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf>
```

12
Documentation/arch/index.md
View File

@ -5,7 +5,15 @@ architectures.
## RISC-V
- [RISC-V documentation](riscv/index.md)
```{toctree}
:maxdepth: 1
RISC-V documentation <riscv/index.md>
```
## x86
- [x86 documentation](x86/index.md)
```{toctree}
:maxdepth: 1
x86 documentation <x86/index.md>
```

14
Documentation/arch/x86/index.md
View File

@ -2,7 +2,11 @@
This section contains documentation about coreboot on x86 architecture.
* [x86 PAE support](pae.md)
```{toctree}
:maxdepth: 1
x86 PAE support <pae.md>
```
## State of x86_64 support
At the moment there's only experimental x86_64 support.
@ -43,8 +47,12 @@ Basic support for x86_64 has been implemented for QEMU mainboard target.
## Reference implementation
The reference implementation is
* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md)
* [QEMU Q35](../../mainboard/emulation/qemu-q35.md)
```{toctree}
:maxdepth: 1
QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md>
QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
```
## TODO
* Identity map memory above 4GiB in ramstage

12
Documentation/community/index.md
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@ -1,6 +1,10 @@
# Community
* [Code of Conduct](code_of_conduct.md)
* [Language style](language_style.md)
* [Community forums](forums.md)
* [coreboot at conferences](conferences.md)
```{toctree}
:maxdepth: 1
Code of Conduct <code_of_conduct.md>
Language style <language_style.md>
Community forums <forums.md>
coreboot at conferences <conferences.md>
```

119
Documentation/conf.py
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@ -1,46 +1,34 @@
# -*- coding: utf-8 -*-
import subprocess
from recommonmark.parser import CommonMarkParser
import sphinx
# Get Sphinx version
major = 0
minor = 0
patchlevel = 0
version = sphinx.__version__.split(".")
if len(version) > 1:
major = int(version[0])
minor = int(version[1])
if len(version) > 2:
patchlevel = int(version[2])
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
source_suffix = ['.md']
# The master toctree document.
master_doc = 'index'
# General information about the project.
project = u'coreboot'
copyright = u'CC-by 4.0 the coreboot project'
author = u'the coreboot project'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
# Configuration file for the Sphinx documentation builder.
#
# The full version, including alpha/beta/rc tags.
# For the full list of built-in configuration values, see the documentation:
# https://www.sphinx-doc.org/en/master/usage/configuration.html
# -- Project information -----------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
import subprocess
project = 'coreboot'
copyright = 'CC-by 4.0 the coreboot project'
author = 'the coreboot project'
release = subprocess.check_output(('git', 'describe')).decode("utf-8")
# The short X.Y version.
version = release.split("-")[0]
extensions = []
# Load recommonmark, supported since 1.8+
if major >= 2 or (major == 1 and minor >= 8):
extensions += ['recommonmark']
# -- General configuration ---------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
extensions = ["myst_parser"]
myst_heading_anchors = 5
templates_path = ['_templates']
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# Try to load DITAA
try:
@ -57,62 +45,11 @@ else:
# Usually you set "language" from the command line for these cases.
language = 'en'
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This patterns also effect to html_static_path and html_extra_path
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# -- Options for HTML output -------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# A list of ignored prefixes for module index sorting.
# modindex_common_prefix = []
# If true, keep warnings as "system message" paragraphs in the built documents.
# keep_warnings = False
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = False
# -- Options for HTML output ----------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'sphinx_rtd_theme'
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
html_css_files = [
'theme_overrides.css', # override wide tables in RTD theme
]
# Output file base name for HTML help builder.
htmlhelp_basename = 'corebootdoc'
enable_auto_toc_tree = True
class MyCommonMarkParser(CommonMarkParser):
# remove this hack once upstream RecommonMark supports inline code
def visit_code(self, mdnode):
from docutils import nodes
n = nodes.literal(mdnode.literal, mdnode.literal)
self.current_node.append(n)
def setup(app):
from recommonmark.transform import AutoStructify
# Load recommonmark on old Sphinx
if major == 1 and minor < 8:
app.add_source_parser('.md', MyCommonMarkParser)
app.add_config_value('recommonmark_config', {
'enable_auto_toc_tree': True,
'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
'enable_eval_rst': True,
'url_resolver': lambda url: '/' + url
}, True)
app.add_transform(AutoStructify)

14
Documentation/contributing/index.md
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@ -1,7 +1,11 @@
# Contributing
* [Coding Style](coding_style.md)
* [Gerrit Guidelines](gerrit_guidelines.md)
* [Project Ideas](project_ideas.md)
* [Documentation Ideas](documentation_ideas.md)
* [Google Summer of Code](gsoc.md)
```{toctree}
:maxdepth: 1
Coding Style <coding_style.md>
Gerrit Guidelines <gerrit_guidelines.md>
Project Ideas <project_ideas.md>
Documentation Ideas <documentation_ideas.md>
Google Summer of Code <gsoc.md>
```

18
Documentation/drivers/index.md
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@ -8,10 +8,14 @@ For details on how to connect device drivers to a mainboard, see [Driver Devicet
Some of the drivers currently available include:
* [Intel DPTF](dptf.md)
* [IPMI KCS](ipmi_kcs.md)
* [SMMSTORE](smmstore.md)
* [SMMSTOREv2](smmstorev2.md)
* [SoundWire](soundwire.md)
* [USB4 Retimer](retimer.md)
* [CBFS SMBIOS hooks](cbfs_smbios.md)
```{toctree}
:maxdepth: 1
Intel DPTF <dptf.md>
IPMI KCS <ipmi_kcs.md>
SMMSTORE <smmstore.md>
SMMSTOREv2 <smmstorev2.md>
SoundWire <soundwire.md>
USB4 Retimer <retimer.md>
CBFS SMBIOS hooks <cbfs_smbios.md>
```

6
Documentation/drivers/smmstore.md
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@ -128,7 +128,11 @@ data or modify the currently running kernel.*
## External links
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
```{toctree}
:maxdepth: 1
A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
```
Note, this differs significantly from coreboot's implementation.
[SMM]: ../security/smm.md

6
Documentation/drivers/smmstorev2.md
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@ -215,7 +215,11 @@ running kernel.
## External links
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
```{toctree}
:maxdepth: 1
A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
```
Note that this differs significantly from coreboot's implementation.
[SMM]: ../security/smm.md

100
Documentation/external_docs.md
View File

@ -17,13 +17,21 @@ Please add any helpful or informational links and sections as you see fit.
* [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
* [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
* [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
```{toctree}
:maxdepth: 1
Boot Guard and PSB have user-hostile defaults <https://mjg59.dreamwidth.org/58424.html>
```
## General Information
* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
* [Interface BUS](http://www.interfacebus.com/)
```{toctree}
:maxdepth: 1
OS Dev <https://wiki.osdev.org/Categorized_Main_Page>
Interface BUS <http://www.interfacebus.com/>
```
## OpenSecurityTraining2
@ -43,10 +51,14 @@ modified works back to the community.
Below is a list of currently available courses that can help understand the
inner workings of coreboot and other firmware-related topics:
* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
* [x86-64 Assembly](https://ost2.fyi/Arch1001)
* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
```{toctree}
:maxdepth: 1
coreboot design principles and boot process <https://ost2.fyi/Arch4031>
x86-64 Assembly <https://ost2.fyi/Arch1001>
x86-64 OS Internals <https://ost2.fyi/Arch2001>
x86-64 Intel Firmware Attack & Defense <https://ost2.fyi/Arch4001>
```
There are [additional security courses](https://p.ost2.fyi/courses) at the site
as well (such as
@ -54,47 +66,79 @@ as well (such as
## Firmware Specifications & Information
* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
```{toctree}
:maxdepth: 1
System Management BIOS - SMBIOS <https://www.dmtf.org/standards/smbios>
Desktop and Mobile Architecture for System Hardware - DASH <https://www.dmtf.org/standards/dash>
PNP BIOS <https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf>
```
### ACPI
* [ACPI Specs](https://uefi.org/acpi/specs)
* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
```{toctree}
:maxdepth: 1
ACPI Specs <https://uefi.org/acpi/specs>
ACPI in Linux <https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf>
ACPI 5 Linux <https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf>
ACPI 6 Linux <https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf>
```
### Security
* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
```{toctree}
:maxdepth: 1
Intel Boot Guard <https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard>
```
## Hardware information
* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
* [Sandpile](https://www.sandpile.org/)
* [CPU-World](https://www.cpu-world.com/index.html)
* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
```{toctree}
:maxdepth: 1
WikiChip <https://en.wikichip.org/wiki/WikiChip>
Sandpile <https://www.sandpile.org/>
CPU-World <https://www.cpu-world.com/index.html>
CPU-Upgrade <https://www.cpu-upgrade.com/index.html>
```
### Hardware Specifications & Standards
* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
eMMC <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED>
```
* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
[Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED>
Memory <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED>
```
* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
PCI / PCIe / M.2 <https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED>
```
* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED>
```
* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
* [USB](https://www.usb.org/documents) - USB Implementers Forum
@ -133,5 +177,9 @@ as well (such as
## Infrastructure software
* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
* [GNU Make](https://www.gnu.org/software/make/manual/)
```{toctree}
:maxdepth: 1
Kconfig <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>
GNU Make <https://www.gnu.org/software/make/manual/>
```

2
Documentation/getting_started/build_system.md
View File

@ -75,7 +75,7 @@ $(call add_intermediate, add_mrc_data)
Note that the second line must start with a tab, not spaces.
```eval_rst
```{eval-rst}
See also :doc:`../tutorial/managing_local_additions`.
```

2
Documentation/getting_started/gpio.md
View File

@ -167,7 +167,7 @@ could cause catastrophic failures, up to and including your mainboard!
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as:
```eval_rst
```{eval-rst}
+------------------------+----------------+-------------+-------------+
| | | PAD Reset ? |
+ PAD Reset Config + Platform Reset +-------------+-------------+

20
Documentation/getting_started/index.md
View File

@ -1,10 +1,14 @@
# Getting Started
* [coreboot architecture](architecture.md)
* [Build System](build_system.md)
* [Submodules](submodules.md)
* [Kconfig](kconfig.md)
* [Writing Documentation](writing_documentation.md)
* [Setting up GPIOs](gpio.md)
* [Adding devices to a device tree](devicetree.md)
* [Frequently Asked Questions](faq.md)
```{toctree}
:maxdepth: 1
coreboot architecture <architecture.md>
Build System <build_system.md>
Submodules <submodules.md>
Kconfig <kconfig.md>
Writing Documentation <writing_documentation.md>
Setting up GPIOs <gpio.md>
Adding devices to a device tree <devicetree.md>
Frequently Asked Questions <faq.md>
```

8
Documentation/getting_started/kconfig.md
View File

@ -11,8 +11,12 @@ configuration front end in coreboot today.
The official Kconfig source and documentation is kept at kernel.org:
- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig)
- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
```{toctree}
:maxdepth: 1
Kconfig source <https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig>
Kconfig Language Documentation <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt>
```
The advantage to using Kconfig is that it allows users to easily select the
high level features of the project to be enabled or disabled at build time.

2
Documentation/gfx/display-panel.md
View File

@ -22,7 +22,7 @@ the power sequence timing parameters, which are usually named T[N] and also
referenced in Intel's respective registers listing. You need the values for
`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`:
```eval_rst
```{eval-rst}
+-----------------------------+---------------------------------------+-----+
| Intel docs | devicetree.cb | eDP |
+-----------------------------+---------------------------------------+-----+

62
Documentation/index.md
View File

@ -170,34 +170,38 @@ for example OpenBSD, is probably the closest cousin of our approach.
Contents:
* [Getting Started](getting_started/index.md)
* [Tutorial](tutorial/index.md)
* [Contributing](contributing/index.md)
* [Community](community/index.md)
* [Payloads](payloads.md)
* [Distributions](distributions.md)
* [Technotes](technotes/index.md)
* [ACPI](acpi/index.md)
* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
* [Display panel](gfx/display-panel.md)
* [CPU Architecture](arch/index.md)
* [Platform independent drivers](drivers/index.md)
* [Northbridge](northbridge/index.md)
* [System on Chip](soc/index.md)
* [Mainboard](mainboard/index.md)
* [Payloads](lib/payloads/index.md)
* [Libraries](lib/index.md)
* [Options](lib/option.md)
* [Security](security/index.md)
* [SuperIO](superio/index.md)
* [Vendorcode](vendorcode/index.md)
* [Utilities](util.md)
* [Software Bill of Materials](sbom/sbom.md)
* [Project infrastructure & services](infrastructure/index.md)
* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
* [Release notes](releases/index.md)
* [Acronyms & Definitions](acronyms.md)
* [External Resources](external_docs.md)
* [Documentation License](documentation_license.md)
```{toctree}
:maxdepth: 1
Getting Started <getting_started/index.md>
Tutorial <tutorial/index.md>
Contributing <contributing/index.md>
Community <community/index.md>
Payloads <payloads.md>
Distributions <distributions.md>
Technotes <technotes/index.md>
ACPI <acpi/index.md>
Native Graphics Initialization with libgfxinit <gfx/libgfxinit.md>
Display panel <gfx/display-panel.md>
CPU Architecture <arch/index.md>
Platform independent drivers <drivers/index.md>
Northbridge <northbridge/index.md>
System on Chip <soc/index.md>
Mainboard <mainboard/index.md>
Payloads <lib/payloads/index.md>
Libraries <lib/index.md>
Options <lib/option.md>
Security <security/index.md>
SuperIO <superio/index.md>
Vendorcode <vendorcode/index.md>
Utilities <util.md>
Software Bill of Materials <sbom/sbom.md>
Project infrastructure & services <infrastructure/index.md>
Boards supported in each release directory <releases/boards_supported_on_branches.md>
Release notes <releases/index.md>
Acronyms & Definitions <acronyms.md>
External Resources <external_docs.md>
Documentation License <documentation_license.md>
```
[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Documentation/

12
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View File

@ -93,11 +93,19 @@ You can see all the builds in the main jenkins interface:
Most of the time on the builders is taken up by the coreboot main and
coreboot gerrit builds.
* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
```{toctree}
:maxdepth: 1
coreboot gerrit build <https://qa.coreboot.org/job/coreboot-gerrit/>
```
([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
* [coreboot main build](https://qa.coreboot.org/job/coreboot/)
```{toctree}
:maxdepth: 1
coreboot main build <https://qa.coreboot.org/job/coreboot/>
```
([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))

16
Documentation/infrastructure/index.md
View File

@ -4,9 +4,17 @@ This section contains documentation about our infrastructure
## Services
* [Project services](services.md)
* [Administrator's handbook](admin.md)
```{toctree}
:maxdepth: 1
Project services <services.md>
Administrator's handbook <admin.md>
```
## Jenkins builders and builds
* [Setting up Jenkins build machines](builders.md)
* [Coverity Scan integration](coverity.md)
```{toctree}
:maxdepth: 1
Setting up Jenkins build machines <builders.md>
Coverity Scan integration <coverity.md>
```

12
Documentation/lib/index.md
View File

@ -3,7 +3,11 @@
This section contains documentation about coreboot internal technical
information and libraries.
- [Flashmap and Flashmap Descriptor](flashmap.md)
- [ABI data consumption](abi-data-consumption.md)
- [Timestamps](timestamp.md)
- [Firmware Configuration Interface](fw_config.md)
```{toctree}
:maxdepth: 1
Flashmap and Flashmap Descriptor <flashmap.md>
ABI data consumption <abi-data-consumption.md>
Timestamps <timestamp.md>
Firmware Configuration Interface <fw_config.md>
```

6
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View File

@ -8,4 +8,8 @@ selected mainboard.
## FIT
- [uImage.FIT support](fit.md)
```{toctree}
:maxdepth: 1
uImage.FIT support <fit.md>
```

6
Documentation/mainboard/acer/g43t-am3.md
View File

@ -5,7 +5,7 @@ Acer models Aspire M3800, Aspire M5800 and possibly more.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | Intel G43 (called x4x in coreboot code) |
+------------------+--------------------------------------------------+
@ -69,7 +69,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
## Flashing coreboot
```eval_rst
```{eval-rst}
+-------------------+---------------------+
| Type | Value |
+===================+=====================+
@ -122,7 +122,7 @@ $ sudo flashrom \
-w coreboot.rom
```
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```

6
Documentation/mainboard/amd/pademelon/pademelon.md
View File

@ -33,7 +33,7 @@ Three items are marked in this picture
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------+
| Type | Value |
+=====================+====================+
@ -53,7 +53,7 @@ Three items are marked in this picture
## Technology
```eval_rst
```{eval-rst}
+---------------+------------------------------+
| Fan control | Using fintek F81803A |
+---------------+------------------------------+
@ -63,7 +63,7 @@ Three items are marked in this picture
## Description of pictures within this document
```eval_rst
```{eval-rst}
+----------------------------+----------------------------------------+
|pademelon.jpg | Motherboard with components identified |
+----------------------------+----------------------------------------+

4
Documentation/mainboard/asrock/h110m-dvs.md
View File

@ -11,7 +11,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
FSP Information:
```eval_rst
```{eval-rst}
+-----------------------------+-------------------+-------------------+
| FSP Project Name | Directory | Specification |
+-----------------------------+-------------------+-------------------+
@ -114,7 +114,7 @@ facing towards the bottom of the board.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Skylake/Kaby Lake (LGA1151) |
+------------------+--------------------------------------------------+

6
Documentation/mainboard/asrock/h77pro4-m.md
View File

@ -5,7 +5,7 @@ Bridge and Ivy Bridge CPUs.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
@ -71,7 +71,7 @@ extlinux
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -115,7 +115,7 @@ $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
The use of `--noverify-all` is required since the Management Engine
region is not readable even by the host.
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```

6
Documentation/mainboard/asrock/h81m-hds.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
## Required proprietary blobs
```eval_rst
```{eval-rst}
Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
```
@ -75,7 +75,7 @@ facing towards the bottom of the board.
in coreboot. The `coretemp` driver can still be used for accurate CPU
temperature readings from an OS.
```eval_rst
```{eval-rst}
Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
```
@ -111,7 +111,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/haswell/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/a88xm-e.md
View File

@ -14,7 +14,7 @@ and their GPU is [Sea Islands] (GCN2-based).
A10 Richland is recommended for the best performance and working IOMMU.
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| A88XM-E | |
+------------------+--------------------------------------------------+
@ -36,7 +36,7 @@ A10 Richland is recommended for the best performance and working IOMMU.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

8
Documentation/mainboard/asus/f2a85-m.md
View File

@ -15,7 +15,7 @@ Both "Trinity" and "Richland" desktop processing units are working,
the CPU architecture in these CPUs/APUs is [Piledriver],
and their GPU is [TeraScale 3] (VLIW4-based).
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| F2A85-M | |
+------------------+--------------------------------------------------+
@ -35,7 +35,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
+------------------+--------------------------------------------------+
```
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| F2A85-M LE | |
+------------------+--------------------------------------------------+
@ -55,7 +55,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
+------------------+--------------------------------------------------+
```
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| F2A85-M PRO | |
+------------------+--------------------------------------------------+
@ -77,7 +77,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

4
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View File

@ -10,7 +10,7 @@ This page describes how to run coreboot on the ASUS P2B-LS mainboard.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------------+
| Type | Value |
+=====================+===========================+
@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+

4
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View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the ASUS P3B-F mainboard.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------------+
| Type | Value |
+=====================+===========================+
@ -88,7 +88,7 @@ for only CPU models that the board will actually be run with.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+

4
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View File

@ -32,7 +32,7 @@ This page describes how to run coreboot on the [ASUS P5Q] desktop board.
## Flashing coreboot
```eval_rst
```{eval-rst}
+-------------------+----------------+
| Type | Value |
+===================+================+
@ -56,7 +56,7 @@ You can flash coreboot into your motherboard using [this guide].
## Technology
```eval_rst
```{eval-rst}
+------------------+---------------------------------------------------+
| Northbridge | Intel P45 (called x4x in coreboot code) |
+------------------+---------------------------------------------------+

4
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View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -69,7 +69,7 @@ flash externally.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/p8h61-m_lx.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M LX].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -84,7 +84,7 @@ region is not readable even by the host.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/p8h61-m_pro.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M Pro].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -78,7 +78,7 @@ region is not readable even by the host.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/p8h77-v.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -56,7 +56,7 @@ work. The flash chip is socketed, so it's easy to remove and reflash.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/p8z77-m.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -112,7 +112,7 @@ therefore they currently do nothing under coreboot.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/p8z77-m_pro.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M PRO]
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -143,7 +143,7 @@ easy to remove and reflash.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/asus/p8z77-v.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-V].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -86,7 +86,7 @@ See [Asus Wi-Fi Go! v1].
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/asus/wifigo_v1.md
View File

@ -8,7 +8,7 @@ through a proprietary 16-1 pin connector.
I managed to grope the most pinout of the proprietary connector.
See [Mini PCIe pinout] for more info.
```eval_rst
```{eval-rst}
+------------+----------+-----------+------------+----------+-----------+
| WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin |
+============+==========+===========+============+==========+===========+

4
Documentation/mainboard/cavium/cn8100_sff_evb.md
View File

@ -17,7 +17,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -58,7 +58,7 @@
## Technology
```eval_rst
```{eval-rst}
+---------------+----------------------------------------+
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
+---------------+----------------------------------------+

4
Documentation/mainboard/clevo/n130wu/index.md
View File

@ -2,7 +2,7 @@
## Hardware
### Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------+
| CPU | Intel i7-8550U |
+------------------+--------------------------------+
@ -15,7 +15,7 @@
```
### Flash chip
```eval_rst
```{eval-rst}
+---------------------+-----------------+
| Type | Value |
+=====================+=================+

6
Documentation/mainboard/dell/optiplex_9010.md
View File

@ -6,7 +6,7 @@ This page describes how to run coreboot on Dell OptiPlex 9010 SFF.
## Technology
```eval_rst
```{eval-rst}
+------------+---------------------------------------------------------------+
| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) |
+------------+---------------------------------------------------------------+
@ -28,7 +28,7 @@ More specifications on [Dell OptiPlex 9010 specifications].
## Required proprietary blobs
```eval_rst
```{eval-rst}
+------------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+==================+=================================+=====================+
@ -50,7 +50,7 @@ signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+

2
Documentation/mainboard/facebook/fbg1701.md
View File

@ -63,7 +63,7 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| SoC | Intel Atom Processor N3710 |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/facebook/monolith.md
View File

@ -14,7 +14,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
FSP Information:
```eval_rst
```{eval-rst}
+-----------------------------+-------------------+-------------------+
| FSP Project Name | Directory | Specification |
+-----------------------------+-------------------+-------------------+
@ -116,7 +116,7 @@ output.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| SoC | Intel Kaby Lake U |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/foxconn/d41s.md
View File

@ -14,7 +14,7 @@ The default options for this board should result in a fully working image:
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------+
| Type | Value |
+=====================+========+
@ -56,7 +56,7 @@ To do this gently take the SPI flash out of its socket and flash with your progr
## Technology
```eval_rst
```{eval-rst}
+------------------+------------------+
| Northbridge | Intel Pinevew |
+------------------+------------------+

6
Documentation/mainboard/gigabyte/ga-g41m-es2l.md
View File

@ -6,7 +6,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Type | Value |
+==================+==================================================+
@ -30,7 +30,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
## Preparation
```eval_rst
```{eval-rst}
For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
```
@ -140,7 +140,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
## Flashing coreboot
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```

4
Documentation/mainboard/gigabyte/ga-h61m-s2pv.md
View File

@ -5,7 +5,7 @@ from [Gigabyte].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -59,7 +59,7 @@ However, this makes DualBIOS unable to recover from a bad flash for some reason.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/hp/2170p.md
View File

@ -74,7 +74,7 @@ The EHCI debug port is the left USB3 port.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Sandy/Ivy Bridge (FCPGA988) |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/hp/2560p.md
View File

@ -80,7 +80,7 @@ Schematic of this laptop can be found on [Lab One].
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Sandy/Ivy Bridge (FCPGA988) |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/hp/8760w.md
View File

@ -7,7 +7,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -66,7 +66,7 @@ clip to read and flash the chip.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/hp/compaq_8200_sff.md
View File

@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-------------------------+
| Type | Value |
+=====================+=========================+
@ -128,7 +128,7 @@ as otherwise there's not enough space near the flash.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/hp/compaq_8300_usdt.md
View File

@ -5,7 +5,7 @@ from [HP].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-------------+
| Type | Value |
+=====================+=============+
@ -42,7 +42,7 @@ Wake on LAN is active works great.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/hp/elitebook_820_g2.md
View File

@ -124,7 +124,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
## Technology
```eval_rst
```{eval-rst}
+------------------+-----------------------------+
| SoC | Intel Broadwell |
+------------------+-----------------------------+

2
Documentation/mainboard/hp/folio_9480m.md
View File

@ -138,7 +138,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
## Technology
```eval_rst
```{eval-rst}
+------------------+-----------------------------+
| CPU | Intel Haswell-ULT |
+------------------+-----------------------------+

4
Documentation/mainboard/hp/z220_sff.md
View File

@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-------------+
| Type | Value |
+=====================+=============+
@ -58,7 +58,7 @@ even interchangeable, so should do coreboot images built for them.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

402
Documentation/mainboard/index.md
View File

@ -4,240 +4,392 @@ This section contains documentation about coreboot on specific mainboards.
## 51NB
- [X210](51nb/x210.md)
```{toctree}
:maxdepth: 1
X210 <51nb/x210.md>
```
## Acer
- [G43T-AM3](acer/g43t-am3.md)
```{toctree}
:maxdepth: 1
G43T-AM3 <acer/g43t-am3.md>
```
## AMD
- [pademelon](amd/pademelon/pademelon.md)
```{toctree}
:maxdepth: 1
pademelon <amd/pademelon/pademelon.md>
```
## ASRock
- [H77 Pro4-M](asrock/h77pro4-m.md)
- [H81M-HDS](asrock/h81m-hds.md)
- [H110M-DVS](asrock/h110m-dvs.md)
```{toctree}
:maxdepth: 1
H77 Pro4-M <asrock/h77pro4-m.md>
H81M-HDS <asrock/h81m-hds.md>
H110M-DVS <asrock/h110m-dvs.md>
```
## ASUS
- [A88XM-E](asus/a88xm-e.md)
- [F2A85-M](asus/f2a85-m.md)
- [P2B-LS](asus/p2b-ls.md)
- [P3B-F](asus/p3b-f.md)
- [P5Q](asus/p5q.md)
- [P8C WS](asus/p8c_ws.md)
- [P8H61-M LX](asus/p8h61-m_lx.md)
- [P8H61-M Pro](asus/p8h61-m_pro.md)
- [P8H77-V](asus/p8h77-v.md)
- [P8Z77-M](asus/p8z77-m.md)
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
- [P8Z77-V](asus/p8z77-v.md)
- [wifigo_v1](asus/wifigo_v1.md)
```{toctree}
:maxdepth: 1
A88XM-E <asus/a88xm-e.md>
F2A85-M <asus/f2a85-m.md>
P2B-LS <asus/p2b-ls.md>
P3B-F <asus/p3b-f.md>
P5Q <asus/p5q.md>
P8C WS <asus/p8c_ws.md>
P8H61-M LX <asus/p8h61-m_lx.md>
P8H61-M Pro <asus/p8h61-m_pro.md>
P8H77-V <asus/p8h77-v.md>
P8Z77-M <asus/p8z77-m.md>
P8Z77-M Pro <asus/p8z77-m_pro.md>
P8Z77-V <asus/p8z77-v.md>
wifigo_v1 <asus/wifigo_v1.md>
```
## Cavium
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
```{toctree}
:maxdepth: 1
CN81XX EVB SFF <cavium/cn8100_sff_evb.md>
```
## Clevo
- [N130WU / N131WU](clevo/n130wu/index.md)
```{toctree}
:maxdepth: 1
N130WU / N131WU <clevo/n130wu/index.md>
```
## Dell
- [OptiPlex 9010 SFF](dell/optiplex_9010.md)
```{toctree}
:maxdepth: 1
OptiPlex 9010 SFF <dell/optiplex_9010.md>
```
## Emulation
The boards in this section are not real mainboards, but emulators.
- [Spike RISC-V emulator](emulation/spike-riscv.md)
- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
- [QEMU x86 Q35](emulation/qemu-q35.md)
- [QEMU x86 PC](emulation/qemu-i440fx.md)
- [QEMU POWER9](emulation/qemu-power9.md)
```{toctree}
:maxdepth: 1
Spike RISC-V emulator <emulation/spike-riscv.md>
QEMU RISC-V emulator <emulation/qemu-riscv.md>
QEMU AArch64 emulator <emulation/qemu-aarch64.md>
QEMU x86 Q35 <emulation/qemu-q35.md>
QEMU x86 PC <emulation/qemu-i440fx.md>
QEMU POWER9 <emulation/qemu-power9.md>
```
## Facebook
- [FBG-1701](facebook/fbg1701.md)
- [Monolith](facebook/monolith.md)
```{toctree}
:maxdepth: 1
FBG-1701 <facebook/fbg1701.md>
Monolith <facebook/monolith.md>
```
## Foxconn
- [D41S](foxconn/d41s.md)
```{toctree}
:maxdepth: 1
D41S <foxconn/d41s.md>
```
## Gigabyte
- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md)
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
```{toctree}
:maxdepth: 1
GA-G41M-ES2L <gigabyte/ga-g41m-es2l.md>
GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
```
## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
- [Z220 Workstation SFF](hp/z220_sff.md)
```{toctree}
:maxdepth: 1
Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
Z220 Workstation SFF <hp/z220_sff.md>
```
### EliteBook series
- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
- [HP Sure Start](hp/hp_sure_start.md)
- [EliteBook 2170p](hp/2170p.md)
- [EliteBook 2560p](hp/2560p.md)
- [EliteBook 8760w](hp/8760w.md)
- [EliteBook Folio 9480m](hp/folio_9480m.md)
- [EliteBook 820 G2](hp/elitebook_820_g2.md)
```{toctree}
:maxdepth: 1
HP Laptops with KBC1126 EC <hp/hp_kbc1126_laptops.md>
HP Sure Start <hp/hp_sure_start.md>
EliteBook 2170p <hp/2170p.md>
EliteBook 2560p <hp/2560p.md>
EliteBook 8760w <hp/8760w.md>
EliteBook Folio 9480m <hp/folio_9480m.md>
EliteBook 820 G2 <hp/elitebook_820_g2.md>
```
## Intel
- [DG43GT](intel/dg43gt.md)
- [DQ67SW](intel/dq67sw.md)
- [KBLRVP11](intel/kblrvp11.md)
```{toctree}
:maxdepth: 1
DG43GT <intel/dg43gt.md>
DQ67SW <intel/dq67sw.md>
KBLRVP11 <intel/kblrvp11.md>
```
## Kontron
- [mAL-10](kontron/mal10.md)
```{toctree}
:maxdepth: 1
mAL-10 <kontron/mal10.md>
```
## Lenovo
- [Mainboard codenames](lenovo/codenames.md)
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
- [R60](lenovo/r60.md)
- [T4xx common](lenovo/t4xx_series.md)
- [X2xx common](lenovo/x2xx_series.md)
- [vboot](lenovo/vboot.md)
```{toctree}
:maxdepth: 1
Mainboard codenames <lenovo/codenames.md>
Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md>
R60 <lenovo/r60.md>
T4xx common <lenovo/t4xx_series.md>
X2xx common <lenovo/x2xx_series.md>
vboot <lenovo/vboot.md>
```
### GM45 series
- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
- [X301](lenovo/x301.md)
```{toctree}
:maxdepth: 1
X200 / T400 / T500 / X301 common <lenovo/montevina_series.md>
X301 <lenovo/x301.md>
```
### Arrandale series
- [T410](lenovo/t410.md)
```{toctree}
:maxdepth: 1
T410 <lenovo/t410.md>
```
### Sandy Bridge series
- [T420](lenovo/t420.md)
- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md)
- [X1](lenovo/x1.md)
```{toctree}
:maxdepth: 1
T420 <lenovo/t420.md>
T420 / T520 / X220 / T420s / W520 common <lenovo/Sandy_Bridge_series.md>
X1 <lenovo/x1.md>
```
### Ivy Bridge series
- [T430](lenovo/t430.md)
- [T530 / W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
- [T431s](lenovo/t431s.md)
- [X230s](lenovo/x230s.md)
- [Internal flashing](lenovo/ivb_internal_flashing.md)
```{toctree}
:maxdepth: 1
T430 <lenovo/t430.md>
T530 / W530 <lenovo/w530.md>
T430 / T530 / X230 / W530 common <lenovo/Ivy_Bridge_series.md>
T431s <lenovo/t431s.md>
X230s <lenovo/x230s.md>
Internal flashing <lenovo/ivb_internal_flashing.md>
```
### Haswell series
- [T440p](lenovo/t440p.md)
```{toctree}
:maxdepth: 1
T440p <lenovo/t440p.md>
```
## Libretrend
- [LT1000](libretrend/lt1000.md)
```{toctree}
:maxdepth: 1
LT1000 <libretrend/lt1000.md>
```
## MSI
- [MS-7707](msi/ms7707/ms7707.md)
```{toctree}
:maxdepth: 1
MS-7707 <msi/ms7707/ms7707.md>
```
## OCP
- [Delta Lake](ocp/deltalake.md)
- [Tioga Pass](ocp/tiogapass.md)
```{toctree}
:maxdepth: 1
Delta Lake <ocp/deltalake.md>
Tioga Pass <ocp/tiogapass.md>
```
## Open Cellular
- [Elgon](opencellular/elgon.md)
```{toctree}
:maxdepth: 1
Elgon <opencellular/elgon.md>
```
## PC Engines
- [APU1](pcengines/apu1.md)
- [APU2](pcengines/apu2.md)
```{toctree}
:maxdepth: 1
APU1 <pcengines/apu1.md>
APU2 <pcengines/apu2.md>
```
## Portwell
- [PQ7-M107](portwell/pq7-m107.md)
```{toctree}
:maxdepth: 1
PQ7-M107 <portwell/pq7-m107.md>
```
## Prodrive
- [Hermes](prodrive/hermes.md)
```{toctree}
:maxdepth: 1
Hermes <prodrive/hermes.md>
```
## Purism
- [Librem 14](purism/librem_14.md)
- [Librem Mini](purism/librem_mini.md)
```{toctree}
:maxdepth: 1
Librem 14 <purism/librem_14.md>
Librem Mini <purism/librem_mini.md>
```
## Protectli
- [FW2B / FW4B](protectli/fw2b_fw4b.md)
- [FW6A / FW6B / FW6C](protectli/fw6.md)
- [VP2420](protectli/vp2420.md)
- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
```{toctree}
:maxdepth: 1
FW2B / FW4B <protectli/fw2b_fw4b.md>
FW6A / FW6B / FW6C <protectli/fw6.md>
VP2420 <protectli/vp2420.md>
VP4630 / VP4650 / VP4670 <protectli/vp46xx.md>
```
## Roda
- [RK9 Flash Header](roda/rk9/flash_header.md)
```{toctree}
:maxdepth: 1
RK9 Flash Header <roda/rk9/flash_header.md>
```
## SiFive
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
```{toctree}
:maxdepth: 1
SiFive HiFive Unleashed <sifive/hifive-unleashed.md>
```
## Star Labs Systems
- [LabTop Mk III](starlabs/labtop_kbl.md)
- [LabTop Mk IV](starlabs/labtop_cml.md)
- [StarLite Mk III](starlabs/lite_glk.md)
- [StarLite Mk IV](starlabs/lite_glkr.md)
- [StarBook Mk V](starlabs/starbook_tgl.md)
- [StarBook Mk VI](starlabs/starbook_adl.md)
- [Flashing devices](starlabs/common/flashing.md)
```{toctree}
:maxdepth: 1
LabTop Mk III <starlabs/labtop_kbl.md>
LabTop Mk IV <starlabs/labtop_cml.md>
StarLite Mk III <starlabs/lite_glk.md>
StarLite Mk IV <starlabs/lite_glkr.md>
StarBook Mk V <starlabs/starbook_tgl.md>
StarBook Mk VI <starlabs/starbook_adl.md>
Flashing devices <starlabs/common/flashing.md>
```
## Supermicro
- [X9SAE](supermicro/x9sae.md)
- [X10SLM+-F](supermicro/x10slm-f.md)
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
```{toctree}
:maxdepth: 1
X9SAE <supermicro/x9sae.md>
X10SLM+-F <supermicro/x10slm-f.md>
X11 LGA1151 series <supermicro/x11-lga1151-series/x11-lga1151-series.md>
Flashing using the BMC <supermicro/flashing_on_vendorbmc.md>
```
## System76
- [Adder Workstation 1](system76/addw1.md)
- [Adder Workstation 2](system76/addw2.md)
- [Adder Workstation 3](system76/addw3.md)
- [Bonobo Workstation 14](system76/bonw14.md)
- [Bonobo Workstation 15](system76/bonw15.md)
- [Darter Pro 6](system76/darp6.md)
- [Darter Pro 7](system76/darp7.md)
- [Darter Pro 8](system76/darp8.md)
- [Darter Pro 9](system76/darp9.md)
- [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md)
- [Galago Pro 6](system76/galp6.md)
- [Galago Pro 7](system76/galp7.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Gazelle 18](system76/gaze18.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md)
- [Lemur Pro 12](system76/lemp12.md)
- [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md)
- [Oryx Pro 7](system76/oryp7.md)
- [Oryx Pro 8](system76/oryp8.md)
- [Oryx Pro 9](system76/oryp9.md)
- [Oryx Pro 10](system76/oryp10.md)
- [Oryx Pro 11](system76/oryp11.md)
- [Serval Workstation 13](system76/serw13.md)
```{toctree}
:maxdepth: 1
Adder Workstation 1 <system76/addw1.md>
Adder Workstation 2 <system76/addw2.md>
Adder Workstation 3 <system76/addw3.md>
Bonobo Workstation 14 <system76/bonw14.md>
Bonobo Workstation 15 <system76/bonw15.md>
Darter Pro 6 <system76/darp6.md>
Darter Pro 7 <system76/darp7.md>
Darter Pro 8 <system76/darp8.md>
Darter Pro 9 <system76/darp9.md>
Galago Pro 4 <system76/galp4.md>
Galago Pro 5 <system76/galp5.md>
Galago Pro 6 <system76/galp6.md>
Galago Pro 7 <system76/galp7.md>
Gazelle 15 <system76/gaze15.md>
Gazelle 16 <system76/gaze16.md>
Gazelle 17 <system76/gaze17.md>
Gazelle 18 <system76/gaze18.md>
Lemur Pro 9 <system76/lemp9.md>
Lemur Pro 10 <system76/lemp10.md>
Lemur Pro 11 <system76/lemp11.md>
Lemur Pro 12 <system76/lemp12.md>
Oryx Pro 5 <system76/oryp5.md>
Oryx Pro 6 <system76/oryp6.md>
Oryx Pro 7 <system76/oryp7.md>
Oryx Pro 8 <system76/oryp8.md>
Oryx Pro 9 <system76/oryp9.md>
Oryx Pro 10 <system76/oryp10.md>
Oryx Pro 11 <system76/oryp11.md>
Serval Workstation 13 <system76/serw13.md>
```
## Texas Instruments
- [Beaglebone Black](ti/beaglebone-black.md)
```{toctree}
:maxdepth: 1
Beaglebone Black <ti/beaglebone-black.md>
```
## UP
- [Squared](up/squared/index.md)
```{toctree}
:maxdepth: 1
Squared <up/squared/index.md>
```

4
Documentation/mainboard/intel/dg43gt.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [Intel DG43GT] desktop.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -79,7 +79,7 @@ The layout of the header is:
## Technology
```eval_rst
```{eval-rst}
+------------------+---------------------------------------------------+
| Northbridge | Intel G43 (called x4x in coreboot code) |
+------------------+---------------------------------------------------+

8
Documentation/mainboard/intel/dq67sw.md
View File

@ -4,7 +4,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
@ -67,7 +67,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -104,7 +104,7 @@ the PCI configuration space of the LPC Interface Bridge, is set.
It is possible to program the chip is to attach an external programmer
with an SOIC-8 clip.
```eval_rst
```{eval-rst}
Another way is to boot the vendor firmware in UEFI mode and exploit the
unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
:doc:`../lenovo/ivb_internal_flashing`.
@ -126,7 +126,7 @@ The boot script contains an entry that writes 0x02 to memory at address
Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
prevents this by making it write a 0 instead.
```eval_rst
```{eval-rst}
After suspending and resuming the board, the BIOS region can be flashed with
a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
so the `--noverify-all` flag is necessary. Please refer to the

4
Documentation/mainboard/intel/kblrvp11.md
View File

@ -23,7 +23,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -65,7 +65,7 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
## Technology
```eval_rst
```{eval-rst}
+------------------+---------------------------------------------------+
| CPU | Kaby lake H (i7-7820EQ) |
+------------------+---------------------------------------------------+

2
Documentation/mainboard/kontron/mal10.md
View File

@ -6,7 +6,7 @@ processors.
## Technology
```eval_rst
```{eval-rst}
+------------------+----------------------------------+
| COMe Type | mini pin-out type 10 |
+------------------+----------------------------------+

4
Documentation/mainboard/lenovo/Ivy_Bridge_series.md
View File

@ -3,7 +3,7 @@
This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md).
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------------+
| Type | Value |
+=====================+================================+
@ -37,7 +37,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
* ROM chip size should be set to 12MiB.
```eval_rst
```{eval-rst}
Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
```

2
Documentation/mainboard/lenovo/Sandy_Bridge_series.md
View File

@ -1,7 +1,7 @@
# Lenovo Sandy Bridge series
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------+
| Type | Value |
+=====================+====================+

2
Documentation/mainboard/lenovo/codenames.md
View File

@ -1,6 +1,6 @@
# Lenovo mainboard codenames
```eval_rst
```{eval-rst}
.. csv-table::
:header: "Marketing name", "Development codename"
:file: codenames.csv

8
Documentation/mainboard/lenovo/ivb_internal_flashing.md
View File

@ -19,7 +19,11 @@ that was discovered and fixed later.
- USB drive (in case you need to downgrade BIOS)
- Linux install that (can be) loaded in UEFI mode
- [CHIPSEC](https://github.com/chipsec/chipsec)
```{toctree}
:maxdepth: 1
CHIPSEC <https://github.com/chipsec/chipsec>
```
## BIOS versions
@ -27,7 +31,7 @@ Below is a table of BIOS versions that are vulnerable enough for our
goals, per model. The version number means that you need to downgrade to
that or earlier version.
```eval_rst
```{eval-rst}
+------------+--------------+
| Model | BIOS version |
+============+==============+

8
Documentation/mainboard/lenovo/montevina_series.md
View File

@ -20,7 +20,7 @@ touch any other regions:
## Installing without ME firmware
```eval_rst
```{eval-rst}
.. Note::
**ThinkPad R500** has slightly different flash layout (it doesn't have
``gbe`` region), so the process would be a little different for that model.
@ -51,7 +51,7 @@ your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
Pick the layout according to your chip size from the table below and save it to
the `new_layout.txt` file:
```eval_rst
```{eval-rst}
+---------------------------+---------------------------+---------------------------+
| 4 MiB chip | 8 MiB chip | 16 MiB chip |
+===========================+===========================+===========================+
@ -102,7 +102,7 @@ $ make
If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
`flreg1_limit` in the `ifd-x200.set` file according to following table:
```eval_rst
```{eval-rst}
+-----------------+-------+-------+--------+
| | 4 MiB | 8 MiB | 16 MiB |
+=================+=======+=======+========+
@ -144,7 +144,7 @@ Then build coreboot and flash whole `build/coreboot.rom` to the chip.
The flash layouts of the OEM firmware are as follows:
```eval_rst
```{eval-rst}
+---------------------------------+---------------------------------+
| 4 MiB chip | 8 MiB chip |
+=================================+=================================+

2
Documentation/mainboard/lenovo/t410.md
View File

@ -5,7 +5,7 @@
* TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB)
## Flashing instructions
```eval_rst
```{eval-rst}
+---------------------+--------------------------------+
| Type | Value |
+=====================+================================+

4
Documentation/mainboard/libretrend/lt1000.md
View File

@ -10,7 +10,7 @@ Librebox).
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -98,7 +98,7 @@ The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not
sold yet). More details on [baseboard site]. Unfortunately the board manual is
not publicly available.
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-6500U |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/msi/ms7707/ms7707.md
View File

@ -9,7 +9,7 @@
* IME 7.0.4.1197
## Flash chip (Winbond 25Q32BV)
```eval_rst
```{eval-rst}
+---------------------+--------------------+
| Type | Value |
+=====================+====================+

2
Documentation/mainboard/ocp/deltalake.md
View File

@ -200,7 +200,7 @@ and [u-root] as initramfs.
## Technology
```eval_rst
```{eval-rst}
+------------------------+---------------------------------------------+
| Processor (1 socket) | Intel Cooper Lake Scalable Processor |
+------------------------+---------------------------------------------+

2
Documentation/mainboard/ocp/tiogapass.md
View File

@ -80,7 +80,7 @@ u-root.
## Technology
```eval_rst
```{eval-rst}
+------------------------+---------------------------------------------+
| Processor (2 sockets) | Intel Skylake Scalable Processor LGA3647 |
+------------------------+---------------------------------------------+

4
Documentation/mainboard/opencellular/elgon.md
View File

@ -9,7 +9,7 @@ from [OpenCellular].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -69,7 +69,7 @@ Dediprog compatible pinout.
## Technology
```eval_rst
```{eval-rst}
+---------------+----------------------------------------+
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
+---------------+----------------------------------------+

4
Documentation/mainboard/pcengines/apu1.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on PC Engines APU1 platform.
## Technology
```eval_rst
```{eval-rst}
+------------+--------------------------------------------------------+
| CPU | AMD G series T40E APU |
+------------+--------------------------------------------------------+
@ -23,7 +23,7 @@ This page describes how to run coreboot on PC Engines APU1 platform.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+

6
Documentation/mainboard/pcengines/apu2.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on PC Engines APU2 platform.
## Technology
```eval_rst
```{eval-rst}
+------------+---------------------------------------------------------------+
| CPU | AMD G series GX-412TC |
+------------+---------------------------------------------------------------+
@ -25,7 +25,7 @@ This page describes how to run coreboot on PC Engines APU2 platform.
To build working coreboot image some blobs are needed.
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -41,7 +41,7 @@ blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP*
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+

2
Documentation/mainboard/portwell/pq7-m107.md
View File

@ -61,7 +61,7 @@ serial/video/pcie ports might be available.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| SoC | Intel Atom Processor N3710 |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/prodrive/hermes.md
View File

@ -32,7 +32,7 @@ The board features:
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | CoffeeLake + CoffeeLake R (Core + Xeon) |
+------------------+--------------------------------------------------+

6
Documentation/mainboard/protectli/fw2b_fw4b.md
View File

@ -9,7 +9,7 @@ This page describes how to run coreboot on the [Protectli FW2B] and
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -91,7 +91,7 @@ connected via [FE1.1 USB 2.0 hub].
- FW2B:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J3060 |
+------------------+--------------------------------------------------+
@ -107,7 +107,7 @@ connected via [FE1.1 USB 2.0 hub].
- FW4B:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J3160 |
+------------------+--------------------------------------------------+

8
Documentation/mainboard/protectli/fw6.md
View File

@ -9,7 +9,7 @@ This page describes how to run coreboot on the [Protectli FW6].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -92,7 +92,7 @@ used SoC.
- FW6A:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron 3865U |
+------------------+--------------------------------------------------+
@ -106,7 +106,7 @@ used SoC.
- FW6B:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i3-7100U |
+------------------+--------------------------------------------------+
@ -120,7 +120,7 @@ used SoC.
- FW6C:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i5-7200U |
+------------------+--------------------------------------------------+

18
Documentation/mainboard/protectli/vp2420.md
View File

@ -10,7 +10,7 @@ This page describes how to run coreboot on the [Protectli VP2420].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -66,7 +66,7 @@ MX25L12835F - [datasheet][MX25L12835F].
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J6412 |
+------------------+--------------------------------------------------+
@ -80,8 +80,12 @@ MX25L12835F - [datasheet][MX25L12835F].
## Useful links
- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
- [VP2420 Product Page](https://protectli.com/product/vp2420/)
- [Protectli TPM module](https://protectli.com/product/tpm-module/)
- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
- [flashrom](https://flashrom.org/Flashrom)
```{toctree}
:maxdepth: 1
VP2420 Hardware Overview <https://protectli.com/kb/vp2400-series-hardware-overview/>
VP2420 Product Page <https://protectli.com/product/vp2420/>
Protectli TPM module <https://protectli.com/product/tpm-module/>
MX25L12835F <https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf>
flashrom <https://flashrom.org/Flashrom>
```

18
Documentation/mainboard/protectli/vp46xx.md
View File

@ -10,7 +10,7 @@ This page describes how to run coreboot on the [Protectli VP46xx].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -84,7 +84,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
- VP4630:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i3-10110U |
+------------------+--------------------------------------------------+
@ -98,7 +98,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
- VP4650:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i5-10210U |
+------------------+--------------------------------------------------+
@ -112,7 +112,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
- VP4670:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-10810U |
+------------------+--------------------------------------------------+
@ -126,9 +126,13 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
## Useful links
- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
- [VP4630 Product Page](https://protectli.com/product/vp4630/)
- [Protectli TPM module](https://protectli.com/product/tpm-module/)
```{toctree}
:maxdepth: 1
VP4600 Hardware Overview <https://protectli.com/kb/vp4600-hardware-overview/>
VP4630 Product Page <https://protectli.com/product/vp4630/>
Protectli TPM module <https://protectli.com/product/tpm-module/>
```
[Protectli VP46xx]: https://protectli.com/vault-6-port/
[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf

4
Documentation/mainboard/purism/librem_14.md
View File

@ -2,7 +2,7 @@
This page describes how to run coreboot on the [Purism Librem 14].
```eval_rst
```{eval-rst}
+------------------+------------------------------------------------------+
| CPU | Intel Core i7-10710U |
+------------------+------------------------------------------------------+
@ -23,7 +23,7 @@ This page describes how to run coreboot on the [Purism Librem 14].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+

4
Documentation/mainboard/purism/librem_mini.md
View File

@ -2,7 +2,7 @@
This page describes how to run coreboot on the [Purism Librem Mini].
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-8565U/8665U (v1) |
| | Intel Core i7-10510U (v2) |
@ -25,7 +25,7 @@ This page describes how to run coreboot on the [Purism Librem Mini].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+

2
Documentation/mainboard/starlabs/labtop_cml.md
View File

@ -45,7 +45,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

2
Documentation/mainboard/starlabs/labtop_kbl.md
View File

@ -42,7 +42,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

2
Documentation/mainboard/starlabs/lite_glk.md
View File

@ -41,7 +41,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

2
Documentation/mainboard/starlabs/lite_glkr.md
View File

@ -41,7 +41,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

2
Documentation/mainboard/starlabs/starbook_adl.md
View File

@ -78,7 +78,7 @@ make
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

2
Documentation/mainboard/starlabs/starbook_tgl.md
View File

@ -44,7 +44,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

12
Documentation/mainboard/supermicro/x10slm-f.md
View File

@ -4,13 +4,13 @@ This section details how to run coreboot on the [Supermicro X10SLM+-F].
## Required proprietary blobs
```eval_rst
```{eval-rst}
Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
```
## Building coreboot
```eval_rst
```{eval-rst}
If you haven't already, build the coreboot toolchain as described in
:doc:`../../tutorial/part1`.
```
@ -40,7 +40,7 @@ Now, run `make` to build the coreboot image.
## Flashing coreboot
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```
@ -119,7 +119,7 @@ eventually start. There is no such delay when running coreboot.
## ECC DRAM
```eval_rst
```{eval-rst}
ECC DRAM seems to work, but please see
:doc:`../../northbridge/intel/haswell/mrc.bin`
for caveats.
@ -139,7 +139,7 @@ for caveats.
in coreboot. The `coretemp` driver can still be used for accurate CPU
temperature readings from an OS, and hence the OS can do fan control.
```eval_rst
```{eval-rst}
Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
```
@ -176,7 +176,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | :doc:`../../northbridge/intel/haswell/index` |
+------------------+--------------------------------------------------+

14
Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
View File

@ -6,10 +6,14 @@ Controller etc.
## Supported boards
- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
- [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md)
- [X11SSM-F](x11ssm-f/x11ssm-f.md)
- [X11SSW-F](x11ssw-f/x11ssw-f.md)
```{toctree}
:maxdepth: 1
X11SSH-TF <x11ssh-tf/x11ssh-tf.md>
X11SSH-F/LN4F <x11ssh-f/x11ssh-f.md>
X11SSM-F <x11ssm-f/x11ssm-f.md>
X11SSW-F <x11ssw-f/x11ssw-f.md>
```
## Required proprietary blobs
@ -42,7 +46,7 @@ These issues apply to all boards. Have a look at the board-specific issues, too.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md
View File

@ -55,7 +55,7 @@ So the X11SSH-F just doesn't have 2 NICs populated.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
View File

@ -35,7 +35,7 @@ See general issue section.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
View File

@ -46,7 +46,7 @@ To disable the proprietary LAN firmware, the undocumented jumper J6 can be set t
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md
View File

@ -31,7 +31,7 @@ Flashing was performed through the BMC web interface, when a valid license was e
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+

4
Documentation/mainboard/supermicro/x9sae.md
View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the Supermicro [X9SAE] and [X9SAE-V]
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -81,7 +81,7 @@ seems that it shall not appear on X9SAE even if it is defined.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/system76/addw1.md
View File

@ -44,7 +44,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+

2
Documentation/mainboard/system76/addw2.md
View File

@ -43,7 +43,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-----------------+
| Type | Value |
+=====================+=================+

2
Documentation/mainboard/system76/addw3.md
View File

@ -48,7 +48,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+

2
Documentation/mainboard/system76/bonw14.md
View File

@ -53,7 +53,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+

2
Documentation/mainboard/system76/bonw15.md
View File

@ -42,7 +42,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+

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