UsbTcPortEn is configured based on pointers to tcss_usb3_port1,
which is part of the ACPI driver.
This is illogical, as the port might need to be enabled, and
the ACPI not needed or included. Change this so it's configured
based on the tcss_port[x] in devicetree.
Tested by connecting a USB 3.0 hub, and checking that Linux
correctly identifies a new USB 3.0 device.
Change-Id: I07ef0759057f7f40210766a73643c9ccf1dc986d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Commit 4c7e97b26a ("Update fsp submodule to upstream master branch")
included an update to the VBT from 240 to 250, breaking parsing of
existing VBTs.
Generate blobs for the new version using Intel Display Configuration
Tool (DisCon) v3.3.
Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Intel introduced a new UPD for setting the HDA subsystem ID in FSP-M.
Using SiSsidTablePtr in FSP-S no longer works as it will be locked with
a default value of 0 by that point.
Change-Id: I174f9a5faf7e8dbbb370d7a4c3d6e9107fb59123
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.
Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration
at the SoC level for all MTL devices. This change streamlines the
configuration process, avoiding redundant selections on individual
mainboards.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/ovis and google/rex.
Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch refactors RAMTOP MTRR type selection to address a critical
NEM logic bug on SoCs with non-power-of-two cache sets. This bug can
cause runtime hangs when Write Back (WB) caching is enabled.
Workaround: Force MTRR type to WC (Write Combining) on affected SoCs
when the cache set count is not a power of two.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a function to determine whether the number of cache sets is
a power of two. This aligns with common cache design practices that
favor power-of-two counts for efficient indexing and addressing.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified functionality on google/ovis and google/rex (including
a non-power-of-two Ovis configuration).
Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the default position for ramtop and exclude it from the checksum.
Fixes invalid checksum after caching ramtop causing things like
disabling CSME to not work.
Change-Id: Ic7e0cac479e88b0c2645511e5ba4fd9622573a17
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Sending the disable and EOP commands will not work if flash descriptor
override is set on meteorlake.
Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee
Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
MRC fast boot causes issues with memory init reusing invalid values
when DIMMs are switched.
Change-Id: Ia053982f747b2e794b974b84d57a9ead61ddd2ea
Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being
mismatched.
If it's mismatched, the TBT port will timeout.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add
The latest Clevo boards connect the TAS5825M to one of the I2C
connections instead of the SMBus connection. The I2C ops are compatible
with SMBus, so always use them.
Change-Id: I5152db647094acf473cc798970dd9d97543df4d7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Port fix from Alder Lake to not set/reset IOM MCTP during
D3 cold entry or exit.
Ports 5008d34003 ("soc/intel/adl: Remove IOM Mctp command from TCSS
ASL"):
> Recently as part of s0ix hang issue, it was found that sending IOM
> MCTP command as part of TCSS D3 Cold enter-exit sequence created an
> issue.
> We discovered that due to change in hardware sequence, ADL should not
> set/reset IOM MCTP during D3 cold entry or exit. This patch removes
> the bit setting from ASL file to prevent hang in the system.
> This patch also removes obsolete Pcode mailbox communication which
> is no longer required for ADL.
> BUG=b:220796339
> BRANCH=firmware-brya-14505.B
> TEST=Check if hang issue is resolved with the CL and no other
> regression
> observed
> https://review.coreboot.org/c/coreboot/+/62861
Test: build/boot drobit to Win11. Verify TCSS XHCI power management
working and USB Root Hub doesn't Code 43 in device manager
Change-Id: I40a537fd2b0c821caf282f52aaff1874f54325f1
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80719
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
BUG=b:301854636
TEST=/sys/devices/system/cpu/cpuidle/
low_power_idle_system_residency_us" will show system idle residency time
Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit 2d48238618 ("soc/intel/alderlake: Set PchHdaSdiEnable for Alder
Lake") hooked up a new UPD, overriding the FSP default and causing HDA
init to break. Hook up the new UPD in the devicetree to restore HDA
functionality.
Also remove PchHdaAudioLinkHdaEnable per board romstage, as it set in
the devicetree.
Change-Id: I2533fa829fac4913308379788911339effa36d9f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
On Raptor Lake based systems with TCSS, Linux will report ACPI
errors for \_SB.PCI0.TDM0 and \_SB.PCI0.TRP0. This is due to the
tcss.asl file only being included for one specific mainboard. This
change includes tcss.asl for all Raptor Lake models.
Change-Id: I2d8de7a77cfa91cd8bdbb9c3048e21d0a677d2fa
Signed-off-by: Dan Campbell <dan@compiledworks.com>
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume. This issue has only been experienced on lemp12, and only with
Samsung drives, but implies it could happen on other systems or with
other drives as well.
Tested on lemp12 with Samsung 980 PRO and 990 PRO drives.
Change-Id: Ieacab03f6cb0943ed2a589e9bb7669d3d8fd45ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Retry calling the SMI 5 times in case the initial write to APM did not
cause SMM entry immediately.
Fixes occasional SMMSTORE initialization failure on Clevo NV4xPZ with
Intel i5-1240P processor. The issue was especially evident when all
logging in coreboot was disabled.
Based on SMMSTORE implementation in MrChromebox's fork of EDK2:
27854bc8c5
Change-Id: I8929af25c4f69873bbdd835fde5cb60fc324b6ab
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Some drives block the CPU from reaching C10 on suspend without the RTD3
config.
Fixes suspend with the following drives:
- Kingston KC3000 (SKC3000D/4096G)
- Kingston HyperX (SHPM2280P2H/240G)
- Solidigm P44 Pro (SSDPFKKW010X7)
The following drives continue to work:
- Samsung 970 Evo (MZVLB250HAHQ)
- WD Black SN770 (WDS250G3X0E)
- WD Green SN350 (WDS240G2G0C-00AJM0)
- WD Blue SN570 (WDS100T3B0C)
Change-Id: I205d78377fa2b0db8d37542cdb94ba86ded1d66e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>
Since these boards will use S0ix they need to leave CSME enabled for the
CPU to reach C10.
Change-Id: I70c908402c9964508bb9c439d48d24773f5a35ab
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The newer batch of these boards do not de-assert VW PLTRST# on S3
resume, causes the units to not power on in the EC code. Switch them to
S0ix by default, but leave S3 available.
Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905
Signed-off-by: Tim Crawford <tcrawford@system76.com>
