Fast SPI code assumes only one SPI flash is present. The SPI flash
driver for older southbridges is able to detect multichip. See the
spi_is_multichip() in src/southbridge/intel/common/spi.c.
Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two
chips populated instead of one. With this change, both chips are probed,
and the correct total size is calculated. Otherwise, only the first one
was probed, which resulted in an error such as:
SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!
Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
intel/common/block/acpi provides default soc_get_ioapic_info for
single IOAPIC model. Use the default soc_get_ioapic_info when
XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and
later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change refactors EDK2 essential header management within the FSP
directory to ensure compatibility.
Header selection is now dynamically based on:
* FSP specification version: Distinguishes between 1.1 and 2.x
* EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header
FSP Header
|
|-> FSP 1.1 specification FSP_INFO_HEADER
|-> FSP 2.0 specification EDK2 release
|-> EDK2_2017 FSP_INFO_HEADER
|-> EDK2_2020 FSP_INFO_HEADER
|-> EDK2_2021 FSP_INFO_HEADER
|-> EDK2_2023 FSP_INFO_HEADER
Any .C/.H file requires to include FSP_INFO_HEADER can now just add the
FSP header alone.
BUG=b:242829490
TEST=Able to build google/rex0 with 64-bit FSP.
Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces the FSP_SIG macro into EDK2 headers to ensure
compilation compatibility when using FSP 2.x specifications.
Previously, the macro was only defined for FSP 1.1.
BUG=b:242829490
TEST=Successful build of google/rex0 with 64-bit FSP.
Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities such as system power down.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:328729536
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
[When connected 60W adapter without battery]
Before:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
After:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:60000000
[When connected 45W adapter without battery]
Before:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
After:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:45000000
constraint_2_power_limit_uw:45000000
Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In order to avoid the noise caused by the codec output to the audio
jack during the shutdown and poweron process, we will use GPP_A11 for
the codec power supply gate, keep low during the startup process, and
wait for the driver to turn on. This change does not affect the beep
output of depthcharge.
BUG=None
TEST=There is no squeaking sound when turning on and off
Change-Id: I5982be5a8d965086b46861f4c2c758d9bdee6e75
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81629
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Currently the SRAT table only exposes one proximity group as
it uses the LAPIC node_id, which is always initialized to 0.
Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it
to make sure that at least one proximity group for every socket
is advertised.
For now the SNC config isn't taken into account.
Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch replaces UINT8 with uint8_t to align with coreboot's
standard data type conventions.
This promotes consistency within the codebase.
BUG=b:242829490
TEST=Verified firmware splash screen functionality on google/rex0.
Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81571
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Deku has two Ethernet ports. Currently both get assigned the wrong
MAC address due to the LAN devices indices being swapped and
vpd ethernet_mac0() affects device eth1 and vpd ethernet_mac1() affects
device eth0.
Correct the device indices for LAN devices so ethernet_mac[0-1] in vpd
can apply to the correct ethernet ports.
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=vpd -s ethernet_mac0=<mac address0>
vpd -s ethernet_mac1=<mac address1>
reboot the system and check ifconfig
eth0 and eth1 MAC addresses are fetched correctly
Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81564
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for
THC0, and 0x7e4b for THC1.
0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0
and THC1 respectively.
Refer MTL EDS vol 1: 640228.
BUG=b:307775082
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81330
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
unlock_pam_regions routes Programmable Attribute Map (PAM) access
to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the
step to SoC specific codes.
TEST=intel/archercity CRB
Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add dynamic PCI domain _OSC ASL generation codes, supporting both
PCIe and CXL domains.
Dynamic SSDT generation is used to generate a list of ASL device
objects based on FSP outputs (e.g. the SoC/SKU configurations)
and _OSC is a method inside these objects (hence it would be
straightforward to be generated altogether, plus some C codes
managed boot configs could be referenced as well).
This usage is optional. It is helpful for cases where the same
code set supports multiple SKUs/SoCs (difficult to be handled by
one set of static SSDT), and the CPU performance is good enough
to run SSDT generation logics with minimal costs.
TEST=intel/archercity CRB
Tested with https://review.coreboot.org/c/coreboot/+/81377.
Change-Id: I711ce5350d718e47feb2912555108801ad7f918d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
IBL (Integrated Boot Logic) provides a subset of server
PCH logics for no-PCH solution. IBL is with limited features
and registers exposed, PCIe root ports/USB/SATA/LAN support are
removed.
Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/
UDS_SOCKET_RES and retires the usages of STACK_RES/
IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common
codes to work for both 6th Gen before and later.
Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81040
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.
I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c as a test for bug b/328729536.
```
const struct cpu_power_limits limits[] = {
{PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}
```
And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this patch: msr_pl4 was not changed, it's always 114
- After this patch: msr_pl4 was changed to 80
BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.
Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
ISH Firmware name needs to be configured only when full sensing
capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA
property needs to be added only when UFS is enabled through STORAGE_UFS
FW_CONFIG. Hence configure the ISH device at run-time based on
FW_CONFIG.
BUG=b:319164720
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:328505938
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_SUNDANCE
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
The RPL FSP currently uses HECI commands to retrieve the chipset
initialization version because the MBP HOB creation is disabled
(SkipMbpHob=1). This has resulted in an approximate 150ms increase in
boot time. Investigations are ongoing to determine the cause of the
delay when using HECI commands. As an interim solution, this patch sets
SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset
initialization version, which is expected to reduce the boot time.
BUG=b:328430167
TEST= Able to build,boot and collect boot time data of brya.
With this patch:
963:returning from FspMultiPhaseSiInit 1,337,481 (249,046)
Without this patch:
963:returning from FspMultiPhaseSiInit 1,496,268 (408,194)
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I8a99a57b644732074e41051d99e63576f1edd229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
GNR N-1 FSP headers are a set of stub headers used to fulfill
build sanity check for GNR SoC and CRB codes before the formal
FSP headers are published. The N-1 headers are forward compatible
with the later formal headers.
Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
