For Gen1 SoCs, the range starting from the end of VTd BAR to the end
of 32-bit domain MMIO resource window is reserved for unknown devices.
Get them reserved.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
vtd_probe_bar_size is used to decide the BAR size.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD
sizes larger than 4KB. If the value in the field is N, the size of
the register set is 2^N 4 KB pages.
Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying
to use the beyond 4KB part of the DRHD BAR if they exist. They need
the DRHD size field to set up page mapping before access those
registers.
Re-add acpi_create_dmar_drhd with a size parameter to support the
needs.
TEST=Build and boot on intel/archercity CRB
Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned
off, based on fw_config. Otherwise, when device boots without the cbi
settings for wifi6, boot may fail with assertion error for line 817 &
819 of file 'src/soc/intel/alderlake/fsp_params.c'.
BUG=b:345596420
BRANCH=NONE
TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along
with enumeration of corresponding BT device.
Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
PCIe based GPIOs of Wifi7 module are enabled based on firmware config.
BUG=b:345596420
BRANCH=NONE
TEST= Based on fw config configured, wifi6 or wifi7 along with
bluetooth ports are detected.
Change-Id: If0584e91b5143c6df742961657d242c046409b3a
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe
based Wifi7 module.
BUG=b:345596420
BRANCH=NONE
TEST=With proper FW config enabled, BT gets detected on port8
Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new fw config field for wifi category as WIFI_6, which is CNVi
based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing
CNVi based wifi port as well as bluetooth port.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add wake configuration and set 'add_acpi_dma_property'=true for CNVi.
Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device.
BUG=b:345596420
BRANCH=NONE
TEST=SSDT dump showed below:
Scope (\_SB.PCI0.RP01.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x23,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 17bef2248:
2024-02-05 23:33:50 +0100 - (Merge "feat(fvp): delegate FFH RAS handling to SP" into integration)
to commit id fe4df8bda:
2024-06-07 12:55:56 +0200 - (Merge "feat(rockchip): add RK3566/RK3568 Socs support" into integration)
This brings in 713 new commits.
Change-Id: Icce3595fef3a844034e7cc76fc8480ed5b21618c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This target looks for symbolic links in the coreboot directory,
excluding the 3rdparty and crossgcc directories, which both typically
have numerous symbolic links, and deletes anything that is found.
All possible links are verified as symbolic links before being removed.
Any removed links show where they were linked from in case they need to
be restored.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a56e7c628701e4a0471833443b08ab2bcceb27e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83123
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This almost completely replaces the original symlink target for creating
symbolic links from site-local into the coreboot tree. Changes include:
- A comment about the format of the symlink.txt file
- Verify that there are symlink.txt files before doing anything.
- Note that symbolic links that already exist are being skipped.
- Only use the first line of the symlink.txt file
- Make sure the symbolic link to be created is inside the coreboot dir.
- Output errors to STDERR
- echo -e isn't supported by posix shells, so replace /t with two spaces
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9b0d1b5bc19556bc41ca98519390e69ea104bd1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document
559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3.
There are countries where Wi-Fi 7 should be disabled by default. This
adds capability for OEM to enable or disable by updating the board
specific Specific Absorption Rate (SAR) binary.
BUG=b:348345300
BRANCH=firmware-rex-15709.B
TEST=SSDT dump shows that the _DSM method returns the value supplied
by the SAR binary for function 12
Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Since the 'maxlen' parameter's type is changed to size_t, the type of
the local variable 'i' which this is compared against should also be
changed to size_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83224
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
The return type of strspn and strcspn is supposed to be a size_t and not
a signed integer.
TEST=Now the openSIL code can be built with the coreboot headers without
needing to add '-Wno-builtin-declaration-mismatch' or
'-Wno-incompatible-library-redeclaration' to the cflags. Before the
build would error out with various 'mismatch in return type of built-in
function' errors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83223
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The third parameter of strncpy and strncmp is supposed to be a size_t
and not a signed int.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83222
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Use the existing `azalia_enter_reset()` function instead of explicitly
clearing the bit (and having to explain in a comment what this means).
Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83217
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Now that the device tree code has been made available in libpayload, we
should reintroduce the node and property allocation optimization for
libpayload's memory allocator that was originally dropped when porting
this code from depthcharge to coreboot.
On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree,
this saves roughly ~145ms. The total scratch space used is about ~1350
nodes and ~5200 properties, so we leave a little room to grow with the
constants hardcoded here.
Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
For most of SoCs, DRHD is by default with the size of 4KB. However,
larger sizes are allowed as well. Rename acpi_create_dmar_drhd to
acpi_create_dmar_drhd_4k to support the default case while a later
patch will re-add acpi_create_dmar_drhd with a size parameter.
TEST=intel/archercity CRB
Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Fn key on Lotso emits a scancode of 94 (0x5e).
BUG=b:322721490
TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I999627f0ea9db1d79376150a04920ac877a48447
Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
On board version 1 and later, touchscreen is not stuffed. Hence
configure the relevant GPIOs as not connected, disable the concerned I2C
bus in the devicetree as well as SoC chip config for board version 1.
BUG=b:347333500
TEST=Build Brox BIOS image and boot to OS. Ensure that there are no
peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no
touchscreen devices are exported through ACPI SSDT table. Ensure that
other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure
that the device is able to suspend and resume for 25 cycles.
Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kernel need the default brightness steps. Otherwise following error
messages are observed in the kernel:
[Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS
ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND
ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous
error (AE_NOT_FOUND)
BUG=b:346807006
TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned
error messages are resolved. Ensure that the backlight controls are
functional.
Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Some dongles require more time to be ready,
this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make
sure the tested dongle display works.
Before:
[WARN ] DP not ready after 500ms. Abort.
After:
[INFO ] DP ready after 1211 ms
BUG=b:348309582
TEST=emerge coreboot
verify tested dongles and monitors display works
Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
If a board supports FW_CONFIG or ChromeEC CBI, the options should be
selected by the mainboard. These are not something that need to be a
choice to enable or disable in Kconfig.
The defaults are pointless, so remove them. The symbols default to no.
Correct the descriptions of FW_CONFIG_SOURCE_CBFS and
FW_CONFIG_SOURCE_VPD. They come after CBI and do not override any other
options.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icf170dc2ef790d6f5a897a9c7c2ea64033bf1dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83118
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The generated dsdt.asl and early_init.c files contained 2 consecutive
blank lines, so remove one of them.
Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83186
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Qemu doesn't provide an XSDT, coreboot adds one as separate ACPI
table. Qemu only provides the smaller ACPI 1.0 RSDP, but the XSDT can
only fit into the bigger ACPI 2.0 RSDP. Currently the exsting RSDP is
being reused, without a size check, which works fine on the first boot.
However after reboot the XSDT pointer seems to be valid, even though the
checksum isn't. Since the XSDT then isn't reserved again on reboot, the
memory it's pointing to is reused by other tables, causing the
payload/OS to see an invalid XSDT.
Instead of corrupting the smaller existing RSDP, allocate a new RSDP
structure and properly fill it with both, existing RSDT and XSDT.
In addition return the correct length of allocated ACPI tables to the
calling code. It was ommiting the size of the allocated XSDT and SSDT.
TEST: Run "qemu-system-x86_64 -M q35" and reboot the virtual machine.
With this patch applied XSDT is always valid from the OS
point of view.
Change-Id: Ie4972230c3654714f3dcbaab46a3f70152e75163
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83116
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set PsysPL2 and PsysPL3 in addition to making adjustments
to PL2 and PL4 in order to prevent brownouts when we don't
have a battery or have an empty battery at boot time.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=flash
Able to successfully boot on a SKU1 with 45W, 60W+ adapters
and SKU2 with a 60W or higher type C adapter.
30W is still being worked on.
Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit simply adds support for a Do Not Disturb key. HUTRR94 added
support for a new usage titled "System Do Not Disturb" which toggles a
system-wide Do Not Disturb setting.
BUG=b:342467600
TEST=Build and flash a board that generates a scancode for a Do Not
Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux
kernel with patches[0] that add this new event code using `evtest`.
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb
Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Add support for an Accessibility key. HUTRR116 added support for a new
usage titled "System Accessibility Binding" which toggles a
system-wide bound accessibility UI or command.
BUG=b:333095388
TEST=Build and flash a board that contains an accessibility key. Verify
that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0]
that add this new event code using `evtest`.
```
Testing ... (interrupt to exit)
Event: time 1718924048.882841, -------------- SYN_REPORT ------------
Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1
Event: time 1718924054.062428, -------------- SYN_REPORT ------------
Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0
Event: time 1718924054.195904, -------------- SYN_REPORT ------------
```
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a
Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
This patch creates a new tereid variant, which is a Twin Lake platform.
This variant uses Nereid board mounted with the Twin Lake SOC and
hence the plan is to reuse the existing nereid variant code.
BUG=b:346442939
TEST=Generate the Tereid firmware builds and verify with boot check.
Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SATA controller is configured to AHCI mode by default. Drop the
setting from the devicetree.
Change-Id: I027b393300e2cbad827e176afddc197007314f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
