Commit Graph

57196 Commits

Author SHA1 Message Date
Amanda Huang
2ecc785a69 mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Orisa
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Orisa variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.

BUG=b:345112878
TEST=Able to enter S0ix on Orisa eMMC sku after disabling UFS
during boot path.

Change-Id: I969b0c0c785ed4c408f6fc6de71e7d0c1a1ea27c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-27 06:53:02 +00:00
Yu-Ping Wu
fa9fbb40f9 arch/arm64/armv8/mmu: Add missing header arch/barrier.h
Also take the chance to sort the headers.

BUG=none
TEST=none
BRANCH=none

Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83651
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-27 05:13:28 +00:00
Varun Upadhyay
015c842620 vc/intel/fsp/twinlake: Update FSP headers to v5222.01
- Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h
- Update UPD Offset in FspsUpd.h

BUG=b:354612775
TEST=Able to build and boot google/Tivviks

Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27 03:41:54 +00:00
Subrata Banik
04762ca929 mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Trulo variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.

Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).

BUG=b:355384185
TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS
during boot path.

Able to grep below debug prints while booting the eMMC sku.

[INFO ]  FW_CONFIG value from CBI is 0x20000000
[INFO ]  Disabling UFS controllers
...
[INFO ]  fw_config match found: STORAGE=STORAGE_EMMC

Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-07-27 03:41:14 +00:00
Subrata Banik
66b9c989ae soc/intel/meteorlake: Remove unnecessary #if ENV_RAMSTAGE
TEST=Able to build google/rex.

Change-Id: I0de87a2ff5ecb37f00ec745ad930e83f6356a3fe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83637
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26 23:03:48 +00:00
Tim Crawford
5f445f21e0 ec/system76/ec: Remove RPM calculation
System76 EC since system76/ec@80cfa91b9f ("acpi: Report RPM values
instead of raw tachometer values") performs the RPM calculation itself
and stores it  in EC RAM where previously the raw tachometer values were
saved. The SBIOS is no longer required to make the conversion.

Change-Id: I82a4e25a8ce0f274b2d98e7ff2b12595acf6c3c5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-07-26 23:03:33 +00:00
Sean Rhodes
c6b5b075ec mb/starlabs/starbook/rpl: Don't set tcss_aux_ori
Not setting tcss_aux_ori in devicetree is the same as
setting it to zero so remove it.

Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-07-26 13:49:10 +00:00
Maximilian Brune
07f0131116 arch/riscv: Remove opensbi submodule includes
Currently we include a header file from the opensbi submodule.
That causes some issues, since we merge outside code with our own.
Most recently there have been made attempts to make the coreboot
codebase C23 ready. The code that we include from opensbi however causes
the build to fail, since it is not C23 ready.

This patch effectivily detaches the coreboot codebase from the opensbi
codebase and just copies the structure and definitions that we need from
opensbi into coreboot.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9d8f85ee805bbbf2627ef419685440b37c15f906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83641
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26 13:05:41 +00:00
Maximilian Brune
7dae497495 commonlib/device_tree.c: Add read reg property helper
Add a helper function to read the reg property from an unflattened
device tree.
It also factors out the common code into a new function called
`read_reg_prop`.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7846eb8af390d709b0757262025cb819e9988699
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-26 11:06:29 +00:00
Li, Jincheng
2c9a12b588 mb/intel/beechnutcity_crb: Update SMBIOS info for type 0,1,2,3
Update wake-up type, mainboard feature flags and enclosure type.
All other info are used from src/lib/smbios_defaults.c

Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-26 11:05:10 +00:00
Li, Jincheng
61d61af6ea mb/intel/avenuecity_crb: Update SMBIOS info for type 0,1,2,3
Update wake-up type, mainboard feature flags and enclosure type.
All other info are used from src/lib/smbios_defaults.c

Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83328
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26 11:05:02 +00:00
Jincheng Li
e44fe6a39e soc/intel/xeon_sp/gnr: Add dimm_slot configuration
Add sample DIMM slot configuration table for avenuecity CRB
and beechnutcity CRB. This table will be used to fill SMBIOS
type 17 table.

TEST=Boot on intel/avenuecity CRB
It will help to update Locator, Bank Locator and Asset Tag
with the value described in dimm_slot_config_table

Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26 11:04:54 +00:00
Rishika Raj
871f93549d soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.

BUG=None
TEST=None

Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-26 10:58:58 +00:00
Yu-Ping Wu
8e48f94b39 soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START comment
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-26 07:23:34 +00:00
Felix Singer
9c78a0e422 mb/starlabs/starbook/cml: Drop superfluous devices from devicetree
In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.

Change-Id: I92765b404508901c7e84fad0bca30489cf69abac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-26 05:44:36 +00:00
Martin Roth
28c669e216 3rdparty: Remove chromeec submodule
The chromeec submodule is the largest submodule being pulled into the
coreboot tree, at over 400MB. The main branch also contains the majority
of these commits, so restricting it to a single branch still fetches
over 350MB.

Because there is only a single mainboard directory that enables the
build of the chromeec codebase by default, most people are fetching this
repo for no reason.

Based on this, we're going to change the way that the chromeec submodule
is used, fetching it the way we currently fetch external payloads. This
gives us 2 large advantages:
1) Only builds that actually need the chromeec repo will pull it down.
2) Each board that wants to build the chromeec codebase can use a
different commit, unlike submodules which all use the same "current"
commit.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I357c4c9b506dd3817a308232446144ae889bc220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-26 04:36:52 +00:00
Matt DeVillier
6d6ec575b7 ec/google/chromeec: Drop 'choice' selections for EC and PD firmware
Since the EC and PD firmware sources are now limited to two options -
'none' and 'external' - drop the choice selection and make the
EC and PD external options independent.

TEST=build google/lulu with external EC binary using existing defconfig

Change-Id: Ie37ff3a188b414fd099fbb344858bca4df419086
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83639
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26 02:58:41 +00:00
Matt DeVillier
a391ae18a8 ec/google/chromeec: Drop ability to build Chrome-EC, PD components
In preparation for dropping the Chrome-EC submodule, remove the ability
for Chrome-EC and PD components to be built as part of coreboot.
These components have not been used or buildable for many years.

Change-Id: Ibf6bd43e755cf5b4d2aa8a42f38dc52e7023e9b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83638
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-26 02:58:36 +00:00
Felix Held
331cb328c2 soc/amd/common/psp_gen2: use MMIO access again
Now that we have a get_psp_mmio_base function that will work on all SoCs
that use the psp_gen2 code, we can move back to accessing the PSP
registers via their MMIO mapping. This sort-of reverts
commit 198cc26e49 ("soc/amd/common/block/psp/psp_gen2: use SMN access
to PSP").

When doing SMN accesses from the SMI handler after the OS has taken over
ownership of the platform, there's the possibility to cause trouble by
clobbering the SMN access index register from SMM. So that should be
either avoided completely or the SMI code needs to save and restore the
original contents of the SMN index register.

The PSP MMIO base will be set up by the FSP before the resource
allocation in coreboot and be treated like a fixed resource by the
allocator. The first SMI where corresponding handler calls
'get_psp_mmio_base' happens when ramstage triggers the APM_CNT_SMMINFO
SMI right after mpinit which happens after the resource allocation. So
the PSP MMIO base address is expected to be configured and so the
'get_psp_mmio_base' function will cache the base address and won't need
to do any SMN access in subsequent calls that might happen after the OS
has take over control.

This isn't currently an issue, since the only PSP mailbox command from
the SMI handler after coreboot is done and the OS has taken over will
be during the S3/S4/S5 entry, and this will be triggered by the OS as
the last step after it is done with all its preparations for suspend/
shutdown.  There will however be future patches that add SMI-handlers
which can send PSP mailbox commands during OS runtime, and so we have
to make sure we don't clobber the SMN index register.

TEST=PSP mailbox commands are still sent correctly on Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83448
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25 22:56:37 +00:00
Felix Held
645203a280 soc/amd/common/psp_gen2: return status from soc_read_c2p38
This sort-of reverts commit 00ec1b9fc7 ("soc/amd/common/block/psp/
psp_gen2: simplify soc_read_c2p38") and is done as a preparation to
switch back to using the MMIO access to the PSP mailbox registers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25 22:55:50 +00:00
Felix Held
c7f022ae95 soc/amd/common/block/psp_gen2: add get_psp_mmio_base
Add get_psp_mmio_base which reads the PSP MMIO base address from the
hardware registers. Since this function will not only be called in
ramstage, but also in SMM, we can't just look for the specific domain
resource consumer like it is done for the IOAPICs in the northbridge,
but have to get this base address from the registers. In order to limit
the performance impact of this, the base address gets cached in a static
variable if an enabled PSP MMIO base register is found. We expect that
this register is locked when it was configured and enabled; if we run
into the unexpected case that the PSP MMIO register is enabled, but not
locked, set the lock bit of the corresponding base address register to
be sure that it won't change until the next reset and that the hardware
value can't be different than the cached value.

This is a preparation to move back to using MMIO access to the PSP
registers and will also enable cases that require the use of the MMIO
mapping of the PSP registers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25 22:55:38 +00:00
Felix Held
ebf90e3a88 soc/amd: add SoC-specific root_complex.c to SMM
The PSP code introduced in a following patch needs both SoC-specific
functions get_iohc_info and get_iohc_non_pci_mmio_regs to also be
available in SMM, so add those compilation units to the corresponding
target.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e32084b45f07131c80b642bc73d865fc57688a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-07-25 22:55:27 +00:00
Felix Held
e9e71132a3 soc/amd/*/root_complex: introduce and use domain_iohc_info struct
Instead of implementing the functions get_iohc_misc_smn_base and
get_iohc_fabric_id in the SoC code, move those functions to the common
AMD code, and implement get_iohc_info in the SoC code that returns a
pointer to and the size of a SoC-specific array of domain_iohc_info
structs that contains the info needed by the common code instead. This
allows to iterate over the domain_iohc_info structs which will be used
in a later patch to find the PSP MMIO base address in both ramstage and
smm.

TEST=Mandolin still boots and all non-PCI MIO resources are still
reported to the resource allocator

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83443
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25 22:55:15 +00:00
Felix Held
9af1d3f857 acpi,soc: use is_domain0 function
No need to open-code this when we have a function for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83643
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-25 22:54:43 +00:00
Felix Held
a17d22e51a device: move is_domain0 and is_dev_on_domain0 to common code
Move is_domain0 and is_dev_on_domain0 from the Intel Xeon SP code to the
common coreboot code so that it can be used elsewhere in coreboot too,
and while moving also implement it as functions instead of macros which
is more in line with the rest of helper functions in that new file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83642
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25 22:54:21 +00:00
Felix Held
b133b7ae23 mb/protectli/vault_[adl_p,bsw]/Kconfig: drop unneeded MAINBOARD_VENDOR
MAINBOARD_VENDOR is already provided by the Kconfig file on the vendor
level, so there's no need to redefine it to the same value at the
mainboard level.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icfcbcec005fadb8eaf1b8f90e1d71b3c6ee32088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83640
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-25 22:08:44 +00:00
Yu-Ping Wu
b6e1007e27 soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.

Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.

To fix the problem, define vbnv_platform_init_cmos() to call
cmos_init(0), which will configure the Register A and therefore allow
saving VBNV to CMOS in verstage.

[1] 48751_16h_bkdg.pdf

BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim

Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83495
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25 20:53:32 +00:00
David Wu
5085fe6478 mb/google/nissa/var/riven: Add Fn key scancode
The Fn key on riven emits a scancode of 94 (0x5e).

BUG=b:345231373
TEST=Flash riven, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.

Change-Id: Iddedd08fc50e8e8e369ce3d73edf0f3077867e87
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-25 14:21:56 +00:00
Sean Rhodes
a3863ca44a ec/starlabs/merlin: Improve accuracy of RSOC
Multiply before dividing to improve accuracy of the result.

Change-Id: I974cad3af4e1f86ae58e90c68db463fc436223af
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83619
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25 14:12:34 +00:00
Subrata Banik
24e550fd61 mb/google/brya/var/trulo: Configure GPIO pins for ramstage
This patch configures GPIO pins as required for booting the Trulo
device from ramstage.

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-25 04:22:16 +00:00
Yu-Ping Wu
adac4af176 soc/amd/psp_verstage: Add -Oz flag for clang
When we tried to add CMOS support to PSP verstage (CB:83495), the clang
builds failed on boards with cezanne SoC (such as Guybrush), due to
over-sized verstage. On the other hand, there is no such problem for gcc
builds on the same boards.

Building PSP verstage by clang generates much larger verstage size (81K)
compared with using gcc (67K). To unblock adding features to verstage,
temporarily enable -Oz for clang builds.

Change-Id: I033458556986ade88fb8e68499b632deae4dd419
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-25 03:29:52 +00:00
Felix Singer
8cb97d804e mb/google/volteer/{delbin,drobit}: Use alias name for DPTF PCI device
Change-Id: If514ee7c1174d13b8ca8eb7fd20359e0730a8893
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83525
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24 21:32:35 +00:00
Felix Singer
26e5194e0d mb/protectli/vault_cml: Drop superfluous devices from devicetree
In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.

Change-Id: Ie485684747efccb8fb0ab87f10694c52a98f3c88
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83455
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24 21:12:51 +00:00
Yidi Lin
552e35b76b Update arm-trusted-firmware submodule to upstream master
Updating from commit id 48f1bc9f5:
2024-05-02 10:13:54 +0200 - (Merge "feat(zynqmp): remove unused pm_get_proc_by_node()" into integration)

to commit id c5b8de86c:
2024-07-22 18:07:11 +0200 - (Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration)

This brings in 447 new commits.

Change-Id: I0a24e2b2b83d18d5ce8f3b1af710b5acde996ad0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-07-24 13:10:46 +00:00
Yu-Ping Wu
928f49ca7a Update vboot submodule to upstream main
Updating from commit id b6f44e62:
2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10)

to commit id 4b12d392:
2024-07-17 01:47:56 +0000 - (scripts: Add a script to convert a vbprivk to a PEM)

This brings in 9 new commits:
4b12d392 scripts: Add a script to convert a vbprivk to a PEM
033d7bfa futility: updater: Increase try count from 10 to 11
f63e088e treewide: Ensure a space after if/for/while keywords
17a45712 2auxfw_sync: Clear display request before EC reset
e529f947 2ec_sync: Reactivate VB2_CONTEXT_EC_SYNC_SLOW
ca2d42d1 Android: Explicitly disable v1/v2 signing when using apksigner
fc7a7a5d futility: flash: Print ro_start and ro_len for debug
86542905 Migrate to new Android.bp build system
aa35a020 host/lib/host_p11_stub: Add missing includes

Change-Id: Ida8a27dcb0acf83022aff0118827e3d310fae1a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83612
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24 13:10:31 +00:00
Nicholas Chin
cf42f5d80f util/autoport/*.md: List Haswell as supported
As of commit 3f0bb2fb07 (autoport: Add support for Haswell-Lynx Point
platform), autoport supports Haswell in addition to Sandy Bridge and Ivy
Bridge.

Change-Id: Iccc10441389580ff8e89c3718484d25d20970f68
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24 13:10:12 +00:00
Weimin Wu
7ba782814d mb/google/dedede/var/awasuki: Initialise overridetree
Initialise overridetree based on the schematics revision 20240715.

BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki

Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-24 13:09:48 +00:00
Jincheng Li
c19e32e69d soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos

TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20

Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-24 09:18:41 +00:00
Arthur Heymans
dc8123a775 arch/x86/Makefile.mk: Remove obsolete romcc reference
No assembly.inc file is being generated by romcc anymore.

The -I. was only used in a single place that can use the common -Isrc
instead.

Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83563
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24 00:28:59 +00:00
Arthur Heymans
9b99eb5cf8 arch/x86: Build all stages using the same function
There is no difference in how early and later stages are linked so
rename the same function.

Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-07-24 00:28:31 +00:00
Arthur Heymans
47254261ba arch/x86: Link ramstage in one step
We only use the bfd linker currently but partial linking is not
supported by other linkers and is also a problem for LTO.

Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71910
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24 00:26:23 +00:00
Matt DeVillier
42b695510a mb/google/dedede/var/galtic: Group fw_config fields together
No need to have separate sections, and will be cleaner when adding
another section in a subsequent patch.

Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-23 18:36:09 +00:00
Michał Żygowski
256e98f604 mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
It is a new incoming Protectli product based on Alder Lake-P SoC.
More details and documentation will be added later.

TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670.

Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23 14:13:25 +00:00
Jarried Lin
3200976c1e mb/google/rauru: Add MediaTek MT8196 reference board
Add mainboard folder and drivers for new reference board 'Rauru'.

TEST=saw the coreboot uart log to bootblock
BUG=b:317009620

Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23 13:46:12 +00:00
Jarried Lin
8cb9641eca soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
Add new folder and basic drivers for Mediatek SoC 'MT8196'.
Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for
MT8196 SPEC detail.
This patch also enables UART and ARM arch timer.

TEST=saw the coreboot uart log to bootblock
BUG=b:317009620

Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-07-23 13:45:33 +00:00
Seunghwan Kim
24eee9bcb0 mb/google/brya/var/xol: Limit power limits for low/no battery case
Xol has a shutdown issue on our reliability test environment:
- High temperature
- No battery condition

It needs to have margin for the PL2 and PL4 values from the adapter
power, this will limit the PL2/PL4 values up to 30W/40W for xol's
45W power adapter. The new values are confirmed by our power team.

BUG=b:353395811
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
     Intel doc #614179 introduces how to check current PL values.

[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
  constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W)
  constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
  constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)

[When connected 60W adapter without battery]
Before:
  constraint_0_power_limit_uw:18000000
  constraint_1_power_limit_uw:55000000
  constraint_2_power_limit_uw:60000000
After:
  constraint_0_power_limit_uw:18000000
  constraint_1_power_limit_uw:30000000
  constraint_2_power_limit_uw:40000000

[When connected 45W adapter without battery]
Before:
  constraint_0_power_limit_uw:18000000
  constraint_1_power_limit_uw:45000000
  constraint_2_power_limit_uw:45000000
After:
  constraint_0_power_limit_uw:18000000
  constraint_1_power_limit_uw:30000000
  constraint_2_power_limit_uw:40000000

Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-23 13:45:10 +00:00
Nico Huber
0c1897e4fd xcompile: Drop CC_RT_EXTRA_GCC for PPC64
It looks like some unused artifact:  The PPC64 Makefile.mk doesn't
pick it up. Also, the only other architecture using this (x86) has
linker flags there, not compiler flags.

Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-07-23 09:36:32 +00:00
Yu-Ping Wu
d8bed2d001 drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.

To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157

BUG=b:346716300
TEST=none
BRANCH=skyrim

Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-23 07:54:39 +00:00
Jincheng Li
9b2d995bdb lib/smbios: Create SMBIOS type 4 entry
One smbios type 4 should be provided for each CPU instance.
Create SMBIOS type 4 entry according to socket number, with a
default value of 1.

TEST=Boot on intel/archercity CRB
No changes in boot log and 'dmidecode' result under centos

Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83331
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22 22:30:47 +00:00
Seunghwan Kim
aa6865291a mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
If user continues to use the touchpad for over 3 minutes on Xol, the
pointer movement is stuttering.

Touchpad I2C transaction should appear during the interrupt signal level
is low, but we could see some more I2C transaction after the interrupt
signal(GPP_F14) went to high.

We found experimentally that changing the interrupt type to GPIO_INT
from APIC_IRQ improved this issue. We are still investigating, would
like to apply this change first for Xol's dogfooding.

BUG=b:350609957
BRANCH=brya
TEST=built and verified there's no stuttering issue on touchpad movement

Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-22 20:02:43 +00:00