Commit Graph

57442 Commits

Author SHA1 Message Date
David Wu
e1e16e0cb9 mb/google/nissa/var/riven: Add elan touchscreen support
This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:348125053 b:348126380
TEST=emerge-nissa coreboot
     boot with elan TS, make sure elan TS is functional.

Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13 13:25:33 +00:00
Keith Hui
f7ed007298 mb/asus/p8z77-m: Light DRAM_LED during early boot
Turn on DRAM_LED on the mainboard in early bootblock, and turn it off
in ramstage. Primarily an indication if boot fails during raminit,
modeled after vendor firmware.

This LED is controlled by GPIO07 on the super I/O.

Boot tested on hardware.

Change-Id: I549b51375d1ef056d5fc01871bfe62d60b8a01cb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-13 13:25:23 +00:00
Jayvik Desai
0de60b2840 drivers/intel/fsp2: Add config for FSP uGOP eSOL
This patch introduces a new configuration option,
FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP
support using FSP-M for the early sign-of-life feature in SOC.

BUG=NA
TEST=Able to build google/rex and checked the config in output.

Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-12 13:13:36 +00:00
Elyes Haouas
259052f9db tree: Use boolean for pch_hda_sdi_enable[]
Change-Id: I27568d1205216f697b48ffb09ce5208505718978
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83863
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:36:58 +00:00
Gang Chen
1ea2a1c182 soc/intel/xeon_sp/gnr: Remove VPD from GNR Kconfig
Remove the unused config VPD from GNR Kconfig.

Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82975
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-08-11 17:36:26 +00:00
Saurabh Mishra
de56d38b07 soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:

1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
   and google/fatcat mainbaord.
5. Ref: Processor EDS documents
	vol0.51 #815002

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
     PTL using google/fatcat mainboard.

Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:35:27 +00:00
Morris Hsu
5bc6bd4c41 mb/google/brox/jubilant: update overridetree for dptf settings
Update dptf settings for EVT.

BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge

Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:34:31 +00:00
Morris Hsu
ffc1cbb8fc mb/google/brox/jubilant: update overridetree
Update touchpad settings.

BUG=b:342867386
TEST=ensure touchpad is working.

Change-Id: Ibf62470b7fd921065201894a63d7e2a83dad53ce
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-11 17:34:09 +00:00
zengqinghong
917f24018a mb/google/nissa/var/teliks: Configure TPM IRQ for teliks
Add TPM TIS ACPI interrupt configuration, set teliks's
`TPM_TIS_ACPI_INTERRUPT` to 13.

BUG=b:352263941
TEST=emerge-nissa coreboot

Change-Id: Iaed51e0bb8abac0ed0b35bfcf12e95fd34f92242
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83832
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-11 17:33:46 +00:00
zengqinghong
9d968c93da mb/google/nissa/var/teliks: Add DP AUX BIAS connect
Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.

BUG=b:352263941
TEST=DP function of MB and DB workable

Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:33:33 +00:00
Yuchi Chen
933031b524 soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include
soc/gpmr.h if necessary.

Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83317
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:32:29 +00:00
Maximilian Brune
eb28f3da7d arch/riscv: Add PMP print function
For easier debugging it is useful to have a function that prints the PMP
regions.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6ab1531c65b14690e37aecf57ff441bf22db1ce5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-08-11 17:10:45 +00:00
Elyes Haouas
96719adda3 azalia: Get rid of "return {-1,0}
Use 'enum cb_err' instead of {-1,0}.

Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-11 17:10:08 +00:00
Nico Huber
af0d4bce65 region: Introduce region_create() functions
We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).

This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.

Also, two cases of strtol() in parse_region() (cbfstool),  where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().

FIT payload support is left out, as it doesn't use the region API
(only the struct).

Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-11 17:07:32 +00:00
Kyösti Mälkki
0e9830884c cpu/x86/lapic: Always have LAPIC enabled
LAPIC has been available since P54C released 1993.

Change-Id: Id564a3007ea7a3d9fb81005a05399a18c4cf7289
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61794
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 17:06:41 +00:00
Dinesh Gehlot
70e62188f4 mb/google/brya/variants: Enable pch_hda_sdi_enable for trulo baseboard
This patch enables pch_hda_sdi_enable for the trulo baseboard and
removes SDI lanes update from its variants.

BUG=b:350931954
TEST=Boot verified on google/craask and google/tivviks

Change-Id: I2e0f43b8fffb5e583089769d2c7446b476ce5d5d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11 02:40:28 +00:00
Subrata Banik
76021a9205 mb/google/rex/var/rex0: Set PCIE WLAN bluetooth companion device
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.

BUG=b:345373187
TEST=Build and test on google/rex0, check BRDS is shown in SSDT.

Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72

Change-Id: I82f6290cb1934e2c0597286702f93e3789e8f345
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2024-08-10 14:09:24 +00:00
Tyler Wang
7c628c4aef mb/google/rex/var/karis: Set PCIE WLAN bluetooth companion device
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.

BUG=b:345373187
TEST=Build and test on karis, check BRDS is shown in SSDT.

Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83791
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2024-08-10 14:09:15 +00:00
Subrata Banik
d55ffdd7eb Revert "mb/google/rex: Set cnvi_wifi bluetooth companion device"
This reverts commit 1f1d8d2bca.

Reason for revert: Intel® Wi-Fi 6E AX211 (CNVi) does not need Bluetooth
Regulator Domain Settings and therefore, the bluetooth companion
device declaration for CNVi is unnecessary.

BUG=b:345373187
TEST=Able to build and boot google/karis.

Change-Id: I296ddb93659af144e1a82a6b8219c9811c5fe545
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83843
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-10 14:09:10 +00:00
Elyes Haouas
efbeb9a394 tree: Remove duplicated <arch/mmio.h>
<device/mmio.h> is supposed to chain-include <arch/mmio.h>. See
`Documentation/contributing/coding_style.md` section `Headers and includes`

Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10 03:35:48 +00:00
Elyes Haouas
d4bbeb8140 tree: Remove unused <smbios.h>
Change-Id: Iab7e9f3d17c87576761333c4b62c40eea5e424a5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10 03:34:42 +00:00
Elyes Haouas
920b2d05b6 device/dram/spd: Add missing <smbios.h>
Use of smbios_memory_type needs <smbios.h>.

Change-Id: Iacab6171c61abd047c09ff7e20313a455bd8414f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-10 03:34:29 +00:00
Yidi Lin
db5dbdf310 soc/mediatek/common: Refactor EINT driver
Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
  `gpio_calc_eint_pos_bit`.
- Implement `gpio_get_eint_reg` to obtain EINT base address.

This change is prepared for the driver change in MT8196.

BUG=b:334723688
TEST=EINT works on Geralt

Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-10 01:10:20 +00:00
Yuchi Chen
b60cfb89e9 soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos
1. print host software ownership, SMI enable and NMI enable registers
after configuring
2. read and print GPIO configuration dword registers after writing
3. use %zu to print size_t values according to CI reporting.

Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-10 01:06:26 +00:00
Felix Held
5eebeaf31c soc/amd/*: pass PSP RPMC NVRAM base and size to amdfwtool
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
and Stoneyridge which don't use/support this.

If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file,
the start and length of it in the flash will be passed to amdfwtool
which then adds the base and length to the corresponding type 0x54 PSP
directory table entry.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83815
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-09 22:22:18 +00:00
PuFF1k
0bdee9ca68 mb/lenovo/t520: Add USB port config into devicetree
Devicetree for lenovo/520 is missing USB ports config, hence they
don't work. This change introduces USB port config.
Tests performed:
- Can select a boot media using a USB keyboard from any port.
- Can boot from each port except usb@1:1.1.
- Measured read speed from a thumb drive on each port 24.5-28.9 MiB/s.

Change-Id: I96dba153a563e0e290b96b837fdca39d7598ef17
Signed-off-by: PuFF1k <exopuf@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-09 21:24:35 +00:00
Harrie Paijmans
fda9741ff9 coreboot-sdk/Dockerfile: Add 'gettext' and 'xfonts-unifont'
Required for building grub2.

BUG=N/A
TEST=Build successfully for 'QEMU x86 i440fx/piix4' with GRUB2 payload.

Change-Id: I97860f33dd3fde2f6db2f005d65b53cd669403e9
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83676
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09 21:08:09 +00:00
Elyes Haouas
4d90a33a31 mb/emulation/qemu-q35: Move QEMU specific macros to "q35.h"
As `qemu-q35/memmap.c` includes `qemu-q35/q35.h`, move macros into q35.h
file.

Change-Id: I0bf13def8bc4510053f6bb44e043bbcb0b958b01
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-09 20:45:23 +00:00
Maximilian Brune
a7c05f5a66 MAINTAINERS: Add Maximilian Brune to RISC-V
I also add myself as the Maintainer for the SiFive boards, since I
happen to have both of them and I also ported the HiFive Unmatched to
coreboot.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic0b8e1053c9f5007e29e997c1ff21ff4a496aea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83697
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-09 19:12:05 +00:00
Saurabh Mishra
de8b77c384 vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
Details:
- Skeleton files to compile google/fatcat mainboard.

BUG=b:348678529
TEST=Build verified on with using PTL SOC and google/fatcat mainboard.

Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83732
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-09 18:00:35 +00:00
Bora Guvendik
d4253a3d56 device/pci_ids: Add new Intel PTL device IDs for Tracehub
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H.

Additionally, updates the tracehub driver's `pci_device_ids` list to
include these new IDs.

Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2

BUG=b:347669091
TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is
reserved.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09 17:59:44 +00:00
Morris Hsu
b0be97b68b mb/google/brox/jubilant: Add Fn key scancode
The Fn key on jubilant emits a scancode of 94 (0x5e).

BUG=b:324079605
TEST=Flash jubilant, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.

Change-Id: I963b0aa85598097fea69ec34d1e79ec0bbec3db3
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83821
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09 17:58:08 +00:00
Michał Żygowski
bfbc5cfcb2 superio/ite: Remove custom ITE GPIO drivers and code
Since a generic ITE GPIO driver is available and in use, the existence
of chips-specific drivers no longer make sense. Remove the dead code
in favor of generic GPIO driver.

Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09 17:01:50 +00:00
Michał Żygowski
001f33cc03 superio/ite,mb: Switch to new ITE GPIO driver
Refactor mainboards' code to use the new GPIO driver.

TEST=Put Google Jecht to S3 sleep and check if the LED blinks.

Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-09 17:01:45 +00:00
Ren Kuo
ec049cb29d mb/google/brox/var/jubilant: Add SAR sensor SX9324
Add SAR Sensor SX9324 for WWAN:
- Apply DRIVERS_I2C_SX9324
- Config GPP_H19 for IRQ
- Add SX9324 registers settings based on tuning value from SEMTECH.
  Refer to datasheet:
  https://chromeos.google.com/partner/dlm/avl/component/3624/

BUG=b:345327104
TEST=Build and verify on jubilant

Change-Id: I629117f20ca513dc0c8eaa91744ad33e162ba4bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83779
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09 16:30:30 +00:00
Kun Liu
548cbc15ca mb/google/brox/var/lotso: Enable wifi sar
wifi.SetTXPower test fail, so enable wifi sar.

BUG=b:351698478
TEST=emerge-brox coreboot

Change-Id: Ibf5425e72eddc45e376ef4e2d077180dab502200
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09 15:52:13 +00:00
Kulkarni, Srinivas
315dba7abb vc/intel/raptorlake: Update header files from 4435_00 to 5045_00
Update header files for FSP for Raptor Lake refresh platform to
version 5045_00, previous version being 4435_00.

FSPM:
1. Add IgdGsm2Size UPD
2. Comment added for Offset 0x0AB6

FSPS:
1. Add CepEnable UPD
2. Offset size updated for UPD ReservedCpuPostMemProduction
2. Comment added for Offset 0x104C

MemInfoHob:
1. Structure updated

BUG=b:355384183
Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=815173

Cq-Depend: chrome-internal:7554984
Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-09 15:51:27 +00:00
David Wu
9ef75eceef mb/google/nissa/var/riven: Add G2 touchscreen support
This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40.

It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset

BUG=b:350844195
TEST=emerge-nissa coreboot
     boot with G2 TS, make sure G2 TS is functional.

Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09 14:34:14 +00:00
Amanda Huang
913942b799 mb/google/trulo: Enable EC MKBP device
MKBP device is required for passing events from input sources to AP.
Input sources include buttons (power, volume); switches (lid, tablet
mode) and sysrq.

BUG=b:357521411
TEST=Build coreboot and switch tablet mode on orisa.

Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83819
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-09 14:34:05 +00:00
Subrata Banik
f6efa4a345 soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.

* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
  used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
  as before.

Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.

BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:

1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""

Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.

Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-09 09:28:12 +00:00
Subrata Banik
ab1d04a0c4 mb/google/fatcat: Add support for soldered-down memory
This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.

* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
    * `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
    * `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.

BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.

Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-08-09 09:24:30 +00:00
Subrata Banik
c84ff28ac5 mb/google/fatcat: Generate LP5 RAM ID for H58G56BK7BX068
Add the support LP5 RAM parts for fatcat:
DRAM Part Name                 ID to assign
H58G56BK7BX068                 0 (0000)

BUG=b:347669091
TEST=emerge-fatcat coreboot

Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2024-08-09 09:24:25 +00:00
Subrata Banik
d0d41f28d3 util/spd_tools: Add Intel Panther Lake (PTL) platform
This patch add support for PTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for fatcat variants.

BUG=b:347669091
TEST=Able to generate SPD for LP5 DRAM part.

Change-Id: I55c3f49439fb1ad961c6866f03594431e54279b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83822
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2024-08-09 09:24:18 +00:00
Subrata Banik
c57564d38a mb/google/brya: Enable storing ISH FW version for trulo
This change enables storing the ISH firmware version on the Trulo
baseboard by selecting the `SOC_INTEL_STORE_ISH_FW_VERSION` config
option.

BUG=b:354607924
TEST=Able to dump ISH version on trulo.
> cbmem -c | grep ISH
[DEBUG]  ISH version: 5.4.2.7780

Change-Id: I69a7fa19c53f435ef1f6306b259f703c7b196137
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83820
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-09 09:23:44 +00:00
Jamie Ryu
8d19e0faa1 soc/intel/cmn/pmc: Add API to dump silicon QDF information
This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC
PMC IPC Command to read and print Intel SoC QDF information using PMC
interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is
supported from Panther Lake SoC.

QDF is a four digit code that can be used to identify enabled features
and capabilities. This information will be useful to debug issues
found during the development phase and in the field as well.

Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83784
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09 05:33:57 +00:00
Nico Huber
6b8c40a95a Makefile: Move `--no-warn-rwx-segments' into xcompile
The parameter is not available for binutils older than 2.39. So move it
to xcompile to provide backwards compatibility for a bit.

Change-Id: I02982769ae2c356f037a747e85d155368bfcb730
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-08 20:16:25 +00:00
Sergii Dmytruk
490e7c3f92 payloads/edk2: set VARIABLE_SUPPORT=SMMSTORE on CONFIG_SMMSTORE_V2
Official EDK2 repository has VARIABLE_SUPPORT defaulting to EMU in
UefiPayloadPkg, switch it to SMMSTORE if coreboot is built with
SMMSTOREv2.

This removes custom default of EDK2_CUSTOM_BUILD_PARAMS for
EDK2_REPO_MRCHROMEBOX which is unnecessary now.

Change-Id: Ic59f89c0f708f9b144bd35cd18870d0e1c65677d
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83737
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-08 17:50:25 +00:00
Felix Held
ab7410a4d0 soc/amd/*: pass PSP NVRAM base and size to amdfwtool
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
which doesn't use/support this. This was previously only implemented for
Picasso, but not for the SoCs that support this, so add the support to
those other SoCs as well.

If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the
start and length of it in the flash will be passed to amdfwtool which
then adds the base and length to the corresponding type 0x04 PSP
directory table entry.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83814
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-08 17:42:05 +00:00
Felix Held
bcc9ad50f9 soc/amd/picasso/Makefile: move PSP_NVRAM_[BASE,SIZE]
Move PSP_NVRAM_BASE and PSP_NVRAM_SIZE from the BIOS directory table
items to the PSP Directory Table items, since the corresponding region
will be referenced by the PSP directory table and not the BIOS directory
table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iff7568ea05c701ecd346cc7590cf93b091ff31a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83813
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-08 17:41:18 +00:00
Felix Held
f9af266189 util/amdfwtool: add support to specify RPMC NVRAM region
Add support to specify the base and size of the replay-protected
monotonic counter (RPMC) non-volatile storage area in the SPI flash. A
later patch will use this to tell amdfwtool about the location and size
of the corresponding FMAP section.

This code is ported from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idafa7d9bf64125bcabd9b47e77147bcffee739e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83812
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-08 17:41:09 +00:00