Commit Graph

57442 Commits

Author SHA1 Message Date
Mate Kukri
ac9ffb9432 mb/dell/optiplex_9020: Fix UB in package power calculation
Fix potential undefined behaviour in the `get_pkg_power()` function:
- If `rapl_power_unit == 0`, `pkg_power_info / rapl_power_unit` is
  invalid
- If `rapl_power_unit > 7`, the result of the shift doesn't fit into a
  `uint8_t`

Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I48ef59c4fbeb0a55675ac24da31e6e0b194cb58d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83736
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-03 14:00:26 +00:00
Subrata Banik
b256e6303c mb/google/rex: Skip UART0 config in FSP
UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.

BUG=none
TEST=Able to build and boot google/rex0. Able to see all debug prints
over CPU uart.

Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-03 07:46:10 +00:00
Yu-Ping Wu
6886a62132 arch/arm64/armv8/mmu: Improve log format
Currently we use "%p" to print the address, which results in different
string lengths, depending on the value of the address. To improve
readability of the printed addresses in the log, change the format to
"0x%013lx", so that the length of the printed addresses will be
consistent.

In addition, print the level of the translation table when setting up a
new table.

Example log:

 Backing address range [0x0000000000000:0x1000000000000) with new L0 ...
 Mapping address range [0x0000000000000:0x0000200000000) as ...
 Backing address range [0x0000000000000:0x0008000000000) with new L1 ...
 Mapping address range [0x0000000100000:0x0000000130000) as ...
 Backing address range [0x0000000000000:0x0000040000000) with new L2
 Backing address range [0x0000000000000:0x0000000200000) with new L3
 Mapping address range [0x0000000107000:0x0000000108000) as ...
 Mapping address range [0x0000000200000:0x0000000300000) as ...
 Backing address range [0x0000000000000:0x0000000200000) with new L3 ...

BUG=none
TEST=emerge-geralt coreboot
BRANCH=none

Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-03 02:13:30 +00:00
Arthur Heymans
7d57bc8eb3 soc/ti/am335x: Remove superfluous formats
These formats are already included in memlayout.ld.

Change-Id: I89d226440308ce3fbe00382698dcd8c88863e694
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02 14:45:13 +00:00
Arthur Heymans
0edab62a28 soc/ti/am335x: Use Linker instead of compiler to link
Clang does not work that well as a linker for the header as it will
default to other linkers which do not work well here. Instead just use
the linker directly.

Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02 14:45:03 +00:00
Dinesh Gehlot
5a70f8a092 soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flag
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is
enabled and the system is currently booting from the RO section.
Additionally, it integrates forced CSE sync into eSOL decision-making.

BUG=b:353053317
TEST=Verified forced CSE sync on rex0 with GBB 0x200000

Cq-Depend: chromium:5718196
Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-02 14:44:10 +00:00
Dinesh Gehlot
896c76c5c1 security/vboot: Include new gbb flag to enforce CSE sync
This patch adds a GBB flag to coreboot, which, when enabled, enforces
CSE sync even if the current CSE version matches the version in CBFS.
The CSME sync GBB and flag are designed to enhance autotest
functionalities and are not intended or recommended for use in
developing any other features.

BUG=b:353053317
TEST=futility gbb --help

Cq-Depend: chromium:5718196
Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83685
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-02 14:43:04 +00:00
Dinesh Gehlot
2534539373 Update vboot submodule to upstream main
Updating from commit id 4b12d392e5b1:
   scripts: Add a script to convert a vbprivk to a PEM
to commit id f1f70f46dc54:
   2lib: Add gbb flag to enforce CSE sync

-Subproject commit 4b12d392e5b12de29c582df4e717b1228e9f1594
+Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2

Change-Id: I2c5b603ce5ea49e6c1aec293960184d84eedd1e7
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-02 14:36:57 +00:00
Sean Rhodes
45d2c3d543 i2c/drivers/generic: Return ROTM in a package
The ROTM method should return a package:

```
  Name (RBUF, Package (0x03)
  {
    "0 1 0",
    "1 0 0",
    "0 0 1"
  })
  Return (RBUF)
```

Adjust the acpigen to do this.

Change-Id: Id493f6955c1d0dc3449402262a8575091a828226
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-02 14:36:31 +00:00
Arthur Heymans
8c509f3645 soc/ti/am335x: Change and optimize memlayout
Clang builds (bootblock: 20800 bytes) are slightly larger than GCC
builds (bootblock: 18688 bytes) so increase the size of both bootblock
and romstage.

The technical reference manual mentions no upper limit to the size of
the bootblock in the TI header so increasing the bootblock size is
allowed.

To be able to link the clang bootblock increase it from 20K to 22K.

Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02 14:34:50 +00:00
Amanda Huang
cb7dad7bc8 mb/google/brya/var/trulo: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.

BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.

Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-02 05:44:50 +00:00
Wu Garen
475c75d34a mb/google/brox/var/greenbayupoc: update ALC236 verb table
The previous uploaded verb table is not fully applied due to
configuration error. Uploaded the verb table provided by Realtek which
can be found in b:336967284.

BUG=b:326412504, b:336967284
TEST=deploy and check volume

Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Terry Cheong <htcheong@chromium.org>
2024-08-02 01:20:08 +00:00
Terry Cheong
3396c4027d mb/google/brox/var/brox: Enable Class-D calibration
DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV.
Add a section in the verb table to enable class-D calibration based
on the updated verb table provided by Realtek in b:342506575 comment#6.

This improves the offset to be less than 1mV.

BUG=b:342506575
BRANCH=main
TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \
     playing -100dB sine waves.

Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-02 01:19:36 +00:00
Ren Kuo
ef4d562d2f mb/google/brox: Create jubilant variant
Create the jubilant variant of the brox reference board by copying
the template files to a new directory named for the variant.

BUG=b:348543712
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUBILANT.

Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-01 20:38:52 +00:00
Felix Held
7e75d1ad26 soc/amd/common/smi_util: add PSP SMI helper functions
The PSP can send SMIs to the x86 side of the system. Add helper
functions to configure and to reset the PSP SMI generation. Since
Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP
define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific
smi.h to bring it in line with the newer SoCs.

This patch is split out from CB:65523.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01 20:27:32 +00:00
Felix Singer
17968caa94 xcompile: Apply -Wextra with temporary exceptions to GCC
In order to detect more issues in our code, make GCC more picky by
enabling -Wextra. Disable a couple of warnings turned on by -Wextra
temporarily in order to keep everything compiling and working for now.
The warnings may be enabled step by step later.

Since xcompiles applies to coreboot and libpayload, add Wextra here
instead of the top-level Makefile.mk.

Change-Id: I60915cb66581dc2c9b6807335fd0e214b45e76d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83347
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01 20:22:53 +00:00
Sean Rhodes
0dba005f04 mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-01 18:49:45 +00:00
Sean Rhodes
e4592e4996 mb/starlabs/*: Add the subsystem ids for HDA
The Windows drivers require the subsystem ID to match on the PCI
device, so set these to allow the driver to install.

Change-Id: I01b36554d5322018efc72734a8e749cc06263577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01 18:49:25 +00:00
Elyes Haouas
ed48fa6847 mb/emulation/qemu-q35/memmap: Remove redefine macros
SMRAMC, C_BASE_SEG, G_SMRAME, D_LCK, D_CLS, D_OPEN, ESMRAMC, T_EN,
TSEG_SZ_MASK and H_SMRAME are already defined in included "q35.h" file.

Change-Id: Ic3c01cca14749f77adecc327a78ac011ba3f4c0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83429
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01 15:46:21 +00:00
Maxim Polyakov
cd55868873 util/superiotool/fintek: Add missing F81804 name for 0x0215 id
"0x1502 F81804 chipset ID, same for F81966" in
https://web.archive.org/web/20240628153609/https://github.com/torvalds/
linux/blob/master/drivers/gpio/gpio-f7188x.c

Change-Id: I6889ad8ad861465316333ff997956a05b74c5855
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01 15:41:22 +00:00
Lu, Pen-ChunX
00d538b562 soc/intel/xeon_sp: Add acpigen_write_pci_root_port
acpigen_write_pci_root_port writes SSDT device objects for PCIe
root port, _ADR and _BBN are provided. SSDT objects for direct
subordinate devices will also be created (if detected), _ADR and
_SUN are provided.

TEST=Build and boot on intel/archercity CRB

Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-08-01 15:32:25 +00:00
zengqinghong
188909aad4 mb/google/nissa: Create teliks variant
Create the teliks variant of the nissa reference board by copying
the anraggar files to a new directory named for the variant.

BUG=b:352263941
BRANCH=None
TEST=1. util/abuild/abuild -p none -t google/brya -x -a
        make sure the build includes GOOGLE_TELIKS
     2. Run part_id_gen tool without any errors

Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01 15:30:59 +00:00
Tyler Wang
f833cffef3 acpi/acpigen_ps2_keybd: Move KEY_DELETE to rest_of_keymaps
This patch supports keyboards that have delete key but without
numpad.

To prevent KEY_DELETE be defined twice, move it from
numeric_keypad_keymaps to rest_of_keymaps.

BUG=b:345231373
TEST=Build and test on Riven/Craaskino, delete key function
works

Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83684
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01 15:30:20 +00:00
Amanda Huang
874eb5bb40 mb/google/brya/var/orisa: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.

BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.

Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01 12:52:41 +00:00
Felix Held
73870298e3 soc/amd/common/psp: move buffer sizes to common header
Since the P2C_BUFFER_MAXSIZE value will be needed in another compilation
unit, move the define to the common psp_def.h. P2C_BUFFER_MAXSIZE is
moved there too for consistency reasons.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d4d93760c90ad6e0ecadf70600b1d697a02fa82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83701
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31 20:07:46 +00:00
Felix Held
930d0b16cc soc/amd/common/psp_smm: introduce and use send_psp_command_smm
When sending mailbox commands to the PSP from SMM, the SMM flag needs to
be set right before sending the mailbox command and cleared right after
the command is sent. In order to not have this code duplicated, factor
it out into a function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31 20:07:32 +00:00
Felix Held
e6c40f6272 soc/amd/common/psp_smm: add comments to psp_notify_smm
The reasoning behind this and the positive side effects of this aren't
too clear from the code, so point those out in a comment.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4f4121031fc1ef600cdf5551f61f1ef4e03b56a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31 20:07:17 +00:00
Felix Held
9c366417df soc/amd/common/psp_smm: add/improve comments to buffers and flags
Since it's not exactly obvious what 'c2p_buffer', 'p2c_buffer' and
'smm_flag' are used for, add comments to those.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ec092a92fe9f0686ffb7103e441802fc05381f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31 20:07:03 +00:00
Felix Held
ad8d0eff74 device/path: rename domain path struct element to 'domain_id'
Rename the 'domain' element of the 'domain_path' struct to 'domain_id'
to clarify that this element is the domain ID.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-07-31 14:32:51 +00:00
Felix Held
32c38ca221 device: introduce and use dev_get_domain_id
To avoid having constructs like 'dev->path.domain.domain' in the SoC
code, create the 'dev_get_domain_id' helper function that returns the
domain ID of either that device if it's a domain device or the
corresponding domain device's domain ID, and use it in the code.

If this function is called with a device other than PCI or domain type,
it won't have a domain number. In order to not need to call 'die',
'dev_get_domain_id' will print an error and return 0 which is a valid
domain number. In that case, the calling code should be fixed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31 14:32:19 +00:00
Maxim Polyakov
2c31e86d6b util/superiotool/fintek: Add f81966 register table
In accordance with the F81962/F81964/F81966/F81967 datasheet:
Release Date: Feb, 2018, Version: V0.18P [1].

[1] https://web.archive.org/web/20240707052102/http://
www.jetwaycomputer.com/download/Fintek/F81966_wdt_gpio.zip

Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-31 14:28:56 +00:00
Maxim Polyakov
365e511ee4 util/superiotool/fintek: Add f81866 register table
In accordance with the F81866A datasheet:
Release Date: Jan, 2012, Version: V0.14P [1].

[1] https://web.archive.org/web/20240707051837/http://www.
jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip

Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83004
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31 14:28:24 +00:00
Maxim Polyakov
dc2ee2096a util/superiotool: Add extra selectors support
Some chips (fintek [1,2]) have registers with specific selector-fields
that can affect the address space of the device (for example, switch the
register bank). At the same time, these registers contain fields that
should not change after they are configured in BIOS (for example, set
the port to 2E/2F or 4E/4F). In this case, the selector should take into
account the mask of the register fields and there is no convenient and
easy way to add this in the code in the utility. The selector-fields
should be set manually before the dump and this action is done several
times.

This patch adds an extra-selector mechanism that allows superiotool to
make a correct dump in automatic mode.

Just add a structure with an index, mask, and value for the selector
inside the superio_registers chip for the corresponding LDN to switch
the register bank:

{FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", {

* * *
{NOLDN, "Global",
  {0x28,0x2a,0x2b,0x2c,EOT},
  {0x00,0x00,0x00,0x00,EOT},
  {.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */
},
{0x03, "LPT",
  {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
  {NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */
},
* * *

Tested with Fintek F81966 on Asrock IMB-1222:

- run superiotool on Ubuntu and dump the registers for the board with
  the vendor's firmware;
- add the superio chip initialization code to the board configuration
  in coreboot and build the project;
- boot Ubuntu on the board with coreboot and re-dump the registers;
- the register values from the board configuration code are the same
  in both dumps.

Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e
(Global) -- ESEL[27h] 0x00 (Port Select Register) --
idx 02 07 20 21 23 24 25 26  27 28 29 2a 2b 2c 2d
val 00 0b 15 02 19 34 5a 23  80 a0 f0 45 02 e3 2e
def NA 00 15 02 19 34 00 23  02 a0 00 00 02 0c 28

* * *

The changes do not affect the configuration of existing chips, which
was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D
(the dump before and after the changes are the same).

[1] CB:83004
[2] CB:83019

Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31 14:28:06 +00:00
Karthikeyan Ramasubramanian
fa66d33336 soc/intel/adl: Update DCACHE_BSP_STACK_SIZE
During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.

BUG=None
TEST=Build Brox BIOS image and boot to OS.

Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31 14:11:30 +00:00
Subrata Banik
8200a9ac38 mb/google/trulo: Keep ISH default enable
This patch drops fw_config probing for ISH because ISH IP should
remains on by default for all Trulo variants.

Additionally, removed the redundant ISH entries from variant
override devicetree.

BUG=b:354607924
TEST=Able to verify ISH PCI Device is available while booting eMMC sku.

```
lspci
00:00.0 Host bridge: Intel Corporation Device 461c
...
00:12.0 Serial controller: Intel Corporation Device 54fc
...
00:1a.0 SD Host controller: Intel Corporation Device 54c4
```

Also, able to enter S0ix with this patch.

```
> suspend_stress_test -c 1 --ignore_s0ix_substates

At AP console:

s0ix errors: 0
s0ix substate errors: 0
s0ix pc10 errors: 0

At EC console:
power state 5 = S0ix, in 0x38d87
```
Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31 03:56:14 +00:00
Raymond Chung
42e4dd5aef mb/google/brya/var/xol: Using baseboard's PchPmSlpAMinAssert settings
Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum
time (98ms) from 2sec.

BUG=b:349595391
BRANCH=firmware-brya-14505.B
Test=Verified on xol

Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31 02:14:15 +00:00
Rishika Raj
97bc693abc mb/google/brya/var/orisa: Remove redundant defaults from overridetree
Streamline variant-level overrides by removing redundant entries that
already exist in either the SoC-level or the platform-level configurations.

BUG=None
TEST=emerge-nissa coreboot

Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-30 13:09:24 +00:00
Rishika Raj
8977282e12 MAINTAINERS: Update email id for ADL and google/brya mbs
Change-Id: Idcdd3e2525b621310aaf43608fd5fede8133d16a
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83675
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-30 13:09:12 +00:00
Sean Rhodes
89282af63e i2c/drivers/generic: Add support for including a CDM
Chip Direct Mapping is exclusive to Windows; it allows specifying the
position where a chip is mounted. There are 8 positions and a _CDM
method should return 0xabcd0X, where X is the position.

Tested by booting Windows 11 on the StarLite Mk V, rotating the device
and checking the orientation is correct, where previously, it was
inverted.

Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81409
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-29 20:24:41 +00:00
Yu-Ping Wu
e822d4b093 soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK comment
The comment for the BOOTBLOCK region should be written right above the
BOOTBLOCK declaration.

BUG=b:317009620
TEST=none
BRANCH=none

Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-29 13:51:06 +00:00
Subrata Banik
e99d22e09f Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity"
This reverts commit 59ee65d271.

Reason for revert:
- Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP
  version v5222.01. Therefore, no special handling is required.

BUG=b:330654700
TEST=Able to build google/tivviks.

Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-07-27 07:00:38 +00:00
Subrata Banik
85dd48fd80 mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10
This change adds a new USB2 Bluetooth device configuration on Port 10
for the Trulo variant.

* A new `drivers/usb/acpi` chip is added with:
    * `desc` set to "USB2 Bluetooth"
    * `type` set to "UPC_TYPE_INTERNAL"
    * `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
    * `device` referencing `usb2_port10`

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27 06:55:03 +00:00
Subrata Banik
a5b6e60411 mb/google/brya/var/trulo: Remove unused Bluetooth device
This change removes the configuration for the unused USB2 Port 6
(index 5) and its associated Bluetooth device on the Trulo variant.

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27 06:54:59 +00:00
Subrata Banik
b91546372a mb/google/brya/var/orisa: Remove unused Bluetooth device
This change removes the configuration for the unused USB2 Port 6
(index 5) and its associated Bluetooth device on the Orisa variant.

It also cleans up a redundant newline before the `serial_io_i2c_mode`
definition.

BUG=b:351976770
TEST=Builds successfully for google/orisa.

Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27 06:54:53 +00:00
Subrata Banik
a5aa6cb0b2 mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboard
This patch moves the configuration for integrated Bluetooth
functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard.

This change is necessary to support the CNVi BT module on Trulo
variants. The configuration is skipped for Orisa.

Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to
       support the CNVi BT module.
Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for
       CNVi WLAN has been removed.

This change ensures proper Bluetooth connectivity is applicable for all
Trulo variants including Orisa and Trulo.

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27 06:54:48 +00:00
Rishika Raj
c694522b52 mb/google/brya/var/orisa: Update fw_config probe for storage devices
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices.

2. Update fw_config probe to enable/disable devices in devicetree.

3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config
is enabled.

BUG=None
TEST=emerge-nissa coreboot

Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83657
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27 06:54:25 +00:00
Amanda Huang
2ecc785a69 mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Orisa
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Orisa variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.

BUG=b:345112878
TEST=Able to enter S0ix on Orisa eMMC sku after disabling UFS
during boot path.

Change-Id: I969b0c0c785ed4c408f6fc6de71e7d0c1a1ea27c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-27 06:53:02 +00:00
Yu-Ping Wu
fa9fbb40f9 arch/arm64/armv8/mmu: Add missing header arch/barrier.h
Also take the chance to sort the headers.

BUG=none
TEST=none
BRANCH=none

Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83651
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-27 05:13:28 +00:00
Varun Upadhyay
015c842620 vc/intel/fsp/twinlake: Update FSP headers to v5222.01
- Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h
- Update UPD Offset in FspsUpd.h

BUG=b:354612775
TEST=Able to build and boot google/Tivviks

Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27 03:41:54 +00:00
Subrata Banik
04762ca929 mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Trulo variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.

Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).

BUG=b:355384185
TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS
during boot path.

Able to grep below debug prints while booting the eMMC sku.

[INFO ]  FW_CONFIG value from CBI is 0x20000000
[INFO ]  Disabling UFS controllers
...
[INFO ]  fw_config match found: STORAGE=STORAGE_EMMC

Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-07-27 03:41:14 +00:00