Setting the clamp bit allows the CPU to operate below the highest
non-turbo frequency in order to obey the power limit.
Tested on ThinkPad T420 with the i7-3940XM.
Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be
Signed-off-by: Anastasios Koutian <akoutian2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This tool helps take off the burden of manually decoding default
configuration registers. Using decoded values can make code more
self-documenting compared to shrouding it with magic numbers.
This is also written as a module which allows easy integration with
other tools written in Go (e.g. autoport).
Change-Id: Ib4fb652e178517b2b7aceaac8be005c5b2d3b03e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Several brya variants were missing VBT files, add and select them in
Kconfig.
Also select in Kconfig for VELL, which already had a VBT but was not
using/selecting it.
TEST=build/boot google/brya (marasov), verify display init functional
/ payload screen shown.
Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83434
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Eliminates the use of a magic number, and the resulting DID entry in
the _DOD method is the same. The first entry was already changed in
commit 1810a18415 ("mb/google/*: Replace use of gfx/generic addr
field with display type"), this one was missed.
TEST=build/boot google/jinlon w/o privacy screen, dump SSDT and verify
DID entry is unchanged but _ADR is now correct (since the DID flags are
not part of the address field).
Change-Id: Ief22928ea831d4cb5b483406ac388218a97ad98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This change removes the unnecessary conditional compilation around
CBMEM_ID_CSE_BP_INFO and CBMEM_ID_CSE_INFO handling in
cb_parse_cbmem_entry. These CBMEM IDs are only relevant on platforms
with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD enabled, and platforms without
this config option won't encounter these IDs when calling
cb_parse_cbmem_entry().
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Issue: System hang occurred due to unhandled SPI synchronous SMI,
triggered by LOCK_ENABLE bit and WPD assertion.
Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration
to allow the system to handle and clear SPI synchronous SMI.
BUG=b:350623902
TEST=reboot test on 40 google/xol by ODM, all passed w/o
hang.
Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Edward Doan <edoan@chromium.org>
This patch extends the crashlog IP support beyond 32-bit mode to
support Intel future generation SoCs, which may require crashlog
support for 64-bit architectures. uintptr_t data type is used for
Address pointers and void* for dereferencing
BUG=b:346676856
TEST=Successfully built Meteor Lake (rex) and tested for google/rex0
and google/rex64 images.
Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
This commit also updates the USB2 port 10 description and set its type
to the more appropriate `UPC_TYPE_INTERNAL' type.
BUG=b:348345301
TEST=BRDS method is added to the CNVW device and returns the data
supplied by the SAR binary blob
Change-Id: I66c9b75d2aaa1b221313b037defcd2c579fd6b61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
The value stored in `gen` is only ever `1` or `0`. Storing `1` causes
Clang to warn, since the only valid values for a 1-bit int are -1 and 0:
```
amdfwtool.c:1487:27: error: implicit truncation from 'int' to a one-bit
wide bit-field changes value from 1 to -1
[-Werror,-Wsingle-bit-bitfield-constant-conversion]
1487 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
```
TEST=Rebuilt coreboot; no warning was emitted.
Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586
Signed-off-by: George Burgess IV <gbiv@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83412
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices,
this is used for the first boot in factory.
2. Add fw_config probe to enable/disable devices in devicetree
instead of variant.c, it can avoid suspend(s0ix) fail issue.
BUG=b:328580882
TEST=On riven eMMC and UFS SKUs, boot to OS and run
`suspend_stress_test -c 10` pass.
Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CMOS entry for CSE partition firmware was incorrectly labeled as
`ramtop` and `partition firmware` in the error messages.
This patch corrects the messages to accurately refer to `CSE partition
firmware`.
Additionally, the alignment and size check comments are updated to
reflect this change.
Change-Id: Ib3a7fb88f52c4d0c47d828bcd1c4649e62d19654
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Updating from commit id ae5fc7d:
2024-03-15 19:58:57 +0100 - (picasso: Update PSP fw to version
00.08.14.7B)
to commit id 26c5729:
2024-07-10 10:10:50 -0500 - (CZN: Update SMU fw to 64.72.0)
This brings in 2 new commits:
26c5729 CZN: Update SMU fw to 64.72.0
942adff Add VanGogh blobs
Change-Id: I4c699379a196a0819201f7a6c9f1b3319edef4ff
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch adds support for x86-64 to the rdtsc() function, allowing
it to correctly read the Time Stamp Counter (TSC) on both 32-bit and
64-bit x86 architectures.
BUG=b:242829490, b:351851626
TEST=Builds and boots on google/rex0 and google/rex64 systems and
manually verified correct TSC readings on x86-32 and x86-64 hardware.
Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch ensures CSE boot partition (RO/RW) version information only
log when the status is "success". If the status is not successful,
log an error message indicating the failure and status code.
This change avoids logging potentially incorrect version information
when the boot partition is not valid.
BUG=b:305898363
TEST=Builds successfully for google/rex variants.
Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch refactors CSE config options, moving the selection of:
* `SOC_INTEL_CSE_LITE_SKU`
* `SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2`
* `SOC_INTEL_CSE_SEND_EOP_ASYNC`
from the generic `BOARD_GOOGLE_REX_COMMON` to individual board models.
This enables finer-grained control over CSE features and sync behavior
on different Rex and variants platforms.
Specifically:
* `google/rex0`: Selects `SOC_INTEL_CSE_LITE_SKU` for CSE sync within
coreboot.
* `google/rex64`: Selects `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` and
`SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD` to defer CSE sync
to the payload.
BUG=b:305898363
TEST=Builds successfully for google/rex variants.
Change-Id: Ib5957496b1e1dad8d135b3e10541cb83dd339539
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83397
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional
on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being
enabled.
This ensures that CSE Lite PSR is only active when both ChromeOS is the
target platform and CSE sync is performed inside coreboot.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and
`ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include
`SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`.
This allows these features to be enabled even when CSE sync is performed
in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU`
config is enabled).
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch updates FSP-M UPDs conditionally to ensure CSE firmware
updates and VGA initialization control only when
`SOC_INTEL_CSE_LITE_SKU` config is enabled.
This ensures eSOL rendering is tied to CSE sync performed in coreboot,
preventing unnecessary setup when sync is deferred to the payload.
Deferring CSE sync to the payload results in the depthcharge screen.
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch refactors the handling of CSE CBMEM IDs to enable platforms
to choose whether to perform CSE sync operations within coreboot or
defer it to the payload. This separation improves code organization,
ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks.
Now, platforms can select:
* `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot
* `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync
This change ensures mutually exclusive options, avoiding unnecessary
SPI flash size increases.
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard is identified as 0Y2MRG.
The version tested is with Nvidia dGPU (gfx 560ti).
The flash is a 4MiB Winbond W25Q32BVSIG.
It can be flashed internally with flashrom.
Add a strap on the service mode pin of the mainboard for internal flash.
Tested working:
- SeaBIOS
- All USB ports
- SATA
- dGPU
- Ethernet
- Environment control
- GPIOs
- S3 Sleep mode
- WakeOnLan
Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059
Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
A previous commit splits out Cirrus display support from Bochs display
support, with both using the pre-existing Bochs config options for the
requested display resolution. Rename these config names to clarify they
are not only specific to the Bochs display driver.
Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
QEMU's Cirrus display device is supported along with the Bochs driver
since commit 7905f9254e ("qemu: cirrus native video init"). It is no
longer the default since QEMU 2.2. The code supporting it can work
independently of the Bochs display driver and depends more heavily on
port I/O and VGA support code, so split it from that code to make it
easier to support the Bochs driver in other architectures.
Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Expose aliased PCI and PNP devices as `pci_/pnp_devfn_t` constants
in <static_devices.h>. They will be named `_sdev_<alias>` to have
a underscore prefix for consistency and to not collide with the
`struct device` objects (with `_dev_` prefix).
Change-Id: I2d1cfe12b1e7309f8235c84dd220bd090ebfe1b5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Allows to use this driver for the SMBus console without sending an index
byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER).
Tested with WiP VIA CX700-M2 port and FT4222H as receiver.
Change-Id: Ic368ef379039b104064c9a91474b188646388dd2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Myst boards.
TEST=untested, but same change as made for Mendocino
Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Skyrim boards.
TEST=build/boot Skyrim (Frostflow), verify RAM training only
run on first boot after flashing.
Change-Id: I9be1699d675331b46ee9c42570700c2b72588025
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The ioapic and ioapic_irq keywords are no longer valid tokens as of
commit e84b095d3a (util/sconfig: Remove unused ioapic and irq
keywords), and the associated driver had previously been removed in
commit ca5a793ec3 (drivers/generic/ioapic: Drop poor implementation).
Thus, drop them from autoport. Also, the IOAPICIRQs map that this code
relied on to generate ioapic_irq entries never seems to have been
populated by any code in any previous commit, so this appears to have
been dead code since autoport was created.
The lapic keyword was removed from sconfig in commit 15d5183e4a
(util/sconfig: Remove lapic devices from devicetree parsers) so remove
autoport handling for it as well.
Change-Id: Icf2582594b244cf5f726c722eb3a3c12573a2662
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
