The purpose of integration function is to pack the FWs into table. We
need to remove other process. Create a dedicate function to link all
the tables together. And this linking function is only called when
both the level 1 and level 2 directory are created. This simplifies
the main function and logic.
TEST=Identical test on all AMD SOC platform
Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This data is used by smm_region_overlaps_handler(). Callers use this
helper to determine if it's safe to read/write to memory buffers taken
from untrusted input.
coreboot SMI handlers must not be confused into writing over any SMRAM
subregion, which includes the TSEG_STAGE_CACHE and chipset-specific area
(sometimes, IED), not just the handlers.
If stage cache writes were permitted, this could compromise the
integrity of the S3 resume path.
The consequences to overwriting the chipset-specific area are undefined.
Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80703
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
CB:77969 made minor changes to the die_if() macro. One of the
consequences is that the format string passed to it can no longer be a
real `char *` variable, it needs to actually be a string literal. In the
vast majority of call sites that is already the case, but there was one
instance in the GDB code where we're reusing the same format string many
times and for that reason put it into a const variable. Fix that by
turning it into a #define macro instead. (Even though this technically
duplicates the format string, the linker is able to merge identical
string literals together again, so it doesn't really end up taking more
space.)
Change-Id: I532a04b868f12aa0e3c01422c075ddaade251827
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81361
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig.
This enables a single binary for both SKU1 and SKU2. For SKU2, upon
boot from cold reset, it will disable the UFS Controller and then
trigger a warm boot.
BUG=b:329209576
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.
Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Instead of including the generated dependency file during the evaluation
of asl_template, add it to the DEPENDENCIES variable so that it is
included at the same time as the rest of the .d files in the top level
Makefile. This makes the handling of .d files cleaner as all of them are
processed in the same way. Tracking all of them in a single variable
also prevents any from being missed if any post-processing is performed
on them, such as running them through the fixdep utility from the Linux
kernel project to replace the config.h dependency with only the configs
that are used.
This should be safe since asl_template is evaluated while calling
includemakefiles, which is occurs before the files in DEPENDENCIES are
included.
TEST:
1. Build dell/e6400
2. Run `touch src/mainboard/dell/e6400/dsdt.asl` (defined as a
prerequisite of build/dsdt.aml in build/dsdt.d)
3. Run `make --debug=b`
4. Verify that dsdt.aml was rebuilt due dsdt.asl being newer than target
Change-Id: Ie8271d1e172395917f2859c8bbfd2041ddc572ca
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This was added in commit 963bed546f (Make: Use unaltered object list for
dependency inclusion) to fix an issue caused by ramstage-postprocess.
The logic for handling dependency inclusion changed in commit db273065f6
(build system: extend src-to-obj for non-.c/.S files), causing the
variable to become unused.
Change-Id: I011ff2070bc31ab9ddf2536873555d0157f91fce
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Adjust touchscreen power sequencing for eKTH5015M.
The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec.
BUG=b:328170008
BRANCH=firmware-nissa-15217.B
TEST=Build and check I2C devices timing meet spec.
[INFO ] input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4
Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.
Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
There are 2 ways of referring to linker symbols, as extern
u8[] or extern u8*. Only the former will be correctly
initiated into an immediate operand (a constant) to asm.
DECLARE_REGION defines reference in form of extern u8[].
Use DECLARE_REGION as a standard way for these references.
TEST=intel/archercity CRB
Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81097
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
As of now coreboot only supported one PCI segment group and thus the
MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the
default FSP doesn't allow to disable unused IIO stacks a patched
version had to be used. Those unused IIO stacks consume lots of PCI
bus ranges, leaving no free buses for the secondary side behind PCI
bridges. The IIO disable mechanism doesn't work after ACPI G3 exit
and thus requires multiple reboots when the previous state was G3.
Since coreboot now supports multi PCI segment groups enable 512
MMCONF buses on 4S platforms by default and drop the IIO stack
disable UPDs on ibm/sbp1. This allows to boot faster without the
need for a patched FSP.
The use of multiple PCI segment groups might prevent legacy software
from working properly, however the only board where multiple PCI
segment groups are used uses u-root as default payload.
TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups.
TEST=intel/archercity CRB
Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add PCI enumeration support by reading the PCIeSegment reported in the
FSP HOB and add it when creating the PCI domain for each stack.
The PCI enumeration will be able to scan the additional PCI segment
groups and properly handle those devices.
TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled
to ubuntu 22.04.
TEST=intel/archercity CRB
Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.
TEST=Booted on ibm/sbp1 with multiple PCI segment groups.
Properly generates multiple SATC headers.
TEST=intel/archercity CRB
Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In DECLARE_REGION and DECLARE_OPTIONAL_REGION, a set of 3 variables
will be defined, that is the region 'base', 'end' and 'size'.
However, in many codes, the users will only selectively use 'end'
or 'size' instead of both of them, which will trigger compiler errors
for unused variables. This patch sets __maybe_unused attributes on
'end' and 'size' so that users do not need to use all of them.
TEST=intel/archercity CRB
Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81209
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DMAR entries of type "PCI" have no "Enumeration ID" and thus
there's no need to print it. Drop all unused Enumeration IDs to
simplify the code and debug prints.
Document ID: Intel Virtualization Technology for Directed I/O
Architecture Specification, Rev. 4.0, Order Number: D51397-015
TEST=intel/archercity CRB
Change-Id: I009fbfb9f9d62855d351c5db2d3d88722b5dbfa2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81186
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our major version is suddenly two digits long to represent the year.
This can't be parsed with the current sed scripts. To make sure that
no unparsed data ends up in our major/minor versions, we'll run sed
with `-n' and only print the extracted numbers if anything. Also, to
allow us to use the version numbers in C code, we strip leading zeros
(a leading 0 identifies octal numbers, so for instance 08 for August
is not a valid number).
This can result in empty major/minor version strings, so we move the
default `0' to the final variable expansion.
As a bonus, this makes an explicit check if the numbers can be parsed
unnecessary.
Change-Id: Ie39381a8ef4b971556168b6996efeefe6adf2b14
Reported-by: Christoph Zechner <christophz@vrvis.at>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81290
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The entry in the table has two categaries, file and pointer. For the
pointer, it does not take table space. The ISH, PSP level 2, BIOS
table are all the pointer type. So integration function only packs FWs
located in folder amd_blobs. And only FWs increase the table size.
So the table size is only set once. Later calls only update the count
and fletcher. The table has a header at least, so the size can not be
0.
The fill_dir_header can take the parameter count as 0, such PSP level
1 only with ISH-A and ISH-B. It doesn't have any file type entries.
This actually reverts
https://review.coreboot.org/c/coreboot/+/78274
and adds other changes.
TEST=Identical test on all AMD SOC platform
Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:77968 made some non-BSD commonlib files part of libpayload when
CONFIG_LP_GPL is set. This patch exports those headers to the payload
(again only when CONFIG_LP_GPL is set) so that payloads can also call
the functions in them directly.
Also make those includes available to tests so that their functions can
be tested. There's no menuconfig for unit tests, so they are included
unconditionally, but this should be fine since the tests are standalone
and won't have to link with any proprietary third-party code.
Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Create the bujia variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:327549688
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_BUJIA
Change-Id: I453a50f1aa64f8d4119bf0f860d928aa3e00a144
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81198
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
The value for CCACHE in site-local/Kconfig gets overridden by the
default in src/Kconfig. Remove the default to make overrides possible.
Change-Id: I6b9dbbb31caa3ef09afd7ecb355c01bd53807b39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration
at the SoC level for all MTL devices. This change streamlines the
configuration process, avoiding redundant selections on individual
mainboards.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/ovis and google/rex.
Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch ensures Ovis baseboard can select RAMTOP caching to improve
the boot time w/o any runtime hang.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis with ~30ms savings in boot time.
Change-Id: Ic0b73eb8fb9cd6ca70d3d7168b79dfd0fbc550e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch refactors RAMTOP MTRR type selection to address a critical
NEM logic bug on SoCs with non-power-of-two cache sets. This bug can
cause runtime hangs when Write Back (WB) caching is enabled.
Workaround: Force MTRR type to WC (Write Combining) on affected SoCs
when the cache set count is not a power of two.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a function to determine whether the number of cache sets is
a power of two. This aligns with common cache design practices that
favor power-of-two counts for efficient indexing and addressing.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified functionality on google/ovis and google/rex (including
a non-power-of-two Ovis configuration).
Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe using clk_src[0] and clk_req[1] mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=0,clk_req=1 in mFIT.
BUG=b:328318578
TEST=build firmware and veirfy suspend function on NVMe SKU DUT.
Cq-Depend: chrome-internal:7063434
Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
