mb/system76: Enable S0ix support but prefer S3

Enable S0ix support but continue using S3 by default as it is not
tested on most boards. TGL-U boards continue to only use S0ix as S3 is
not supported on them.

Change-Id: Idc881d30009e3ef170e5430596652548aa434fda
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/system76/addw1/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/adl/devicetree.cb

@@ -11,6 +11,10 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/bonw14/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/cml-u/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
 	register "enable_c6dram" = "1"

src/mainboard/system76/gaze15/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/oryp5/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/oryp6/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/rpl/devicetree.cb

@@ -11,6 +11,10 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/tgl-h/devicetree.cb

@@ -12,6 +12,10 @@ chip soc/intel/tigerlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # CPU (soc/intel/tigerlake/cpu.c)
 	# Power limits
 	register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{

src/mainboard/system76/whl-u/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
 	register "enable_c6dram" = "1"

src/soc/intel/alderlake/acpi.c

@@ -158,7 +158,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_io(fadt);
 
-	if (config->s0ix_enable)
+	if (config->s0ix_enable && !config->prefer_s3_suspend)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 

src/soc/intel/alderlake/chip.h

@@ -771,6 +771,14 @@ struct soc_intel_alderlake_config {
 	 * Set this to 0 in order to disable hwp scalability tracking.
 	 */
 	bool enable_hwp_scalability_tracking;
+
+	/*
+	 * Used with `s0ix_enable` to indicate S3 is the preferred suspend
+	 * method via the FADT feature flag.
+	 * Default is set to false, using S0ix for suspend.
+	 * Set this to true to indicate to the OS that S3 should be used.
+	 */
+	bool prefer_s3_suspend;
 };
 
 typedef struct soc_intel_alderlake_config config_t;

src/soc/intel/cannonlake/acpi.c

@@ -157,7 +157,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_io(fadt);
 
-	if (config->s0ix_enable)
+	if (config->s0ix_enable && !config->prefer_s3_suspend)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 

src/soc/intel/cannonlake/chip.h

@@ -452,6 +452,14 @@ struct soc_intel_cannonlake_config {
 	bool cpu_turbo_disable;
 
 	bool disable_vmx;
+
+	/*
+	 * Used with `s0ix_enable` to indicate S3 is the preferred suspend
+	 * method via the FADT feature flag.
+	 * Default is set to false, using S0ix for suspend.
+	 * Set this to true to indicate to the OS that S3 should be used.
+	 */
+	bool prefer_s3_suspend;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/meteorlake/acpi.c

@@ -159,7 +159,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_io(fadt);
 
-	if (config->s0ix_enable)
+	if (config->s0ix_enable && !config->prefer_s3_suspend)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 

src/soc/intel/meteorlake/chip.h

@@ -525,6 +525,14 @@ struct soc_intel_meteorlake_config {
 	 * as per `enum slew_rate` data type.
 	 */
 	uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
+
+	/*
+	 * Used with `s0ix_enable` to indicate S3 is the preferred suspend
+	 * method via the FADT feature flag.
+	 * Default is set to false, using S0ix for suspend.
+	 * Set this to true to indicate to the OS that S3 should be used.
+	 */
+	bool prefer_s3_suspend;
 };
 
 typedef struct soc_intel_meteorlake_config config_t;

src/soc/intel/tigerlake/acpi.c

@@ -156,7 +156,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_io(fadt);
 
-	if (config->s0ix_enable)
+	if (config->s0ix_enable && !config->prefer_s3_suspend)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 

src/soc/intel/tigerlake/chip.h

@@ -533,6 +533,14 @@ struct soc_intel_tigerlake_config {
 
 	/* i915 struct for GMA backlight control */
 	struct i915_gpu_controller_info gfx;
+
+	/*
+	 * Used with `s0ix_enable` to indicate S3 is the preferred suspend
+	 * method via the FADT feature flag.
+	 * Default is set to false, using S0ix for suspend.
+	 * Set this to true to indicate to the OS that S3 should be used.
+	 */
+	bool prefer_s3_suspend;
 };
 
 typedef struct soc_intel_tigerlake_config config_t;