WIP: lemp9 vboot support

Change-Id: I47fbc95a8bd242b4261f5fc52b073f0b2b6ab080

.gitmodules

@@ -1,53 +1,53 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty

MAINTAINERS

@@ -378,6 +378,13 @@ F:	src/mainboard/siemens/mc_apl1/
 
 
 
+SYSTEM76 MAINBOARDS
+M:	Jeremy Soller <jeremy@system76.com>
+S:	Maintained
+F:	src/mainboard/system76/
+
+
+
 SUPERMICRO X10SLM+-F MAINBOARD
 M:	Tristan Corrick <tristan@corrick.kiwi>
 S:	Maintained
@@ -438,6 +445,11 @@ M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
 F:	src/ec/lenovo/
 
+SYSTEM76 EC
+M:	Jeremy Soller <jeremy@system76.com>
+S:	Maintained
+F:	src/ec/system76/
+
 ################################################################################
 # Northbridges
 ################################################################################

src/console/Kconfig

@@ -302,6 +302,13 @@ config SPI_CONSOLE
 	  This is currently working only in ramstage due to how the spi
 	  drivers are written.
 
+config CONSOLE_SYSTEM76_EC
+	bool "System76 EC console output"
+	default n
+	depends on EC_SYSTEM76_EC
+	help
+	  Send coreboot debug output to a System76 embedded controller.
+
 config CONSOLE_OVERRIDE_LOGLEVEL
 	bool
 	help

src/console/console.c

@@ -9,6 +9,7 @@
 #include <console/usb.h>
 #include <console/spi.h>
 #include <console/flash.h>
+#include <console/system76_ec.h>
 
 void console_hw_init(void)
 {
@@ -21,6 +22,7 @@ void console_hw_init(void)
 	__usbdebug_init();
 	__spiconsole_init();
 	__flashconsole_init();
+	__system76_ec_init();
 }
 
 void console_tx_byte(unsigned char byte)
@@ -42,6 +44,7 @@ void console_tx_byte(unsigned char byte)
 	__usb_tx_byte(byte);
 	__spiconsole_tx_byte(byte);
 	__flashconsole_tx_byte(byte);
+	__system76_ec_tx_byte(byte);
 }
 
 void console_tx_flush(void)
@@ -50,6 +53,7 @@ void console_tx_flush(void)
 	__ne2k_tx_flush();
 	__usb_tx_flush();
 	__flashconsole_tx_flush();
+	__system76_ec_tx_flush();
 }
 
 void console_write_line(uint8_t *buffer, size_t number_of_bytes)

src/drivers/i2c/tas5825m/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_I2C_TAS5825M
+	bool
+	default n
+	help
+	  Enable support for TI TAS5825M Amplifier.

src/drivers/i2c/tas5825m/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += tas5825m.c

src/drivers/i2c/tas5825m/chip.h

@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+struct drivers_i2c_tas5825m_config {
+	//TODO
+};

src/drivers/i2c/tas5825m/tas5825m.c

@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include "tas5825m.h"
+
+int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) {
+	return smbus_write_byte(dev, addr, value);
+}
+
+//TODO: use I2C block write for better performance
+int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length) {
+	int res = 0;
+	for (uint8_t i = 0; i < length; i++) {
+		res = smbus_write_byte(dev, addr + i, values[i]);
+		if (res < 0) return res;
+	}
+	return (int)length;
+}
+
+int tas5825m_set_page(struct device *dev, uint8_t page) {
+	return tas5825m_write_at(dev, 0x00, page);
+}
+
+int tas5825m_set_book(struct device *dev, uint8_t book) {
+	int res = tas5825m_set_page(dev, 0x00);
+	if (res < 0) return res;
+	return tas5825m_write_at(dev, 0x7F, book);
+}
+
+__weak int tas5825m_setup(struct device *dev) {
+	struct drivers_i2c_tas5825m_config *config = dev->chip_info;
+
+	if (!config) {
+		printk(BIOS_ERR, "tas5825m: failed to find config\n");
+		return -1;
+	}
+
+	printk(BIOS_ERR, "tas5825m: setup not implemented\n");
+	return -1;
+}
+
+static void tas5825m_init(struct device *dev) {
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C &&
+		ops_smbus_bus(get_pbus_smbus(dev))) {
+		printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev));
+		int res = tas5825m_setup(dev);
+		if (res) {
+			printk(BIOS_ERR, "tas5825m init failed: %d\n", res);
+		} else {
+			printk(BIOS_DEBUG, "tas5825m init successful\n");
+		}
+	}
+}
+
+static struct device_operations tas5825m_operations = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.init			= tas5825m_init,
+};
+
+static void tas5825m_enable_dev(struct device *dev) {
+	dev->ops = &tas5825m_operations;
+}
+
+struct chip_operations drivers_i2c_tas5825m_ops = {
+	CHIP_NAME("TI TAS5825M Amplifier")
+	.enable_dev = tas5825m_enable_dev,
+};

src/drivers/i2c/tas5825m/tas5825m.h

@@ -0,0 +1,12 @@
+#ifndef TAS5825M_H
+#define TAS5825M_H
+
+#include <device/device.h>
+
+int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value);
+int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length);
+int tas5825m_set_page(struct device *dev, uint8_t page);
+int tas5825m_set_book(struct device *dev, uint8_t book);
+int tas5825m_setup(struct device *dev);
+
+#endif // TAS5825M_H

src/drivers/intel/gma/acpi/configure_brightness_levels.asl

@@ -148,7 +148,7 @@
 	{
 		If (LEqual(^BOX3.XBCM (Arg0), Ones))
 		{
-			^LEGA.XBCM (Arg0)
+			//TODO: fix Windows initial setup ^LEGA.XBCM (Arg0)
 		}
 	}
 

src/drivers/system76/dgpu/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_SYSTEM76_DGPU
+	bool
+	default n
+	help
+		System76 switchable graphics support

src/drivers/system76/dgpu/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_SYSTEM76_DGPU) += ramstage.c

src/drivers/system76/dgpu/acpi/dgpu.asl

@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEGP) {
+	Name (_ADR, 0x00010000)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
+		}
+
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
+		}
+	}
+
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
+}
+
+Device (\_SB.PCI0.PEGP.DEV0) {
+	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+	OperationRegion (RPCX, SystemMemory, 0xE0008000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
+
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
+
+				Debug = "    Sleep 16"
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
+	}
+
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
+}

src/drivers/system76/dgpu/bootblock.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: do not require this to be included in mainboard bootblock.c
+
+#include <console/console.h>
+#include <delay.h>
+#include <gpio.h>
+
+static void dgpu_power_enable(int onoff) {
+	printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff);
+	if (onoff) {
+		gpio_set(DGPU_RST_N, 0);
+		mdelay(4);
+		gpio_set(DGPU_PWR_EN, 1);
+		mdelay(4);
+		gpio_set(DGPU_RST_N, 1);
+	} else {
+		gpio_set(DGPU_RST_N, 0);
+		mdelay(4);
+		gpio_set(DGPU_PWR_EN, 0);
+	}
+	mdelay(50);
+}

src/drivers/system76/dgpu/ramstage.c

@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/pci.h>
+
+static void dgpu_read_resources(struct device *dev) {
+	printk(BIOS_INFO, "system76: dgpu_read_resources %s\n", dev_path(dev));
+
+    pci_dev_read_resources(dev);
+
+	int bar;
+	// Find all BARs on DGPU, mark them above 4g if prefetchable
+	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		printk(BIOS_INFO, "  BAR at 0x%02x\n", bar);
+
+	    struct resource *res;
+		res = probe_resource(dev, bar);
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "    marked above 4g\n");
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_INFO, "    not prefetch\n");
+			}
+		} else {
+			printk(BIOS_INFO, "    not found\n");
+		}
+	}
+}
+
+static void dgpu_enable_resources(struct device *dev) {
+	printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev));
+
+	dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID;
+	dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID;
+	printk(BIOS_INFO, "  subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device);
+	pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff));
+
+	pci_dev_enable_resources(dev);
+}
+
+static struct device_operations dgpu_pci_ops_dev = {
+	.read_resources   = dgpu_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = dgpu_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &pci_dev_ops_pci,
+};
+
+static void dgpu_above_4g(void *unused) {
+	struct device *pdev;
+
+	// Find PEG0
+	pdev = pcidev_on_root(1, 0);
+	if (!pdev) {
+		printk(BIOS_ERR, "system76: failed to find PEG0\n");
+		return;
+	}
+	printk(BIOS_INFO, "system76: PEG0 at %p, %04x:%04x\n", pdev, pdev->vendor, pdev->device);
+
+    int fn;
+    for (fn = 0; fn < 8; fn++) {
+	    struct device *dev;
+
+        // Find DGPU functions
+        dev = pcidev_path_behind(pdev->link_list, PCI_DEVFN(0, fn));
+        if (dev) {
+            printk(BIOS_INFO, "system76: DGPU fn %d at %p, %04x:%04x\n", fn, dev, dev->vendor, dev->device);
+            dev->ops = &dgpu_pci_ops_dev;
+        } else {
+            printk(BIOS_ERR, "system76: failed to find DGPU fn %d\n", fn);
+        }
+    }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, dgpu_above_4g, NULL);

src/ec/system76/ec/Kconfig

@@ -0,0 +1,9 @@
+config EC_SYSTEM76_EC
+	bool
+	help
+	  System76 EC
+
+config EC_SYSTEM76_EC_COLOR_KEYBOARD
+	depends on EC_SYSTEM76_EC
+	bool
+	default n

src/ec/system76/ec/Makefile.inc

@@ -0,0 +1,6 @@
+ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
+
+all-y += system76_ec.c
+smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
+
+endif

src/ec/system76/ec/acpi/buttons.asl

@@ -3,11 +3,11 @@
 Device (PWRB)
 {
 	Name (_HID, EisaId ("PNP0C0C"))
-	Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 })
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
 }
 
 Device (SLPB)
 {
 	Name (_HID, EisaId ("PNP0C0E"))
-	Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 })
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
 }

src/ec/system76/ec/acpi/ec.asl

@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "ac.asl"
+	#include "battery.asl"
+	#include "buttons.asl"
+	#include "hid.asl"
+	#include "lid.asl"
+	#include "s76.asl"
+}
+
+Device (\_SB.PCI0.LPCB.EC0)
+{
+	Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */)  // _HID: Hardware ID
+	Name (_GPE, EC_GPE_SCI)  // _GPE: General Purpose Events
+	Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+	{
+		IO (Decode16,
+			0x0062,             // Range Minimum
+			0x0062,             // Range Maximum
+			0x00,               // Alignment
+			0x01,               // Length
+			)
+		IO (Decode16,
+			0x0066,             // Range Minimum
+			0x0066,             // Range Maximum
+			0x00,               // Alignment
+			0x01,               // Length
+			)
+	})
+
+	#include "ec_ram.asl"
+
+	Name (ECOK, Zero)
+	Method (_REG, 2, Serialized)  // _REG: Region Availability
+	{
+		Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1))))
+		If (((Arg0 == 0x03) && (Arg1 == One))) {
+			// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
+			ECOS = 1
+
+			// Enable software display brightness keys
+			WINF = 1
+
+			// Set current AC state
+			^^^^AC.ACFG = ADP
+			// Update battery information and status
+			^^^^BAT0.UPBI()
+			^^^^BAT0.UPBS()
+
+			// Notify of changes
+			Notify(^^^^AC, Zero)
+			Notify(^^^^BAT0, Zero)
+
+			PNOT ()
+
+			// EC is now available
+			ECOK = Arg1
+
+			// Reset System76 Device
+			^^^^S76D.RSET()
+		}
+	}
+
+	Method (PTS, 1, Serialized) {
+		Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
+		If (ECOK) {
+			// Clear wake cause
+			WFNO = Zero
+		}
+	}
+
+	Method (WAK, 1, Serialized) {
+		Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
+		If (ECOK) {
+			// Set current AC state
+			^^^^AC.ACFG = ADP
+
+			// Update battery information and status
+			^^^^BAT0.UPBI()
+			^^^^BAT0.UPBS()
+
+			// Notify of changes
+			Notify(^^^^AC, Zero)
+			Notify(^^^^BAT0, Zero)
+
+			// Reset System76 Device
+			^^^^S76D.RSET()
+		}
+	}
+
+	Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
+	{
+		Debug = "EC: Touchpad Toggle"
+	}
+
+	Method (_Q0B, 0, NotSerialized) // Screen Toggle
+	{
+		Debug = "EC: Screen Toggle"
+	}
+
+	Method (_Q0C, 0, NotSerialized)  // Mute
+	{
+		Debug = "EC: Mute"
+	}
+
+	Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
+	{
+		Debug = "EC: Keyboard Backlight"
+	}
+
+	Method (_Q0E, 0, NotSerialized) // Volume Down
+	{
+		Debug = "EC: Volume Down"
+	}
+
+	Method (_Q0F, 0, NotSerialized) // Volume Up
+	{
+		Debug = "EC: Volume Up"
+	}
+
+	Method (_Q10, 0, NotSerialized) // Switch Video Mode
+	{
+		Debug = "EC: Switch Video Mode"
+	}
+
+	Method (_Q11, 0, NotSerialized) // Brightness Down
+	{
+		Debug = "EC: Brightness Down"
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (20)
+		}
+	}
+
+	Method (_Q12, 0, NotSerialized) // Brightness Up
+	{
+		Debug = "EC: Brightness Up"
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (19)
+		}
+	}
+
+	Method (_Q13, 0, NotSerialized) // Camera Toggle
+	{
+		Debug = "EC: Camera Toggle"
+	}
+
+	Method (_Q14, 0, NotSerialized) // Airplane Mode
+	{
+		Debug = "EC: Airplane Mode"
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (8)
+		}
+		// TODO: hardware airplane mode
+	}
+
+	Method (_Q15, 0, NotSerialized) // Suspend Button
+	{
+		Debug = "EC: Suspend Button"
+		Notify (SLPB, 0x80)
+	}
+
+	Method (_Q16, 0, NotSerialized) // AC Detect
+	{
+		Debug = "EC: AC Detect"
+		^^^^AC.ACFG = ADP
+		Notify (AC, 0x80) // Status Change
+		If (BAT0)
+		{
+			Notify (^^^^BAT0, 0x81) // Information Change
+			Notify (^^^^BAT0, 0x80) // Status Change
+		}
+	}
+
+	Method (_Q17, 0, NotSerialized)  // BAT0 Update
+	{
+		Debug = "EC: BAT0 Update (17)"
+		Notify (^^^^BAT0, 0x81) // Information Change
+	}
+
+	Method (_Q19, 0, NotSerialized)  // BAT0 Update
+	{
+		Debug = "EC: BAT0 Update (19)"
+		Notify (^^^^BAT0, 0x81) // Information Change
+	}
+
+	Method (_Q1B, 0, NotSerialized) // Lid Close
+	{
+		Debug = "EC: Lid Close"
+		Notify (LID0, 0x80)
+	}
+
+	Method (_Q1C, 0, NotSerialized) // Thermal Trip
+	{
+		Debug = "EC: Thermal Trip"
+		/* TODO
+		Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
+		Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
+		*/
+	}
+
+	Method (_Q1D, 0, NotSerialized) // Power Button
+	{
+		Debug = "EC: Power Button"
+		Notify (PWRB, 0x80)
+	}
+
+	Method (_Q50, 0, NotSerialized) // Other Events
+	{
+		Local0 = OEM4
+		If (Local0 == 0x8A) {
+			Debug = "EC: White Keyboard Backlight"
+			Notify (^^^^S76D, 0x80)
+		} ElseIf (Local0 == 0x9F) {
+			Debug = "EC: Color Keyboard Toggle"
+			Notify (^^^^S76D, 0x81)
+		} ElseIf (Local0 == 0x81) {
+			Debug = "EC: Color Keyboard Down"
+			Notify (^^^^S76D, 0x82)
+		} ElseIf (Local0 == 0x82) {
+			Debug = "EC: Color Keyboard Up"
+			Notify (^^^^S76D, 0x83)
+		} ElseIf (Local0 == 0x80) {
+			Debug = "EC: Color Keyboard Color Change"
+			Notify (^^^^S76D, 0x84)
+		} Else {
+			Debug = Concatenate("EC: Other: ", ToHexString(Local0))
+		}
+	}
+}

src/ec/system76/ec/acpi/lid.asl

@@ -3,7 +3,7 @@
 Device (LID0)
 {
 	Name (_HID, EisaId ("PNP0C0D"))
-	Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 })
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
 
 	Method (_LID, 0, NotSerialized) {
 		DEBUG = "LID: _LID"

src/ec/system76/ec/acpi/s76.asl

@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Notifications:
+//   0x80 - hardware backlight toggle
+//   0x81 - backlight toggle
+//   0x82 - backlight down
+//   0x83 - backlight up
+//   0x84 - backlight color change
+Device (S76D) {
+	Name (_HID, "17761776")
+	Name (_UID, 0)
+
+	Method (RSET, 0, Serialized) {
+		Debug = "S76D: RSET"
+		SAPL(0)
+		SKBL(0)
+#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+			SKBC(0xFFFFFF)
+#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+	}
+
+	Method (INIT, 0, Serialized) {
+		Debug = "S76D: INIT"
+		RSET()
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			// Set flags to use software control
+			^^PCI0.LPCB.EC0.ECOS = 2
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+
+	Method (FINI, 0, Serialized) {
+		Debug = "S76D: FINI"
+		RSET()
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			// Set flags to use hardware control
+			^^PCI0.LPCB.EC0.ECOS = 1
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+
+	// Get Airplane LED
+	Method (GAPL, 0, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
+				Return (1)
+			}
+		}
+		Return (0)
+	}
+
+	// Set Airplane LED
+	Method (SAPL, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0) {
+				^^PCI0.LPCB.EC0.AIRP |= 0x40
+			} Else {
+				^^PCI0.LPCB.EC0.AIRP &= 0xBF
+			}
+		}
+	}
+
+#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+	// Set KB LED Brightness
+	Method (SKBL, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 6
+			^^PCI0.LPCB.EC0.FBUF = Arg0
+			^^PCI0.LPCB.EC0.FBF1 = 0
+			^^PCI0.LPCB.EC0.FBF2 = Arg0
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
+
+	// Set Keyboard Color
+	Method (SKBC, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 0x3
+			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
+			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
+			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Return (Arg0)
+		} Else {
+			Return (0)
+		}
+	}
+#else // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+	// Get KB LED
+	Method (GKBL, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = One
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+			^^PCI0.LPCB.EC0.FCMD = Zero
+		}
+		Return (Local0)
+	}
+
+	// Set KB Led
+	Method (SKBL, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = Zero
+			^^PCI0.LPCB.EC0.FBUF = Arg0
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
+#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+}

src/ec/system76/ec/system76_ec.c

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <console/system76_ec.h>
+#include <timer.h>
+
+#define SYSTEM76_EC_BASE 0x0E00
+
+static inline uint8_t system76_ec_read(uint8_t addr)
+{
+	return inb(SYSTEM76_EC_BASE + (uint16_t)addr);
+}
+
+static inline void system76_ec_write(uint8_t addr, uint8_t data)
+{
+	outb(data, SYSTEM76_EC_BASE + (uint16_t)addr);
+}
+
+void system76_ec_init(void)
+{
+	// Clear entire command region
+	for (int i = 0; i < 256; i++)
+		system76_ec_write((uint8_t)i, 0);
+}
+
+void system76_ec_flush(void)
+{
+	// Send command
+	system76_ec_write(0, 4);
+
+	// Wait for command completion, for up to 10 milliseconds
+	wait_us(10000, system76_ec_read(0) == 0);
+
+	// Clear length
+	system76_ec_write(3, 0);
+}
+
+void system76_ec_print(uint8_t byte)
+{
+	// Read length
+	uint8_t len = system76_ec_read(3);
+	// Write data at offset
+	system76_ec_write(len + 4, byte);
+	// Update length
+	system76_ec_write(3, len + 1);
+
+	// If we hit the end of the buffer, or were given a newline, flush
+	if (byte == '\n' || len >= 128)
+		system76_ec_flush();
+}

src/include/console/system76_ec.h

@@ -0,0 +1,35 @@
+#ifndef CONSOLE_SYSTEM76_EC_H
+#define CONSOLE_SYSTEM76_EC_H 1
+
+#include <stddef.h>
+#include <stdint.h>
+
+void system76_ec_init(void);
+void system76_ec_flush(void);
+void system76_ec_print(uint8_t byte);
+
+#define __CONSOLE_SYSTEM76_EC_ENABLE__	(CONFIG(CONSOLE_SYSTEM76_EC) && \
+	(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE \
+	 || ENV_SEPARATE_VERSTAGE || ENV_POSTCAR \
+	 || (ENV_SMM && CONFIG(DEBUG_SMI))))
+
+#if __CONSOLE_SYSTEM76_EC_ENABLE__
+static inline void __system76_ec_init(void)
+{
+	system76_ec_init();
+}
+static inline void __system76_ec_tx_flush(void)
+{
+	system76_ec_flush();
+}
+static inline void __system76_ec_tx_byte(unsigned char byte)
+{
+	system76_ec_print(byte);
+}
+#else
+static inline void __system76_ec_init(void) {}
+static inline void __system76_ec_tx_flush(void) {}
+static inline void __system76_ec_tx_byte(unsigned char byte) {}
+#endif
+
+#endif

src/mainboard/system76/addw2/Kconfig

@@ -0,0 +1,96 @@
+if BOARD_SYSTEM76_ADDW2
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/addw2"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "addw2"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Adder WS"
+
+config MAINBOARD_VERSION
+	string
+	default "addw2"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1558
+
+config SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x65e1
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 16
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9bc4.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9bc4"
+
+config FSP_M_XIP
+	bool
+	default y
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/addw2/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ADDW2
+	bool "addw2"

src/mainboard/system76/addw2/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/addw2/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/addw2/acpi/mainboard.asl

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/addw2/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/addw2/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: addw2
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/addw2/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/addw2/devicetree.cb

@@ -0,0 +1,330 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Enable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C and Thunderbolt
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+	register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "0"
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "1"
+	register "PchHdaAudioLinkDmic1" = "1"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+	register "usb3_ports[6]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock  (NVIDIA GPU)
+	register "PcieClkSrcUsage[8]" = "0x40"
+
+	# PCI Express root port #9 x4, Clock 9 (SSD1)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[9]" = "8"
+
+	# PCI Express root port #14 x1, Clock 5 (GLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[5]" = "13"
+
+	# PCI Express root port #15 x1, Clock 7 (Card Reader)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[7]" = "14"
+
+	# PCI Express root port #16 x1, Clock 6 (WLAN)
+	register "PcieRpEnable[15]" = "1"
+	register "PcieRpLtrEnable[15]" = "1"
+	register "PcieClkSrcUsage[6]" = "15"
+
+	# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
+	register "PcieRpEnable[16]" = "1"
+	register "PcieRpLtrEnable[16]" = "1"
+	register "PcieRpHotPlug[16]" = "1"
+	register "PcieClkSrcUsage[0]" = "16"
+
+	# PCI Express root port #21 x4, Clock 10 (SSD2)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[10]" = "20"
+
+    # Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A14_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on  end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on  end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 on  end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on
+			chip drivers/i2c/tas5825m
+				device i2c 4e on end # (8bit address: 0x9c)
+			end # tas5825m
+		end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/addw2/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/addw2/gpio.h

@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_K21
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD7, NONE, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+		_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
+		PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A0, NONE, DEEP),
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+		PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT#
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
+		PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000),
+		PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+		PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
+		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CR_CLKREQ#
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+		PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
+		PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
+		PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
+		PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, DEEP), // TBT_RTD3_PWR_EN_R
+		PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST#
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J3, NONE, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000),
+		PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_K16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K23, NONE, DEEP),
+};
+
+#endif
+
+#endif

src/mainboard/system76/addw2/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865e1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/addw2/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/addw2/romstage.c

@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 75, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+ 	.rcomp_targets = { 50, 25, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd) {
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/cml-u/Kconfig

@@ -0,0 +1,104 @@
+if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP6
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select USE_OPTION_TABLE
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/cml-u"
+
+config VARIANT_DIR
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1558
+
+config SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x1403 if BOARD_SYSTEM76_GALP4
+	default 0x1404 if BOARD_SYSTEM76_DARP6
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 8
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9b41.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9b41"
+
+config PXE_ROM_ID
+	string
+	default "10ec,8168"
+
+config FSP_M_XIP
+	bool
+	default y
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/cml-u/Kconfig.name

@@ -0,0 +1,5 @@
+config BOARD_SYSTEM76_GALP4
+	bool "galp4"
+
+config BOARD_SYSTEM76_DARP6
+	bool "darp6"

src/mainboard/system76/cml-u/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/cml-u/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_D9 SCI
+Method (_L29, 0, Serialized) {
+	Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x50 /* GPP_E16 */
+#define EC_GPE_SWI 0x29 /* GPP_D9 */
+
+#if defined(CONFIG_BOARD_SYSTEM76_DARP6)
+	#define EC_COLOR_KEYBOARD 1
+#elif defined(CONFIG_BOARD_SYSTEM76_GALP4)
+	#define EC_COLOR_KEYBOARD 0
+#else
+	#error Unknown Mainboard
+#endif
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}
+
+#include "tbt.asl"

src/mainboard/system76/cml-u/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/cml-u/acpi/tbt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// See https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
+Scope(\_SB.PCI0.RP05) {
+    Method(_DSD, 0, NotSerialized) {
+        Return (Package(4) {
+            // https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports#identifying-pcie-root-ports-supporting-hot-plug-in-d3
+            ToUUID("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
+            Package(1) {
+                Package(2) {
+                    "HotPlugSupportInD3",
+                    1
+                }
+            },
+            // https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports#identifying-externally-exposed-pcie-root-ports
+            ToUUID("efcc06cc-73ac-4bc3-bff0-76143807c389"),
+            Package(2) {
+                Package(2) {
+                    "ExternalFacingPort",
+                    1
+                },
+                Package(2) {
+                    "UID",
+                    0
+                }
+            }
+        })
+    }
+}

src/mainboard/system76/cml-u/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: cml-u
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/cml-u/bootblock.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/cml-u/cmos.default

@@ -0,0 +1 @@
+DisplayPort_Output=Mini_DisplayPort

src/mainboard/system76/cml-u/cmos.layout

@@ -0,0 +1,33 @@
+#*****************************************************************************
+#
+#  This file is part of the coreboot project.
+#
+#  Copyright (C) 2019 System76
+#
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; version 2 of the License.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+#start  length  type    id      name
+0       384     r       0       reserved_memory
+384     1       e       1       DisplayPort_Output
+984     16      h       0       check_sum
+
+enumerations
+
+#ID     value   text
+1       0       Mini_DisplayPort
+1       1       USB-C
+
+checksums
+
+#checksum   start   end     location
+checksum    384     983     984

src/mainboard/system76/cml-u/devicetree.cb

@@ -0,0 +1,271 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Enable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 30,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "0"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "0"
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "1"
+	register "PchHdaAudioLinkDmic1" = "1"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"		# 3G / LTE
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C port 3
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# USB Board port 4
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"			# Finger print
+	register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"     # Camera
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"			# T17, T18
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[13]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"			# NC
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" 	# Type-A port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# 4G
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type C port 3
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# USB Board port 4
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"				# Used by TBT
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"				# Used by TBT
+	register "usb3_ports[6]" = "USB3_PORT_EMPTY"				# NC
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"				# NC
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"				# NC
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"				# NC
+
+	# PCI Express Root port #5 x4, Clock 4 (TBT)
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpLtrEnable[4]" = "1"
+	register "PcieRpHotPlug[4]" = "1"
+	register "PcieClkSrcUsage[4]" = "4"
+	register "PcieClkSrcClkReq[4]" = "4"
+
+	# PCI Express Root port #9 x1, Clock 3 (LAN)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[3]" = "8"
+	register "PcieClkSrcClkReq[3]" = "3"
+
+	# PCI Express Root port #10 x1, Clock 2 (WLAN)
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpLtrEnable[9]" = "0"
+	register "PcieClkSrcUsage[2]" = "9"
+	register "PcieClkSrcClkReq[2]" = "2"
+
+	# PCI Express Root port #13 x4, Clock 5 (NVMe)
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpLtrEnable[12]" = "1"
+	register "PcieClkSrcUsage[5]" = "12"
+	register "PcieClkSrcClkReq[5]" = "5"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3"		# 50ms
+	register "PchPmSlpS4MinAssert" = "1"		# 1s
+	register "PchPmSlpSusMinAssert" = "2"		# 500ms
+	register "PchPmSlpAMinAssert" = "4"		# 2s
+
+	# Thermal
+	register "tcc_offset" = "12"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_C"
+	register "gpe0_dw1" = "PMC_GPP_D"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on  end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/cml-u/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/cml-u/gpio.h

@@ -0,0 +1,534 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+#define PAD_CFG_NC(pad) PAD_NC(pad, NONE)
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_C22),
+		// NC
+		PAD_CFG_NC(GPP_C23),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+// GPD
+	// Power Management
+		// PM_BATLOW#
+		PAD_CFG_NC(GPD0),
+		// AC_PRESENT
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPD2),
+		// PWR_BTN#
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		// SUSB#_PCH
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		// SUSC#_PCH
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		// SLP_A#
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_CFG_NC(GPD7),
+
+	// Clock Signals
+		// SUS_CLK
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+
+	// Power Management
+		// GPD9_RTD3
+		PAD_CFG_NC(GPD9),
+		// NC
+		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPD11),
+
+// GPP_A
+	// LPC
+		// SB_KBCRST#
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		// LPC_AD0
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		// LPC_AD1
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		// LPC_AD2
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		// LPC_AD3
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		// LPC_FRAME#
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		// SERIRQ with pull up
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+
+	// GSPI0
+		// TPM_PIRQ#
+		PAD_CFG_NC(GPP_A7),
+
+	// LPC
+		// PM_CLKRUN# with pull-up
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		// PCLK_KBC
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+
+	// GSPI1
+		// NC
+		PAD_CFG_NC(GPP_A11),
+
+	// ISH_GP
+		// PCH_GPP_A12
+		PAD_CFG_NC(GPP_A12),
+
+	// Power Management
+		// SUSWARN#
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+
+	// LPC
+		// NC
+		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+
+	// Power Management
+		// SUS_PWR_ACK
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+
+	// SD
+		// NC
+		PAD_CFG_NC(GPP_A16),
+		// LIGHT_KB_DET#
+		PAD_CFG_NC(GPP_A17),
+
+	// ISH_GP
+		// NC
+		PAD_CFG_NC(GPP_A18),
+		// SATA_PWR_EN
+		PAD_CFG_GPO(GPP_A19, 1, DEEP),
+		// NC
+		PAD_CFG_NC(GPP_A20),
+		// NC
+		PAD_CFG_NC(GPP_A21),
+		// PS8338B_SW
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		// PS8338B_PCH
+		PAD_CFG_NC(GPP_A23),
+
+// GPP_B
+	// Power
+		// CORE_VID0
+		PAD_CFG_NC(GPP_B0),
+		// CORE_VID1
+		PAD_CFG_NC(GPP_B1),
+
+	// Power Management
+		// CNVI_WAKE#
+		PAD_CFG_NC(GPP_B2),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_NC(GPP_B3),
+		// NC
+		PAD_CFG_NC(GPP_B4),
+
+	// Clock Signals
+		// NC
+		PAD_CFG_NC(GPP_B5),
+		// NC
+		PAD_CFG_NC(GPP_B6),
+		// WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+		// LAN_CLKREQ#
+		PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+		// TBT_CLKREQ#
+		PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+		// SSD_CLKREQ#
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+
+	// Power Management
+		// EXT_PWR_GATE#
+		PAD_CFG_NC(GPP_B11),
+		// SLP_S0#
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		// PLT_RST#
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	// SPKR
+		// PCH_SPKR
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+
+	// GSPI0
+		// NC
+		PAD_CFG_NC(GPP_B15),
+		// PCH_GPP_B16
+		PAD_CFG_NC(GPP_B16),
+		// PCH_GPP_B17
+		PAD_CFG_NC(GPP_B17),
+		// PCH_GPP_B18 - strap for disabling no reboot mode
+		PAD_CFG_NC(GPP_B18),
+
+	// GSPI1
+		// NC
+		PAD_CFG_NC(GPP_B19),
+		// NC
+		PAD_CFG_NC(GPP_B20),
+		// NC
+		PAD_CFG_NC(GPP_B21),
+		// PCH_GPP_B22
+		PAD_CFG_NC(GPP_B22),
+
+	// SMBUS
+		// NC
+		PAD_CFG_NC(GPP_B23),
+
+// GPP_C
+	// SMBUS
+		// SMB_CLK_DDR
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		// SMB_DAT_DDR
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		// PCH_GPP_C2 with pull-up
+		PAD_CFG_NC(GPP_C2),
+		// NC
+		PAD_CFG_NC(GPP_C3),
+		// NC
+		PAD_CFG_NC(GPP_C4),
+		// NC
+		PAD_CFG_NC(GPP_C5),
+		// LAN_WAKEUP#
+		PAD_CFG_NC(GPP_C6),
+		// NC
+		PAD_CFG_NC(GPP_C7),
+
+	// UART0
+		// NC
+		PAD_CFG_NC(GPP_C8),
+		// TBCIO_PLUG_EVENT
+		_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
+		// TBT_FRC_PWR
+		PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
+		// NC
+		PAD_CFG_NC(GPP_C11),
+
+	// UART1
+		// GPP_C12_RTD3
+		PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
+		// SSD_PWR_DN#
+		PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
+		// TBTA_HRESET
+		PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
+		// TBT_PERST_N
+		PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
+
+	// I2C
+		// T_SDA
+		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+		// T_SCL
+		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_C18),
+		// SWI
+		PAD_CFG_NC(GPP_C19),
+
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_C22),
+		// TP_ATTN#
+		PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
+
+// GPP_D
+	// SPI1
+		// NC
+		PAD_CFG_NC(GPP_D0),
+		// NC
+		PAD_CFG_NC(GPP_D1),
+		// NC
+		PAD_CFG_NC(GPP_D2),
+		// NC
+		PAD_CFG_NC(GPP_D3),
+
+	// IMGCLKOUT
+		// NC
+		PAD_CFG_NC(GPP_D4),
+
+	// I2C
+		// NC
+		PAD_CFG_NC(GPP_D5),
+		// NC
+		PAD_CFG_NC(GPP_D6),
+		// NC
+		PAD_CFG_NC(GPP_D7),
+		// SB_BLON
+		PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
+
+	// GSPI2
+		// SWI#
+		_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
+		// NC
+		PAD_CFG_NC(GPP_D10),
+		// RTD3_PCIE_WAKE#
+		_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
+		// PCH_GPP_D12
+		PAD_CFG_NC(GPP_D12),
+
+	// UART0
+		// NC
+		PAD_CFG_NC(GPP_D13),
+		// NC
+		PAD_CFG_NC(GPP_D14),
+		// NC
+		PAD_CFG_NC(GPP_D15),
+		// RTD3_3G_PW R_EN
+		PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
+
+	// DMIC
+		// NC
+		PAD_CFG_NC(GPP_D17),
+		// NC
+		PAD_CFG_NC(GPP_D18),
+		// GPPC_DMIC_CLK
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		// GPPC_DMIC_DATA
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	// SPI1
+		// TPM_DET#
+		PAD_CFG_NC(GPP_D21),
+		// TPM_TCM_Detect
+		PAD_CFG_NC(GPP_D22),
+
+	// I2S
+		// NC
+		PAD_CFG_NC(GPP_D23),
+
+// GPP_E
+	// SATA
+		// PCH_GPP_E0 with pull-up
+		PAD_CFG_NC(GPP_E0),
+		// SATA_ODD_PRSNT#
+		PAD_CFG_NC(GPP_E1),
+		// SATAGP2
+		PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_NC(GPP_E3),
+
+	// DEVSLP
+		// NC
+		PAD_CFG_NC(GPP_E4),
+		// NC
+		PAD_CFG_NC(GPP_E5),
+		// DEVSLP2
+		PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_NC(GPP_E7),
+
+	// SATA
+		// PCH_SATAHDD_LED#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	// USB2
+		// GP_BSSB_CLK
+		PAD_CFG_NC(GPP_E9),
+		// GPP_E10
+		PAD_CFG_NC(GPP_E10),
+		// GPP_E11
+		PAD_CFG_NC(GPP_E11),
+		// USB_OC#78
+		PAD_CFG_NC(GPP_E12),
+
+	// Display Signals
+		// MUX_HPD
+		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+		// HDMI_HPD
+		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+		// SMI#
+		_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
+		// SCI#
+		_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
+		// EDP_HPD
+		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+		// MDP_CTRLCLK
+		PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+		// MDP_CTRLDATA
+		PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+		// HDMI_CTRLCLK
+		PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+		// HDMI_CTRLDATA
+		PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_E22),
+		// NC
+		PAD_CFG_NC(GPP_E23),
+
+// GPP_F
+	// CNVI
+		// CNVI_GNSS_PA_BLANKING
+		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_CFG_NC(GPP_F1),
+		// NC
+		PAD_CFG_NC(GPP_F2),
+		// NC
+		PAD_CFG_NC(GPP_F3),
+
+	// CNVI
+		// CNVI_BRI_DT
+		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+		// CNVI_BRI_RSP
+		PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+		// CNVI_RGI_DT
+		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+		// CNVI_RGI_RSP
+		PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+		// CNVI_MFUART2_RXD
+		PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+		// CNVI_MFUART2_TXD
+		PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_CFG_NC(GPP_F10),
+
+	// EMMC
+		// NC
+		PAD_CFG_NC(GPP_F11),
+		// NC
+		PAD_CFG_NC(GPP_F12),
+		// NC
+		PAD_CFG_NC(GPP_F13),
+		// NC
+		PAD_CFG_NC(GPP_F14),
+		// NC
+		PAD_CFG_NC(GPP_F15),
+		// NC
+		PAD_CFG_NC(GPP_F16),
+		// NC
+		PAD_CFG_NC(GPP_F17),
+		// NC
+		PAD_CFG_NC(GPP_F18),
+		// NC
+		PAD_CFG_NC(GPP_F19),
+		// NC
+		PAD_CFG_NC(GPP_F20),
+		// NC
+		PAD_CFG_NC(GPP_F21),
+		// NC
+		PAD_CFG_NC(GPP_F22),
+
+	// A4WP
+		// A4WP_PRESENT
+		PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
+
+// GPP_G
+	// SD
+		// EDP_DET
+		PAD_CFG_NC(GPP_G0),
+		// NC
+		PAD_CFG_NC(GPP_G1),
+		// NC
+		PAD_CFG_NC(GPP_G2),
+		// ASM1543_I_SEL0
+		PAD_CFG_NC(GPP_G3),
+		// ASM1543_I_SEL1
+		PAD_CFG_NC(GPP_G4),
+		// BOARD_ID
+		PAD_CFG_NC(GPP_G5),
+		// NC
+		PAD_CFG_NC(GPP_G6),
+		// TBT_Detect
+		PAD_CFG_NC(GPP_G7),
+
+// GPP_H
+	// CNVI
+		// NC
+		PAD_CFG_NC(GPP_H0),
+		// CNVI_RST#
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
+		// CNVI_CLKREQ
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+		// NC
+		PAD_CFG_NC(GPP_H3),
+
+	// I2C
+		// T23
+		PAD_CFG_NC(GPP_H4),
+		// T22
+		PAD_CFG_NC(GPP_H5),
+		// NC
+		PAD_CFG_NC(GPP_H6),
+		// NC
+		PAD_CFG_NC(GPP_H7),
+		// NC
+		PAD_CFG_NC(GPP_H8),
+		// NC
+		PAD_CFG_NC(GPP_H9),
+
+	// I2C
+		// NC
+		PAD_CFG_NC(GPP_H10),
+		// NC
+		PAD_CFG_NC(GPP_H11),
+
+	// PCIE
+		// NC
+		PAD_CFG_NC(GPP_H12),
+		// NC
+		PAD_CFG_NC(GPP_H13),
+		// G_INT1
+		PAD_CFG_NC(GPP_H14),
+		// NC
+		PAD_CFG_NC(GPP_H15),
+
+	// Display Signals
+		// NC
+		PAD_CFG_NC(GPP_H16),
+		// NC
+		PAD_CFG_NC(GPP_H17),
+
+	// CPU Power
+		// CPU_C10_GATE#
+		PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	// TIMESYNC
+		// NC
+		PAD_CFG_NC(GPP_H19),
+
+	// IMGCLKOUT
+		// NC
+		PAD_CFG_NC(GPP_H20),
+
+	// GPIO
+		// GPPC_H21
+		PAD_CFG_NC(GPP_H21),
+		// TBT_RTD3_PWR_EN_R
+		PAD_NC(GPP_H22, NONE),
+		// NC, WIGIG_PEWAKE
+		PAD_CFG_NC(GPP_H23),
+};
+
+#endif
+
+#endif

src/mainboard/system76/cml-u/ramstage.c

@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <string.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <option.h>
+#include <pc80/keyboard.h>
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static u8 superio_read(u8 reg) {
+	outb(reg, 0x2E);
+	return inb(0x2F);
+}
+
+static void superio_write(u8 reg, u8 value) {
+	outb(reg, 0x2E);
+	outb(value, 0x2F);
+}
+
+static u8 d2_read(u8 reg) {
+	superio_write(0x2E, reg);
+	return superio_read(0x2F);
+}
+
+static void d2_write(u8 reg, u8 value) {
+	superio_write(0x2E, reg);
+	superio_write(0x2F, value);
+}
+
+static u8 i2ec_read(u16 addr) {
+	d2_write(0x11, (u8)(addr >> 8));
+	d2_write(0x10, (u8)addr);
+	return d2_read(0x12);
+}
+
+static void i2ec_write(u16 addr, u8 value) {
+	d2_write(0x11, (u8)(addr >> 8));
+	d2_write(0x10, (u8)addr);
+	d2_write(0x12, value);
+}
+
+static void mainboard_init(struct device *dev) {
+	printk(BIOS_INFO, "system76: keyboard init\n");
+	pc_keyboard_init(NO_AUX_DEVICE);
+
+	printk(BIOS_INFO, "system76: EC init\n");
+
+	// Black magic - force enable camera toggle
+	u16 addr = 0x01CA;
+	u8 value = i2ec_read(addr);
+	if ((value & (1 << 2)) == 0) {
+		printk(BIOS_INFO, "system76: enabling camera toggle\n");
+		i2ec_write(addr, value | (1 << 2));
+	} else {
+		printk(BIOS_INFO, "system76: camera toggle already enabled\n");
+	}
+}
+
+static bool mainboard_pcie_hotplug(int port_number) {
+	printk(BIOS_DEBUG, "system76: pcie_hotplug(%d)\n", port_number);
+	/* RP01 */
+	return port_number == 0;
+}
+
+static void pcie_hotplug_generator(int port_number)
+{
+	int port;
+	int have_hotplug = 0;
+
+	for (port = 0; port < port_number; port++) {
+		if (mainboard_pcie_hotplug(port)) {
+			have_hotplug = 1;
+		}
+	}
+
+	if (!have_hotplug) {
+		return;
+	}
+
+	for (port = 0; port < port_number; port++) {
+		if (mainboard_pcie_hotplug(port)) {
+			char scope_name[] = "\\_SB.PCI0.RP0x";
+			scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port;
+			acpigen_write_scope(scope_name);
+
+			/*
+			  Device (SLOT)
+			  {
+				Name (_ADR, 0x00)
+				Method (_RMV, 0, NotSerialized)
+				{
+					Return (0x01)
+				}
+			  }
+			*/
+
+			acpigen_write_device("SLOT");
+
+			acpigen_write_name_byte("_ADR", 0x00);
+
+			acpigen_write_method("_RMV", 0);
+			/* ReturnOp  */
+			acpigen_emit_byte (0xa4);
+			/* One  */
+			acpigen_emit_byte (0x01);
+			acpigen_pop_len();
+			acpigen_pop_len();
+			acpigen_pop_len();
+		}
+	}
+
+	/* Method (_L01, 0, NotSerialized)
+	{
+		If (\_SB.PCI0.RP04.HPCS)
+		{
+			Sleep (100)
+			Store (0x01, \_SB.PCI0.RP04.HPCS)
+			If (\_SB.PCI0.RP04.PDC)
+			{
+				Store (0x01, \_SB.PCI0.RP04.PDC)
+				Notify (\_SB.PCI0.RP04, 0x00)
+			}
+		}
+	}
+
+	*/
+	acpigen_write_scope("\\_GPE");
+	acpigen_write_method("_L01", 0);
+	for (port = 0; port < port_number; port++) {
+		if (mainboard_pcie_hotplug(port)) {
+			char reg_name[] = "\\_SB.PCI0.RP0x.HPCS";
+			reg_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port;
+			acpigen_emit_byte(0xa0); /* IfOp. */
+			acpigen_write_len_f();
+			acpigen_emit_namestring(reg_name);
+
+			/* Sleep (100) */
+			acpigen_emit_byte(0x5b); /* SleepOp. */
+			acpigen_emit_byte(0x22);
+			acpigen_write_byte(100);
+
+			/* Store (0x01, \_SB.PCI0.RP04.HPCS) */
+			acpigen_emit_byte(0x70);
+			acpigen_emit_byte(0x01);
+			acpigen_emit_namestring(reg_name);
+
+			memcpy(reg_name + sizeof("\\_SB.PCI0.RP0x.") - 1, "PDC", 4);
+
+			/* If (\_SB.PCI0.RP04.PDC) */
+			acpigen_emit_byte(0xa0); /* IfOp. */
+			acpigen_write_len_f();
+			acpigen_emit_namestring(reg_name);
+
+			/* Store (0x01, \_SB.PCI0.RP04.PDC) */
+			acpigen_emit_byte(0x70);
+			acpigen_emit_byte(0x01);
+			acpigen_emit_namestring(reg_name);
+
+			reg_name[sizeof("\\_SB.PCI0.RP0x") - 1] = '\0';
+
+			/* Notify(\_SB.PCI0.RP04, 0x00) */
+			acpigen_emit_byte(0x86);
+			acpigen_emit_namestring(reg_name);
+			acpigen_emit_byte(0x00);
+			acpigen_pop_len();
+			acpigen_pop_len();
+		}
+	}
+	acpigen_pop_len();
+	acpigen_pop_len();
+}
+
+static void fill_ssdt(const struct device *device) {
+	printk(BIOS_INFO, "system76: fill_ssdt\n");
+	pcie_hotplug_generator(CONFIG_MAX_ROOT_PORTS);
+}
+
+static void mainboard_enable(struct device *dev) {
+	dev->ops->init = mainboard_init;
+	dev->ops->acpi_fill_ssdt = fill_ssdt;
+
+	// Configure pad for DisplayPort
+	uint32_t config = 0x44000200;
+
+	uint8_t nvram = 0;
+	if (get_option(&nvram, "DisplayPort_Output") == CB_SUCCESS) {
+		if (nvram) {
+			config |= 1;
+		}
+	}
+
+	if (nvram) {
+		printk(BIOS_INFO, "system76: DisplayPort_Output set to USB-C: 0x%x\n", config);
+	} else {
+		printk(BIOS_INFO, "system76: DisplayPort_Output set to Mini_DisplayPort: 0x%x\n", config);
+	}
+
+	struct pad_config displayport_gpio_table[] = {
+		/* PS8338B_SW */
+		_PAD_CFG_STRUCT(GPP_A22, config, 0x0),
+	};
+	gpio_configure_pads(displayport_gpio_table, ARRAY_SIZE(displayport_gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};

src/mainboard/system76/cml-u/romstage.c

@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 81, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/cml-u/variants/darp6/hda_verb.c

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581404, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581404),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11050),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x02451130),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/cml-u/variants/darp6/overridetree.cb

@@ -0,0 +1,14 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+	end
+end

src/mainboard/system76/cml-u/variants/galp4/hda_verb.c

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581403, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581403),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

@@ -0,0 +1,7 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		device pci 15.0 on
+			# I2C HID not supported on galp4
+		end # I2C #0
+	end
+end

src/mainboard/system76/gaze14/Kconfig

@@ -0,0 +1,100 @@
+if BOARD_SYSTEM76_GAZE14_1650_15 || BOARD_SYSTEM76_GAZE14_1650_17 || BOARD_SYSTEM76_GAZE14_1660TI_15 || BOARD_SYSTEM76_GAZE14_1660TI_17
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COFFEELAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/gaze14"
+
+config VARIANT_DIR
+	string
+	default "gaze14_1650_15" if BOARD_SYSTEM76_GAZE14_1650_15
+	default "gaze14_1650_17" if BOARD_SYSTEM76_GAZE14_1650_17
+	default "gaze14_1660ti_15" if BOARD_SYSTEM76_GAZE14_1660TI_15
+	default "gaze14_1660ti_17" if BOARD_SYSTEM76_GAZE14_1660TI_17
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Gazelle"
+
+config MAINBOARD_VERSION
+	string
+	default "gaze14"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1558
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x8560 if BOARD_SYSTEM76_GAZE14_1650_15
+	default 0x8561 if BOARD_SYSTEM76_GAZE14_1650_17
+	default 0x8550 if BOARD_SYSTEM76_GAZE14_1660TI_15
+	default 0x8551 if BOARD_SYSTEM76_GAZE14_1660TI_17
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 12
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+# config VGA_BIOS_FILE
+# 	string
+# 	default "pci8086,3ea0.rom"
+
+# config VGA_BIOS_ID
+# 	string
+# 	default "8086,3ea0"
+
+config FSP_M_XIP
+	bool
+	default y
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/gaze14/Kconfig.name

@@ -0,0 +1,11 @@
+config BOARD_SYSTEM76_GAZE14_1650_15
+	bool "gaze14 1650 15"
+
+config BOARD_SYSTEM76_GAZE14_1650_17
+	bool "gaze14 1650 17"
+
+config BOARD_SYSTEM76_GAZE14_1660TI_15
+	bool "gaze14 1660Ti 15"
+
+config BOARD_SYSTEM76_GAZE14_1660TI_17
+	bool "gaze14 1660Ti 17"

src/mainboard/system76/gaze14/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/system76/gaze14/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/gaze14/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/gaze14/acpi/mainboard.asl

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/gaze14/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/gaze14/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: gaze14
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/gaze14/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/gaze14/devicetree.cb

@@ -0,0 +1,318 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Enable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "1"
+	register "PchHdaAudioLinkDmic1" = "1"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+	register "PcieClkSrcUsage[8]" = "0x40"
+
+	# PCI Express root port #9 x4, Clock 10 (SSD)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[10]" = "8"
+
+	# PCI Express root port #14 x1, Clock 6 (WLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[6]" = "13"
+
+	# PCI Express root port #15 x1, Clock 5 (LAN)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[5]" = "14"
+
+	# PCI Express root port #21 x4, Clock 11 (SSD2)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[11]" = "20"
+
+    # Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 off end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on  end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/gaze14/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/gaze14/gpio.h

@@ -0,0 +1 @@
+#include <variant/gpio.h>

src/mainboard/system76/gaze14/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/gaze14/romstage.c

@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 75, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+ 	.rcomp_targets = { 50, 25, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd) {
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/gaze14/variants/gaze14_1650_15/hda_verb.c

@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC269VC */
+	0x10ec0269, /* Vendor ID */
+	0x15588560, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588560),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a1103f),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40f00001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/gaze14/variants/gaze14_1650_15/include/variant/gpio.h

@@ -0,0 +1,620 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_NC(GPP_C22, NONE),
+		// NC
+		PAD_NC(GPP_C23, NONE),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+// GPD
+	// Power Management
+		// NC
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		// AC_PRESENT
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		// PWR_BTN#
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		// SUSB#_PCH
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		// SUSC#_PCH
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000),
+
+	// GPIO
+		// NC
+		_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000),
+
+	// Power Management
+		// SUS_CLK_R
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPD9, NONE, PWROK),
+		// NC
+		PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+		// NC
+		PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK),
+
+// GPP_A
+	// LPC
+		// SB_KBCRST#
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		// LPC_AD0
+		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+		// LPC_AD1
+		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+		// LPC_AD2
+		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+		// LPC_AD3
+		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+		// LPC_FRAME#
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		// SERIRQ
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+		// PM_CLKRUN#
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		// PCLK_KBC
+		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+
+	// Power Management
+		// TODO: LAN_WAKEUP#
+		PAD_CFG_GPI(GPP_A11, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		// SUSWARN#
+		PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
+
+	// LPC
+		// NC
+		PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP),
+
+	// Power Management
+		// SUS_PWR_ACK
+		PAD_CFG_GPI(GPP_A15, NONE, DEEP),
+
+	// Clock Signals
+		// NC
+		PAD_NC(GPP_A16, NONE),
+
+	// ISH
+		// NC
+		PAD_NC(GPP_A17, NONE),
+		// SB_BLON
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_A19, NONE),
+		// NC
+		PAD_NC(GPP_A20, NONE),
+		// NC
+		PAD_NC(GPP_A21, NONE),
+		// SATA_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_A23, NONE),
+
+// GPP_B
+	// GSPI
+		// TODO: TPM_PIRQ#
+		PAD_CFG_GPI(GPP_B0, NONE, DEEP),
+		// NC
+		PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP),
+
+	// Power Management
+		// NC
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+		// TODO: EXTTS_SNI_DRV1
+		PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP),
+
+	// Clock Signals
+		// NC
+		PAD_CFG_GPI(GPP_B5, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B6, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B7, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B8, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B9, NONE, PLTRST),
+		// LAN_CLKREQ#
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+
+	// Audio
+		// TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
+		PAD_CFG_GPI(GPP_B11, UP_20K, DEEP),
+
+	// Power Management
+		// SLP_S0#
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		// PLT_RST#
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	// Audio
+		// PCH_SPKR
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+
+	// GSPI
+		// NC
+		PAD_NC(GPP_B15, NONE),
+		// NC
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		// LPSS_GSPI0_MOSI - strap for no reboot mode
+		PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+		// NC
+		PAD_NC(GPP_B19, NONE),
+		// NC
+		PAD_NC(GPP_B20, NONE),
+		// NC
+		PAD_NC(GPP_B21, NONE),
+		// LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
+		PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+
+	// SMBUS
+		// PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
+		PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
+
+// GPP_C
+	// SMBUS
+		// SMB_CLK
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		// SMB_DATA
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_C3, NONE),
+		// NC
+		PAD_NC(GPP_C4, NONE),
+		// NC
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+
+	// UART
+		// NC
+		PAD_NC(GPP_C8, NONE),
+		// TODO: CNVI_DET#
+		PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_C10, NONE),
+		// NC
+		PAD_NC(GPP_C11, NONE),
+		// NC
+		PAD_NC(GPP_C12, NONE),
+		// NC
+		PAD_NC(GPP_C13, NONE),
+		// NC
+		PAD_NC(GPP_C14, NONE),
+		// NC
+		PAD_NC(GPP_C15, NONE),
+
+	// I2C
+		// I2C_SCL_TP
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		// I2C_SDA_TP
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		// NC
+		PAD_NC(GPP_C18, NONE),
+		// NC
+		PAD_NC(GPP_C19, NONE),
+
+	// UART
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+
+// GPP_D
+	// SPI
+		// NC
+		PAD_NC(GPP_D0, NONE),
+		// NC
+		PAD_NC(GPP_D1, NONE),
+		// NC
+		PAD_NC(GPP_D2, NONE),
+		// NC
+		PAD_NC(GPP_D3, NONE),
+
+	// I2C
+		// NC
+		PAD_NC(GPP_D4, NONE),
+
+	// CNVI
+		// CNVI_RF_RST#
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		// XTAL_CLKREQ
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		// NC
+		PAD_NC(GPP_D7, NONE),
+		// NC
+		PAD_NC(GPP_D8, NONE),
+
+	// ISH
+		// NC
+		PAD_NC(GPP_D9, NONE),
+		// NC
+		PAD_NC(GPP_D10, NONE),
+		// NC
+		PAD_NC(GPP_D11, NONE),
+		// NC
+		PAD_NC(GPP_D12, NONE),
+		// NC
+		PAD_NC(GPP_D13, NONE),
+		// NC
+		PAD_NC(GPP_D14, NONE),
+		// NC
+		PAD_NC(GPP_D15, NONE),
+		// NC
+		PAD_NC(GPP_D16, NONE),
+
+	// DMIC
+		// NC
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	// SPI
+		// NC
+		PAD_NC(GPP_D21, NONE),
+		// NC
+		PAD_NC(GPP_D22, NONE),
+
+	// ISH
+		// NC
+		PAD_NC(GPP_D23, NONE),
+
+// GPP_E
+	// SATA
+		// NC
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		// SATAGP1
+		PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+
+	// CPU Misc
+		// TODO: EXTTS_SNI_DRV0
+		_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000),
+
+	// SATA
+		// DEVSLP0
+		PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
+		// DEVSLP1
+		PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
+		// NC
+		PAD_NC(GPP_E6, NONE),
+
+	// CPU Misc
+		// TODO: TP_ATTN#
+		_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000),
+
+	// SATA
+		// SATA_LED#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	// USB2
+		// NC
+		PAD_NC(GPP_E9, NONE),
+		// NC
+		PAD_NC(GPP_E10, NONE),
+		// NC
+		PAD_NC(GPP_E11, NONE),
+		// NC
+		PAD_NC(GPP_E12, NONE),
+
+// GPP_F
+	// SATA
+		// NC
+		PAD_NC(GPP_F0, NONE),
+		// NC
+		PAD_NC(GPP_F1, NONE),
+		// NC
+		PAD_NC(GPP_F2, NONE),
+		// NC
+		PAD_NC(GPP_F3, NONE),
+		// NC
+		PAD_NC(GPP_F4, NONE),
+		// KBLED_DET
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		// LIGHT_KB_DET#
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_F7, NONE),
+		// NC
+		PAD_NC(GPP_F8, NONE),
+		// NC
+		PAD_NC(GPP_F9, NONE),
+		// BIOS_REC - strap for bios recovery enable
+		PAD_NC(GPP_F10, NONE),
+		// PCH_RSVD - unused strap
+		PAD_NC(GPP_F11, NONE),
+		// MFG_MODE - strap for manufacturing mode
+		PAD_NC(GPP_F12, NONE),
+		// TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
+		PAD_NC(GPP_F13, NONE),
+
+	// Power Management
+		// H_SKTOCC_N
+		PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
+
+	// USB2
+		// NC
+		PAD_NC(GPP_F15, NONE),
+		// NC
+		PAD_NC(GPP_F16, NONE),
+		// NC
+		PAD_NC(GPP_F17, NONE),
+		// NC
+		PAD_NC(GPP_F18, NONE),
+
+	// Display Signals
+		// NB_ENAVDD
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		// BLON
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+		// EDP_BRIGHTNESS
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		// TODO: DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST),
+		// TODO: DGPU_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
+
+// GPP_G
+	// SD
+		// BOARD_ID1
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+		// BOARD_ID2
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		// TPM_DET
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		// TODO: GPIO4_1V8_MAIN_EN_R
+		PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
+		// NC
+		PAD_NC(GPP_G4, NONE),
+		// NC
+		PAD_NC(GPP_G5, NONE),
+		// NC
+		PAD_NC(GPP_G6, NONE),
+		// NC
+		PAD_NC(GPP_G7, NONE),
+
+// GPP_H
+	// Clock Signals
+		// WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000),
+		// PEG_CLKREQ#
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000),
+		// SSD_CLKREQ#
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+		// SSD2_CLKREQ#
+		PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000),
+
+	// SMBUS
+		// NC
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		// GPP_H_12 - strap for ESPI flash sharing mode
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H17, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+
+	// ISH
+		// NC
+		PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+
+	// GPIO
+		// NC
+		PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+
+// GPP_I
+	// Display Signals
+		// NC
+		PAD_CFG_GPI(GPP_I0, NONE, DEEP),
+		// HDMI_HPD
+		PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
+		// NC
+		PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
+		// MDP_E_HPD
+		_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
+		// EDP_HPD
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_I5, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+		// HDMI_CTRLCLK
+		PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+		// HDMI_CTRLDATA
+		PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_I9, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+
+	// PCIE
+		// TODO: H_SKTOCC_N
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I12, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+
+// GPP_J
+	// CNVI
+		// CNVI_GNSS_PA_BLANKING
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+
+	// Power Management
+		// NC
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
+
+	// GPIO
+		// NC
+		PAD_NC(GPP_J2, NONE),
+		// NC
+		PAD_NC(GPP_J3, NONE),
+
+	// CNVI
+		// CNVI_BRI_DT
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		// CNVI_BRI_RSP
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		// CNVI_RGI_DT
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		// CNVI_RGI_RSP
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		// CNVI_MFUART2_RXD
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		// CNVI_MFUART2_TXD
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_NC(GPP_J10, NONE),
+
+	// A4WP
+		// NC
+		PAD_NC(GPP_J11, NONE),
+
+// GPP_K
+	// GPIO
+		// NC
+		PAD_NC(GPP_K0, NONE),
+		// NC
+		PAD_NC(GPP_K1, NONE),
+		// NC
+		PAD_NC(GPP_K2, NONE),
+		// SCI#
+		_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
+		// NC
+		PAD_NC(GPP_K4, NONE),
+		// NC
+		PAD_NC(GPP_K5, NONE),
+		// SWI#
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000),
+		// NC
+		PAD_NC(GPP_K7, NONE),
+		// SATA_M2_PWR_EN1
+		PAD_CFG_GPI(GPP_K8, NONE, DEEP),
+		// SATA_M2_PWR_EN2
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+
+	// GSX
+		// NC
+		PAD_NC(GPP_K12, NONE),
+		// NC
+		PAD_NC(GPP_K13, NONE),
+		// NC
+		PAD_NC(GPP_K14, NONE),
+		// NC
+		PAD_NC(GPP_K15, NONE),
+		// NC
+		PAD_NC(GPP_K16, NONE),
+
+	// GPIO
+		// NC
+		PAD_NC(GPP_K17, NONE),
+		// NC
+		PAD_NC(GPP_K18, NONE),
+		// SMI#
+		_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
+		// TODO: GPU_EVENT#
+		_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000),
+		// TODO: GC6_FB_EN_PCH
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		// TODO: DGPU_PWRGD_R
+		_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
+		// NC
+		PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1),
+};
+
+#endif
+
+#endif

src/mainboard/system76/gaze14/variants/gaze14_1650_17/hda_verb.c

@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC269VC */
+	0x10ec0269, /* Vendor ID */
+	0x15588561, /* Subsystem ID */
+	11, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588561),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a1103f),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40f00001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/gaze14/variants/gaze14_1650_17/include/variant/gpio.h

@@ -0,0 +1,620 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_NC(GPP_C22, NONE),
+		// NC
+		PAD_NC(GPP_C23, NONE),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+// GPD
+	// Power Management
+		// NC
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		// AC_PRESENT
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		// PWR_BTN#
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		// SUSB#_PCH
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		// SUSC#_PCH
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000),
+
+	// GPIO
+		// NC
+		_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000),
+
+	// Power Management
+		// SUS_CLK_R
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPD9, NONE, PWROK),
+		// NC
+		PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+		// NC
+		PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK),
+
+// GPP_A
+	// LPC
+		// SB_KBCRST#
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		// LPC_AD0
+		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+		// LPC_AD1
+		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+		// LPC_AD2
+		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+		// LPC_AD3
+		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+		// LPC_FRAME#
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		// SERIRQ
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+		// PM_CLKRUN#
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		// PCLK_KBC
+		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+
+	// Power Management
+		// TODO: LAN_WAKEUP#
+		PAD_CFG_GPI(GPP_A11, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		// SUSWARN#
+		PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
+
+	// LPC
+		// NC
+		PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP),
+
+	// Power Management
+		// SUS_PWR_ACK
+		PAD_CFG_GPI(GPP_A15, NONE, DEEP),
+
+	// Clock Signals
+		// NC
+		PAD_NC(GPP_A16, NONE),
+
+	// ISH
+		// NC
+		PAD_NC(GPP_A17, NONE),
+		// SB_BLON
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_A19, NONE),
+		// NC
+		PAD_NC(GPP_A20, NONE),
+		// NC
+		PAD_NC(GPP_A21, NONE),
+		// SATA_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_A23, NONE),
+
+// GPP_B
+	// GSPI
+		// TODO: TPM_PIRQ#
+		PAD_CFG_GPI(GPP_B0, NONE, DEEP),
+		// NC
+		PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP),
+
+	// Power Management
+		// NC
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+		// TODO: EXTTS_SNI_DRV1
+		PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP),
+
+	// Clock Signals
+		// NC
+		PAD_CFG_GPI(GPP_B5, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B6, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B7, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B8, NONE, PLTRST),
+		// NC
+		PAD_CFG_GPI(GPP_B9, NONE, PLTRST),
+		// LAN_CLKREQ#
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+
+	// Audio
+		// TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
+		PAD_CFG_GPI(GPP_B11, UP_20K, DEEP),
+
+	// Power Management
+		// SLP_S0#
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		// PLT_RST#
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	// Audio
+		// PCH_SPKR
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+
+	// GSPI
+		// NC
+		PAD_NC(GPP_B15, NONE),
+		// NC
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		// LPSS_GSPI0_MOSI - strap for no reboot mode
+		PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+		// NC
+		PAD_NC(GPP_B19, NONE),
+		// NC
+		PAD_NC(GPP_B20, NONE),
+		// NC
+		PAD_NC(GPP_B21, NONE),
+		// LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
+		PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+
+	// SMBUS
+		// PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
+		PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
+
+// GPP_C
+	// SMBUS
+		// SMB_CLK
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		// SMB_DATA
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_C3, NONE),
+		// NC
+		PAD_NC(GPP_C4, NONE),
+		// NC
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+
+	// UART
+		// NC
+		PAD_NC(GPP_C8, NONE),
+		// TODO: CNVI_DET#
+		PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_C10, NONE),
+		// NC
+		PAD_NC(GPP_C11, NONE),
+		// NC
+		PAD_NC(GPP_C12, NONE),
+		// NC
+		PAD_NC(GPP_C13, NONE),
+		// NC
+		PAD_NC(GPP_C14, NONE),
+		// NC
+		PAD_NC(GPP_C15, NONE),
+
+	// I2C
+		// I2C_SCL_TP
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		// I2C_SDA_TP
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		// NC
+		PAD_NC(GPP_C18, NONE),
+		// NC
+		PAD_NC(GPP_C19, NONE),
+
+	// UART
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+
+// GPP_D
+	// SPI
+		// NC
+		PAD_NC(GPP_D0, NONE),
+		// NC
+		PAD_NC(GPP_D1, NONE),
+		// NC
+		PAD_NC(GPP_D2, NONE),
+		// NC
+		PAD_NC(GPP_D3, NONE),
+
+	// I2C
+		// NC
+		PAD_NC(GPP_D4, NONE),
+
+	// CNVI
+		// CNVI_RF_RST#
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		// XTAL_CLKREQ
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		// NC
+		PAD_NC(GPP_D7, NONE),
+		// NC
+		PAD_NC(GPP_D8, NONE),
+
+	// ISH
+		// NC
+		PAD_NC(GPP_D9, NONE),
+		// NC
+		PAD_NC(GPP_D10, NONE),
+		// NC
+		PAD_NC(GPP_D11, NONE),
+		// NC
+		PAD_NC(GPP_D12, NONE),
+		// NC
+		PAD_NC(GPP_D13, NONE),
+		// NC
+		PAD_NC(GPP_D14, NONE),
+		// NC
+		PAD_NC(GPP_D15, NONE),
+		// NC
+		PAD_NC(GPP_D16, NONE),
+
+	// DMIC
+		// NC
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	// SPI
+		// NC
+		PAD_NC(GPP_D21, NONE),
+		// NC
+		PAD_NC(GPP_D22, NONE),
+
+	// ISH
+		// NC
+		PAD_NC(GPP_D23, NONE),
+
+// GPP_E
+	// SATA
+		// NC
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		// SATAGP1
+		PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+
+	// CPU Misc
+		// TODO: EXTTS_SNI_DRV0
+		_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000),
+
+	// SATA
+		// DEVSLP0
+		PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
+		// DEVSLP1
+		PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
+		// NC
+		PAD_NC(GPP_E6, NONE),
+
+	// CPU Misc
+		// TODO: TP_ATTN#
+		_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000),
+
+	// SATA
+		// SATA_LED#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	// USB2
+		// NC
+		PAD_NC(GPP_E9, NONE),
+		// NC
+		PAD_NC(GPP_E10, NONE),
+		// NC
+		PAD_NC(GPP_E11, NONE),
+		// NC
+		PAD_NC(GPP_E12, NONE),
+
+// GPP_F
+	// SATA
+		// NC
+		PAD_NC(GPP_F0, NONE),
+		// NC
+		PAD_NC(GPP_F1, NONE),
+		// NC
+		PAD_NC(GPP_F2, NONE),
+		// NC
+		PAD_NC(GPP_F3, NONE),
+		// NC
+		PAD_NC(GPP_F4, NONE),
+		// KBLED_DET
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		// LIGHT_KB_DET#
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		// NC
+		PAD_NC(GPP_F7, NONE),
+		// NC
+		PAD_NC(GPP_F8, NONE),
+		// NC
+		PAD_NC(GPP_F9, NONE),
+		// BIOS_REC - strap for bios recovery enable
+		PAD_NC(GPP_F10, NONE),
+		// PCH_RSVD - unused strap
+		PAD_NC(GPP_F11, NONE),
+		// MFG_MODE - strap for manufacturing mode
+		PAD_NC(GPP_F12, NONE),
+		// TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
+		PAD_NC(GPP_F13, NONE),
+
+	// Power Management
+		// H_SKTOCC_N
+		PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
+
+	// USB2
+		// NC
+		PAD_NC(GPP_F15, NONE),
+		// NC
+		PAD_NC(GPP_F16, NONE),
+		// NC
+		PAD_NC(GPP_F17, NONE),
+		// NC
+		PAD_NC(GPP_F18, NONE),
+
+	// Display Signals
+		// NB_ENAVDD
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		// BLON
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+		// EDP_BRIGHTNESS
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		// TODO: DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST),
+		// TODO: DGPU_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
+
+// GPP_G
+	// SD
+		// BOARD_ID1
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+		// BOARD_ID2
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		// TPM_DET
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		// TODO: GPIO4_1V8_MAIN_EN_R
+		PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
+		// NC
+		PAD_NC(GPP_G4, NONE),
+		// NC
+		PAD_NC(GPP_G5, NONE),
+		// NC
+		PAD_NC(GPP_G6, NONE),
+		// NC
+		PAD_NC(GPP_G7, NONE),
+
+// GPP_H
+	// Clock Signals
+		// WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000),
+		// PEG_CLKREQ#
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000),
+		// SSD_CLKREQ#
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+		// SSD2_CLKREQ#
+		PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000),
+		// NC
+		_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000),
+
+	// SMBUS
+		// NC
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		// GPP_H_12 - strap for ESPI flash sharing mode
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H17, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+
+	// ISH
+		// NC
+		PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+
+	// GPIO
+		// NC
+		PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+
+// GPP_I
+	// Display Signals
+		// NC
+		PAD_CFG_GPI(GPP_I0, NONE, DEEP),
+		// HDMI_HPD
+		PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
+		// NC
+		PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
+		// MDP_E_HPD
+		_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
+		// EDP_HPD
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_I5, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+		// HDMI_CTRLCLK
+		PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+		// HDMI_CTRLDATA
+		PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_GPI(GPP_I9, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+
+	// PCIE
+		// TODO: H_SKTOCC_N
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I12, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+
+// GPP_J
+	// CNVI
+		// CNVI_GNSS_PA_BLANKING
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+
+	// Power Management
+		// NC
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
+
+	// GPIO
+		// NC
+		PAD_NC(GPP_J2, NONE),
+		// NC
+		PAD_NC(GPP_J3, NONE),
+
+	// CNVI
+		// CNVI_BRI_DT
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		// CNVI_BRI_RSP
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		// CNVI_RGI_DT
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		// CNVI_RGI_RSP
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		// CNVI_MFUART2_RXD
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		// CNVI_MFUART2_TXD
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_NC(GPP_J10, NONE),
+
+	// A4WP
+		// NC
+		PAD_NC(GPP_J11, NONE),
+
+// GPP_K
+	// GPIO
+		// NC
+		PAD_NC(GPP_K0, NONE),
+		// NC
+		PAD_NC(GPP_K1, NONE),
+		// NC
+		PAD_NC(GPP_K2, NONE),
+		// SCI#
+		_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
+		// NC
+		PAD_NC(GPP_K4, NONE),
+		// NC
+		PAD_NC(GPP_K5, NONE),
+		// SWI#
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000),
+		// NC
+		PAD_NC(GPP_K7, NONE),
+		// SATA_M2_PWR_EN1
+		PAD_CFG_GPI(GPP_K8, NONE, DEEP),
+		// SATA_M2_PWR_EN2
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		// NC
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+
+	// GSX
+		// NC
+		PAD_NC(GPP_K12, NONE),
+		// NC
+		PAD_NC(GPP_K13, NONE),
+		// NC
+		PAD_NC(GPP_K14, NONE),
+		// NC
+		PAD_NC(GPP_K15, NONE),
+		// NC
+		PAD_NC(GPP_K16, NONE),
+
+	// GPIO
+		// NC
+		PAD_NC(GPP_K17, NONE),
+		// NC
+		PAD_NC(GPP_K18, NONE),
+		// SMI#
+		_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
+		// TODO: GPU_EVENT#
+		_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000),
+		// TODO: GC6_FB_EN_PCH
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		// TODO: DGPU_PWRGD_R
+		_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
+		// NC
+		PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1),
+};
+
+#endif
+
+#endif

src/mainboard/system76/gaze14/variants/gaze14_1660ti_15/hda_verb.c

@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15588550, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588550),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/gaze14/variants/gaze14_1660ti_17/hda_verb.c

@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15588551, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588550),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/gaze15/Kconfig

@@ -0,0 +1,94 @@
+if BOARD_SYSTEM76_GAZE15
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/gaze15"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "gaze15"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Gazelle"
+
+config MAINBOARD_VERSION
+	string
+	default "gaze15"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1558
+
+config SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x8520
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 16
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9bc4.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9bc4"
+
+config FSP_M_XIP
+	bool
+	default y
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/gaze15/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_GAZE15
+	bool "gaze15"

src/mainboard/system76/gaze15/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c

src/mainboard/system76/gaze15/acpi/backlight.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0) {
+       Name (BRIG, Package (22) {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/gaze15/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/gaze15/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/gaze15/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: gaze15
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/gaze15/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/gaze15/devicetree.cb

@@ -0,0 +1,318 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Enable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "1"
+	register "PchHdaAudioLinkDmic1" = "1"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
+	register "usb3_ports[1]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+	register "PcieClkSrcUsage[8]" = "0x40"
+
+	# PCI Express root port #9 x4, Clock 10 (SSD)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[10]" = "8"
+
+	# PCI Express root port #14 x1, Clock 6 (WLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[6]" = "13"
+
+	# PCI Express root port #15 x1, Clock 5 (LAN)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[5]" = "14"
+
+	# PCI Express root port #21 x4, Clock 11 (SSD2)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[11]" = "20"
+
+    # Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 off end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on  end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/gaze15/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/gaze15/gpio.h

@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_K21
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+		PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(DGPU_RST_N, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(DGPU_PWR_EN, 0, NONE, DEEP),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_GPI(GPD0, NONE, PWROK),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD7, NONE, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD9, NONE, PWROK),
+		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD11, NONE, PWROK),
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
+		PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B4, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+		PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H1, NONE, DEEP),
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H3, NONE, DEEP),
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H23, NONE, DEEP),
+		PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
+		PAD_CFG_GPI(GPP_I2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
+		PAD_CFG_GPI(GPP_J2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J3, NONE, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
+		PAD_CFG_GPI(GPP_K0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000),
+		PAD_CFG_GPI(GPP_K4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K19, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH
+		PAD_CFG_GPI(GPP_K22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K23, NONE, DEEP),
+};
+
+#endif
+
+#endif

src/mainboard/system76/gaze15/hda_verb.c

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15588520, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588520),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/gaze15/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}